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c04a611f4a84bd835fc79d368fc84d699df412ea
[mesa.git] / src / amd / vulkan / radv_meta_blit.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_meta.h"
25 #include "nir/nir_builder.h"
26
27 struct blit_region {
28 VkOffset3D src_offset;
29 VkExtent3D src_extent;
30 VkOffset3D dest_offset;
31 VkExtent3D dest_extent;
32 };
33
34 static nir_shader *
35 build_nir_vertex_shader(void)
36 {
37 const struct glsl_type *vec4 = glsl_vec4_type();
38 nir_builder b;
39
40 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
41 b.shader->info->name = ralloc_strdup(b.shader, "meta_blit_vs");
42
43 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
44 vec4, "gl_Position");
45 pos_out->data.location = VARYING_SLOT_POS;
46
47 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
48 vec4, "v_tex_pos");
49 tex_pos_out->data.location = VARYING_SLOT_VAR0;
50 tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
51
52 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
53
54 nir_store_var(&b, pos_out, outvec, 0xf);
55
56 nir_intrinsic_instr *src_box = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
57 src_box->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
58 nir_intrinsic_set_base(src_box, 0);
59 nir_intrinsic_set_range(src_box, 16);
60 src_box->num_components = 4;
61 nir_ssa_dest_init(&src_box->instr, &src_box->dest, 4, 32, "src_box");
62 nir_builder_instr_insert(&b, &src_box->instr);
63
64 nir_intrinsic_instr *src0_z = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
65 src0_z->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
66 nir_intrinsic_set_base(src0_z, 16);
67 nir_intrinsic_set_range(src0_z, 4);
68 src0_z->num_components = 1;
69 nir_ssa_dest_init(&src0_z->instr, &src0_z->dest, 1, 32, "src0_z");
70 nir_builder_instr_insert(&b, &src0_z->instr);
71
72 nir_intrinsic_instr *vertex_id = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_vertex_id_zero_base);
73 nir_ssa_dest_init(&vertex_id->instr, &vertex_id->dest, 1, 32, "vertexid");
74 nir_builder_instr_insert(&b, &vertex_id->instr);
75
76 /* vertex 0 - src0_x, src0_y, src0_z */
77 /* vertex 1 - src0_x, src1_y, src0_z*/
78 /* vertex 2 - src1_x, src0_y, src0_z */
79 /* so channel 0 is vertex_id != 2 ? src_x : src_x + w
80 channel 1 is vertex id != 1 ? src_y : src_y + w */
81
82 nir_ssa_def *c0cmp = nir_ine(&b, &vertex_id->dest.ssa,
83 nir_imm_int(&b, 2));
84 nir_ssa_def *c1cmp = nir_ine(&b, &vertex_id->dest.ssa,
85 nir_imm_int(&b, 1));
86
87 nir_ssa_def *comp[4];
88 comp[0] = nir_bcsel(&b, c0cmp,
89 nir_channel(&b, &src_box->dest.ssa, 0),
90 nir_channel(&b, &src_box->dest.ssa, 2));
91
92 comp[1] = nir_bcsel(&b, c1cmp,
93 nir_channel(&b, &src_box->dest.ssa, 1),
94 nir_channel(&b, &src_box->dest.ssa, 3));
95 comp[2] = &src0_z->dest.ssa;
96 comp[3] = nir_imm_float(&b, 1.0);
97 nir_ssa_def *out_tex_vec = nir_vec(&b, comp, 4);
98 nir_store_var(&b, tex_pos_out, out_tex_vec, 0xf);
99 return b.shader;
100 }
101
102 static nir_shader *
103 build_nir_copy_fragment_shader(enum glsl_sampler_dim tex_dim)
104 {
105 char shader_name[64];
106 const struct glsl_type *vec4 = glsl_vec4_type();
107 nir_builder b;
108
109 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
110
111 sprintf(shader_name, "meta_blit_fs.%d", tex_dim);
112 b.shader->info->name = ralloc_strdup(b.shader, shader_name);
113
114 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
115 vec4, "v_tex_pos");
116 tex_pos_in->data.location = VARYING_SLOT_VAR0;
117
118 /* Swizzle the array index which comes in as Z coordinate into the right
119 * position.
120 */
121 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
122 nir_ssa_def *const tex_pos =
123 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
124 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
125
126 const struct glsl_type *sampler_type =
127 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
128 glsl_get_base_type(vec4));
129 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
130 sampler_type, "s_tex");
131 sampler->data.descriptor_set = 0;
132 sampler->data.binding = 0;
133
134 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
135 tex->sampler_dim = tex_dim;
136 tex->op = nir_texop_tex;
137 tex->src[0].src_type = nir_tex_src_coord;
138 tex->src[0].src = nir_src_for_ssa(tex_pos);
139 tex->dest_type = nir_type_float; /* TODO */
140 tex->is_array = glsl_sampler_type_is_array(sampler_type);
141 tex->coord_components = tex_pos->num_components;
142 tex->texture = nir_deref_var_create(tex, sampler);
143 tex->sampler = nir_deref_var_create(tex, sampler);
144
145 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
146 nir_builder_instr_insert(&b, &tex->instr);
147
148 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
149 vec4, "f_color");
150 color_out->data.location = FRAG_RESULT_DATA0;
151 nir_store_var(&b, color_out, &tex->dest.ssa, 0xf);
152
153 return b.shader;
154 }
155
156 static nir_shader *
157 build_nir_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim)
158 {
159 char shader_name[64];
160 const struct glsl_type *vec4 = glsl_vec4_type();
161 nir_builder b;
162
163 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
164
165 sprintf(shader_name, "meta_blit_depth_fs.%d", tex_dim);
166 b.shader->info->name = ralloc_strdup(b.shader, shader_name);
167
168 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
169 vec4, "v_tex_pos");
170 tex_pos_in->data.location = VARYING_SLOT_VAR0;
171
172 /* Swizzle the array index which comes in as Z coordinate into the right
173 * position.
174 */
175 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
176 nir_ssa_def *const tex_pos =
177 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
178 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
179
180 const struct glsl_type *sampler_type =
181 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
182 glsl_get_base_type(vec4));
183 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
184 sampler_type, "s_tex");
185 sampler->data.descriptor_set = 0;
186 sampler->data.binding = 0;
187
188 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
189 tex->sampler_dim = tex_dim;
190 tex->op = nir_texop_tex;
191 tex->src[0].src_type = nir_tex_src_coord;
192 tex->src[0].src = nir_src_for_ssa(tex_pos);
193 tex->dest_type = nir_type_float; /* TODO */
194 tex->is_array = glsl_sampler_type_is_array(sampler_type);
195 tex->coord_components = tex_pos->num_components;
196 tex->texture = nir_deref_var_create(tex, sampler);
197 tex->sampler = nir_deref_var_create(tex, sampler);
198
199 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
200 nir_builder_instr_insert(&b, &tex->instr);
201
202 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
203 vec4, "f_color");
204 color_out->data.location = FRAG_RESULT_DEPTH;
205 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
206
207 return b.shader;
208 }
209
210 static nir_shader *
211 build_nir_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim)
212 {
213 char shader_name[64];
214 const struct glsl_type *vec4 = glsl_vec4_type();
215 nir_builder b;
216
217 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
218
219 sprintf(shader_name, "meta_blit_stencil_fs.%d", tex_dim);
220 b.shader->info->name = ralloc_strdup(b.shader, shader_name);
221
222 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
223 vec4, "v_tex_pos");
224 tex_pos_in->data.location = VARYING_SLOT_VAR0;
225
226 /* Swizzle the array index which comes in as Z coordinate into the right
227 * position.
228 */
229 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
230 nir_ssa_def *const tex_pos =
231 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
232 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
233
234 const struct glsl_type *sampler_type =
235 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
236 glsl_get_base_type(vec4));
237 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
238 sampler_type, "s_tex");
239 sampler->data.descriptor_set = 0;
240 sampler->data.binding = 0;
241
242 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
243 tex->sampler_dim = tex_dim;
244 tex->op = nir_texop_tex;
245 tex->src[0].src_type = nir_tex_src_coord;
246 tex->src[0].src = nir_src_for_ssa(tex_pos);
247 tex->dest_type = nir_type_float; /* TODO */
248 tex->is_array = glsl_sampler_type_is_array(sampler_type);
249 tex->coord_components = tex_pos->num_components;
250 tex->texture = nir_deref_var_create(tex, sampler);
251 tex->sampler = nir_deref_var_create(tex, sampler);
252
253 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
254 nir_builder_instr_insert(&b, &tex->instr);
255
256 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
257 vec4, "f_color");
258 color_out->data.location = FRAG_RESULT_STENCIL;
259 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
260
261 return b.shader;
262 }
263
264 static void
265 meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
266 struct radv_image *src_image,
267 struct radv_image_view *src_iview,
268 VkOffset3D src_offset_0,
269 VkOffset3D src_offset_1,
270 struct radv_image *dest_image,
271 struct radv_image_view *dest_iview,
272 VkOffset3D dest_offset_0,
273 VkOffset3D dest_offset_1,
274 VkRect2D dest_box,
275 VkFilter blit_filter)
276 {
277 struct radv_device *device = cmd_buffer->device;
278
279 assert(src_image->info.samples == dest_image->info.samples);
280
281 float vertex_push_constants[5] = {
282 (float)src_offset_0.x / (float)src_iview->extent.width,
283 (float)src_offset_0.y / (float)src_iview->extent.height,
284 (float)src_offset_1.x / (float)src_iview->extent.width,
285 (float)src_offset_1.y / (float)src_iview->extent.height,
286 (float)src_offset_0.z / (float)src_iview->extent.depth,
287 };
288
289 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
290 device->meta_state.blit.pipeline_layout,
291 VK_SHADER_STAGE_VERTEX_BIT, 0, 20,
292 vertex_push_constants);
293
294 VkSampler sampler;
295 radv_CreateSampler(radv_device_to_handle(device),
296 &(VkSamplerCreateInfo) {
297 .sType = VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO,
298 .magFilter = blit_filter,
299 .minFilter = blit_filter,
300 .addressModeU = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
301 .addressModeV = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
302 .addressModeW = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
303 }, &cmd_buffer->pool->alloc, &sampler);
304
305 VkFramebuffer fb;
306 radv_CreateFramebuffer(radv_device_to_handle(device),
307 &(VkFramebufferCreateInfo) {
308 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
309 .attachmentCount = 1,
310 .pAttachments = (VkImageView[]) {
311 radv_image_view_to_handle(dest_iview),
312 },
313 .width = dest_iview->extent.width,
314 .height = dest_iview->extent.height,
315 .layers = 1,
316 }, &cmd_buffer->pool->alloc, &fb);
317 VkPipeline pipeline;
318 switch (src_iview->aspect_mask) {
319 case VK_IMAGE_ASPECT_COLOR_BIT: {
320 unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format);
321
322 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
323 &(VkRenderPassBeginInfo) {
324 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
325 .renderPass = device->meta_state.blit.render_pass[fs_key],
326 .framebuffer = fb,
327 .renderArea = {
328 .offset = { dest_box.offset.x, dest_box.offset.y },
329 .extent = { dest_box.extent.width, dest_box.extent.height },
330 },
331 .clearValueCount = 0,
332 .pClearValues = NULL,
333 }, VK_SUBPASS_CONTENTS_INLINE);
334 switch (src_image->type) {
335 case VK_IMAGE_TYPE_1D:
336 pipeline = device->meta_state.blit.pipeline_1d_src[fs_key];
337 break;
338 case VK_IMAGE_TYPE_2D:
339 pipeline = device->meta_state.blit.pipeline_2d_src[fs_key];
340 break;
341 case VK_IMAGE_TYPE_3D:
342 pipeline = device->meta_state.blit.pipeline_3d_src[fs_key];
343 break;
344 default:
345 unreachable(!"bad VkImageType");
346 }
347 break;
348 }
349 case VK_IMAGE_ASPECT_DEPTH_BIT:
350 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
351 &(VkRenderPassBeginInfo) {
352 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
353 .renderPass = device->meta_state.blit.depth_only_rp,
354 .framebuffer = fb,
355 .renderArea = {
356 .offset = { dest_box.offset.x, dest_box.offset.y },
357 .extent = { dest_box.extent.width, dest_box.extent.height },
358 },
359 .clearValueCount = 0,
360 .pClearValues = NULL,
361 }, VK_SUBPASS_CONTENTS_INLINE);
362 switch (src_image->type) {
363 case VK_IMAGE_TYPE_1D:
364 pipeline = device->meta_state.blit.depth_only_1d_pipeline;
365 break;
366 case VK_IMAGE_TYPE_2D:
367 pipeline = device->meta_state.blit.depth_only_2d_pipeline;
368 break;
369 case VK_IMAGE_TYPE_3D:
370 pipeline = device->meta_state.blit.depth_only_3d_pipeline;
371 break;
372 default:
373 unreachable(!"bad VkImageType");
374 }
375 break;
376 case VK_IMAGE_ASPECT_STENCIL_BIT:
377 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
378 &(VkRenderPassBeginInfo) {
379 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
380 .renderPass = device->meta_state.blit.stencil_only_rp,
381 .framebuffer = fb,
382 .renderArea = {
383 .offset = { dest_box.offset.x, dest_box.offset.y },
384 .extent = { dest_box.extent.width, dest_box.extent.height },
385 },
386 .clearValueCount = 0,
387 .pClearValues = NULL,
388 }, VK_SUBPASS_CONTENTS_INLINE);
389 switch (src_image->type) {
390 case VK_IMAGE_TYPE_1D:
391 pipeline = device->meta_state.blit.stencil_only_1d_pipeline;
392 break;
393 case VK_IMAGE_TYPE_2D:
394 pipeline = device->meta_state.blit.stencil_only_2d_pipeline;
395 break;
396 case VK_IMAGE_TYPE_3D:
397 pipeline = device->meta_state.blit.stencil_only_3d_pipeline;
398 break;
399 default:
400 unreachable(!"bad VkImageType");
401 }
402 break;
403 default:
404 unreachable(!"bad VkImageType");
405 }
406
407 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
408 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
409 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
410 }
411
412 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
413 device->meta_state.blit.pipeline_layout,
414 0, /* set */
415 1, /* descriptorWriteCount */
416 (VkWriteDescriptorSet[]) {
417 {
418 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
419 .dstBinding = 0,
420 .dstArrayElement = 0,
421 .descriptorCount = 1,
422 .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
423 .pImageInfo = (VkDescriptorImageInfo[]) {
424 {
425 .sampler = sampler,
426 .imageView = radv_image_view_to_handle(src_iview),
427 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
428 },
429 }
430 }
431 });
432
433 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
434 .x = dest_offset_0.x,
435 .y = dest_offset_0.y,
436 .width = dest_offset_1.x - dest_offset_0.x,
437 .height = dest_offset_1.y - dest_offset_0.y,
438 .minDepth = 0.0f,
439 .maxDepth = 1.0f
440 });
441
442 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
443 .offset = (VkOffset2D) { MIN2(dest_offset_0.x, dest_offset_1.x), MIN2(dest_offset_0.y, dest_offset_1.y) },
444 .extent = (VkExtent2D) {
445 abs(dest_offset_1.x - dest_offset_0.x),
446 abs(dest_offset_1.y - dest_offset_0.y)
447 },
448 });
449
450 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
451
452 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
453
454 /* At the point where we emit the draw call, all data from the
455 * descriptor sets, etc. has been used. We are free to delete it.
456 */
457 /* TODO: above comment is not valid for at least descriptor sets/pools,
458 * as we may not free them till after execution finishes. Check others. */
459
460 radv_DestroySampler(radv_device_to_handle(device), sampler,
461 &cmd_buffer->pool->alloc);
462 radv_DestroyFramebuffer(radv_device_to_handle(device), fb,
463 &cmd_buffer->pool->alloc);
464 }
465
466 static bool
467 flip_coords(unsigned *src0, unsigned *src1, unsigned *dst0, unsigned *dst1)
468 {
469 bool flip = false;
470 if (*src0 > *src1) {
471 unsigned tmp = *src0;
472 *src0 = *src1;
473 *src1 = tmp;
474 flip = !flip;
475 }
476
477 if (*dst0 > *dst1) {
478 unsigned tmp = *dst0;
479 *dst0 = *dst1;
480 *dst1 = tmp;
481 flip = !flip;
482 }
483 return flip;
484 }
485
486 void radv_CmdBlitImage(
487 VkCommandBuffer commandBuffer,
488 VkImage srcImage,
489 VkImageLayout srcImageLayout,
490 VkImage destImage,
491 VkImageLayout destImageLayout,
492 uint32_t regionCount,
493 const VkImageBlit* pRegions,
494 VkFilter filter)
495
496 {
497 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
498 RADV_FROM_HANDLE(radv_image, src_image, srcImage);
499 RADV_FROM_HANDLE(radv_image, dest_image, destImage);
500 struct radv_meta_saved_state saved_state;
501
502 /* From the Vulkan 1.0 spec:
503 *
504 * vkCmdBlitImage must not be used for multisampled source or
505 * destination images. Use vkCmdResolveImage for this purpose.
506 */
507 assert(src_image->info.samples == 1);
508 assert(dest_image->info.samples == 1);
509
510 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
511
512 for (unsigned r = 0; r < regionCount; r++) {
513 const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
514 const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;
515 struct radv_image_view src_iview;
516 radv_image_view_init(&src_iview, cmd_buffer->device,
517 &(VkImageViewCreateInfo) {
518 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
519 .image = srcImage,
520 .viewType = radv_meta_get_view_type(src_image),
521 .format = src_image->vk_format,
522 .subresourceRange = {
523 .aspectMask = src_res->aspectMask,
524 .baseMipLevel = src_res->mipLevel,
525 .levelCount = 1,
526 .baseArrayLayer = src_res->baseArrayLayer,
527 .layerCount = 1
528 },
529 },
530 cmd_buffer, VK_IMAGE_USAGE_SAMPLED_BIT);
531
532 unsigned dst_start, dst_end;
533 if (dest_image->type == VK_IMAGE_TYPE_3D) {
534 assert(dst_res->baseArrayLayer == 0);
535 dst_start = pRegions[r].dstOffsets[0].z;
536 dst_end = pRegions[r].dstOffsets[1].z;
537 } else {
538 dst_start = dst_res->baseArrayLayer;
539 dst_end = dst_start + dst_res->layerCount;
540 }
541
542 unsigned src_start, src_end;
543 if (src_image->type == VK_IMAGE_TYPE_3D) {
544 assert(src_res->baseArrayLayer == 0);
545 src_start = pRegions[r].srcOffsets[0].z;
546 src_end = pRegions[r].srcOffsets[1].z;
547 } else {
548 src_start = src_res->baseArrayLayer;
549 src_end = src_start + src_res->layerCount;
550 }
551
552 bool flip_z = flip_coords(&src_start, &src_end, &dst_start, &dst_end);
553 float src_z_step = (float)(src_end + 1 - src_start) /
554 (float)(dst_end + 1 - dst_start);
555
556 if (flip_z) {
557 src_start = src_end;
558 src_z_step *= -1;
559 }
560
561 unsigned src_x0 = pRegions[r].srcOffsets[0].x;
562 unsigned src_x1 = pRegions[r].srcOffsets[1].x;
563 unsigned dst_x0 = pRegions[r].dstOffsets[0].x;
564 unsigned dst_x1 = pRegions[r].dstOffsets[1].x;
565
566 unsigned src_y0 = pRegions[r].srcOffsets[0].y;
567 unsigned src_y1 = pRegions[r].srcOffsets[1].y;
568 unsigned dst_y0 = pRegions[r].dstOffsets[0].y;
569 unsigned dst_y1 = pRegions[r].dstOffsets[1].y;
570
571 VkRect2D dest_box;
572 dest_box.offset.x = MIN2(dst_x0, dst_x1);
573 dest_box.offset.y = MIN2(dst_y0, dst_y1);
574 dest_box.extent.width = abs(dst_x1 - dst_x0);
575 dest_box.extent.height = abs(dst_y1 - dst_y0);
576
577 struct radv_image_view dest_iview;
578 unsigned usage;
579 if (dst_res->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT)
580 usage = VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
581 else
582 usage = VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT;
583
584 const unsigned num_layers = dst_end - dst_start;
585 for (unsigned i = 0; i < num_layers; i++) {
586 const VkOffset3D dest_offset_0 = {
587 .x = dst_x0,
588 .y = dst_y0,
589 .z = dst_start + i ,
590 };
591 const VkOffset3D dest_offset_1 = {
592 .x = dst_x1,
593 .y = dst_y1,
594 .z = dst_start + i ,
595 };
596 VkOffset3D src_offset_0 = {
597 .x = src_x0,
598 .y = src_y0,
599 .z = src_start + i * src_z_step,
600 };
601 VkOffset3D src_offset_1 = {
602 .x = src_x1,
603 .y = src_y1,
604 .z = src_start + i * src_z_step,
605 };
606 const uint32_t dest_array_slice =
607 radv_meta_get_iview_layer(dest_image, dst_res,
608 &dest_offset_0);
609
610 radv_image_view_init(&dest_iview, cmd_buffer->device,
611 &(VkImageViewCreateInfo) {
612 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
613 .image = destImage,
614 .viewType = radv_meta_get_view_type(dest_image),
615 .format = dest_image->vk_format,
616 .subresourceRange = {
617 .aspectMask = dst_res->aspectMask,
618 .baseMipLevel = dst_res->mipLevel,
619 .levelCount = 1,
620 .baseArrayLayer = dest_array_slice,
621 .layerCount = 1
622 },
623 },
624 cmd_buffer, usage);
625 meta_emit_blit(cmd_buffer,
626 src_image, &src_iview,
627 src_offset_0, src_offset_1,
628 dest_image, &dest_iview,
629 dest_offset_0, dest_offset_1,
630 dest_box,
631 filter);
632 }
633 }
634
635 radv_meta_restore(&saved_state, cmd_buffer);
636 }
637
638 void
639 radv_device_finish_meta_blit_state(struct radv_device *device)
640 {
641 for (unsigned i = 0; i < NUM_META_FS_KEYS; ++i) {
642 if (device->meta_state.blit.render_pass[i])
643 radv_DestroyRenderPass(radv_device_to_handle(device),
644 device->meta_state.blit.render_pass[i],
645 &device->meta_state.alloc);
646 if (device->meta_state.blit.pipeline_1d_src[i])
647 radv_DestroyPipeline(radv_device_to_handle(device),
648 device->meta_state.blit.pipeline_1d_src[i],
649 &device->meta_state.alloc);
650 if (device->meta_state.blit.pipeline_2d_src[i])
651 radv_DestroyPipeline(radv_device_to_handle(device),
652 device->meta_state.blit.pipeline_2d_src[i],
653 &device->meta_state.alloc);
654 if (device->meta_state.blit.pipeline_3d_src[i])
655 radv_DestroyPipeline(radv_device_to_handle(device),
656 device->meta_state.blit.pipeline_3d_src[i],
657 &device->meta_state.alloc);
658 }
659
660 if (device->meta_state.blit.depth_only_rp)
661 radv_DestroyRenderPass(radv_device_to_handle(device),
662 device->meta_state.blit.depth_only_rp,
663 &device->meta_state.alloc);
664 if (device->meta_state.blit.depth_only_1d_pipeline)
665 radv_DestroyPipeline(radv_device_to_handle(device),
666 device->meta_state.blit.depth_only_1d_pipeline,
667 &device->meta_state.alloc);
668 if (device->meta_state.blit.depth_only_2d_pipeline)
669 radv_DestroyPipeline(radv_device_to_handle(device),
670 device->meta_state.blit.depth_only_2d_pipeline,
671 &device->meta_state.alloc);
672 if (device->meta_state.blit.depth_only_3d_pipeline)
673 radv_DestroyPipeline(radv_device_to_handle(device),
674 device->meta_state.blit.depth_only_3d_pipeline,
675 &device->meta_state.alloc);
676 if (device->meta_state.blit.stencil_only_rp)
677 radv_DestroyRenderPass(radv_device_to_handle(device),
678 device->meta_state.blit.stencil_only_rp,
679 &device->meta_state.alloc);
680 if (device->meta_state.blit.stencil_only_1d_pipeline)
681 radv_DestroyPipeline(radv_device_to_handle(device),
682 device->meta_state.blit.stencil_only_1d_pipeline,
683 &device->meta_state.alloc);
684 if (device->meta_state.blit.stencil_only_2d_pipeline)
685 radv_DestroyPipeline(radv_device_to_handle(device),
686 device->meta_state.blit.stencil_only_2d_pipeline,
687 &device->meta_state.alloc);
688 if (device->meta_state.blit.stencil_only_3d_pipeline)
689 radv_DestroyPipeline(radv_device_to_handle(device),
690 device->meta_state.blit.stencil_only_3d_pipeline,
691 &device->meta_state.alloc);
692 if (device->meta_state.blit.pipeline_layout)
693 radv_DestroyPipelineLayout(radv_device_to_handle(device),
694 device->meta_state.blit.pipeline_layout,
695 &device->meta_state.alloc);
696 if (device->meta_state.blit.ds_layout)
697 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
698 device->meta_state.blit.ds_layout,
699 &device->meta_state.alloc);
700 }
701
702 static VkFormat pipeline_formats[] = {
703 VK_FORMAT_R8G8B8A8_UNORM,
704 VK_FORMAT_R8G8B8A8_UINT,
705 VK_FORMAT_R8G8B8A8_SINT,
706 VK_FORMAT_R16G16B16A16_UNORM,
707 VK_FORMAT_R16G16B16A16_SNORM,
708 VK_FORMAT_R16G16B16A16_UINT,
709 VK_FORMAT_R16G16B16A16_SINT,
710 VK_FORMAT_R32_SFLOAT,
711 VK_FORMAT_R32G32_SFLOAT,
712 VK_FORMAT_R32G32B32A32_SFLOAT
713 };
714
715 static VkResult
716 radv_device_init_meta_blit_color(struct radv_device *device,
717 struct radv_shader_module *vs)
718 {
719 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
720 VkResult result;
721
722 fs_1d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_1D);
723 fs_2d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_2D);
724 fs_3d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_3D);
725
726 for (unsigned i = 0; i < ARRAY_SIZE(pipeline_formats); ++i) {
727 unsigned key = radv_format_meta_fs_key(pipeline_formats[i]);
728 result = radv_CreateRenderPass(radv_device_to_handle(device),
729 &(VkRenderPassCreateInfo) {
730 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
731 .attachmentCount = 1,
732 .pAttachments = &(VkAttachmentDescription) {
733 .format = pipeline_formats[i],
734 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
735 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
736 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
737 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
738 },
739 .subpassCount = 1,
740 .pSubpasses = &(VkSubpassDescription) {
741 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
742 .inputAttachmentCount = 0,
743 .colorAttachmentCount = 1,
744 .pColorAttachments = &(VkAttachmentReference) {
745 .attachment = 0,
746 .layout = VK_IMAGE_LAYOUT_GENERAL,
747 },
748 .pResolveAttachments = NULL,
749 .pDepthStencilAttachment = &(VkAttachmentReference) {
750 .attachment = VK_ATTACHMENT_UNUSED,
751 .layout = VK_IMAGE_LAYOUT_GENERAL,
752 },
753 .preserveAttachmentCount = 1,
754 .pPreserveAttachments = (uint32_t[]) { 0 },
755 },
756 .dependencyCount = 0,
757 }, &device->meta_state.alloc, &device->meta_state.blit.render_pass[key]);
758 if (result != VK_SUCCESS)
759 goto fail;
760
761 VkPipelineVertexInputStateCreateInfo vi_create_info = {
762 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
763 .vertexBindingDescriptionCount = 0,
764 .vertexAttributeDescriptionCount = 0,
765 };
766
767 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
768 {
769 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
770 .stage = VK_SHADER_STAGE_VERTEX_BIT,
771 .module = radv_shader_module_to_handle(vs),
772 .pName = "main",
773 .pSpecializationInfo = NULL
774 }, {
775 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
776 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
777 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
778 .pName = "main",
779 .pSpecializationInfo = NULL
780 },
781 };
782
783 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
784 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
785 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
786 .pStages = pipeline_shader_stages,
787 .pVertexInputState = &vi_create_info,
788 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
789 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
790 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
791 .primitiveRestartEnable = false,
792 },
793 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
794 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
795 .viewportCount = 1,
796 .scissorCount = 1,
797 },
798 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
799 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
800 .rasterizerDiscardEnable = false,
801 .polygonMode = VK_POLYGON_MODE_FILL,
802 .cullMode = VK_CULL_MODE_NONE,
803 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
804 },
805 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
806 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
807 .rasterizationSamples = 1,
808 .sampleShadingEnable = false,
809 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
810 },
811 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
812 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
813 .attachmentCount = 1,
814 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
815 { .colorWriteMask =
816 VK_COLOR_COMPONENT_A_BIT |
817 VK_COLOR_COMPONENT_R_BIT |
818 VK_COLOR_COMPONENT_G_BIT |
819 VK_COLOR_COMPONENT_B_BIT },
820 }
821 },
822 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
823 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
824 .dynamicStateCount = 4,
825 .pDynamicStates = (VkDynamicState[]) {
826 VK_DYNAMIC_STATE_VIEWPORT,
827 VK_DYNAMIC_STATE_SCISSOR,
828 VK_DYNAMIC_STATE_LINE_WIDTH,
829 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
830 },
831 },
832 .flags = 0,
833 .layout = device->meta_state.blit.pipeline_layout,
834 .renderPass = device->meta_state.blit.render_pass[key],
835 .subpass = 0,
836 };
837
838 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
839 .use_rectlist = true
840 };
841
842 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
843 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
844 radv_pipeline_cache_to_handle(&device->meta_state.cache),
845 &vk_pipeline_info, &radv_pipeline_info,
846 &device->meta_state.alloc, &device->meta_state.blit.pipeline_1d_src[key]);
847 if (result != VK_SUCCESS)
848 goto fail;
849
850 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
851 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
852 radv_pipeline_cache_to_handle(&device->meta_state.cache),
853 &vk_pipeline_info, &radv_pipeline_info,
854 &device->meta_state.alloc, &device->meta_state.blit.pipeline_2d_src[key]);
855 if (result != VK_SUCCESS)
856 goto fail;
857
858 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
859 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
860 radv_pipeline_cache_to_handle(&device->meta_state.cache),
861 &vk_pipeline_info, &radv_pipeline_info,
862 &device->meta_state.alloc, &device->meta_state.blit.pipeline_3d_src[key]);
863 if (result != VK_SUCCESS)
864 goto fail;
865
866 }
867
868 result = VK_SUCCESS;
869 fail:
870 ralloc_free(fs_1d.nir);
871 ralloc_free(fs_2d.nir);
872 ralloc_free(fs_3d.nir);
873 return result;
874 }
875
876 static VkResult
877 radv_device_init_meta_blit_depth(struct radv_device *device,
878 struct radv_shader_module *vs)
879 {
880 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
881 VkResult result;
882
883 fs_1d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_1D);
884 fs_2d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_2D);
885 fs_3d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_3D);
886
887 result = radv_CreateRenderPass(radv_device_to_handle(device),
888 &(VkRenderPassCreateInfo) {
889 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
890 .attachmentCount = 1,
891 .pAttachments = &(VkAttachmentDescription) {
892 .format = 0,
893 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
894 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
895 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
896 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
897 },
898 .subpassCount = 1,
899 .pSubpasses = &(VkSubpassDescription) {
900 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
901 .inputAttachmentCount = 0,
902 .colorAttachmentCount = 0,
903 .pColorAttachments = NULL,
904 .pResolveAttachments = NULL,
905 .pDepthStencilAttachment = &(VkAttachmentReference) {
906 .attachment = 0,
907 .layout = VK_IMAGE_LAYOUT_GENERAL,
908 },
909 .preserveAttachmentCount = 1,
910 .pPreserveAttachments = (uint32_t[]) { 0 },
911 },
912 .dependencyCount = 0,
913 }, &device->meta_state.alloc, &device->meta_state.blit.depth_only_rp);
914 if (result != VK_SUCCESS)
915 goto fail;
916
917 VkPipelineVertexInputStateCreateInfo vi_create_info = {
918 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
919 .vertexBindingDescriptionCount = 0,
920 .vertexAttributeDescriptionCount = 0,
921 };
922
923 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
924 {
925 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
926 .stage = VK_SHADER_STAGE_VERTEX_BIT,
927 .module = radv_shader_module_to_handle(vs),
928 .pName = "main",
929 .pSpecializationInfo = NULL
930 }, {
931 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
932 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
933 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
934 .pName = "main",
935 .pSpecializationInfo = NULL
936 },
937 };
938
939 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
940 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
941 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
942 .pStages = pipeline_shader_stages,
943 .pVertexInputState = &vi_create_info,
944 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
945 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
946 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
947 .primitiveRestartEnable = false,
948 },
949 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
950 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
951 .viewportCount = 1,
952 .scissorCount = 1,
953 },
954 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
955 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
956 .rasterizerDiscardEnable = false,
957 .polygonMode = VK_POLYGON_MODE_FILL,
958 .cullMode = VK_CULL_MODE_NONE,
959 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
960 },
961 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
962 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
963 .rasterizationSamples = 1,
964 .sampleShadingEnable = false,
965 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
966 },
967 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
968 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
969 .attachmentCount = 0,
970 .pAttachments = NULL,
971 },
972 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
973 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
974 .depthTestEnable = true,
975 .depthWriteEnable = true,
976 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
977 },
978 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
979 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
980 .dynamicStateCount = 9,
981 .pDynamicStates = (VkDynamicState[]) {
982 VK_DYNAMIC_STATE_VIEWPORT,
983 VK_DYNAMIC_STATE_SCISSOR,
984 VK_DYNAMIC_STATE_LINE_WIDTH,
985 VK_DYNAMIC_STATE_DEPTH_BIAS,
986 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
987 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
988 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
989 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
990 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
991 },
992 },
993 .flags = 0,
994 .layout = device->meta_state.blit.pipeline_layout,
995 .renderPass = device->meta_state.blit.depth_only_rp,
996 .subpass = 0,
997 };
998
999 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1000 .use_rectlist = true
1001 };
1002
1003 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
1004 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1005 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1006 &vk_pipeline_info, &radv_pipeline_info,
1007 &device->meta_state.alloc, &device->meta_state.blit.depth_only_1d_pipeline);
1008 if (result != VK_SUCCESS)
1009 goto fail;
1010
1011 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
1012 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1013 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1014 &vk_pipeline_info, &radv_pipeline_info,
1015 &device->meta_state.alloc, &device->meta_state.blit.depth_only_2d_pipeline);
1016 if (result != VK_SUCCESS)
1017 goto fail;
1018
1019 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
1020 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1021 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1022 &vk_pipeline_info, &radv_pipeline_info,
1023 &device->meta_state.alloc, &device->meta_state.blit.depth_only_3d_pipeline);
1024 if (result != VK_SUCCESS)
1025 goto fail;
1026
1027 fail:
1028 ralloc_free(fs_1d.nir);
1029 ralloc_free(fs_2d.nir);
1030 ralloc_free(fs_3d.nir);
1031 return result;
1032 }
1033
1034 static VkResult
1035 radv_device_init_meta_blit_stencil(struct radv_device *device,
1036 struct radv_shader_module *vs)
1037 {
1038 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
1039 VkResult result;
1040
1041 fs_1d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_1D);
1042 fs_2d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_2D);
1043 fs_3d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_3D);
1044
1045 result = radv_CreateRenderPass(radv_device_to_handle(device),
1046 &(VkRenderPassCreateInfo) {
1047 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1048 .attachmentCount = 1,
1049 .pAttachments = &(VkAttachmentDescription) {
1050 .format = 0,
1051 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1052 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1053 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
1054 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
1055 },
1056 .subpassCount = 1,
1057 .pSubpasses = &(VkSubpassDescription) {
1058 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1059 .inputAttachmentCount = 0,
1060 .colorAttachmentCount = 0,
1061 .pColorAttachments = NULL,
1062 .pResolveAttachments = NULL,
1063 .pDepthStencilAttachment = &(VkAttachmentReference) {
1064 .attachment = 0,
1065 .layout = VK_IMAGE_LAYOUT_GENERAL,
1066 },
1067 .preserveAttachmentCount = 1,
1068 .pPreserveAttachments = (uint32_t[]) { 0 },
1069 },
1070 .dependencyCount = 0,
1071 }, &device->meta_state.alloc, &device->meta_state.blit.stencil_only_rp);
1072 if (result != VK_SUCCESS)
1073 goto fail;
1074
1075 VkPipelineVertexInputStateCreateInfo vi_create_info = {
1076 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
1077 .vertexBindingDescriptionCount = 0,
1078 .vertexAttributeDescriptionCount = 0,
1079 };
1080
1081 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
1082 {
1083 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1084 .stage = VK_SHADER_STAGE_VERTEX_BIT,
1085 .module = radv_shader_module_to_handle(vs),
1086 .pName = "main",
1087 .pSpecializationInfo = NULL
1088 }, {
1089 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1090 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
1091 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
1092 .pName = "main",
1093 .pSpecializationInfo = NULL
1094 },
1095 };
1096
1097 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1098 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1099 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
1100 .pStages = pipeline_shader_stages,
1101 .pVertexInputState = &vi_create_info,
1102 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1103 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1104 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1105 .primitiveRestartEnable = false,
1106 },
1107 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
1108 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1109 .viewportCount = 1,
1110 .scissorCount = 1,
1111 },
1112 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1113 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1114 .rasterizerDiscardEnable = false,
1115 .polygonMode = VK_POLYGON_MODE_FILL,
1116 .cullMode = VK_CULL_MODE_NONE,
1117 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1118 },
1119 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1120 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1121 .rasterizationSamples = 1,
1122 .sampleShadingEnable = false,
1123 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1124 },
1125 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1126 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1127 .attachmentCount = 0,
1128 .pAttachments = NULL,
1129 },
1130 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1131 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1132 .depthTestEnable = false,
1133 .depthWriteEnable = false,
1134 .stencilTestEnable = true,
1135 .front = {
1136 .failOp = VK_STENCIL_OP_REPLACE,
1137 .passOp = VK_STENCIL_OP_REPLACE,
1138 .depthFailOp = VK_STENCIL_OP_REPLACE,
1139 .compareOp = VK_COMPARE_OP_ALWAYS,
1140 .compareMask = 0xff,
1141 .writeMask = 0xff,
1142 .reference = 0
1143 },
1144 .back = {
1145 .failOp = VK_STENCIL_OP_REPLACE,
1146 .passOp = VK_STENCIL_OP_REPLACE,
1147 .depthFailOp = VK_STENCIL_OP_REPLACE,
1148 .compareOp = VK_COMPARE_OP_ALWAYS,
1149 .compareMask = 0xff,
1150 .writeMask = 0xff,
1151 .reference = 0
1152 },
1153 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
1154 },
1155
1156 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1157 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1158 .dynamicStateCount = 6,
1159 .pDynamicStates = (VkDynamicState[]) {
1160 VK_DYNAMIC_STATE_VIEWPORT,
1161 VK_DYNAMIC_STATE_SCISSOR,
1162 VK_DYNAMIC_STATE_LINE_WIDTH,
1163 VK_DYNAMIC_STATE_DEPTH_BIAS,
1164 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1165 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1166 },
1167 },
1168 .flags = 0,
1169 .layout = device->meta_state.blit.pipeline_layout,
1170 .renderPass = device->meta_state.blit.stencil_only_rp,
1171 .subpass = 0,
1172 };
1173
1174 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1175 .use_rectlist = true
1176 };
1177
1178 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
1179 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1180 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1181 &vk_pipeline_info, &radv_pipeline_info,
1182 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_1d_pipeline);
1183 if (result != VK_SUCCESS)
1184 goto fail;
1185
1186 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
1187 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1188 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1189 &vk_pipeline_info, &radv_pipeline_info,
1190 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_2d_pipeline);
1191 if (result != VK_SUCCESS)
1192 goto fail;
1193
1194 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
1195 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1196 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1197 &vk_pipeline_info, &radv_pipeline_info,
1198 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_3d_pipeline);
1199 if (result != VK_SUCCESS)
1200 goto fail;
1201
1202 fail:
1203 ralloc_free(fs_1d.nir);
1204 ralloc_free(fs_2d.nir);
1205 ralloc_free(fs_3d.nir);
1206 return result;
1207 }
1208
1209 VkResult
1210 radv_device_init_meta_blit_state(struct radv_device *device)
1211 {
1212 VkResult result;
1213 struct radv_shader_module vs = {0};
1214 zero(device->meta_state.blit);
1215
1216 VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1217 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1218 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1219 .bindingCount = 1,
1220 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1221 {
1222 .binding = 0,
1223 .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
1224 .descriptorCount = 1,
1225 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1226 .pImmutableSamplers = NULL
1227 },
1228 }
1229 };
1230 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1231 &ds_layout_info,
1232 &device->meta_state.alloc,
1233 &device->meta_state.blit.ds_layout);
1234 if (result != VK_SUCCESS)
1235 goto fail;
1236
1237 const VkPushConstantRange push_constant_range = {VK_SHADER_STAGE_VERTEX_BIT, 0, 20};
1238
1239 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1240 &(VkPipelineLayoutCreateInfo) {
1241 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1242 .setLayoutCount = 1,
1243 .pSetLayouts = &device->meta_state.blit.ds_layout,
1244 .pushConstantRangeCount = 1,
1245 .pPushConstantRanges = &push_constant_range,
1246 },
1247 &device->meta_state.alloc, &device->meta_state.blit.pipeline_layout);
1248 if (result != VK_SUCCESS)
1249 goto fail;
1250
1251 vs.nir = build_nir_vertex_shader();
1252
1253 result = radv_device_init_meta_blit_color(device, &vs);
1254 if (result != VK_SUCCESS)
1255 goto fail;
1256
1257 result = radv_device_init_meta_blit_depth(device, &vs);
1258 if (result != VK_SUCCESS)
1259 goto fail;
1260
1261 result = radv_device_init_meta_blit_stencil(device, &vs);
1262 if (result != VK_SUCCESS)
1263 goto fail;
1264 return VK_SUCCESS;
1265
1266 fail:
1267 ralloc_free(vs.nir);
1268 radv_device_finish_meta_blit_state(device);
1269 return result;
1270 }