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radv: Disable depth & stencil tests when the depthbuffer doesn't support it.
[mesa.git] / src / amd / vulkan / radv_meta_blit.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_meta.h"
25 #include "nir/nir_builder.h"
26
27 struct blit_region {
28 VkOffset3D src_offset;
29 VkExtent3D src_extent;
30 VkOffset3D dest_offset;
31 VkExtent3D dest_extent;
32 };
33
34 static nir_shader *
35 build_nir_vertex_shader(void)
36 {
37 const struct glsl_type *vec4 = glsl_vec4_type();
38 nir_builder b;
39
40 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
41 b.shader->info.name = ralloc_strdup(b.shader, "meta_blit_vs");
42
43 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
44 vec4, "gl_Position");
45 pos_out->data.location = VARYING_SLOT_POS;
46
47 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
48 vec4, "v_tex_pos");
49 tex_pos_out->data.location = VARYING_SLOT_VAR0;
50 tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
51
52 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
53
54 nir_store_var(&b, pos_out, outvec, 0xf);
55
56 nir_intrinsic_instr *src_box = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
57 src_box->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
58 nir_intrinsic_set_base(src_box, 0);
59 nir_intrinsic_set_range(src_box, 16);
60 src_box->num_components = 4;
61 nir_ssa_dest_init(&src_box->instr, &src_box->dest, 4, 32, "src_box");
62 nir_builder_instr_insert(&b, &src_box->instr);
63
64 nir_intrinsic_instr *src0_z = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
65 src0_z->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
66 nir_intrinsic_set_base(src0_z, 16);
67 nir_intrinsic_set_range(src0_z, 4);
68 src0_z->num_components = 1;
69 nir_ssa_dest_init(&src0_z->instr, &src0_z->dest, 1, 32, "src0_z");
70 nir_builder_instr_insert(&b, &src0_z->instr);
71
72 nir_intrinsic_instr *vertex_id = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_vertex_id_zero_base);
73 nir_ssa_dest_init(&vertex_id->instr, &vertex_id->dest, 1, 32, "vertexid");
74 nir_builder_instr_insert(&b, &vertex_id->instr);
75
76 /* vertex 0 - src0_x, src0_y, src0_z */
77 /* vertex 1 - src0_x, src1_y, src0_z*/
78 /* vertex 2 - src1_x, src0_y, src0_z */
79 /* so channel 0 is vertex_id != 2 ? src_x : src_x + w
80 channel 1 is vertex id != 1 ? src_y : src_y + w */
81
82 nir_ssa_def *c0cmp = nir_ine(&b, &vertex_id->dest.ssa,
83 nir_imm_int(&b, 2));
84 nir_ssa_def *c1cmp = nir_ine(&b, &vertex_id->dest.ssa,
85 nir_imm_int(&b, 1));
86
87 nir_ssa_def *comp[4];
88 comp[0] = nir_bcsel(&b, c0cmp,
89 nir_channel(&b, &src_box->dest.ssa, 0),
90 nir_channel(&b, &src_box->dest.ssa, 2));
91
92 comp[1] = nir_bcsel(&b, c1cmp,
93 nir_channel(&b, &src_box->dest.ssa, 1),
94 nir_channel(&b, &src_box->dest.ssa, 3));
95 comp[2] = &src0_z->dest.ssa;
96 comp[3] = nir_imm_float(&b, 1.0);
97 nir_ssa_def *out_tex_vec = nir_vec(&b, comp, 4);
98 nir_store_var(&b, tex_pos_out, out_tex_vec, 0xf);
99 return b.shader;
100 }
101
102 static nir_shader *
103 build_nir_copy_fragment_shader(enum glsl_sampler_dim tex_dim)
104 {
105 char shader_name[64];
106 const struct glsl_type *vec4 = glsl_vec4_type();
107 nir_builder b;
108
109 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
110
111 sprintf(shader_name, "meta_blit_fs.%d", tex_dim);
112 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
113
114 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
115 vec4, "v_tex_pos");
116 tex_pos_in->data.location = VARYING_SLOT_VAR0;
117
118 /* Swizzle the array index which comes in as Z coordinate into the right
119 * position.
120 */
121 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
122 nir_ssa_def *const tex_pos =
123 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
124 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
125
126 const struct glsl_type *sampler_type =
127 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
128 glsl_get_base_type(vec4));
129 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
130 sampler_type, "s_tex");
131 sampler->data.descriptor_set = 0;
132 sampler->data.binding = 0;
133
134 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
135 tex->sampler_dim = tex_dim;
136 tex->op = nir_texop_tex;
137 tex->src[0].src_type = nir_tex_src_coord;
138 tex->src[0].src = nir_src_for_ssa(tex_pos);
139 tex->dest_type = nir_type_float; /* TODO */
140 tex->is_array = glsl_sampler_type_is_array(sampler_type);
141 tex->coord_components = tex_pos->num_components;
142 tex->texture = nir_deref_var_create(tex, sampler);
143 tex->sampler = nir_deref_var_create(tex, sampler);
144
145 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
146 nir_builder_instr_insert(&b, &tex->instr);
147
148 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
149 vec4, "f_color");
150 color_out->data.location = FRAG_RESULT_DATA0;
151 nir_store_var(&b, color_out, &tex->dest.ssa, 0xf);
152
153 return b.shader;
154 }
155
156 static nir_shader *
157 build_nir_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim)
158 {
159 char shader_name[64];
160 const struct glsl_type *vec4 = glsl_vec4_type();
161 nir_builder b;
162
163 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
164
165 sprintf(shader_name, "meta_blit_depth_fs.%d", tex_dim);
166 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
167
168 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
169 vec4, "v_tex_pos");
170 tex_pos_in->data.location = VARYING_SLOT_VAR0;
171
172 /* Swizzle the array index which comes in as Z coordinate into the right
173 * position.
174 */
175 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
176 nir_ssa_def *const tex_pos =
177 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
178 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
179
180 const struct glsl_type *sampler_type =
181 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
182 glsl_get_base_type(vec4));
183 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
184 sampler_type, "s_tex");
185 sampler->data.descriptor_set = 0;
186 sampler->data.binding = 0;
187
188 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
189 tex->sampler_dim = tex_dim;
190 tex->op = nir_texop_tex;
191 tex->src[0].src_type = nir_tex_src_coord;
192 tex->src[0].src = nir_src_for_ssa(tex_pos);
193 tex->dest_type = nir_type_float; /* TODO */
194 tex->is_array = glsl_sampler_type_is_array(sampler_type);
195 tex->coord_components = tex_pos->num_components;
196 tex->texture = nir_deref_var_create(tex, sampler);
197 tex->sampler = nir_deref_var_create(tex, sampler);
198
199 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
200 nir_builder_instr_insert(&b, &tex->instr);
201
202 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
203 vec4, "f_color");
204 color_out->data.location = FRAG_RESULT_DEPTH;
205 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
206
207 return b.shader;
208 }
209
210 static nir_shader *
211 build_nir_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim)
212 {
213 char shader_name[64];
214 const struct glsl_type *vec4 = glsl_vec4_type();
215 nir_builder b;
216
217 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
218
219 sprintf(shader_name, "meta_blit_stencil_fs.%d", tex_dim);
220 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
221
222 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
223 vec4, "v_tex_pos");
224 tex_pos_in->data.location = VARYING_SLOT_VAR0;
225
226 /* Swizzle the array index which comes in as Z coordinate into the right
227 * position.
228 */
229 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
230 nir_ssa_def *const tex_pos =
231 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
232 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
233
234 const struct glsl_type *sampler_type =
235 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
236 glsl_get_base_type(vec4));
237 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
238 sampler_type, "s_tex");
239 sampler->data.descriptor_set = 0;
240 sampler->data.binding = 0;
241
242 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
243 tex->sampler_dim = tex_dim;
244 tex->op = nir_texop_tex;
245 tex->src[0].src_type = nir_tex_src_coord;
246 tex->src[0].src = nir_src_for_ssa(tex_pos);
247 tex->dest_type = nir_type_float; /* TODO */
248 tex->is_array = glsl_sampler_type_is_array(sampler_type);
249 tex->coord_components = tex_pos->num_components;
250 tex->texture = nir_deref_var_create(tex, sampler);
251 tex->sampler = nir_deref_var_create(tex, sampler);
252
253 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
254 nir_builder_instr_insert(&b, &tex->instr);
255
256 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
257 vec4, "f_color");
258 color_out->data.location = FRAG_RESULT_STENCIL;
259 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
260
261 return b.shader;
262 }
263
264 static void
265 meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
266 struct radv_image *src_image,
267 struct radv_image_view *src_iview,
268 VkOffset3D src_offset_0,
269 VkOffset3D src_offset_1,
270 struct radv_image *dest_image,
271 struct radv_image_view *dest_iview,
272 VkOffset3D dest_offset_0,
273 VkOffset3D dest_offset_1,
274 VkRect2D dest_box,
275 VkFilter blit_filter)
276 {
277 struct radv_device *device = cmd_buffer->device;
278
279 assert(src_image->info.samples == dest_image->info.samples);
280
281 float vertex_push_constants[5] = {
282 (float)src_offset_0.x / (float)src_iview->extent.width,
283 (float)src_offset_0.y / (float)src_iview->extent.height,
284 (float)src_offset_1.x / (float)src_iview->extent.width,
285 (float)src_offset_1.y / (float)src_iview->extent.height,
286 (float)src_offset_0.z / (float)src_iview->extent.depth,
287 };
288
289 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
290 device->meta_state.blit.pipeline_layout,
291 VK_SHADER_STAGE_VERTEX_BIT, 0, 20,
292 vertex_push_constants);
293
294 VkSampler sampler;
295 radv_CreateSampler(radv_device_to_handle(device),
296 &(VkSamplerCreateInfo) {
297 .sType = VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO,
298 .magFilter = blit_filter,
299 .minFilter = blit_filter,
300 .addressModeU = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
301 .addressModeV = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
302 .addressModeW = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
303 }, &cmd_buffer->pool->alloc, &sampler);
304
305 VkFramebuffer fb;
306 radv_CreateFramebuffer(radv_device_to_handle(device),
307 &(VkFramebufferCreateInfo) {
308 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
309 .attachmentCount = 1,
310 .pAttachments = (VkImageView[]) {
311 radv_image_view_to_handle(dest_iview),
312 },
313 .width = dest_iview->extent.width,
314 .height = dest_iview->extent.height,
315 .layers = 1,
316 }, &cmd_buffer->pool->alloc, &fb);
317 VkPipeline pipeline;
318 switch (src_iview->aspect_mask) {
319 case VK_IMAGE_ASPECT_COLOR_BIT: {
320 unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format);
321
322 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
323 &(VkRenderPassBeginInfo) {
324 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
325 .renderPass = device->meta_state.blit.render_pass[fs_key],
326 .framebuffer = fb,
327 .renderArea = {
328 .offset = { dest_box.offset.x, dest_box.offset.y },
329 .extent = { dest_box.extent.width, dest_box.extent.height },
330 },
331 .clearValueCount = 0,
332 .pClearValues = NULL,
333 }, VK_SUBPASS_CONTENTS_INLINE);
334 switch (src_image->type) {
335 case VK_IMAGE_TYPE_1D:
336 pipeline = device->meta_state.blit.pipeline_1d_src[fs_key];
337 break;
338 case VK_IMAGE_TYPE_2D:
339 pipeline = device->meta_state.blit.pipeline_2d_src[fs_key];
340 break;
341 case VK_IMAGE_TYPE_3D:
342 pipeline = device->meta_state.blit.pipeline_3d_src[fs_key];
343 break;
344 default:
345 unreachable(!"bad VkImageType");
346 }
347 break;
348 }
349 case VK_IMAGE_ASPECT_DEPTH_BIT:
350 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
351 &(VkRenderPassBeginInfo) {
352 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
353 .renderPass = device->meta_state.blit.depth_only_rp,
354 .framebuffer = fb,
355 .renderArea = {
356 .offset = { dest_box.offset.x, dest_box.offset.y },
357 .extent = { dest_box.extent.width, dest_box.extent.height },
358 },
359 .clearValueCount = 0,
360 .pClearValues = NULL,
361 }, VK_SUBPASS_CONTENTS_INLINE);
362 switch (src_image->type) {
363 case VK_IMAGE_TYPE_1D:
364 pipeline = device->meta_state.blit.depth_only_1d_pipeline;
365 break;
366 case VK_IMAGE_TYPE_2D:
367 pipeline = device->meta_state.blit.depth_only_2d_pipeline;
368 break;
369 case VK_IMAGE_TYPE_3D:
370 pipeline = device->meta_state.blit.depth_only_3d_pipeline;
371 break;
372 default:
373 unreachable(!"bad VkImageType");
374 }
375 break;
376 case VK_IMAGE_ASPECT_STENCIL_BIT:
377 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
378 &(VkRenderPassBeginInfo) {
379 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
380 .renderPass = device->meta_state.blit.stencil_only_rp,
381 .framebuffer = fb,
382 .renderArea = {
383 .offset = { dest_box.offset.x, dest_box.offset.y },
384 .extent = { dest_box.extent.width, dest_box.extent.height },
385 },
386 .clearValueCount = 0,
387 .pClearValues = NULL,
388 }, VK_SUBPASS_CONTENTS_INLINE);
389 switch (src_image->type) {
390 case VK_IMAGE_TYPE_1D:
391 pipeline = device->meta_state.blit.stencil_only_1d_pipeline;
392 break;
393 case VK_IMAGE_TYPE_2D:
394 pipeline = device->meta_state.blit.stencil_only_2d_pipeline;
395 break;
396 case VK_IMAGE_TYPE_3D:
397 pipeline = device->meta_state.blit.stencil_only_3d_pipeline;
398 break;
399 default:
400 unreachable(!"bad VkImageType");
401 }
402 break;
403 default:
404 unreachable(!"bad VkImageType");
405 }
406
407 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
408 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
409 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
410 }
411
412 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
413 device->meta_state.blit.pipeline_layout,
414 0, /* set */
415 1, /* descriptorWriteCount */
416 (VkWriteDescriptorSet[]) {
417 {
418 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
419 .dstBinding = 0,
420 .dstArrayElement = 0,
421 .descriptorCount = 1,
422 .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
423 .pImageInfo = (VkDescriptorImageInfo[]) {
424 {
425 .sampler = sampler,
426 .imageView = radv_image_view_to_handle(src_iview),
427 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
428 },
429 }
430 }
431 });
432
433 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
434 .x = dest_offset_0.x,
435 .y = dest_offset_0.y,
436 .width = dest_offset_1.x - dest_offset_0.x,
437 .height = dest_offset_1.y - dest_offset_0.y,
438 .minDepth = 0.0f,
439 .maxDepth = 1.0f
440 });
441
442 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
443 .offset = (VkOffset2D) { MIN2(dest_offset_0.x, dest_offset_1.x), MIN2(dest_offset_0.y, dest_offset_1.y) },
444 .extent = (VkExtent2D) {
445 abs(dest_offset_1.x - dest_offset_0.x),
446 abs(dest_offset_1.y - dest_offset_0.y)
447 },
448 });
449
450 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
451
452 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
453
454 /* At the point where we emit the draw call, all data from the
455 * descriptor sets, etc. has been used. We are free to delete it.
456 */
457 /* TODO: above comment is not valid for at least descriptor sets/pools,
458 * as we may not free them till after execution finishes. Check others. */
459
460 radv_DestroySampler(radv_device_to_handle(device), sampler,
461 &cmd_buffer->pool->alloc);
462 radv_DestroyFramebuffer(radv_device_to_handle(device), fb,
463 &cmd_buffer->pool->alloc);
464 }
465
466 static bool
467 flip_coords(unsigned *src0, unsigned *src1, unsigned *dst0, unsigned *dst1)
468 {
469 bool flip = false;
470 if (*src0 > *src1) {
471 unsigned tmp = *src0;
472 *src0 = *src1;
473 *src1 = tmp;
474 flip = !flip;
475 }
476
477 if (*dst0 > *dst1) {
478 unsigned tmp = *dst0;
479 *dst0 = *dst1;
480 *dst1 = tmp;
481 flip = !flip;
482 }
483 return flip;
484 }
485
486 void radv_CmdBlitImage(
487 VkCommandBuffer commandBuffer,
488 VkImage srcImage,
489 VkImageLayout srcImageLayout,
490 VkImage destImage,
491 VkImageLayout destImageLayout,
492 uint32_t regionCount,
493 const VkImageBlit* pRegions,
494 VkFilter filter)
495
496 {
497 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
498 RADV_FROM_HANDLE(radv_image, src_image, srcImage);
499 RADV_FROM_HANDLE(radv_image, dest_image, destImage);
500 struct radv_meta_saved_state saved_state;
501
502 /* From the Vulkan 1.0 spec:
503 *
504 * vkCmdBlitImage must not be used for multisampled source or
505 * destination images. Use vkCmdResolveImage for this purpose.
506 */
507 assert(src_image->info.samples == 1);
508 assert(dest_image->info.samples == 1);
509
510 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
511
512 for (unsigned r = 0; r < regionCount; r++) {
513 const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
514 const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;
515 struct radv_image_view src_iview;
516 radv_image_view_init(&src_iview, cmd_buffer->device,
517 &(VkImageViewCreateInfo) {
518 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
519 .image = srcImage,
520 .viewType = radv_meta_get_view_type(src_image),
521 .format = src_image->vk_format,
522 .subresourceRange = {
523 .aspectMask = src_res->aspectMask,
524 .baseMipLevel = src_res->mipLevel,
525 .levelCount = 1,
526 .baseArrayLayer = src_res->baseArrayLayer,
527 .layerCount = 1
528 },
529 });
530
531 unsigned dst_start, dst_end;
532 if (dest_image->type == VK_IMAGE_TYPE_3D) {
533 assert(dst_res->baseArrayLayer == 0);
534 dst_start = pRegions[r].dstOffsets[0].z;
535 dst_end = pRegions[r].dstOffsets[1].z;
536 } else {
537 dst_start = dst_res->baseArrayLayer;
538 dst_end = dst_start + dst_res->layerCount;
539 }
540
541 unsigned src_start, src_end;
542 if (src_image->type == VK_IMAGE_TYPE_3D) {
543 assert(src_res->baseArrayLayer == 0);
544 src_start = pRegions[r].srcOffsets[0].z;
545 src_end = pRegions[r].srcOffsets[1].z;
546 } else {
547 src_start = src_res->baseArrayLayer;
548 src_end = src_start + src_res->layerCount;
549 }
550
551 bool flip_z = flip_coords(&src_start, &src_end, &dst_start, &dst_end);
552 float src_z_step = (float)(src_end + 1 - src_start) /
553 (float)(dst_end + 1 - dst_start);
554
555 if (flip_z) {
556 src_start = src_end;
557 src_z_step *= -1;
558 }
559
560 unsigned src_x0 = pRegions[r].srcOffsets[0].x;
561 unsigned src_x1 = pRegions[r].srcOffsets[1].x;
562 unsigned dst_x0 = pRegions[r].dstOffsets[0].x;
563 unsigned dst_x1 = pRegions[r].dstOffsets[1].x;
564
565 unsigned src_y0 = pRegions[r].srcOffsets[0].y;
566 unsigned src_y1 = pRegions[r].srcOffsets[1].y;
567 unsigned dst_y0 = pRegions[r].dstOffsets[0].y;
568 unsigned dst_y1 = pRegions[r].dstOffsets[1].y;
569
570 VkRect2D dest_box;
571 dest_box.offset.x = MIN2(dst_x0, dst_x1);
572 dest_box.offset.y = MIN2(dst_y0, dst_y1);
573 dest_box.extent.width = abs(dst_x1 - dst_x0);
574 dest_box.extent.height = abs(dst_y1 - dst_y0);
575
576 struct radv_image_view dest_iview;
577 const unsigned num_layers = dst_end - dst_start;
578 for (unsigned i = 0; i < num_layers; i++) {
579 const VkOffset3D dest_offset_0 = {
580 .x = dst_x0,
581 .y = dst_y0,
582 .z = dst_start + i ,
583 };
584 const VkOffset3D dest_offset_1 = {
585 .x = dst_x1,
586 .y = dst_y1,
587 .z = dst_start + i ,
588 };
589 VkOffset3D src_offset_0 = {
590 .x = src_x0,
591 .y = src_y0,
592 .z = src_start + i * src_z_step,
593 };
594 VkOffset3D src_offset_1 = {
595 .x = src_x1,
596 .y = src_y1,
597 .z = src_start + i * src_z_step,
598 };
599 const uint32_t dest_array_slice =
600 radv_meta_get_iview_layer(dest_image, dst_res,
601 &dest_offset_0);
602
603 radv_image_view_init(&dest_iview, cmd_buffer->device,
604 &(VkImageViewCreateInfo) {
605 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
606 .image = destImage,
607 .viewType = radv_meta_get_view_type(dest_image),
608 .format = dest_image->vk_format,
609 .subresourceRange = {
610 .aspectMask = dst_res->aspectMask,
611 .baseMipLevel = dst_res->mipLevel,
612 .levelCount = 1,
613 .baseArrayLayer = dest_array_slice,
614 .layerCount = 1
615 },
616 });
617 meta_emit_blit(cmd_buffer,
618 src_image, &src_iview,
619 src_offset_0, src_offset_1,
620 dest_image, &dest_iview,
621 dest_offset_0, dest_offset_1,
622 dest_box,
623 filter);
624 }
625 }
626
627 radv_meta_restore(&saved_state, cmd_buffer);
628 }
629
630 void
631 radv_device_finish_meta_blit_state(struct radv_device *device)
632 {
633 for (unsigned i = 0; i < NUM_META_FS_KEYS; ++i) {
634 if (device->meta_state.blit.render_pass[i])
635 radv_DestroyRenderPass(radv_device_to_handle(device),
636 device->meta_state.blit.render_pass[i],
637 &device->meta_state.alloc);
638 if (device->meta_state.blit.pipeline_1d_src[i])
639 radv_DestroyPipeline(radv_device_to_handle(device),
640 device->meta_state.blit.pipeline_1d_src[i],
641 &device->meta_state.alloc);
642 if (device->meta_state.blit.pipeline_2d_src[i])
643 radv_DestroyPipeline(radv_device_to_handle(device),
644 device->meta_state.blit.pipeline_2d_src[i],
645 &device->meta_state.alloc);
646 if (device->meta_state.blit.pipeline_3d_src[i])
647 radv_DestroyPipeline(radv_device_to_handle(device),
648 device->meta_state.blit.pipeline_3d_src[i],
649 &device->meta_state.alloc);
650 }
651
652 if (device->meta_state.blit.depth_only_rp)
653 radv_DestroyRenderPass(radv_device_to_handle(device),
654 device->meta_state.blit.depth_only_rp,
655 &device->meta_state.alloc);
656 if (device->meta_state.blit.depth_only_1d_pipeline)
657 radv_DestroyPipeline(radv_device_to_handle(device),
658 device->meta_state.blit.depth_only_1d_pipeline,
659 &device->meta_state.alloc);
660 if (device->meta_state.blit.depth_only_2d_pipeline)
661 radv_DestroyPipeline(radv_device_to_handle(device),
662 device->meta_state.blit.depth_only_2d_pipeline,
663 &device->meta_state.alloc);
664 if (device->meta_state.blit.depth_only_3d_pipeline)
665 radv_DestroyPipeline(radv_device_to_handle(device),
666 device->meta_state.blit.depth_only_3d_pipeline,
667 &device->meta_state.alloc);
668 if (device->meta_state.blit.stencil_only_rp)
669 radv_DestroyRenderPass(radv_device_to_handle(device),
670 device->meta_state.blit.stencil_only_rp,
671 &device->meta_state.alloc);
672 if (device->meta_state.blit.stencil_only_1d_pipeline)
673 radv_DestroyPipeline(radv_device_to_handle(device),
674 device->meta_state.blit.stencil_only_1d_pipeline,
675 &device->meta_state.alloc);
676 if (device->meta_state.blit.stencil_only_2d_pipeline)
677 radv_DestroyPipeline(radv_device_to_handle(device),
678 device->meta_state.blit.stencil_only_2d_pipeline,
679 &device->meta_state.alloc);
680 if (device->meta_state.blit.stencil_only_3d_pipeline)
681 radv_DestroyPipeline(radv_device_to_handle(device),
682 device->meta_state.blit.stencil_only_3d_pipeline,
683 &device->meta_state.alloc);
684 if (device->meta_state.blit.pipeline_layout)
685 radv_DestroyPipelineLayout(radv_device_to_handle(device),
686 device->meta_state.blit.pipeline_layout,
687 &device->meta_state.alloc);
688 if (device->meta_state.blit.ds_layout)
689 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
690 device->meta_state.blit.ds_layout,
691 &device->meta_state.alloc);
692 }
693
694 static VkFormat pipeline_formats[] = {
695 VK_FORMAT_R8G8B8A8_UNORM,
696 VK_FORMAT_R8G8B8A8_UINT,
697 VK_FORMAT_R8G8B8A8_SINT,
698 VK_FORMAT_R16G16B16A16_UNORM,
699 VK_FORMAT_R16G16B16A16_SNORM,
700 VK_FORMAT_R16G16B16A16_UINT,
701 VK_FORMAT_R16G16B16A16_SINT,
702 VK_FORMAT_R32_SFLOAT,
703 VK_FORMAT_R32G32_SFLOAT,
704 VK_FORMAT_R32G32B32A32_SFLOAT
705 };
706
707 static VkResult
708 radv_device_init_meta_blit_color(struct radv_device *device,
709 struct radv_shader_module *vs)
710 {
711 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
712 VkResult result;
713
714 fs_1d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_1D);
715 fs_2d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_2D);
716 fs_3d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_3D);
717
718 for (unsigned i = 0; i < ARRAY_SIZE(pipeline_formats); ++i) {
719 unsigned key = radv_format_meta_fs_key(pipeline_formats[i]);
720 result = radv_CreateRenderPass(radv_device_to_handle(device),
721 &(VkRenderPassCreateInfo) {
722 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
723 .attachmentCount = 1,
724 .pAttachments = &(VkAttachmentDescription) {
725 .format = pipeline_formats[i],
726 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
727 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
728 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
729 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
730 },
731 .subpassCount = 1,
732 .pSubpasses = &(VkSubpassDescription) {
733 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
734 .inputAttachmentCount = 0,
735 .colorAttachmentCount = 1,
736 .pColorAttachments = &(VkAttachmentReference) {
737 .attachment = 0,
738 .layout = VK_IMAGE_LAYOUT_GENERAL,
739 },
740 .pResolveAttachments = NULL,
741 .pDepthStencilAttachment = &(VkAttachmentReference) {
742 .attachment = VK_ATTACHMENT_UNUSED,
743 .layout = VK_IMAGE_LAYOUT_GENERAL,
744 },
745 .preserveAttachmentCount = 1,
746 .pPreserveAttachments = (uint32_t[]) { 0 },
747 },
748 .dependencyCount = 0,
749 }, &device->meta_state.alloc, &device->meta_state.blit.render_pass[key]);
750 if (result != VK_SUCCESS)
751 goto fail;
752
753 VkPipelineVertexInputStateCreateInfo vi_create_info = {
754 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
755 .vertexBindingDescriptionCount = 0,
756 .vertexAttributeDescriptionCount = 0,
757 };
758
759 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
760 {
761 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
762 .stage = VK_SHADER_STAGE_VERTEX_BIT,
763 .module = radv_shader_module_to_handle(vs),
764 .pName = "main",
765 .pSpecializationInfo = NULL
766 }, {
767 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
768 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
769 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
770 .pName = "main",
771 .pSpecializationInfo = NULL
772 },
773 };
774
775 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
776 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
777 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
778 .pStages = pipeline_shader_stages,
779 .pVertexInputState = &vi_create_info,
780 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
781 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
782 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
783 .primitiveRestartEnable = false,
784 },
785 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
786 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
787 .viewportCount = 1,
788 .scissorCount = 1,
789 },
790 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
791 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
792 .rasterizerDiscardEnable = false,
793 .polygonMode = VK_POLYGON_MODE_FILL,
794 .cullMode = VK_CULL_MODE_NONE,
795 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
796 },
797 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
798 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
799 .rasterizationSamples = 1,
800 .sampleShadingEnable = false,
801 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
802 },
803 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
804 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
805 .attachmentCount = 1,
806 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
807 { .colorWriteMask =
808 VK_COLOR_COMPONENT_A_BIT |
809 VK_COLOR_COMPONENT_R_BIT |
810 VK_COLOR_COMPONENT_G_BIT |
811 VK_COLOR_COMPONENT_B_BIT },
812 }
813 },
814 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
815 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
816 .dynamicStateCount = 4,
817 .pDynamicStates = (VkDynamicState[]) {
818 VK_DYNAMIC_STATE_VIEWPORT,
819 VK_DYNAMIC_STATE_SCISSOR,
820 VK_DYNAMIC_STATE_LINE_WIDTH,
821 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
822 },
823 },
824 .flags = 0,
825 .layout = device->meta_state.blit.pipeline_layout,
826 .renderPass = device->meta_state.blit.render_pass[key],
827 .subpass = 0,
828 };
829
830 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
831 .use_rectlist = true
832 };
833
834 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
835 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
836 radv_pipeline_cache_to_handle(&device->meta_state.cache),
837 &vk_pipeline_info, &radv_pipeline_info,
838 &device->meta_state.alloc, &device->meta_state.blit.pipeline_1d_src[key]);
839 if (result != VK_SUCCESS)
840 goto fail;
841
842 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
843 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
844 radv_pipeline_cache_to_handle(&device->meta_state.cache),
845 &vk_pipeline_info, &radv_pipeline_info,
846 &device->meta_state.alloc, &device->meta_state.blit.pipeline_2d_src[key]);
847 if (result != VK_SUCCESS)
848 goto fail;
849
850 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
851 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
852 radv_pipeline_cache_to_handle(&device->meta_state.cache),
853 &vk_pipeline_info, &radv_pipeline_info,
854 &device->meta_state.alloc, &device->meta_state.blit.pipeline_3d_src[key]);
855 if (result != VK_SUCCESS)
856 goto fail;
857
858 }
859
860 result = VK_SUCCESS;
861 fail:
862 ralloc_free(fs_1d.nir);
863 ralloc_free(fs_2d.nir);
864 ralloc_free(fs_3d.nir);
865 return result;
866 }
867
868 static VkResult
869 radv_device_init_meta_blit_depth(struct radv_device *device,
870 struct radv_shader_module *vs)
871 {
872 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
873 VkResult result;
874
875 fs_1d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_1D);
876 fs_2d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_2D);
877 fs_3d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_3D);
878
879 result = radv_CreateRenderPass(radv_device_to_handle(device),
880 &(VkRenderPassCreateInfo) {
881 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
882 .attachmentCount = 1,
883 .pAttachments = &(VkAttachmentDescription) {
884 .format = VK_FORMAT_D32_SFLOAT,
885 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
886 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
887 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
888 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
889 },
890 .subpassCount = 1,
891 .pSubpasses = &(VkSubpassDescription) {
892 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
893 .inputAttachmentCount = 0,
894 .colorAttachmentCount = 0,
895 .pColorAttachments = NULL,
896 .pResolveAttachments = NULL,
897 .pDepthStencilAttachment = &(VkAttachmentReference) {
898 .attachment = 0,
899 .layout = VK_IMAGE_LAYOUT_GENERAL,
900 },
901 .preserveAttachmentCount = 1,
902 .pPreserveAttachments = (uint32_t[]) { 0 },
903 },
904 .dependencyCount = 0,
905 }, &device->meta_state.alloc, &device->meta_state.blit.depth_only_rp);
906 if (result != VK_SUCCESS)
907 goto fail;
908
909 VkPipelineVertexInputStateCreateInfo vi_create_info = {
910 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
911 .vertexBindingDescriptionCount = 0,
912 .vertexAttributeDescriptionCount = 0,
913 };
914
915 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
916 {
917 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
918 .stage = VK_SHADER_STAGE_VERTEX_BIT,
919 .module = radv_shader_module_to_handle(vs),
920 .pName = "main",
921 .pSpecializationInfo = NULL
922 }, {
923 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
924 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
925 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
926 .pName = "main",
927 .pSpecializationInfo = NULL
928 },
929 };
930
931 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
932 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
933 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
934 .pStages = pipeline_shader_stages,
935 .pVertexInputState = &vi_create_info,
936 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
937 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
938 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
939 .primitiveRestartEnable = false,
940 },
941 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
942 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
943 .viewportCount = 1,
944 .scissorCount = 1,
945 },
946 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
947 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
948 .rasterizerDiscardEnable = false,
949 .polygonMode = VK_POLYGON_MODE_FILL,
950 .cullMode = VK_CULL_MODE_NONE,
951 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
952 },
953 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
954 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
955 .rasterizationSamples = 1,
956 .sampleShadingEnable = false,
957 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
958 },
959 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
960 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
961 .attachmentCount = 0,
962 .pAttachments = NULL,
963 },
964 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
965 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
966 .depthTestEnable = true,
967 .depthWriteEnable = true,
968 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
969 },
970 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
971 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
972 .dynamicStateCount = 9,
973 .pDynamicStates = (VkDynamicState[]) {
974 VK_DYNAMIC_STATE_VIEWPORT,
975 VK_DYNAMIC_STATE_SCISSOR,
976 VK_DYNAMIC_STATE_LINE_WIDTH,
977 VK_DYNAMIC_STATE_DEPTH_BIAS,
978 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
979 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
980 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
981 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
982 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
983 },
984 },
985 .flags = 0,
986 .layout = device->meta_state.blit.pipeline_layout,
987 .renderPass = device->meta_state.blit.depth_only_rp,
988 .subpass = 0,
989 };
990
991 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
992 .use_rectlist = true
993 };
994
995 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
996 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
997 radv_pipeline_cache_to_handle(&device->meta_state.cache),
998 &vk_pipeline_info, &radv_pipeline_info,
999 &device->meta_state.alloc, &device->meta_state.blit.depth_only_1d_pipeline);
1000 if (result != VK_SUCCESS)
1001 goto fail;
1002
1003 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
1004 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1005 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1006 &vk_pipeline_info, &radv_pipeline_info,
1007 &device->meta_state.alloc, &device->meta_state.blit.depth_only_2d_pipeline);
1008 if (result != VK_SUCCESS)
1009 goto fail;
1010
1011 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
1012 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1013 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1014 &vk_pipeline_info, &radv_pipeline_info,
1015 &device->meta_state.alloc, &device->meta_state.blit.depth_only_3d_pipeline);
1016 if (result != VK_SUCCESS)
1017 goto fail;
1018
1019 fail:
1020 ralloc_free(fs_1d.nir);
1021 ralloc_free(fs_2d.nir);
1022 ralloc_free(fs_3d.nir);
1023 return result;
1024 }
1025
1026 static VkResult
1027 radv_device_init_meta_blit_stencil(struct radv_device *device,
1028 struct radv_shader_module *vs)
1029 {
1030 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
1031 VkResult result;
1032
1033 fs_1d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_1D);
1034 fs_2d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_2D);
1035 fs_3d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_3D);
1036
1037 result = radv_CreateRenderPass(radv_device_to_handle(device),
1038 &(VkRenderPassCreateInfo) {
1039 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1040 .attachmentCount = 1,
1041 .pAttachments = &(VkAttachmentDescription) {
1042 .format = VK_FORMAT_S8_UINT,
1043 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1044 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1045 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
1046 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
1047 },
1048 .subpassCount = 1,
1049 .pSubpasses = &(VkSubpassDescription) {
1050 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1051 .inputAttachmentCount = 0,
1052 .colorAttachmentCount = 0,
1053 .pColorAttachments = NULL,
1054 .pResolveAttachments = NULL,
1055 .pDepthStencilAttachment = &(VkAttachmentReference) {
1056 .attachment = 0,
1057 .layout = VK_IMAGE_LAYOUT_GENERAL,
1058 },
1059 .preserveAttachmentCount = 1,
1060 .pPreserveAttachments = (uint32_t[]) { 0 },
1061 },
1062 .dependencyCount = 0,
1063 }, &device->meta_state.alloc, &device->meta_state.blit.stencil_only_rp);
1064 if (result != VK_SUCCESS)
1065 goto fail;
1066
1067 VkPipelineVertexInputStateCreateInfo vi_create_info = {
1068 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
1069 .vertexBindingDescriptionCount = 0,
1070 .vertexAttributeDescriptionCount = 0,
1071 };
1072
1073 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
1074 {
1075 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1076 .stage = VK_SHADER_STAGE_VERTEX_BIT,
1077 .module = radv_shader_module_to_handle(vs),
1078 .pName = "main",
1079 .pSpecializationInfo = NULL
1080 }, {
1081 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1082 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
1083 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
1084 .pName = "main",
1085 .pSpecializationInfo = NULL
1086 },
1087 };
1088
1089 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1090 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1091 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
1092 .pStages = pipeline_shader_stages,
1093 .pVertexInputState = &vi_create_info,
1094 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1095 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1096 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1097 .primitiveRestartEnable = false,
1098 },
1099 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
1100 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1101 .viewportCount = 1,
1102 .scissorCount = 1,
1103 },
1104 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1105 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1106 .rasterizerDiscardEnable = false,
1107 .polygonMode = VK_POLYGON_MODE_FILL,
1108 .cullMode = VK_CULL_MODE_NONE,
1109 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1110 },
1111 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1112 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1113 .rasterizationSamples = 1,
1114 .sampleShadingEnable = false,
1115 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1116 },
1117 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1118 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1119 .attachmentCount = 0,
1120 .pAttachments = NULL,
1121 },
1122 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1123 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1124 .depthTestEnable = false,
1125 .depthWriteEnable = false,
1126 .stencilTestEnable = true,
1127 .front = {
1128 .failOp = VK_STENCIL_OP_REPLACE,
1129 .passOp = VK_STENCIL_OP_REPLACE,
1130 .depthFailOp = VK_STENCIL_OP_REPLACE,
1131 .compareOp = VK_COMPARE_OP_ALWAYS,
1132 .compareMask = 0xff,
1133 .writeMask = 0xff,
1134 .reference = 0
1135 },
1136 .back = {
1137 .failOp = VK_STENCIL_OP_REPLACE,
1138 .passOp = VK_STENCIL_OP_REPLACE,
1139 .depthFailOp = VK_STENCIL_OP_REPLACE,
1140 .compareOp = VK_COMPARE_OP_ALWAYS,
1141 .compareMask = 0xff,
1142 .writeMask = 0xff,
1143 .reference = 0
1144 },
1145 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
1146 },
1147
1148 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1149 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1150 .dynamicStateCount = 6,
1151 .pDynamicStates = (VkDynamicState[]) {
1152 VK_DYNAMIC_STATE_VIEWPORT,
1153 VK_DYNAMIC_STATE_SCISSOR,
1154 VK_DYNAMIC_STATE_LINE_WIDTH,
1155 VK_DYNAMIC_STATE_DEPTH_BIAS,
1156 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1157 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1158 },
1159 },
1160 .flags = 0,
1161 .layout = device->meta_state.blit.pipeline_layout,
1162 .renderPass = device->meta_state.blit.stencil_only_rp,
1163 .subpass = 0,
1164 };
1165
1166 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1167 .use_rectlist = true
1168 };
1169
1170 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
1171 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1172 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1173 &vk_pipeline_info, &radv_pipeline_info,
1174 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_1d_pipeline);
1175 if (result != VK_SUCCESS)
1176 goto fail;
1177
1178 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
1179 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1180 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1181 &vk_pipeline_info, &radv_pipeline_info,
1182 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_2d_pipeline);
1183 if (result != VK_SUCCESS)
1184 goto fail;
1185
1186 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
1187 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1188 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1189 &vk_pipeline_info, &radv_pipeline_info,
1190 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_3d_pipeline);
1191 if (result != VK_SUCCESS)
1192 goto fail;
1193
1194 fail:
1195 ralloc_free(fs_1d.nir);
1196 ralloc_free(fs_2d.nir);
1197 ralloc_free(fs_3d.nir);
1198 return result;
1199 }
1200
1201 VkResult
1202 radv_device_init_meta_blit_state(struct radv_device *device)
1203 {
1204 VkResult result;
1205 struct radv_shader_module vs = {0};
1206 zero(device->meta_state.blit);
1207
1208 VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1209 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1210 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1211 .bindingCount = 1,
1212 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1213 {
1214 .binding = 0,
1215 .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
1216 .descriptorCount = 1,
1217 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1218 .pImmutableSamplers = NULL
1219 },
1220 }
1221 };
1222 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1223 &ds_layout_info,
1224 &device->meta_state.alloc,
1225 &device->meta_state.blit.ds_layout);
1226 if (result != VK_SUCCESS)
1227 goto fail;
1228
1229 const VkPushConstantRange push_constant_range = {VK_SHADER_STAGE_VERTEX_BIT, 0, 20};
1230
1231 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1232 &(VkPipelineLayoutCreateInfo) {
1233 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1234 .setLayoutCount = 1,
1235 .pSetLayouts = &device->meta_state.blit.ds_layout,
1236 .pushConstantRangeCount = 1,
1237 .pPushConstantRanges = &push_constant_range,
1238 },
1239 &device->meta_state.alloc, &device->meta_state.blit.pipeline_layout);
1240 if (result != VK_SUCCESS)
1241 goto fail;
1242
1243 vs.nir = build_nir_vertex_shader();
1244
1245 result = radv_device_init_meta_blit_color(device, &vs);
1246 if (result != VK_SUCCESS)
1247 goto fail;
1248
1249 result = radv_device_init_meta_blit_depth(device, &vs);
1250 if (result != VK_SUCCESS)
1251 goto fail;
1252
1253 result = radv_device_init_meta_blit_stencil(device, &vs);
1254
1255 fail:
1256 ralloc_free(vs.nir);
1257 if (result != VK_SUCCESS)
1258 radv_device_finish_meta_blit_state(device);
1259 return result;
1260 }