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radv: move some image info into a separate struct.
[mesa.git] / src / amd / vulkan / radv_meta_blit.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_meta.h"
25 #include "nir/nir_builder.h"
26
27 struct blit_region {
28 VkOffset3D src_offset;
29 VkExtent3D src_extent;
30 VkOffset3D dest_offset;
31 VkExtent3D dest_extent;
32 };
33
34 static nir_shader *
35 build_nir_vertex_shader(void)
36 {
37 const struct glsl_type *vec4 = glsl_vec4_type();
38 nir_builder b;
39
40 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
41 b.shader->info->name = ralloc_strdup(b.shader, "meta_blit_vs");
42
43 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
44 vec4, "gl_Position");
45 pos_out->data.location = VARYING_SLOT_POS;
46
47 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
48 vec4, "a_tex_pos");
49 tex_pos_in->data.location = VERT_ATTRIB_GENERIC0;
50 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
51 vec4, "v_tex_pos");
52 tex_pos_out->data.location = VARYING_SLOT_VAR0;
53 tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
54 nir_copy_var(&b, tex_pos_out, tex_pos_in);
55
56 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
57
58 nir_store_var(&b, pos_out, outvec, 0xf);
59 return b.shader;
60 }
61
62 static nir_shader *
63 build_nir_copy_fragment_shader(enum glsl_sampler_dim tex_dim)
64 {
65 char shader_name[64];
66 const struct glsl_type *vec4 = glsl_vec4_type();
67 nir_builder b;
68
69 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
70
71 sprintf(shader_name, "meta_blit_fs.%d", tex_dim);
72 b.shader->info->name = ralloc_strdup(b.shader, shader_name);
73
74 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
75 vec4, "v_tex_pos");
76 tex_pos_in->data.location = VARYING_SLOT_VAR0;
77
78 /* Swizzle the array index which comes in as Z coordinate into the right
79 * position.
80 */
81 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
82 nir_ssa_def *const tex_pos =
83 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
84 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
85
86 const struct glsl_type *sampler_type =
87 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
88 glsl_get_base_type(vec4));
89 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
90 sampler_type, "s_tex");
91 sampler->data.descriptor_set = 0;
92 sampler->data.binding = 0;
93
94 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
95 tex->sampler_dim = tex_dim;
96 tex->op = nir_texop_tex;
97 tex->src[0].src_type = nir_tex_src_coord;
98 tex->src[0].src = nir_src_for_ssa(tex_pos);
99 tex->dest_type = nir_type_float; /* TODO */
100 tex->is_array = glsl_sampler_type_is_array(sampler_type);
101 tex->coord_components = tex_pos->num_components;
102 tex->texture = nir_deref_var_create(tex, sampler);
103 tex->sampler = nir_deref_var_create(tex, sampler);
104
105 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
106 nir_builder_instr_insert(&b, &tex->instr);
107
108 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
109 vec4, "f_color");
110 color_out->data.location = FRAG_RESULT_DATA0;
111 nir_store_var(&b, color_out, &tex->dest.ssa, 0xf);
112
113 return b.shader;
114 }
115
116 static nir_shader *
117 build_nir_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim)
118 {
119 char shader_name[64];
120 const struct glsl_type *vec4 = glsl_vec4_type();
121 nir_builder b;
122
123 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
124
125 sprintf(shader_name, "meta_blit_depth_fs.%d", tex_dim);
126 b.shader->info->name = ralloc_strdup(b.shader, shader_name);
127
128 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
129 vec4, "v_tex_pos");
130 tex_pos_in->data.location = VARYING_SLOT_VAR0;
131
132 /* Swizzle the array index which comes in as Z coordinate into the right
133 * position.
134 */
135 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
136 nir_ssa_def *const tex_pos =
137 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
138 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
139
140 const struct glsl_type *sampler_type =
141 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
142 glsl_get_base_type(vec4));
143 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
144 sampler_type, "s_tex");
145 sampler->data.descriptor_set = 0;
146 sampler->data.binding = 0;
147
148 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
149 tex->sampler_dim = tex_dim;
150 tex->op = nir_texop_tex;
151 tex->src[0].src_type = nir_tex_src_coord;
152 tex->src[0].src = nir_src_for_ssa(tex_pos);
153 tex->dest_type = nir_type_float; /* TODO */
154 tex->is_array = glsl_sampler_type_is_array(sampler_type);
155 tex->coord_components = tex_pos->num_components;
156 tex->texture = nir_deref_var_create(tex, sampler);
157 tex->sampler = nir_deref_var_create(tex, sampler);
158
159 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
160 nir_builder_instr_insert(&b, &tex->instr);
161
162 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
163 vec4, "f_color");
164 color_out->data.location = FRAG_RESULT_DEPTH;
165 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
166
167 return b.shader;
168 }
169
170 static nir_shader *
171 build_nir_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim)
172 {
173 char shader_name[64];
174 const struct glsl_type *vec4 = glsl_vec4_type();
175 nir_builder b;
176
177 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
178
179 sprintf(shader_name, "meta_blit_stencil_fs.%d", tex_dim);
180 b.shader->info->name = ralloc_strdup(b.shader, shader_name);
181
182 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
183 vec4, "v_tex_pos");
184 tex_pos_in->data.location = VARYING_SLOT_VAR0;
185
186 /* Swizzle the array index which comes in as Z coordinate into the right
187 * position.
188 */
189 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
190 nir_ssa_def *const tex_pos =
191 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
192 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
193
194 const struct glsl_type *sampler_type =
195 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
196 glsl_get_base_type(vec4));
197 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
198 sampler_type, "s_tex");
199 sampler->data.descriptor_set = 0;
200 sampler->data.binding = 0;
201
202 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
203 tex->sampler_dim = tex_dim;
204 tex->op = nir_texop_tex;
205 tex->src[0].src_type = nir_tex_src_coord;
206 tex->src[0].src = nir_src_for_ssa(tex_pos);
207 tex->dest_type = nir_type_float; /* TODO */
208 tex->is_array = glsl_sampler_type_is_array(sampler_type);
209 tex->coord_components = tex_pos->num_components;
210 tex->texture = nir_deref_var_create(tex, sampler);
211 tex->sampler = nir_deref_var_create(tex, sampler);
212
213 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
214 nir_builder_instr_insert(&b, &tex->instr);
215
216 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
217 vec4, "f_color");
218 color_out->data.location = FRAG_RESULT_STENCIL;
219 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
220
221 return b.shader;
222 }
223
224 static void
225 meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
226 struct radv_image *src_image,
227 struct radv_image_view *src_iview,
228 VkOffset3D src_offset_0,
229 VkOffset3D src_offset_1,
230 struct radv_image *dest_image,
231 struct radv_image_view *dest_iview,
232 VkOffset3D dest_offset_0,
233 VkOffset3D dest_offset_1,
234 VkRect2D dest_box,
235 VkFilter blit_filter)
236 {
237 struct radv_device *device = cmd_buffer->device;
238 unsigned offset = 0;
239 struct blit_vb_data {
240 float tex_coord[3];
241 } vb_data[3];
242
243 assert(src_image->info.samples == dest_image->info.samples);
244 unsigned vb_size = 3 * sizeof(*vb_data);
245 vb_data[0] = (struct blit_vb_data) {
246 .tex_coord = {
247 (float)src_offset_0.x / (float)src_iview->extent.width,
248 (float)src_offset_0.y / (float)src_iview->extent.height,
249 (float)src_offset_0.z / (float)src_iview->extent.depth,
250 },
251 };
252
253 vb_data[1] = (struct blit_vb_data) {
254 .tex_coord = {
255 (float)src_offset_0.x / (float)src_iview->extent.width,
256 (float)src_offset_1.y / (float)src_iview->extent.height,
257 (float)src_offset_0.z / (float)src_iview->extent.depth,
258 },
259 };
260
261 vb_data[2] = (struct blit_vb_data) {
262 .tex_coord = {
263 (float)src_offset_1.x / (float)src_iview->extent.width,
264 (float)src_offset_0.y / (float)src_iview->extent.height,
265 (float)src_offset_0.z / (float)src_iview->extent.depth,
266 },
267 };
268 radv_cmd_buffer_upload_data(cmd_buffer, vb_size, 16, vb_data, &offset);
269
270 struct radv_buffer vertex_buffer = {
271 .device = device,
272 .size = vb_size,
273 .bo = cmd_buffer->upload.upload_bo,
274 .offset = offset,
275 };
276
277 radv_CmdBindVertexBuffers(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
278 (VkBuffer[]) {
279 radv_buffer_to_handle(&vertex_buffer)
280 },
281 (VkDeviceSize[]) {
282 0,
283 });
284
285 VkSampler sampler;
286 radv_CreateSampler(radv_device_to_handle(device),
287 &(VkSamplerCreateInfo) {
288 .sType = VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO,
289 .magFilter = blit_filter,
290 .minFilter = blit_filter,
291 .addressModeU = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
292 .addressModeV = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
293 .addressModeW = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
294 }, &cmd_buffer->pool->alloc, &sampler);
295
296 VkFramebuffer fb;
297 radv_CreateFramebuffer(radv_device_to_handle(device),
298 &(VkFramebufferCreateInfo) {
299 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
300 .attachmentCount = 1,
301 .pAttachments = (VkImageView[]) {
302 radv_image_view_to_handle(dest_iview),
303 },
304 .width = dest_iview->extent.width,
305 .height = dest_iview->extent.height,
306 .layers = 1,
307 }, &cmd_buffer->pool->alloc, &fb);
308 VkPipeline pipeline;
309 switch (src_iview->aspect_mask) {
310 case VK_IMAGE_ASPECT_COLOR_BIT: {
311 unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format);
312
313 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
314 &(VkRenderPassBeginInfo) {
315 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
316 .renderPass = device->meta_state.blit.render_pass[fs_key],
317 .framebuffer = fb,
318 .renderArea = {
319 .offset = { dest_box.offset.x, dest_box.offset.y },
320 .extent = { dest_box.extent.width, dest_box.extent.height },
321 },
322 .clearValueCount = 0,
323 .pClearValues = NULL,
324 }, VK_SUBPASS_CONTENTS_INLINE);
325 switch (src_image->type) {
326 case VK_IMAGE_TYPE_1D:
327 pipeline = device->meta_state.blit.pipeline_1d_src[fs_key];
328 break;
329 case VK_IMAGE_TYPE_2D:
330 pipeline = device->meta_state.blit.pipeline_2d_src[fs_key];
331 break;
332 case VK_IMAGE_TYPE_3D:
333 pipeline = device->meta_state.blit.pipeline_3d_src[fs_key];
334 break;
335 default:
336 unreachable(!"bad VkImageType");
337 }
338 break;
339 }
340 case VK_IMAGE_ASPECT_DEPTH_BIT:
341 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
342 &(VkRenderPassBeginInfo) {
343 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
344 .renderPass = device->meta_state.blit.depth_only_rp,
345 .framebuffer = fb,
346 .renderArea = {
347 .offset = { dest_box.offset.x, dest_box.offset.y },
348 .extent = { dest_box.extent.width, dest_box.extent.height },
349 },
350 .clearValueCount = 0,
351 .pClearValues = NULL,
352 }, VK_SUBPASS_CONTENTS_INLINE);
353 switch (src_image->type) {
354 case VK_IMAGE_TYPE_1D:
355 pipeline = device->meta_state.blit.depth_only_1d_pipeline;
356 break;
357 case VK_IMAGE_TYPE_2D:
358 pipeline = device->meta_state.blit.depth_only_2d_pipeline;
359 break;
360 case VK_IMAGE_TYPE_3D:
361 pipeline = device->meta_state.blit.depth_only_3d_pipeline;
362 break;
363 default:
364 unreachable(!"bad VkImageType");
365 }
366 break;
367 case VK_IMAGE_ASPECT_STENCIL_BIT:
368 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
369 &(VkRenderPassBeginInfo) {
370 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
371 .renderPass = device->meta_state.blit.stencil_only_rp,
372 .framebuffer = fb,
373 .renderArea = {
374 .offset = { dest_box.offset.x, dest_box.offset.y },
375 .extent = { dest_box.extent.width, dest_box.extent.height },
376 },
377 .clearValueCount = 0,
378 .pClearValues = NULL,
379 }, VK_SUBPASS_CONTENTS_INLINE);
380 switch (src_image->type) {
381 case VK_IMAGE_TYPE_1D:
382 pipeline = device->meta_state.blit.stencil_only_1d_pipeline;
383 break;
384 case VK_IMAGE_TYPE_2D:
385 pipeline = device->meta_state.blit.stencil_only_2d_pipeline;
386 break;
387 case VK_IMAGE_TYPE_3D:
388 pipeline = device->meta_state.blit.stencil_only_3d_pipeline;
389 break;
390 default:
391 unreachable(!"bad VkImageType");
392 }
393 break;
394 default:
395 unreachable(!"bad VkImageType");
396 }
397
398 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
399 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
400 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
401 }
402
403 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
404 device->meta_state.blit.pipeline_layout,
405 0, /* set */
406 1, /* descriptorWriteCount */
407 (VkWriteDescriptorSet[]) {
408 {
409 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
410 .dstBinding = 0,
411 .dstArrayElement = 0,
412 .descriptorCount = 1,
413 .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
414 .pImageInfo = (VkDescriptorImageInfo[]) {
415 {
416 .sampler = sampler,
417 .imageView = radv_image_view_to_handle(src_iview),
418 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
419 },
420 }
421 }
422 });
423
424 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
425 .x = dest_offset_0.x,
426 .y = dest_offset_0.y,
427 .width = dest_offset_1.x - dest_offset_0.x,
428 .height = dest_offset_1.y - dest_offset_0.y,
429 .minDepth = 0.0f,
430 .maxDepth = 1.0f
431 });
432
433 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
434 .offset = (VkOffset2D) { MIN2(dest_offset_0.x, dest_offset_1.x), MIN2(dest_offset_0.y, dest_offset_1.y) },
435 .extent = (VkExtent2D) {
436 abs(dest_offset_1.x - dest_offset_0.x),
437 abs(dest_offset_1.y - dest_offset_0.y)
438 },
439 });
440
441 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
442
443 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
444
445 /* At the point where we emit the draw call, all data from the
446 * descriptor sets, etc. has been used. We are free to delete it.
447 */
448 /* TODO: above comment is not valid for at least descriptor sets/pools,
449 * as we may not free them till after execution finishes. Check others. */
450
451 radv_DestroySampler(radv_device_to_handle(device), sampler,
452 &cmd_buffer->pool->alloc);
453 radv_DestroyFramebuffer(radv_device_to_handle(device), fb,
454 &cmd_buffer->pool->alloc);
455 }
456
457 static bool
458 flip_coords(unsigned *src0, unsigned *src1, unsigned *dst0, unsigned *dst1)
459 {
460 bool flip = false;
461 if (*src0 > *src1) {
462 unsigned tmp = *src0;
463 *src0 = *src1;
464 *src1 = tmp;
465 flip = !flip;
466 }
467
468 if (*dst0 > *dst1) {
469 unsigned tmp = *dst0;
470 *dst0 = *dst1;
471 *dst1 = tmp;
472 flip = !flip;
473 }
474 return flip;
475 }
476
477 void radv_CmdBlitImage(
478 VkCommandBuffer commandBuffer,
479 VkImage srcImage,
480 VkImageLayout srcImageLayout,
481 VkImage destImage,
482 VkImageLayout destImageLayout,
483 uint32_t regionCount,
484 const VkImageBlit* pRegions,
485 VkFilter filter)
486
487 {
488 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
489 RADV_FROM_HANDLE(radv_image, src_image, srcImage);
490 RADV_FROM_HANDLE(radv_image, dest_image, destImage);
491 struct radv_meta_saved_state saved_state;
492
493 /* From the Vulkan 1.0 spec:
494 *
495 * vkCmdBlitImage must not be used for multisampled source or
496 * destination images. Use vkCmdResolveImage for this purpose.
497 */
498 assert(src_image->info.samples == 1);
499 assert(dest_image->info.samples == 1);
500
501 radv_meta_save_graphics_reset_vport_scissor(&saved_state, cmd_buffer);
502
503 for (unsigned r = 0; r < regionCount; r++) {
504 const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
505 const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;
506 struct radv_image_view src_iview;
507 radv_image_view_init(&src_iview, cmd_buffer->device,
508 &(VkImageViewCreateInfo) {
509 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
510 .image = srcImage,
511 .viewType = radv_meta_get_view_type(src_image),
512 .format = src_image->vk_format,
513 .subresourceRange = {
514 .aspectMask = src_res->aspectMask,
515 .baseMipLevel = src_res->mipLevel,
516 .levelCount = 1,
517 .baseArrayLayer = src_res->baseArrayLayer,
518 .layerCount = 1
519 },
520 },
521 cmd_buffer, VK_IMAGE_USAGE_SAMPLED_BIT);
522
523 unsigned dst_start, dst_end;
524 if (dest_image->type == VK_IMAGE_TYPE_3D) {
525 assert(dst_res->baseArrayLayer == 0);
526 dst_start = pRegions[r].dstOffsets[0].z;
527 dst_end = pRegions[r].dstOffsets[1].z;
528 } else {
529 dst_start = dst_res->baseArrayLayer;
530 dst_end = dst_start + dst_res->layerCount;
531 }
532
533 unsigned src_start, src_end;
534 if (src_image->type == VK_IMAGE_TYPE_3D) {
535 assert(src_res->baseArrayLayer == 0);
536 src_start = pRegions[r].srcOffsets[0].z;
537 src_end = pRegions[r].srcOffsets[1].z;
538 } else {
539 src_start = src_res->baseArrayLayer;
540 src_end = src_start + src_res->layerCount;
541 }
542
543 bool flip_z = flip_coords(&src_start, &src_end, &dst_start, &dst_end);
544 float src_z_step = (float)(src_end + 1 - src_start) /
545 (float)(dst_end + 1 - dst_start);
546
547 if (flip_z) {
548 src_start = src_end;
549 src_z_step *= -1;
550 }
551
552 unsigned src_x0 = pRegions[r].srcOffsets[0].x;
553 unsigned src_x1 = pRegions[r].srcOffsets[1].x;
554 unsigned dst_x0 = pRegions[r].dstOffsets[0].x;
555 unsigned dst_x1 = pRegions[r].dstOffsets[1].x;
556
557 unsigned src_y0 = pRegions[r].srcOffsets[0].y;
558 unsigned src_y1 = pRegions[r].srcOffsets[1].y;
559 unsigned dst_y0 = pRegions[r].dstOffsets[0].y;
560 unsigned dst_y1 = pRegions[r].dstOffsets[1].y;
561
562 VkRect2D dest_box;
563 dest_box.offset.x = MIN2(dst_x0, dst_x1);
564 dest_box.offset.y = MIN2(dst_y0, dst_y1);
565 dest_box.extent.width = abs(dst_x1 - dst_x0);
566 dest_box.extent.height = abs(dst_y1 - dst_y0);
567
568 struct radv_image_view dest_iview;
569 unsigned usage;
570 if (dst_res->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT)
571 usage = VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
572 else
573 usage = VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT;
574
575 const unsigned num_layers = dst_end - dst_start;
576 for (unsigned i = 0; i < num_layers; i++) {
577 const VkOffset3D dest_offset_0 = {
578 .x = dst_x0,
579 .y = dst_y0,
580 .z = dst_start + i ,
581 };
582 const VkOffset3D dest_offset_1 = {
583 .x = dst_x1,
584 .y = dst_y1,
585 .z = dst_start + i ,
586 };
587 VkOffset3D src_offset_0 = {
588 .x = src_x0,
589 .y = src_y0,
590 .z = src_start + i * src_z_step,
591 };
592 VkOffset3D src_offset_1 = {
593 .x = src_x1,
594 .y = src_y1,
595 .z = src_start + i * src_z_step,
596 };
597 const uint32_t dest_array_slice =
598 radv_meta_get_iview_layer(dest_image, dst_res,
599 &dest_offset_0);
600
601 radv_image_view_init(&dest_iview, cmd_buffer->device,
602 &(VkImageViewCreateInfo) {
603 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
604 .image = destImage,
605 .viewType = radv_meta_get_view_type(dest_image),
606 .format = dest_image->vk_format,
607 .subresourceRange = {
608 .aspectMask = dst_res->aspectMask,
609 .baseMipLevel = dst_res->mipLevel,
610 .levelCount = 1,
611 .baseArrayLayer = dest_array_slice,
612 .layerCount = 1
613 },
614 },
615 cmd_buffer, usage);
616 meta_emit_blit(cmd_buffer,
617 src_image, &src_iview,
618 src_offset_0, src_offset_1,
619 dest_image, &dest_iview,
620 dest_offset_0, dest_offset_1,
621 dest_box,
622 filter);
623 }
624 }
625
626 radv_meta_restore(&saved_state, cmd_buffer);
627 }
628
629 void
630 radv_device_finish_meta_blit_state(struct radv_device *device)
631 {
632 for (unsigned i = 0; i < NUM_META_FS_KEYS; ++i) {
633 if (device->meta_state.blit.render_pass[i])
634 radv_DestroyRenderPass(radv_device_to_handle(device),
635 device->meta_state.blit.render_pass[i],
636 &device->meta_state.alloc);
637 if (device->meta_state.blit.pipeline_1d_src[i])
638 radv_DestroyPipeline(radv_device_to_handle(device),
639 device->meta_state.blit.pipeline_1d_src[i],
640 &device->meta_state.alloc);
641 if (device->meta_state.blit.pipeline_2d_src[i])
642 radv_DestroyPipeline(radv_device_to_handle(device),
643 device->meta_state.blit.pipeline_2d_src[i],
644 &device->meta_state.alloc);
645 if (device->meta_state.blit.pipeline_3d_src[i])
646 radv_DestroyPipeline(radv_device_to_handle(device),
647 device->meta_state.blit.pipeline_3d_src[i],
648 &device->meta_state.alloc);
649 }
650
651 if (device->meta_state.blit.depth_only_rp)
652 radv_DestroyRenderPass(radv_device_to_handle(device),
653 device->meta_state.blit.depth_only_rp,
654 &device->meta_state.alloc);
655 if (device->meta_state.blit.depth_only_1d_pipeline)
656 radv_DestroyPipeline(radv_device_to_handle(device),
657 device->meta_state.blit.depth_only_1d_pipeline,
658 &device->meta_state.alloc);
659 if (device->meta_state.blit.depth_only_2d_pipeline)
660 radv_DestroyPipeline(radv_device_to_handle(device),
661 device->meta_state.blit.depth_only_2d_pipeline,
662 &device->meta_state.alloc);
663 if (device->meta_state.blit.depth_only_3d_pipeline)
664 radv_DestroyPipeline(radv_device_to_handle(device),
665 device->meta_state.blit.depth_only_3d_pipeline,
666 &device->meta_state.alloc);
667 if (device->meta_state.blit.stencil_only_rp)
668 radv_DestroyRenderPass(radv_device_to_handle(device),
669 device->meta_state.blit.stencil_only_rp,
670 &device->meta_state.alloc);
671 if (device->meta_state.blit.stencil_only_1d_pipeline)
672 radv_DestroyPipeline(radv_device_to_handle(device),
673 device->meta_state.blit.stencil_only_1d_pipeline,
674 &device->meta_state.alloc);
675 if (device->meta_state.blit.stencil_only_2d_pipeline)
676 radv_DestroyPipeline(radv_device_to_handle(device),
677 device->meta_state.blit.stencil_only_2d_pipeline,
678 &device->meta_state.alloc);
679 if (device->meta_state.blit.stencil_only_3d_pipeline)
680 radv_DestroyPipeline(radv_device_to_handle(device),
681 device->meta_state.blit.stencil_only_3d_pipeline,
682 &device->meta_state.alloc);
683 if (device->meta_state.blit.pipeline_layout)
684 radv_DestroyPipelineLayout(radv_device_to_handle(device),
685 device->meta_state.blit.pipeline_layout,
686 &device->meta_state.alloc);
687 if (device->meta_state.blit.ds_layout)
688 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
689 device->meta_state.blit.ds_layout,
690 &device->meta_state.alloc);
691 }
692
693 static VkFormat pipeline_formats[] = {
694 VK_FORMAT_R8G8B8A8_UNORM,
695 VK_FORMAT_R8G8B8A8_UINT,
696 VK_FORMAT_R8G8B8A8_SINT,
697 VK_FORMAT_R16G16B16A16_UNORM,
698 VK_FORMAT_R16G16B16A16_SNORM,
699 VK_FORMAT_R16G16B16A16_UINT,
700 VK_FORMAT_R16G16B16A16_SINT,
701 VK_FORMAT_R32_SFLOAT,
702 VK_FORMAT_R32G32_SFLOAT,
703 VK_FORMAT_R32G32B32A32_SFLOAT
704 };
705
706 static VkResult
707 radv_device_init_meta_blit_color(struct radv_device *device,
708 struct radv_shader_module *vs)
709 {
710 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
711 VkResult result;
712
713 fs_1d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_1D);
714 fs_2d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_2D);
715 fs_3d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_3D);
716
717 for (unsigned i = 0; i < ARRAY_SIZE(pipeline_formats); ++i) {
718 unsigned key = radv_format_meta_fs_key(pipeline_formats[i]);
719 result = radv_CreateRenderPass(radv_device_to_handle(device),
720 &(VkRenderPassCreateInfo) {
721 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
722 .attachmentCount = 1,
723 .pAttachments = &(VkAttachmentDescription) {
724 .format = pipeline_formats[i],
725 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
726 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
727 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
728 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
729 },
730 .subpassCount = 1,
731 .pSubpasses = &(VkSubpassDescription) {
732 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
733 .inputAttachmentCount = 0,
734 .colorAttachmentCount = 1,
735 .pColorAttachments = &(VkAttachmentReference) {
736 .attachment = 0,
737 .layout = VK_IMAGE_LAYOUT_GENERAL,
738 },
739 .pResolveAttachments = NULL,
740 .pDepthStencilAttachment = &(VkAttachmentReference) {
741 .attachment = VK_ATTACHMENT_UNUSED,
742 .layout = VK_IMAGE_LAYOUT_GENERAL,
743 },
744 .preserveAttachmentCount = 1,
745 .pPreserveAttachments = (uint32_t[]) { 0 },
746 },
747 .dependencyCount = 0,
748 }, &device->meta_state.alloc, &device->meta_state.blit.render_pass[key]);
749 if (result != VK_SUCCESS)
750 goto fail;
751
752 VkPipelineVertexInputStateCreateInfo vi_create_info = {
753 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
754 .vertexBindingDescriptionCount = 1,
755 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
756 {
757 .binding = 0,
758 .stride = 3 * sizeof(float),
759 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
760 },
761 },
762 .vertexAttributeDescriptionCount = 1,
763 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
764 {
765 /* Texture Coordinate */
766 .location = 0,
767 .binding = 0,
768 .format = VK_FORMAT_R32G32B32_SFLOAT,
769 .offset = 0
770 }
771 }
772 };
773
774 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
775 {
776 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
777 .stage = VK_SHADER_STAGE_VERTEX_BIT,
778 .module = radv_shader_module_to_handle(vs),
779 .pName = "main",
780 .pSpecializationInfo = NULL
781 }, {
782 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
783 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
784 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
785 .pName = "main",
786 .pSpecializationInfo = NULL
787 },
788 };
789
790 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
791 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
792 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
793 .pStages = pipeline_shader_stages,
794 .pVertexInputState = &vi_create_info,
795 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
796 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
797 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
798 .primitiveRestartEnable = false,
799 },
800 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
801 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
802 .viewportCount = 1,
803 .scissorCount = 1,
804 },
805 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
806 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
807 .rasterizerDiscardEnable = false,
808 .polygonMode = VK_POLYGON_MODE_FILL,
809 .cullMode = VK_CULL_MODE_NONE,
810 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
811 },
812 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
813 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
814 .rasterizationSamples = 1,
815 .sampleShadingEnable = false,
816 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
817 },
818 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
819 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
820 .attachmentCount = 1,
821 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
822 { .colorWriteMask =
823 VK_COLOR_COMPONENT_A_BIT |
824 VK_COLOR_COMPONENT_R_BIT |
825 VK_COLOR_COMPONENT_G_BIT |
826 VK_COLOR_COMPONENT_B_BIT },
827 }
828 },
829 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
830 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
831 .dynamicStateCount = 4,
832 .pDynamicStates = (VkDynamicState[]) {
833 VK_DYNAMIC_STATE_VIEWPORT,
834 VK_DYNAMIC_STATE_SCISSOR,
835 VK_DYNAMIC_STATE_LINE_WIDTH,
836 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
837 },
838 },
839 .flags = 0,
840 .layout = device->meta_state.blit.pipeline_layout,
841 .renderPass = device->meta_state.blit.render_pass[key],
842 .subpass = 0,
843 };
844
845 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
846 .use_rectlist = true
847 };
848
849 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
850 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
851 radv_pipeline_cache_to_handle(&device->meta_state.cache),
852 &vk_pipeline_info, &radv_pipeline_info,
853 &device->meta_state.alloc, &device->meta_state.blit.pipeline_1d_src[key]);
854 if (result != VK_SUCCESS)
855 goto fail;
856
857 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
858 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
859 radv_pipeline_cache_to_handle(&device->meta_state.cache),
860 &vk_pipeline_info, &radv_pipeline_info,
861 &device->meta_state.alloc, &device->meta_state.blit.pipeline_2d_src[key]);
862 if (result != VK_SUCCESS)
863 goto fail;
864
865 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
866 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
867 radv_pipeline_cache_to_handle(&device->meta_state.cache),
868 &vk_pipeline_info, &radv_pipeline_info,
869 &device->meta_state.alloc, &device->meta_state.blit.pipeline_3d_src[key]);
870 if (result != VK_SUCCESS)
871 goto fail;
872
873 }
874
875 result = VK_SUCCESS;
876 fail:
877 ralloc_free(fs_1d.nir);
878 ralloc_free(fs_2d.nir);
879 ralloc_free(fs_3d.nir);
880 return result;
881 }
882
883 static VkResult
884 radv_device_init_meta_blit_depth(struct radv_device *device,
885 struct radv_shader_module *vs)
886 {
887 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
888 VkResult result;
889
890 fs_1d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_1D);
891 fs_2d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_2D);
892 fs_3d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_3D);
893
894 result = radv_CreateRenderPass(radv_device_to_handle(device),
895 &(VkRenderPassCreateInfo) {
896 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
897 .attachmentCount = 1,
898 .pAttachments = &(VkAttachmentDescription) {
899 .format = 0,
900 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
901 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
902 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
903 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
904 },
905 .subpassCount = 1,
906 .pSubpasses = &(VkSubpassDescription) {
907 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
908 .inputAttachmentCount = 0,
909 .colorAttachmentCount = 0,
910 .pColorAttachments = NULL,
911 .pResolveAttachments = NULL,
912 .pDepthStencilAttachment = &(VkAttachmentReference) {
913 .attachment = 0,
914 .layout = VK_IMAGE_LAYOUT_GENERAL,
915 },
916 .preserveAttachmentCount = 1,
917 .pPreserveAttachments = (uint32_t[]) { 0 },
918 },
919 .dependencyCount = 0,
920 }, &device->meta_state.alloc, &device->meta_state.blit.depth_only_rp);
921 if (result != VK_SUCCESS)
922 goto fail;
923
924 VkPipelineVertexInputStateCreateInfo vi_create_info = {
925 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
926 .vertexBindingDescriptionCount = 1,
927 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
928 {
929 .binding = 0,
930 .stride = 3 * sizeof(float),
931 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
932 },
933 },
934 .vertexAttributeDescriptionCount = 1,
935 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
936 {
937 /* Texture Coordinate */
938 .location = 0,
939 .binding = 0,
940 .format = VK_FORMAT_R32G32B32_SFLOAT,
941 .offset = 0,
942 }
943 }
944 };
945
946 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
947 {
948 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
949 .stage = VK_SHADER_STAGE_VERTEX_BIT,
950 .module = radv_shader_module_to_handle(vs),
951 .pName = "main",
952 .pSpecializationInfo = NULL
953 }, {
954 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
955 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
956 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
957 .pName = "main",
958 .pSpecializationInfo = NULL
959 },
960 };
961
962 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
963 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
964 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
965 .pStages = pipeline_shader_stages,
966 .pVertexInputState = &vi_create_info,
967 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
968 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
969 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
970 .primitiveRestartEnable = false,
971 },
972 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
973 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
974 .viewportCount = 1,
975 .scissorCount = 1,
976 },
977 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
978 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
979 .rasterizerDiscardEnable = false,
980 .polygonMode = VK_POLYGON_MODE_FILL,
981 .cullMode = VK_CULL_MODE_NONE,
982 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
983 },
984 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
985 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
986 .rasterizationSamples = 1,
987 .sampleShadingEnable = false,
988 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
989 },
990 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
991 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
992 .attachmentCount = 0,
993 .pAttachments = NULL,
994 },
995 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
996 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
997 .depthTestEnable = true,
998 .depthWriteEnable = true,
999 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
1000 },
1001 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1002 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1003 .dynamicStateCount = 9,
1004 .pDynamicStates = (VkDynamicState[]) {
1005 VK_DYNAMIC_STATE_VIEWPORT,
1006 VK_DYNAMIC_STATE_SCISSOR,
1007 VK_DYNAMIC_STATE_LINE_WIDTH,
1008 VK_DYNAMIC_STATE_DEPTH_BIAS,
1009 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1010 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1011 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
1012 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
1013 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
1014 },
1015 },
1016 .flags = 0,
1017 .layout = device->meta_state.blit.pipeline_layout,
1018 .renderPass = device->meta_state.blit.depth_only_rp,
1019 .subpass = 0,
1020 };
1021
1022 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1023 .use_rectlist = true
1024 };
1025
1026 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
1027 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1028 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1029 &vk_pipeline_info, &radv_pipeline_info,
1030 &device->meta_state.alloc, &device->meta_state.blit.depth_only_1d_pipeline);
1031 if (result != VK_SUCCESS)
1032 goto fail;
1033
1034 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
1035 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1036 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1037 &vk_pipeline_info, &radv_pipeline_info,
1038 &device->meta_state.alloc, &device->meta_state.blit.depth_only_2d_pipeline);
1039 if (result != VK_SUCCESS)
1040 goto fail;
1041
1042 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
1043 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1044 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1045 &vk_pipeline_info, &radv_pipeline_info,
1046 &device->meta_state.alloc, &device->meta_state.blit.depth_only_3d_pipeline);
1047 if (result != VK_SUCCESS)
1048 goto fail;
1049
1050 fail:
1051 ralloc_free(fs_1d.nir);
1052 ralloc_free(fs_2d.nir);
1053 ralloc_free(fs_3d.nir);
1054 return result;
1055 }
1056
1057 static VkResult
1058 radv_device_init_meta_blit_stencil(struct radv_device *device,
1059 struct radv_shader_module *vs)
1060 {
1061 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
1062 VkResult result;
1063
1064 fs_1d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_1D);
1065 fs_2d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_2D);
1066 fs_3d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_3D);
1067
1068 result = radv_CreateRenderPass(radv_device_to_handle(device),
1069 &(VkRenderPassCreateInfo) {
1070 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1071 .attachmentCount = 1,
1072 .pAttachments = &(VkAttachmentDescription) {
1073 .format = 0,
1074 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1075 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1076 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
1077 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
1078 },
1079 .subpassCount = 1,
1080 .pSubpasses = &(VkSubpassDescription) {
1081 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1082 .inputAttachmentCount = 0,
1083 .colorAttachmentCount = 0,
1084 .pColorAttachments = NULL,
1085 .pResolveAttachments = NULL,
1086 .pDepthStencilAttachment = &(VkAttachmentReference) {
1087 .attachment = 0,
1088 .layout = VK_IMAGE_LAYOUT_GENERAL,
1089 },
1090 .preserveAttachmentCount = 1,
1091 .pPreserveAttachments = (uint32_t[]) { 0 },
1092 },
1093 .dependencyCount = 0,
1094 }, &device->meta_state.alloc, &device->meta_state.blit.stencil_only_rp);
1095 if (result != VK_SUCCESS)
1096 goto fail;
1097
1098 VkPipelineVertexInputStateCreateInfo vi_create_info = {
1099 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
1100 .vertexBindingDescriptionCount = 1,
1101 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
1102 {
1103 .binding = 0,
1104 .stride = 3 * sizeof(float),
1105 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
1106 },
1107 },
1108 .vertexAttributeDescriptionCount = 1,
1109 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
1110 {
1111 /* Texture Coordinate */
1112 .location = 0,
1113 .binding = 0,
1114 .format = VK_FORMAT_R32G32B32_SFLOAT,
1115 .offset = 0
1116 }
1117 }
1118 };
1119
1120 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
1121 {
1122 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1123 .stage = VK_SHADER_STAGE_VERTEX_BIT,
1124 .module = radv_shader_module_to_handle(vs),
1125 .pName = "main",
1126 .pSpecializationInfo = NULL
1127 }, {
1128 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1129 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
1130 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
1131 .pName = "main",
1132 .pSpecializationInfo = NULL
1133 },
1134 };
1135
1136 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1137 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1138 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
1139 .pStages = pipeline_shader_stages,
1140 .pVertexInputState = &vi_create_info,
1141 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1142 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1143 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1144 .primitiveRestartEnable = false,
1145 },
1146 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
1147 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1148 .viewportCount = 1,
1149 .scissorCount = 1,
1150 },
1151 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1152 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1153 .rasterizerDiscardEnable = false,
1154 .polygonMode = VK_POLYGON_MODE_FILL,
1155 .cullMode = VK_CULL_MODE_NONE,
1156 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1157 },
1158 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1159 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1160 .rasterizationSamples = 1,
1161 .sampleShadingEnable = false,
1162 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1163 },
1164 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1165 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1166 .attachmentCount = 0,
1167 .pAttachments = NULL,
1168 },
1169 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1170 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1171 .depthTestEnable = false,
1172 .depthWriteEnable = false,
1173 .stencilTestEnable = true,
1174 .front = {
1175 .failOp = VK_STENCIL_OP_REPLACE,
1176 .passOp = VK_STENCIL_OP_REPLACE,
1177 .depthFailOp = VK_STENCIL_OP_REPLACE,
1178 .compareOp = VK_COMPARE_OP_ALWAYS,
1179 .compareMask = 0xff,
1180 .writeMask = 0xff,
1181 .reference = 0
1182 },
1183 .back = {
1184 .failOp = VK_STENCIL_OP_REPLACE,
1185 .passOp = VK_STENCIL_OP_REPLACE,
1186 .depthFailOp = VK_STENCIL_OP_REPLACE,
1187 .compareOp = VK_COMPARE_OP_ALWAYS,
1188 .compareMask = 0xff,
1189 .writeMask = 0xff,
1190 .reference = 0
1191 },
1192 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
1193 },
1194
1195 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1196 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1197 .dynamicStateCount = 6,
1198 .pDynamicStates = (VkDynamicState[]) {
1199 VK_DYNAMIC_STATE_VIEWPORT,
1200 VK_DYNAMIC_STATE_SCISSOR,
1201 VK_DYNAMIC_STATE_LINE_WIDTH,
1202 VK_DYNAMIC_STATE_DEPTH_BIAS,
1203 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1204 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1205 },
1206 },
1207 .flags = 0,
1208 .layout = device->meta_state.blit.pipeline_layout,
1209 .renderPass = device->meta_state.blit.stencil_only_rp,
1210 .subpass = 0,
1211 };
1212
1213 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1214 .use_rectlist = true
1215 };
1216
1217 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
1218 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1219 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1220 &vk_pipeline_info, &radv_pipeline_info,
1221 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_1d_pipeline);
1222 if (result != VK_SUCCESS)
1223 goto fail;
1224
1225 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
1226 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1227 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1228 &vk_pipeline_info, &radv_pipeline_info,
1229 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_2d_pipeline);
1230 if (result != VK_SUCCESS)
1231 goto fail;
1232
1233 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
1234 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1235 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1236 &vk_pipeline_info, &radv_pipeline_info,
1237 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_3d_pipeline);
1238 if (result != VK_SUCCESS)
1239 goto fail;
1240
1241 fail:
1242 ralloc_free(fs_1d.nir);
1243 ralloc_free(fs_2d.nir);
1244 ralloc_free(fs_3d.nir);
1245 return result;
1246 }
1247
1248 VkResult
1249 radv_device_init_meta_blit_state(struct radv_device *device)
1250 {
1251 VkResult result;
1252 struct radv_shader_module vs = {0};
1253 zero(device->meta_state.blit);
1254
1255 VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1256 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1257 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1258 .bindingCount = 1,
1259 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1260 {
1261 .binding = 0,
1262 .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
1263 .descriptorCount = 1,
1264 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1265 .pImmutableSamplers = NULL
1266 },
1267 }
1268 };
1269 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1270 &ds_layout_info,
1271 &device->meta_state.alloc,
1272 &device->meta_state.blit.ds_layout);
1273 if (result != VK_SUCCESS)
1274 goto fail;
1275
1276 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1277 &(VkPipelineLayoutCreateInfo) {
1278 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1279 .setLayoutCount = 1,
1280 .pSetLayouts = &device->meta_state.blit.ds_layout,
1281 },
1282 &device->meta_state.alloc, &device->meta_state.blit.pipeline_layout);
1283 if (result != VK_SUCCESS)
1284 goto fail;
1285
1286 vs.nir = build_nir_vertex_shader();
1287
1288 result = radv_device_init_meta_blit_color(device, &vs);
1289 if (result != VK_SUCCESS)
1290 goto fail;
1291
1292 result = radv_device_init_meta_blit_depth(device, &vs);
1293 if (result != VK_SUCCESS)
1294 goto fail;
1295
1296 result = radv_device_init_meta_blit_stencil(device, &vs);
1297 if (result != VK_SUCCESS)
1298 goto fail;
1299 return VK_SUCCESS;
1300
1301 fail:
1302 ralloc_free(vs.nir);
1303 radv_device_finish_meta_blit_state(device);
1304 return result;
1305 }