radv/meta: just local vars for src/dst subresources.
[mesa.git] / src / amd / vulkan / radv_meta_blit.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_meta.h"
25 #include "nir/nir_builder.h"
26
27 struct blit_region {
28 VkOffset3D src_offset;
29 VkExtent3D src_extent;
30 VkOffset3D dest_offset;
31 VkExtent3D dest_extent;
32 };
33
34 static nir_shader *
35 build_nir_vertex_shader(void)
36 {
37 const struct glsl_type *vec4 = glsl_vec4_type();
38 nir_builder b;
39
40 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
41 b.shader->info->name = ralloc_strdup(b.shader, "meta_blit_vs");
42
43 nir_variable *pos_in = nir_variable_create(b.shader, nir_var_shader_in,
44 vec4, "a_pos");
45 pos_in->data.location = VERT_ATTRIB_GENERIC0;
46 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
47 vec4, "gl_Position");
48 pos_out->data.location = VARYING_SLOT_POS;
49 nir_copy_var(&b, pos_out, pos_in);
50
51 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
52 vec4, "a_tex_pos");
53 tex_pos_in->data.location = VERT_ATTRIB_GENERIC1;
54 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
55 vec4, "v_tex_pos");
56 tex_pos_out->data.location = VARYING_SLOT_VAR0;
57 tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
58 nir_copy_var(&b, tex_pos_out, tex_pos_in);
59
60 return b.shader;
61 }
62
63 static nir_shader *
64 build_nir_copy_fragment_shader(enum glsl_sampler_dim tex_dim)
65 {
66 char shader_name[64];
67 const struct glsl_type *vec4 = glsl_vec4_type();
68 nir_builder b;
69
70 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
71
72 sprintf(shader_name, "meta_blit_fs.%d", tex_dim);
73 b.shader->info->name = ralloc_strdup(b.shader, shader_name);
74
75 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
76 vec4, "v_tex_pos");
77 tex_pos_in->data.location = VARYING_SLOT_VAR0;
78
79 /* Swizzle the array index which comes in as Z coordinate into the right
80 * position.
81 */
82 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
83 nir_ssa_def *const tex_pos =
84 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
85 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
86
87 const struct glsl_type *sampler_type =
88 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
89 glsl_get_base_type(vec4));
90 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
91 sampler_type, "s_tex");
92 sampler->data.descriptor_set = 0;
93 sampler->data.binding = 0;
94
95 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
96 tex->sampler_dim = tex_dim;
97 tex->op = nir_texop_tex;
98 tex->src[0].src_type = nir_tex_src_coord;
99 tex->src[0].src = nir_src_for_ssa(tex_pos);
100 tex->dest_type = nir_type_float; /* TODO */
101 tex->is_array = glsl_sampler_type_is_array(sampler_type);
102 tex->coord_components = tex_pos->num_components;
103 tex->texture = nir_deref_var_create(tex, sampler);
104 tex->sampler = nir_deref_var_create(tex, sampler);
105
106 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
107 nir_builder_instr_insert(&b, &tex->instr);
108
109 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
110 vec4, "f_color");
111 color_out->data.location = FRAG_RESULT_DATA0;
112 nir_store_var(&b, color_out, &tex->dest.ssa, 0xf);
113
114 return b.shader;
115 }
116
117 static nir_shader *
118 build_nir_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim)
119 {
120 char shader_name[64];
121 const struct glsl_type *vec4 = glsl_vec4_type();
122 nir_builder b;
123
124 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
125
126 sprintf(shader_name, "meta_blit_depth_fs.%d", tex_dim);
127 b.shader->info->name = ralloc_strdup(b.shader, shader_name);
128
129 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
130 vec4, "v_tex_pos");
131 tex_pos_in->data.location = VARYING_SLOT_VAR0;
132
133 /* Swizzle the array index which comes in as Z coordinate into the right
134 * position.
135 */
136 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
137 nir_ssa_def *const tex_pos =
138 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
139 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
140
141 const struct glsl_type *sampler_type =
142 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
143 glsl_get_base_type(vec4));
144 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
145 sampler_type, "s_tex");
146 sampler->data.descriptor_set = 0;
147 sampler->data.binding = 0;
148
149 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
150 tex->sampler_dim = tex_dim;
151 tex->op = nir_texop_tex;
152 tex->src[0].src_type = nir_tex_src_coord;
153 tex->src[0].src = nir_src_for_ssa(tex_pos);
154 tex->dest_type = nir_type_float; /* TODO */
155 tex->is_array = glsl_sampler_type_is_array(sampler_type);
156 tex->coord_components = tex_pos->num_components;
157 tex->texture = nir_deref_var_create(tex, sampler);
158 tex->sampler = nir_deref_var_create(tex, sampler);
159
160 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
161 nir_builder_instr_insert(&b, &tex->instr);
162
163 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
164 vec4, "f_color");
165 color_out->data.location = FRAG_RESULT_DEPTH;
166 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
167
168 return b.shader;
169 }
170
171 static nir_shader *
172 build_nir_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim)
173 {
174 char shader_name[64];
175 const struct glsl_type *vec4 = glsl_vec4_type();
176 nir_builder b;
177
178 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
179
180 sprintf(shader_name, "meta_blit_stencil_fs.%d", tex_dim);
181 b.shader->info->name = ralloc_strdup(b.shader, shader_name);
182
183 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
184 vec4, "v_tex_pos");
185 tex_pos_in->data.location = VARYING_SLOT_VAR0;
186
187 /* Swizzle the array index which comes in as Z coordinate into the right
188 * position.
189 */
190 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
191 nir_ssa_def *const tex_pos =
192 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
193 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
194
195 const struct glsl_type *sampler_type =
196 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
197 glsl_get_base_type(vec4));
198 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
199 sampler_type, "s_tex");
200 sampler->data.descriptor_set = 0;
201 sampler->data.binding = 0;
202
203 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
204 tex->sampler_dim = tex_dim;
205 tex->op = nir_texop_tex;
206 tex->src[0].src_type = nir_tex_src_coord;
207 tex->src[0].src = nir_src_for_ssa(tex_pos);
208 tex->dest_type = nir_type_float; /* TODO */
209 tex->is_array = glsl_sampler_type_is_array(sampler_type);
210 tex->coord_components = tex_pos->num_components;
211 tex->texture = nir_deref_var_create(tex, sampler);
212 tex->sampler = nir_deref_var_create(tex, sampler);
213
214 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
215 nir_builder_instr_insert(&b, &tex->instr);
216
217 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
218 vec4, "f_color");
219 color_out->data.location = FRAG_RESULT_STENCIL;
220 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
221
222 return b.shader;
223 }
224
225 static void
226 meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
227 struct radv_image *src_image,
228 struct radv_image_view *src_iview,
229 VkOffset3D src_offset,
230 VkExtent3D src_extent,
231 struct radv_image *dest_image,
232 struct radv_image_view *dest_iview,
233 VkOffset3D dest_offset,
234 VkExtent3D dest_extent,
235 VkFilter blit_filter)
236 {
237 struct radv_device *device = cmd_buffer->device;
238 unsigned offset = 0;
239 struct blit_vb_data {
240 float pos[2];
241 float tex_coord[3];
242 } vb_data[3];
243
244 assert(src_image->samples == dest_image->samples);
245 unsigned vb_size = 3 * sizeof(*vb_data);
246 vb_data[0] = (struct blit_vb_data) {
247 .pos = {
248 dest_offset.x,
249 dest_offset.y,
250 },
251 .tex_coord = {
252 (float)(src_offset.x) / (float)src_iview->extent.width,
253 (float)(src_offset.y) / (float)src_iview->extent.height,
254 (float)src_offset.z / (float)src_iview->extent.depth,
255 },
256 };
257
258 vb_data[1] = (struct blit_vb_data) {
259 .pos = {
260 dest_offset.x,
261 dest_offset.y + dest_extent.height,
262 },
263 .tex_coord = {
264 (float)src_offset.x / (float)src_iview->extent.width,
265 (float)(src_offset.y + src_extent.height) /
266 (float)src_iview->extent.height,
267 (float)src_offset.z / (float)src_iview->extent.depth,
268 },
269 };
270
271 vb_data[2] = (struct blit_vb_data) {
272 .pos = {
273 dest_offset.x + dest_extent.width,
274 dest_offset.y,
275 },
276 .tex_coord = {
277 (float)(src_offset.x + src_extent.width) / (float)src_iview->extent.width,
278 (float)src_offset.y / (float)src_iview->extent.height,
279 (float)src_offset.z / (float)src_iview->extent.depth,
280 },
281 };
282 radv_cmd_buffer_upload_data(cmd_buffer, vb_size, 16, vb_data, &offset);
283
284 struct radv_buffer vertex_buffer = {
285 .device = device,
286 .size = vb_size,
287 .bo = cmd_buffer->upload.upload_bo,
288 .offset = offset,
289 };
290
291 radv_CmdBindVertexBuffers(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
292 (VkBuffer[]) {
293 radv_buffer_to_handle(&vertex_buffer)
294 },
295 (VkDeviceSize[]) {
296 0,
297 });
298
299 VkSampler sampler;
300 radv_CreateSampler(radv_device_to_handle(device),
301 &(VkSamplerCreateInfo) {
302 .sType = VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO,
303 .magFilter = blit_filter,
304 .minFilter = blit_filter,
305 .addressModeU = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
306 .addressModeV = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
307 .addressModeW = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
308 }, &cmd_buffer->pool->alloc, &sampler);
309
310 VkDescriptorSet set;
311 radv_temp_descriptor_set_create(cmd_buffer->device, cmd_buffer,
312 device->meta_state.blit.ds_layout,
313 &set);
314
315 radv_UpdateDescriptorSets(radv_device_to_handle(device),
316 1, /* writeCount */
317 (VkWriteDescriptorSet[]) {
318 {
319 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
320 .dstSet = set,
321 .dstBinding = 0,
322 .dstArrayElement = 0,
323 .descriptorCount = 1,
324 .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
325 .pImageInfo = (VkDescriptorImageInfo[]) {
326 {
327 .sampler = sampler,
328 .imageView = radv_image_view_to_handle(src_iview),
329 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
330 },
331 }
332 }
333 }, 0, NULL);
334
335 VkFramebuffer fb;
336 radv_CreateFramebuffer(radv_device_to_handle(device),
337 &(VkFramebufferCreateInfo) {
338 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
339 .attachmentCount = 1,
340 .pAttachments = (VkImageView[]) {
341 radv_image_view_to_handle(dest_iview),
342 },
343 .width = dest_iview->extent.width,
344 .height = dest_iview->extent.height,
345 .layers = 1,
346 }, &cmd_buffer->pool->alloc, &fb);
347 VkPipeline pipeline;
348 switch (src_iview->aspect_mask) {
349 case VK_IMAGE_ASPECT_COLOR_BIT: {
350 unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format);
351
352 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
353 &(VkRenderPassBeginInfo) {
354 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
355 .renderPass = device->meta_state.blit.render_pass[fs_key],
356 .framebuffer = fb,
357 .renderArea = {
358 .offset = { dest_offset.x, dest_offset.y },
359 .extent = { dest_extent.width, dest_extent.height },
360 },
361 .clearValueCount = 0,
362 .pClearValues = NULL,
363 }, VK_SUBPASS_CONTENTS_INLINE);
364 switch (src_image->type) {
365 case VK_IMAGE_TYPE_1D:
366 pipeline = device->meta_state.blit.pipeline_1d_src[fs_key];
367 break;
368 case VK_IMAGE_TYPE_2D:
369 pipeline = device->meta_state.blit.pipeline_2d_src[fs_key];
370 break;
371 case VK_IMAGE_TYPE_3D:
372 pipeline = device->meta_state.blit.pipeline_3d_src[fs_key];
373 break;
374 default:
375 unreachable(!"bad VkImageType");
376 }
377 break;
378 }
379 case VK_IMAGE_ASPECT_DEPTH_BIT:
380 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
381 &(VkRenderPassBeginInfo) {
382 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
383 .renderPass = device->meta_state.blit.depth_only_rp,
384 .framebuffer = fb,
385 .renderArea = {
386 .offset = { dest_offset.x, dest_offset.y },
387 .extent = { dest_extent.width, dest_extent.height },
388 },
389 .clearValueCount = 0,
390 .pClearValues = NULL,
391 }, VK_SUBPASS_CONTENTS_INLINE);
392 switch (src_image->type) {
393 case VK_IMAGE_TYPE_1D:
394 pipeline = device->meta_state.blit.depth_only_1d_pipeline;
395 break;
396 case VK_IMAGE_TYPE_2D:
397 pipeline = device->meta_state.blit.depth_only_2d_pipeline;
398 break;
399 case VK_IMAGE_TYPE_3D:
400 pipeline = device->meta_state.blit.depth_only_3d_pipeline;
401 break;
402 default:
403 unreachable(!"bad VkImageType");
404 }
405 break;
406 case VK_IMAGE_ASPECT_STENCIL_BIT:
407 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
408 &(VkRenderPassBeginInfo) {
409 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
410 .renderPass = device->meta_state.blit.stencil_only_rp,
411 .framebuffer = fb,
412 .renderArea = {
413 .offset = { dest_offset.x, dest_offset.y },
414 .extent = { dest_extent.width, dest_extent.height },
415 },
416 .clearValueCount = 0,
417 .pClearValues = NULL,
418 }, VK_SUBPASS_CONTENTS_INLINE);
419 switch (src_image->type) {
420 case VK_IMAGE_TYPE_1D:
421 pipeline = device->meta_state.blit.stencil_only_1d_pipeline;
422 break;
423 case VK_IMAGE_TYPE_2D:
424 pipeline = device->meta_state.blit.stencil_only_2d_pipeline;
425 break;
426 case VK_IMAGE_TYPE_3D:
427 pipeline = device->meta_state.blit.stencil_only_3d_pipeline;
428 break;
429 default:
430 unreachable(!"bad VkImageType");
431 }
432 break;
433 default:
434 unreachable(!"bad VkImageType");
435 }
436
437 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
438 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
439 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
440 }
441
442 radv_CmdBindDescriptorSets(radv_cmd_buffer_to_handle(cmd_buffer),
443 VK_PIPELINE_BIND_POINT_GRAPHICS,
444 device->meta_state.blit.pipeline_layout, 0, 1,
445 &set, 0, NULL);
446
447 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
448
449 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
450
451 /* At the point where we emit the draw call, all data from the
452 * descriptor sets, etc. has been used. We are free to delete it.
453 */
454 /* TODO: above comment is not valid for at least descriptor sets/pools,
455 * as we may not free them till after execution finishes. Check others. */
456
457 radv_temp_descriptor_set_destroy(cmd_buffer->device, set);
458 radv_DestroySampler(radv_device_to_handle(device), sampler,
459 &cmd_buffer->pool->alloc);
460 radv_DestroyFramebuffer(radv_device_to_handle(device), fb,
461 &cmd_buffer->pool->alloc);
462 }
463
464 void radv_CmdBlitImage(
465 VkCommandBuffer commandBuffer,
466 VkImage srcImage,
467 VkImageLayout srcImageLayout,
468 VkImage destImage,
469 VkImageLayout destImageLayout,
470 uint32_t regionCount,
471 const VkImageBlit* pRegions,
472 VkFilter filter)
473
474 {
475 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
476 RADV_FROM_HANDLE(radv_image, src_image, srcImage);
477 RADV_FROM_HANDLE(radv_image, dest_image, destImage);
478 struct radv_meta_saved_state saved_state;
479
480 /* From the Vulkan 1.0 spec:
481 *
482 * vkCmdBlitImage must not be used for multisampled source or
483 * destination images. Use vkCmdResolveImage for this purpose.
484 */
485 assert(src_image->samples == 1);
486 assert(dest_image->samples == 1);
487
488 radv_meta_save_graphics_reset_vport_scissor(&saved_state, cmd_buffer);
489
490 for (unsigned r = 0; r < regionCount; r++) {
491 const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
492 const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;
493 struct radv_image_view src_iview;
494 radv_image_view_init(&src_iview, cmd_buffer->device,
495 &(VkImageViewCreateInfo) {
496 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
497 .image = srcImage,
498 .viewType = radv_meta_get_view_type(src_image),
499 .format = src_image->vk_format,
500 .subresourceRange = {
501 .aspectMask = src_res->aspectMask,
502 .baseMipLevel = src_res->mipLevel,
503 .levelCount = 1,
504 .baseArrayLayer = src_res->baseArrayLayer,
505 .layerCount = 1
506 },
507 },
508 cmd_buffer, VK_IMAGE_USAGE_SAMPLED_BIT);
509
510 if (pRegions[r].dstOffsets[1].x < pRegions[r].dstOffsets[0].x ||
511 pRegions[r].dstOffsets[1].y < pRegions[r].dstOffsets[0].y ||
512 pRegions[r].srcOffsets[1].x < pRegions[r].srcOffsets[0].x ||
513 pRegions[r].srcOffsets[1].y < pRegions[r].srcOffsets[0].y)
514 radv_finishme("FINISHME: Allow flipping in blits");
515
516 const VkExtent3D dest_extent = {
517 .width = pRegions[r].dstOffsets[1].x - pRegions[r].dstOffsets[0].x,
518 .height = pRegions[r].dstOffsets[1].y - pRegions[r].dstOffsets[0].y,
519 .depth = 1,
520 };
521
522 const VkExtent3D src_extent = {
523 .width = pRegions[r].srcOffsets[1].x - pRegions[r].srcOffsets[0].x,
524 .height = pRegions[r].srcOffsets[1].y - pRegions[r].srcOffsets[0].y,
525 .depth = pRegions[r].srcOffsets[1].z - pRegions[r].srcOffsets[0].z,
526 };
527
528
529 if (src_res->layerCount > 1)
530 radv_finishme("FINISHME: copy multiple array layers");
531
532 struct radv_image_view dest_iview;
533 unsigned usage;
534 if (dst_res->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT)
535 usage = VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
536 else
537 usage = VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT;
538
539 for (unsigned i = pRegions[r].dstOffsets[0].z; i < pRegions[r].dstOffsets[1].z; i++) {
540
541 const VkOffset3D dest_offset = {
542 .x = pRegions[r].dstOffsets[0].x,
543 .y = pRegions[r].dstOffsets[0].y,
544 .z = i,
545 };
546 VkOffset3D src_offset = {
547 .x = pRegions[r].srcOffsets[0].x,
548 .y = pRegions[r].srcOffsets[0].y,
549 .z = i,
550 };
551 const uint32_t dest_array_slice =
552 radv_meta_get_iview_layer(dest_image, dst_res,
553 &dest_offset);
554
555 radv_image_view_init(&dest_iview, cmd_buffer->device,
556 &(VkImageViewCreateInfo) {
557 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
558 .image = destImage,
559 .viewType = radv_meta_get_view_type(dest_image),
560 .format = dest_image->vk_format,
561 .subresourceRange = {
562 .aspectMask = dst_res->aspectMask,
563 .baseMipLevel = dst_res->mipLevel,
564 .levelCount = 1,
565 .baseArrayLayer = dest_array_slice,
566 .layerCount = 1
567 },
568 },
569 cmd_buffer, usage);
570 meta_emit_blit(cmd_buffer,
571 src_image, &src_iview,
572 src_offset, src_extent,
573 dest_image, &dest_iview,
574 dest_offset, dest_extent,
575 filter);
576 }
577 }
578
579 radv_meta_restore(&saved_state, cmd_buffer);
580 }
581
582 void
583 radv_device_finish_meta_blit_state(struct radv_device *device)
584 {
585 for (unsigned i = 0; i < NUM_META_FS_KEYS; ++i) {
586 if (device->meta_state.blit.render_pass[i])
587 radv_DestroyRenderPass(radv_device_to_handle(device),
588 device->meta_state.blit.render_pass[i],
589 &device->meta_state.alloc);
590 if (device->meta_state.blit.pipeline_1d_src[i])
591 radv_DestroyPipeline(radv_device_to_handle(device),
592 device->meta_state.blit.pipeline_1d_src[i],
593 &device->meta_state.alloc);
594 if (device->meta_state.blit.pipeline_2d_src[i])
595 radv_DestroyPipeline(radv_device_to_handle(device),
596 device->meta_state.blit.pipeline_2d_src[i],
597 &device->meta_state.alloc);
598 if (device->meta_state.blit.pipeline_3d_src[i])
599 radv_DestroyPipeline(radv_device_to_handle(device),
600 device->meta_state.blit.pipeline_3d_src[i],
601 &device->meta_state.alloc);
602 }
603
604 if (device->meta_state.blit.depth_only_rp)
605 radv_DestroyRenderPass(radv_device_to_handle(device),
606 device->meta_state.blit.depth_only_rp,
607 &device->meta_state.alloc);
608 if (device->meta_state.blit.depth_only_1d_pipeline)
609 radv_DestroyPipeline(radv_device_to_handle(device),
610 device->meta_state.blit.depth_only_1d_pipeline,
611 &device->meta_state.alloc);
612 if (device->meta_state.blit.depth_only_2d_pipeline)
613 radv_DestroyPipeline(radv_device_to_handle(device),
614 device->meta_state.blit.depth_only_2d_pipeline,
615 &device->meta_state.alloc);
616 if (device->meta_state.blit.depth_only_3d_pipeline)
617 radv_DestroyPipeline(radv_device_to_handle(device),
618 device->meta_state.blit.depth_only_3d_pipeline,
619 &device->meta_state.alloc);
620 if (device->meta_state.blit.stencil_only_rp)
621 radv_DestroyRenderPass(radv_device_to_handle(device),
622 device->meta_state.blit.stencil_only_rp,
623 &device->meta_state.alloc);
624 if (device->meta_state.blit.stencil_only_1d_pipeline)
625 radv_DestroyPipeline(radv_device_to_handle(device),
626 device->meta_state.blit.stencil_only_1d_pipeline,
627 &device->meta_state.alloc);
628 if (device->meta_state.blit.stencil_only_2d_pipeline)
629 radv_DestroyPipeline(radv_device_to_handle(device),
630 device->meta_state.blit.stencil_only_2d_pipeline,
631 &device->meta_state.alloc);
632 if (device->meta_state.blit.stencil_only_3d_pipeline)
633 radv_DestroyPipeline(radv_device_to_handle(device),
634 device->meta_state.blit.stencil_only_3d_pipeline,
635 &device->meta_state.alloc);
636 if (device->meta_state.blit.pipeline_layout)
637 radv_DestroyPipelineLayout(radv_device_to_handle(device),
638 device->meta_state.blit.pipeline_layout,
639 &device->meta_state.alloc);
640 if (device->meta_state.blit.ds_layout)
641 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
642 device->meta_state.blit.ds_layout,
643 &device->meta_state.alloc);
644 }
645
646 static VkFormat pipeline_formats[] = {
647 VK_FORMAT_R8G8B8A8_UNORM,
648 VK_FORMAT_R8G8B8A8_UINT,
649 VK_FORMAT_R8G8B8A8_SINT,
650 VK_FORMAT_R16G16B16A16_UNORM,
651 VK_FORMAT_R16G16B16A16_SNORM,
652 VK_FORMAT_R16G16B16A16_UINT,
653 VK_FORMAT_R16G16B16A16_SINT,
654 VK_FORMAT_R32_SFLOAT,
655 VK_FORMAT_R32G32_SFLOAT,
656 VK_FORMAT_R32G32B32A32_SFLOAT
657 };
658
659 static VkResult
660 radv_device_init_meta_blit_color(struct radv_device *device,
661 struct radv_shader_module *vs)
662 {
663 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
664 VkResult result;
665
666 fs_1d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_1D);
667 fs_2d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_2D);
668 fs_3d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_3D);
669
670 for (unsigned i = 0; i < ARRAY_SIZE(pipeline_formats); ++i) {
671 unsigned key = radv_format_meta_fs_key(pipeline_formats[i]);
672 result = radv_CreateRenderPass(radv_device_to_handle(device),
673 &(VkRenderPassCreateInfo) {
674 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
675 .attachmentCount = 1,
676 .pAttachments = &(VkAttachmentDescription) {
677 .format = pipeline_formats[i],
678 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
679 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
680 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
681 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
682 },
683 .subpassCount = 1,
684 .pSubpasses = &(VkSubpassDescription) {
685 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
686 .inputAttachmentCount = 0,
687 .colorAttachmentCount = 1,
688 .pColorAttachments = &(VkAttachmentReference) {
689 .attachment = 0,
690 .layout = VK_IMAGE_LAYOUT_GENERAL,
691 },
692 .pResolveAttachments = NULL,
693 .pDepthStencilAttachment = &(VkAttachmentReference) {
694 .attachment = VK_ATTACHMENT_UNUSED,
695 .layout = VK_IMAGE_LAYOUT_GENERAL,
696 },
697 .preserveAttachmentCount = 1,
698 .pPreserveAttachments = (uint32_t[]) { 0 },
699 },
700 .dependencyCount = 0,
701 }, &device->meta_state.alloc, &device->meta_state.blit.render_pass[key]);
702 if (result != VK_SUCCESS)
703 goto fail;
704
705 VkPipelineVertexInputStateCreateInfo vi_create_info = {
706 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
707 .vertexBindingDescriptionCount = 1,
708 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
709 {
710 .binding = 0,
711 .stride = 5 * sizeof(float),
712 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
713 },
714 },
715 .vertexAttributeDescriptionCount = 2,
716 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
717 {
718 /* Position */
719 .location = 0,
720 .binding = 0,
721 .format = VK_FORMAT_R32G32_SFLOAT,
722 .offset = 0
723 },
724 {
725 /* Texture Coordinate */
726 .location = 1,
727 .binding = 0,
728 .format = VK_FORMAT_R32G32B32_SFLOAT,
729 .offset = 8
730 }
731 }
732 };
733
734 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
735 {
736 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
737 .stage = VK_SHADER_STAGE_VERTEX_BIT,
738 .module = radv_shader_module_to_handle(vs),
739 .pName = "main",
740 .pSpecializationInfo = NULL
741 }, {
742 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
743 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
744 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
745 .pName = "main",
746 .pSpecializationInfo = NULL
747 },
748 };
749
750 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
751 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
752 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
753 .pStages = pipeline_shader_stages,
754 .pVertexInputState = &vi_create_info,
755 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
756 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
757 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
758 .primitiveRestartEnable = false,
759 },
760 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
761 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
762 .viewportCount = 0,
763 .scissorCount = 0,
764 },
765 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
766 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
767 .rasterizerDiscardEnable = false,
768 .polygonMode = VK_POLYGON_MODE_FILL,
769 .cullMode = VK_CULL_MODE_NONE,
770 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
771 },
772 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
773 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
774 .rasterizationSamples = 1,
775 .sampleShadingEnable = false,
776 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
777 },
778 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
779 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
780 .attachmentCount = 1,
781 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
782 { .colorWriteMask =
783 VK_COLOR_COMPONENT_A_BIT |
784 VK_COLOR_COMPONENT_R_BIT |
785 VK_COLOR_COMPONENT_G_BIT |
786 VK_COLOR_COMPONENT_B_BIT },
787 }
788 },
789 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
790 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
791 .dynamicStateCount = 2,
792 .pDynamicStates = (VkDynamicState[]) {
793 VK_DYNAMIC_STATE_LINE_WIDTH,
794 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
795 },
796 },
797 .flags = 0,
798 .layout = device->meta_state.blit.pipeline_layout,
799 .renderPass = device->meta_state.blit.render_pass[key],
800 .subpass = 0,
801 };
802
803 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
804 .use_rectlist = true
805 };
806
807 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
808 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
809 radv_pipeline_cache_to_handle(&device->meta_state.cache),
810 &vk_pipeline_info, &radv_pipeline_info,
811 &device->meta_state.alloc, &device->meta_state.blit.pipeline_1d_src[key]);
812 if (result != VK_SUCCESS)
813 goto fail;
814
815 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
816 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
817 radv_pipeline_cache_to_handle(&device->meta_state.cache),
818 &vk_pipeline_info, &radv_pipeline_info,
819 &device->meta_state.alloc, &device->meta_state.blit.pipeline_2d_src[key]);
820 if (result != VK_SUCCESS)
821 goto fail;
822
823 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
824 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
825 radv_pipeline_cache_to_handle(&device->meta_state.cache),
826 &vk_pipeline_info, &radv_pipeline_info,
827 &device->meta_state.alloc, &device->meta_state.blit.pipeline_3d_src[key]);
828 if (result != VK_SUCCESS)
829 goto fail;
830
831 }
832
833 result = VK_SUCCESS;
834 fail:
835 ralloc_free(fs_1d.nir);
836 ralloc_free(fs_2d.nir);
837 ralloc_free(fs_3d.nir);
838 return result;
839 }
840
841 static VkResult
842 radv_device_init_meta_blit_depth(struct radv_device *device,
843 struct radv_shader_module *vs)
844 {
845 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
846 VkResult result;
847
848 fs_1d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_1D);
849 fs_2d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_2D);
850 fs_3d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_3D);
851
852 result = radv_CreateRenderPass(radv_device_to_handle(device),
853 &(VkRenderPassCreateInfo) {
854 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
855 .attachmentCount = 1,
856 .pAttachments = &(VkAttachmentDescription) {
857 .format = 0,
858 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
859 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
860 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
861 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
862 },
863 .subpassCount = 1,
864 .pSubpasses = &(VkSubpassDescription) {
865 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
866 .inputAttachmentCount = 0,
867 .colorAttachmentCount = 0,
868 .pColorAttachments = NULL,
869 .pResolveAttachments = NULL,
870 .pDepthStencilAttachment = &(VkAttachmentReference) {
871 .attachment = 0,
872 .layout = VK_IMAGE_LAYOUT_GENERAL,
873 },
874 .preserveAttachmentCount = 1,
875 .pPreserveAttachments = (uint32_t[]) { 0 },
876 },
877 .dependencyCount = 0,
878 }, &device->meta_state.alloc, &device->meta_state.blit.depth_only_rp);
879 if (result != VK_SUCCESS)
880 goto fail;
881
882 VkPipelineVertexInputStateCreateInfo vi_create_info = {
883 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
884 .vertexBindingDescriptionCount = 1,
885 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
886 {
887 .binding = 0,
888 .stride = 5 * sizeof(float),
889 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
890 },
891 },
892 .vertexAttributeDescriptionCount = 2,
893 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
894 {
895 /* Position */
896 .location = 0,
897 .binding = 0,
898 .format = VK_FORMAT_R32G32_SFLOAT,
899 .offset = 0
900 },
901 {
902 /* Texture Coordinate */
903 .location = 1,
904 .binding = 0,
905 .format = VK_FORMAT_R32G32B32_SFLOAT,
906 .offset = 8
907 }
908 }
909 };
910
911 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
912 {
913 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
914 .stage = VK_SHADER_STAGE_VERTEX_BIT,
915 .module = radv_shader_module_to_handle(vs),
916 .pName = "main",
917 .pSpecializationInfo = NULL
918 }, {
919 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
920 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
921 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
922 .pName = "main",
923 .pSpecializationInfo = NULL
924 },
925 };
926
927 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
928 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
929 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
930 .pStages = pipeline_shader_stages,
931 .pVertexInputState = &vi_create_info,
932 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
933 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
934 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
935 .primitiveRestartEnable = false,
936 },
937 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
938 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
939 .viewportCount = 0,
940 .scissorCount = 0,
941 },
942 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
943 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
944 .rasterizerDiscardEnable = false,
945 .polygonMode = VK_POLYGON_MODE_FILL,
946 .cullMode = VK_CULL_MODE_NONE,
947 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
948 },
949 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
950 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
951 .rasterizationSamples = 1,
952 .sampleShadingEnable = false,
953 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
954 },
955 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
956 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
957 .attachmentCount = 0,
958 .pAttachments = NULL,
959 },
960 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
961 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
962 .depthTestEnable = true,
963 .depthWriteEnable = true,
964 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
965 },
966 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
967 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
968 .dynamicStateCount = 7,
969 .pDynamicStates = (VkDynamicState[]) {
970 VK_DYNAMIC_STATE_LINE_WIDTH,
971 VK_DYNAMIC_STATE_DEPTH_BIAS,
972 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
973 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
974 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
975 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
976 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
977 },
978 },
979 .flags = 0,
980 .layout = device->meta_state.blit.pipeline_layout,
981 .renderPass = device->meta_state.blit.depth_only_rp,
982 .subpass = 0,
983 };
984
985 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
986 .use_rectlist = true
987 };
988
989 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
990 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
991 radv_pipeline_cache_to_handle(&device->meta_state.cache),
992 &vk_pipeline_info, &radv_pipeline_info,
993 &device->meta_state.alloc, &device->meta_state.blit.depth_only_1d_pipeline);
994 if (result != VK_SUCCESS)
995 goto fail;
996
997 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
998 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
999 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1000 &vk_pipeline_info, &radv_pipeline_info,
1001 &device->meta_state.alloc, &device->meta_state.blit.depth_only_2d_pipeline);
1002 if (result != VK_SUCCESS)
1003 goto fail;
1004
1005 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
1006 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1007 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1008 &vk_pipeline_info, &radv_pipeline_info,
1009 &device->meta_state.alloc, &device->meta_state.blit.depth_only_3d_pipeline);
1010 if (result != VK_SUCCESS)
1011 goto fail;
1012
1013 fail:
1014 ralloc_free(fs_1d.nir);
1015 ralloc_free(fs_2d.nir);
1016 ralloc_free(fs_3d.nir);
1017 return result;
1018 }
1019
1020 static VkResult
1021 radv_device_init_meta_blit_stencil(struct radv_device *device,
1022 struct radv_shader_module *vs)
1023 {
1024 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
1025 VkResult result;
1026
1027 fs_1d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_1D);
1028 fs_2d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_2D);
1029 fs_3d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_3D);
1030
1031 result = radv_CreateRenderPass(radv_device_to_handle(device),
1032 &(VkRenderPassCreateInfo) {
1033 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1034 .attachmentCount = 1,
1035 .pAttachments = &(VkAttachmentDescription) {
1036 .format = 0,
1037 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1038 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1039 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
1040 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
1041 },
1042 .subpassCount = 1,
1043 .pSubpasses = &(VkSubpassDescription) {
1044 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1045 .inputAttachmentCount = 0,
1046 .colorAttachmentCount = 0,
1047 .pColorAttachments = NULL,
1048 .pResolveAttachments = NULL,
1049 .pDepthStencilAttachment = &(VkAttachmentReference) {
1050 .attachment = 0,
1051 .layout = VK_IMAGE_LAYOUT_GENERAL,
1052 },
1053 .preserveAttachmentCount = 1,
1054 .pPreserveAttachments = (uint32_t[]) { 0 },
1055 },
1056 .dependencyCount = 0,
1057 }, &device->meta_state.alloc, &device->meta_state.blit.stencil_only_rp);
1058 if (result != VK_SUCCESS)
1059 goto fail;
1060
1061 VkPipelineVertexInputStateCreateInfo vi_create_info = {
1062 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
1063 .vertexBindingDescriptionCount = 1,
1064 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
1065 {
1066 .binding = 0,
1067 .stride = 5 * sizeof(float),
1068 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
1069 },
1070 },
1071 .vertexAttributeDescriptionCount = 2,
1072 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
1073 {
1074 /* Position */
1075 .location = 0,
1076 .binding = 0,
1077 .format = VK_FORMAT_R32G32_SFLOAT,
1078 .offset = 0
1079 },
1080 {
1081 /* Texture Coordinate */
1082 .location = 1,
1083 .binding = 0,
1084 .format = VK_FORMAT_R32G32B32_SFLOAT,
1085 .offset = 8
1086 }
1087 }
1088 };
1089
1090 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
1091 {
1092 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1093 .stage = VK_SHADER_STAGE_VERTEX_BIT,
1094 .module = radv_shader_module_to_handle(vs),
1095 .pName = "main",
1096 .pSpecializationInfo = NULL
1097 }, {
1098 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1099 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
1100 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
1101 .pName = "main",
1102 .pSpecializationInfo = NULL
1103 },
1104 };
1105
1106 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1107 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1108 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
1109 .pStages = pipeline_shader_stages,
1110 .pVertexInputState = &vi_create_info,
1111 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1112 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1113 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1114 .primitiveRestartEnable = false,
1115 },
1116 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
1117 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1118 .viewportCount = 0,
1119 .scissorCount = 0,
1120 },
1121 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1122 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1123 .rasterizerDiscardEnable = false,
1124 .polygonMode = VK_POLYGON_MODE_FILL,
1125 .cullMode = VK_CULL_MODE_NONE,
1126 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1127 },
1128 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1129 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1130 .rasterizationSamples = 1,
1131 .sampleShadingEnable = false,
1132 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1133 },
1134 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1135 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1136 .attachmentCount = 0,
1137 .pAttachments = NULL,
1138 },
1139 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1140 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1141 .depthTestEnable = false,
1142 .depthWriteEnable = false,
1143 .stencilTestEnable = true,
1144 .front = {
1145 .failOp = VK_STENCIL_OP_REPLACE,
1146 .passOp = VK_STENCIL_OP_REPLACE,
1147 .depthFailOp = VK_STENCIL_OP_REPLACE,
1148 .compareOp = VK_COMPARE_OP_ALWAYS,
1149 .compareMask = 0xff,
1150 .writeMask = 0xff,
1151 .reference = 0
1152 },
1153 .back = {
1154 .failOp = VK_STENCIL_OP_REPLACE,
1155 .passOp = VK_STENCIL_OP_REPLACE,
1156 .depthFailOp = VK_STENCIL_OP_REPLACE,
1157 .compareOp = VK_COMPARE_OP_ALWAYS,
1158 .compareMask = 0xff,
1159 .writeMask = 0xff,
1160 .reference = 0
1161 },
1162 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
1163 },
1164
1165 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1166 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1167 .dynamicStateCount = 4,
1168 .pDynamicStates = (VkDynamicState[]) {
1169 VK_DYNAMIC_STATE_LINE_WIDTH,
1170 VK_DYNAMIC_STATE_DEPTH_BIAS,
1171 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1172 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1173 },
1174 },
1175 .flags = 0,
1176 .layout = device->meta_state.blit.pipeline_layout,
1177 .renderPass = device->meta_state.blit.stencil_only_rp,
1178 .subpass = 0,
1179 };
1180
1181 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1182 .use_rectlist = true
1183 };
1184
1185 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
1186 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1187 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1188 &vk_pipeline_info, &radv_pipeline_info,
1189 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_1d_pipeline);
1190 if (result != VK_SUCCESS)
1191 goto fail;
1192
1193 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
1194 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1195 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1196 &vk_pipeline_info, &radv_pipeline_info,
1197 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_2d_pipeline);
1198 if (result != VK_SUCCESS)
1199 goto fail;
1200
1201 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
1202 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1203 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1204 &vk_pipeline_info, &radv_pipeline_info,
1205 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_3d_pipeline);
1206 if (result != VK_SUCCESS)
1207 goto fail;
1208
1209 fail:
1210 ralloc_free(fs_1d.nir);
1211 ralloc_free(fs_2d.nir);
1212 ralloc_free(fs_3d.nir);
1213 return result;
1214 }
1215
1216 VkResult
1217 radv_device_init_meta_blit_state(struct radv_device *device)
1218 {
1219 VkResult result;
1220 struct radv_shader_module vs = {0};
1221 zero(device->meta_state.blit);
1222
1223 VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1224 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1225 .bindingCount = 1,
1226 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1227 {
1228 .binding = 0,
1229 .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
1230 .descriptorCount = 1,
1231 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1232 .pImmutableSamplers = NULL
1233 },
1234 }
1235 };
1236 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1237 &ds_layout_info,
1238 &device->meta_state.alloc,
1239 &device->meta_state.blit.ds_layout);
1240 if (result != VK_SUCCESS)
1241 goto fail;
1242
1243 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1244 &(VkPipelineLayoutCreateInfo) {
1245 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1246 .setLayoutCount = 1,
1247 .pSetLayouts = &device->meta_state.blit.ds_layout,
1248 },
1249 &device->meta_state.alloc, &device->meta_state.blit.pipeline_layout);
1250 if (result != VK_SUCCESS)
1251 goto fail;
1252
1253 vs.nir = build_nir_vertex_shader();
1254
1255 result = radv_device_init_meta_blit_color(device, &vs);
1256 if (result != VK_SUCCESS)
1257 goto fail;
1258
1259 result = radv_device_init_meta_blit_depth(device, &vs);
1260 if (result != VK_SUCCESS)
1261 goto fail;
1262
1263 result = radv_device_init_meta_blit_stencil(device, &vs);
1264 if (result != VK_SUCCESS)
1265 goto fail;
1266 return VK_SUCCESS;
1267
1268 fail:
1269 ralloc_free(vs.nir);
1270 radv_device_finish_meta_blit_state(device);
1271 return result;
1272 }