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radv: Fix multi-layer blits.
[mesa.git] / src / amd / vulkan / radv_meta_blit.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_meta.h"
25 #include "nir/nir_builder.h"
26
27 struct blit_region {
28 VkOffset3D src_offset;
29 VkExtent3D src_extent;
30 VkOffset3D dest_offset;
31 VkExtent3D dest_extent;
32 };
33
34 static nir_shader *
35 build_nir_vertex_shader(void)
36 {
37 const struct glsl_type *vec4 = glsl_vec4_type();
38 nir_builder b;
39
40 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
41 b.shader->info.name = ralloc_strdup(b.shader, "meta_blit_vs");
42
43 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
44 vec4, "gl_Position");
45 pos_out->data.location = VARYING_SLOT_POS;
46
47 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
48 vec4, "v_tex_pos");
49 tex_pos_out->data.location = VARYING_SLOT_VAR0;
50 tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
51
52 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
53
54 nir_store_var(&b, pos_out, outvec, 0xf);
55
56 nir_intrinsic_instr *src_box = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
57 src_box->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
58 nir_intrinsic_set_base(src_box, 0);
59 nir_intrinsic_set_range(src_box, 16);
60 src_box->num_components = 4;
61 nir_ssa_dest_init(&src_box->instr, &src_box->dest, 4, 32, "src_box");
62 nir_builder_instr_insert(&b, &src_box->instr);
63
64 nir_intrinsic_instr *src0_z = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
65 src0_z->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
66 nir_intrinsic_set_base(src0_z, 16);
67 nir_intrinsic_set_range(src0_z, 4);
68 src0_z->num_components = 1;
69 nir_ssa_dest_init(&src0_z->instr, &src0_z->dest, 1, 32, "src0_z");
70 nir_builder_instr_insert(&b, &src0_z->instr);
71
72 nir_intrinsic_instr *vertex_id = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_vertex_id_zero_base);
73 nir_ssa_dest_init(&vertex_id->instr, &vertex_id->dest, 1, 32, "vertexid");
74 nir_builder_instr_insert(&b, &vertex_id->instr);
75
76 /* vertex 0 - src0_x, src0_y, src0_z */
77 /* vertex 1 - src0_x, src1_y, src0_z*/
78 /* vertex 2 - src1_x, src0_y, src0_z */
79 /* so channel 0 is vertex_id != 2 ? src_x : src_x + w
80 channel 1 is vertex id != 1 ? src_y : src_y + w */
81
82 nir_ssa_def *c0cmp = nir_ine(&b, &vertex_id->dest.ssa,
83 nir_imm_int(&b, 2));
84 nir_ssa_def *c1cmp = nir_ine(&b, &vertex_id->dest.ssa,
85 nir_imm_int(&b, 1));
86
87 nir_ssa_def *comp[4];
88 comp[0] = nir_bcsel(&b, c0cmp,
89 nir_channel(&b, &src_box->dest.ssa, 0),
90 nir_channel(&b, &src_box->dest.ssa, 2));
91
92 comp[1] = nir_bcsel(&b, c1cmp,
93 nir_channel(&b, &src_box->dest.ssa, 1),
94 nir_channel(&b, &src_box->dest.ssa, 3));
95 comp[2] = &src0_z->dest.ssa;
96 comp[3] = nir_imm_float(&b, 1.0);
97 nir_ssa_def *out_tex_vec = nir_vec(&b, comp, 4);
98 nir_store_var(&b, tex_pos_out, out_tex_vec, 0xf);
99 return b.shader;
100 }
101
102 static nir_shader *
103 build_nir_copy_fragment_shader(enum glsl_sampler_dim tex_dim)
104 {
105 char shader_name[64];
106 const struct glsl_type *vec4 = glsl_vec4_type();
107 nir_builder b;
108
109 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
110
111 sprintf(shader_name, "meta_blit_fs.%d", tex_dim);
112 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
113
114 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
115 vec4, "v_tex_pos");
116 tex_pos_in->data.location = VARYING_SLOT_VAR0;
117
118 /* Swizzle the array index which comes in as Z coordinate into the right
119 * position.
120 */
121 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
122 nir_ssa_def *const tex_pos =
123 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
124 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
125
126 const struct glsl_type *sampler_type =
127 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
128 glsl_get_base_type(vec4));
129 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
130 sampler_type, "s_tex");
131 sampler->data.descriptor_set = 0;
132 sampler->data.binding = 0;
133
134 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
135 tex->sampler_dim = tex_dim;
136 tex->op = nir_texop_tex;
137 tex->src[0].src_type = nir_tex_src_coord;
138 tex->src[0].src = nir_src_for_ssa(tex_pos);
139 tex->dest_type = nir_type_float; /* TODO */
140 tex->is_array = glsl_sampler_type_is_array(sampler_type);
141 tex->coord_components = tex_pos->num_components;
142 tex->texture = nir_deref_var_create(tex, sampler);
143 tex->sampler = nir_deref_var_create(tex, sampler);
144
145 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
146 nir_builder_instr_insert(&b, &tex->instr);
147
148 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
149 vec4, "f_color");
150 color_out->data.location = FRAG_RESULT_DATA0;
151 nir_store_var(&b, color_out, &tex->dest.ssa, 0xf);
152
153 return b.shader;
154 }
155
156 static nir_shader *
157 build_nir_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim)
158 {
159 char shader_name[64];
160 const struct glsl_type *vec4 = glsl_vec4_type();
161 nir_builder b;
162
163 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
164
165 sprintf(shader_name, "meta_blit_depth_fs.%d", tex_dim);
166 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
167
168 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
169 vec4, "v_tex_pos");
170 tex_pos_in->data.location = VARYING_SLOT_VAR0;
171
172 /* Swizzle the array index which comes in as Z coordinate into the right
173 * position.
174 */
175 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
176 nir_ssa_def *const tex_pos =
177 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
178 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
179
180 const struct glsl_type *sampler_type =
181 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
182 glsl_get_base_type(vec4));
183 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
184 sampler_type, "s_tex");
185 sampler->data.descriptor_set = 0;
186 sampler->data.binding = 0;
187
188 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
189 tex->sampler_dim = tex_dim;
190 tex->op = nir_texop_tex;
191 tex->src[0].src_type = nir_tex_src_coord;
192 tex->src[0].src = nir_src_for_ssa(tex_pos);
193 tex->dest_type = nir_type_float; /* TODO */
194 tex->is_array = glsl_sampler_type_is_array(sampler_type);
195 tex->coord_components = tex_pos->num_components;
196 tex->texture = nir_deref_var_create(tex, sampler);
197 tex->sampler = nir_deref_var_create(tex, sampler);
198
199 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
200 nir_builder_instr_insert(&b, &tex->instr);
201
202 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
203 vec4, "f_color");
204 color_out->data.location = FRAG_RESULT_DEPTH;
205 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
206
207 return b.shader;
208 }
209
210 static nir_shader *
211 build_nir_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim)
212 {
213 char shader_name[64];
214 const struct glsl_type *vec4 = glsl_vec4_type();
215 nir_builder b;
216
217 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
218
219 sprintf(shader_name, "meta_blit_stencil_fs.%d", tex_dim);
220 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
221
222 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
223 vec4, "v_tex_pos");
224 tex_pos_in->data.location = VARYING_SLOT_VAR0;
225
226 /* Swizzle the array index which comes in as Z coordinate into the right
227 * position.
228 */
229 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
230 nir_ssa_def *const tex_pos =
231 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
232 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
233
234 const struct glsl_type *sampler_type =
235 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
236 glsl_get_base_type(vec4));
237 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
238 sampler_type, "s_tex");
239 sampler->data.descriptor_set = 0;
240 sampler->data.binding = 0;
241
242 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
243 tex->sampler_dim = tex_dim;
244 tex->op = nir_texop_tex;
245 tex->src[0].src_type = nir_tex_src_coord;
246 tex->src[0].src = nir_src_for_ssa(tex_pos);
247 tex->dest_type = nir_type_float; /* TODO */
248 tex->is_array = glsl_sampler_type_is_array(sampler_type);
249 tex->coord_components = tex_pos->num_components;
250 tex->texture = nir_deref_var_create(tex, sampler);
251 tex->sampler = nir_deref_var_create(tex, sampler);
252
253 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
254 nir_builder_instr_insert(&b, &tex->instr);
255
256 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
257 vec4, "f_color");
258 color_out->data.location = FRAG_RESULT_STENCIL;
259 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
260
261 return b.shader;
262 }
263
264 static void
265 meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
266 struct radv_image *src_image,
267 struct radv_image_view *src_iview,
268 VkOffset3D src_offset_0,
269 VkOffset3D src_offset_1,
270 struct radv_image *dest_image,
271 struct radv_image_view *dest_iview,
272 VkOffset2D dest_offset_0,
273 VkOffset2D dest_offset_1,
274 VkRect2D dest_box,
275 VkFilter blit_filter)
276 {
277 struct radv_device *device = cmd_buffer->device;
278 uint32_t src_width = radv_minify(src_iview->image->info.width, src_iview->base_mip);
279 uint32_t src_height = radv_minify(src_iview->image->info.height, src_iview->base_mip);
280 uint32_t src_depth = radv_minify(src_iview->image->info.depth, src_iview->base_mip);
281 uint32_t dst_width = radv_minify(dest_iview->image->info.width, dest_iview->base_mip);
282 uint32_t dst_height = radv_minify(dest_iview->image->info.height, dest_iview->base_mip);
283
284 assert(src_image->info.samples == dest_image->info.samples);
285
286 float vertex_push_constants[5] = {
287 (float)src_offset_0.x / (float)src_width,
288 (float)src_offset_0.y / (float)src_height,
289 (float)src_offset_1.x / (float)src_width,
290 (float)src_offset_1.y / (float)src_height,
291 (float)src_offset_0.z / (float)src_depth,
292 };
293
294 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
295 device->meta_state.blit.pipeline_layout,
296 VK_SHADER_STAGE_VERTEX_BIT, 0, 20,
297 vertex_push_constants);
298
299 VkSampler sampler;
300 radv_CreateSampler(radv_device_to_handle(device),
301 &(VkSamplerCreateInfo) {
302 .sType = VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO,
303 .magFilter = blit_filter,
304 .minFilter = blit_filter,
305 .addressModeU = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
306 .addressModeV = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
307 .addressModeW = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
308 }, &cmd_buffer->pool->alloc, &sampler);
309
310 VkFramebuffer fb;
311 radv_CreateFramebuffer(radv_device_to_handle(device),
312 &(VkFramebufferCreateInfo) {
313 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
314 .attachmentCount = 1,
315 .pAttachments = (VkImageView[]) {
316 radv_image_view_to_handle(dest_iview),
317 },
318 .width = dst_width,
319 .height = dst_height,
320 .layers = 1,
321 }, &cmd_buffer->pool->alloc, &fb);
322 VkPipeline pipeline;
323 switch (src_iview->aspect_mask) {
324 case VK_IMAGE_ASPECT_COLOR_BIT: {
325 unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format);
326
327 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
328 &(VkRenderPassBeginInfo) {
329 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
330 .renderPass = device->meta_state.blit.render_pass[fs_key],
331 .framebuffer = fb,
332 .renderArea = {
333 .offset = { dest_box.offset.x, dest_box.offset.y },
334 .extent = { dest_box.extent.width, dest_box.extent.height },
335 },
336 .clearValueCount = 0,
337 .pClearValues = NULL,
338 }, VK_SUBPASS_CONTENTS_INLINE);
339 switch (src_image->type) {
340 case VK_IMAGE_TYPE_1D:
341 pipeline = device->meta_state.blit.pipeline_1d_src[fs_key];
342 break;
343 case VK_IMAGE_TYPE_2D:
344 pipeline = device->meta_state.blit.pipeline_2d_src[fs_key];
345 break;
346 case VK_IMAGE_TYPE_3D:
347 pipeline = device->meta_state.blit.pipeline_3d_src[fs_key];
348 break;
349 default:
350 unreachable(!"bad VkImageType");
351 }
352 break;
353 }
354 case VK_IMAGE_ASPECT_DEPTH_BIT:
355 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
356 &(VkRenderPassBeginInfo) {
357 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
358 .renderPass = device->meta_state.blit.depth_only_rp,
359 .framebuffer = fb,
360 .renderArea = {
361 .offset = { dest_box.offset.x, dest_box.offset.y },
362 .extent = { dest_box.extent.width, dest_box.extent.height },
363 },
364 .clearValueCount = 0,
365 .pClearValues = NULL,
366 }, VK_SUBPASS_CONTENTS_INLINE);
367 switch (src_image->type) {
368 case VK_IMAGE_TYPE_1D:
369 pipeline = device->meta_state.blit.depth_only_1d_pipeline;
370 break;
371 case VK_IMAGE_TYPE_2D:
372 pipeline = device->meta_state.blit.depth_only_2d_pipeline;
373 break;
374 case VK_IMAGE_TYPE_3D:
375 pipeline = device->meta_state.blit.depth_only_3d_pipeline;
376 break;
377 default:
378 unreachable(!"bad VkImageType");
379 }
380 break;
381 case VK_IMAGE_ASPECT_STENCIL_BIT:
382 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
383 &(VkRenderPassBeginInfo) {
384 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
385 .renderPass = device->meta_state.blit.stencil_only_rp,
386 .framebuffer = fb,
387 .renderArea = {
388 .offset = { dest_box.offset.x, dest_box.offset.y },
389 .extent = { dest_box.extent.width, dest_box.extent.height },
390 },
391 .clearValueCount = 0,
392 .pClearValues = NULL,
393 }, VK_SUBPASS_CONTENTS_INLINE);
394 switch (src_image->type) {
395 case VK_IMAGE_TYPE_1D:
396 pipeline = device->meta_state.blit.stencil_only_1d_pipeline;
397 break;
398 case VK_IMAGE_TYPE_2D:
399 pipeline = device->meta_state.blit.stencil_only_2d_pipeline;
400 break;
401 case VK_IMAGE_TYPE_3D:
402 pipeline = device->meta_state.blit.stencil_only_3d_pipeline;
403 break;
404 default:
405 unreachable(!"bad VkImageType");
406 }
407 break;
408 default:
409 unreachable(!"bad VkImageType");
410 }
411
412 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
413 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
414
415 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
416 device->meta_state.blit.pipeline_layout,
417 0, /* set */
418 1, /* descriptorWriteCount */
419 (VkWriteDescriptorSet[]) {
420 {
421 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
422 .dstBinding = 0,
423 .dstArrayElement = 0,
424 .descriptorCount = 1,
425 .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
426 .pImageInfo = (VkDescriptorImageInfo[]) {
427 {
428 .sampler = sampler,
429 .imageView = radv_image_view_to_handle(src_iview),
430 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
431 },
432 }
433 }
434 });
435
436 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
437 .x = dest_offset_0.x,
438 .y = dest_offset_0.y,
439 .width = dest_offset_1.x - dest_offset_0.x,
440 .height = dest_offset_1.y - dest_offset_0.y,
441 .minDepth = 0.0f,
442 .maxDepth = 1.0f
443 });
444
445 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
446 .offset = (VkOffset2D) { MIN2(dest_offset_0.x, dest_offset_1.x), MIN2(dest_offset_0.y, dest_offset_1.y) },
447 .extent = (VkExtent2D) {
448 abs(dest_offset_1.x - dest_offset_0.x),
449 abs(dest_offset_1.y - dest_offset_0.y)
450 },
451 });
452
453 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
454
455 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
456
457 /* At the point where we emit the draw call, all data from the
458 * descriptor sets, etc. has been used. We are free to delete it.
459 */
460 /* TODO: above comment is not valid for at least descriptor sets/pools,
461 * as we may not free them till after execution finishes. Check others. */
462
463 radv_DestroySampler(radv_device_to_handle(device), sampler,
464 &cmd_buffer->pool->alloc);
465 radv_DestroyFramebuffer(radv_device_to_handle(device), fb,
466 &cmd_buffer->pool->alloc);
467 }
468
469 static bool
470 flip_coords(unsigned *src0, unsigned *src1, unsigned *dst0, unsigned *dst1)
471 {
472 bool flip = false;
473 if (*src0 > *src1) {
474 unsigned tmp = *src0;
475 *src0 = *src1;
476 *src1 = tmp;
477 flip = !flip;
478 }
479
480 if (*dst0 > *dst1) {
481 unsigned tmp = *dst0;
482 *dst0 = *dst1;
483 *dst1 = tmp;
484 flip = !flip;
485 }
486 return flip;
487 }
488
489 void radv_CmdBlitImage(
490 VkCommandBuffer commandBuffer,
491 VkImage srcImage,
492 VkImageLayout srcImageLayout,
493 VkImage destImage,
494 VkImageLayout destImageLayout,
495 uint32_t regionCount,
496 const VkImageBlit* pRegions,
497 VkFilter filter)
498
499 {
500 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
501 RADV_FROM_HANDLE(radv_image, src_image, srcImage);
502 RADV_FROM_HANDLE(radv_image, dest_image, destImage);
503 struct radv_meta_saved_state saved_state;
504
505 /* From the Vulkan 1.0 spec:
506 *
507 * vkCmdBlitImage must not be used for multisampled source or
508 * destination images. Use vkCmdResolveImage for this purpose.
509 */
510 assert(src_image->info.samples == 1);
511 assert(dest_image->info.samples == 1);
512
513 radv_meta_save(&saved_state, cmd_buffer,
514 RADV_META_SAVE_GRAPHICS_PIPELINE |
515 RADV_META_SAVE_CONSTANTS |
516 RADV_META_SAVE_DESCRIPTORS);
517
518 for (unsigned r = 0; r < regionCount; r++) {
519 const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
520 const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;
521
522 unsigned dst_start, dst_end;
523 if (dest_image->type == VK_IMAGE_TYPE_3D) {
524 assert(dst_res->baseArrayLayer == 0);
525 dst_start = pRegions[r].dstOffsets[0].z;
526 dst_end = pRegions[r].dstOffsets[1].z;
527 } else {
528 dst_start = dst_res->baseArrayLayer;
529 dst_end = dst_start + dst_res->layerCount;
530 }
531
532 unsigned src_start, src_end;
533 if (src_image->type == VK_IMAGE_TYPE_3D) {
534 assert(src_res->baseArrayLayer == 0);
535 src_start = pRegions[r].srcOffsets[0].z;
536 src_end = pRegions[r].srcOffsets[1].z;
537 } else {
538 src_start = src_res->baseArrayLayer;
539 src_end = src_start + src_res->layerCount;
540 }
541
542 bool flip_z = flip_coords(&src_start, &src_end, &dst_start, &dst_end);
543 float src_z_step = (float)(src_end + 1 - src_start) /
544 (float)(dst_end + 1 - dst_start);
545
546 if (flip_z) {
547 src_start = src_end;
548 src_z_step *= -1;
549 }
550
551 unsigned src_x0 = pRegions[r].srcOffsets[0].x;
552 unsigned src_x1 = pRegions[r].srcOffsets[1].x;
553 unsigned dst_x0 = pRegions[r].dstOffsets[0].x;
554 unsigned dst_x1 = pRegions[r].dstOffsets[1].x;
555
556 unsigned src_y0 = pRegions[r].srcOffsets[0].y;
557 unsigned src_y1 = pRegions[r].srcOffsets[1].y;
558 unsigned dst_y0 = pRegions[r].dstOffsets[0].y;
559 unsigned dst_y1 = pRegions[r].dstOffsets[1].y;
560
561 VkRect2D dest_box;
562 dest_box.offset.x = MIN2(dst_x0, dst_x1);
563 dest_box.offset.y = MIN2(dst_y0, dst_y1);
564 dest_box.extent.width = abs(dst_x1 - dst_x0);
565 dest_box.extent.height = abs(dst_y1 - dst_y0);
566
567 const unsigned num_layers = dst_end - dst_start;
568 for (unsigned i = 0; i < num_layers; i++) {
569 struct radv_image_view dest_iview, src_iview;
570
571 const VkOffset2D dest_offset_0 = {
572 .x = dst_x0,
573 .y = dst_y0,
574 };
575 const VkOffset2D dest_offset_1 = {
576 .x = dst_x1,
577 .y = dst_y1,
578 };
579 VkOffset3D src_offset_0 = {
580 .x = src_x0,
581 .y = src_y0,
582 .z = src_start + i * src_z_step,
583 };
584 VkOffset3D src_offset_1 = {
585 .x = src_x1,
586 .y = src_y1,
587 .z = src_start + i * src_z_step,
588 };
589 const uint32_t dest_array_slice = dst_start + i;
590
591 /* 3D images have just 1 layer */
592 const uint32_t src_array_slice = src_image->type == VK_IMAGE_TYPE_3D ? 0 : src_start + i;
593
594 radv_image_view_init(&dest_iview, cmd_buffer->device,
595 &(VkImageViewCreateInfo) {
596 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
597 .image = destImage,
598 .viewType = radv_meta_get_view_type(dest_image),
599 .format = dest_image->vk_format,
600 .subresourceRange = {
601 .aspectMask = dst_res->aspectMask,
602 .baseMipLevel = dst_res->mipLevel,
603 .levelCount = 1,
604 .baseArrayLayer = dest_array_slice,
605 .layerCount = 1
606 },
607 });
608 radv_image_view_init(&src_iview, cmd_buffer->device,
609 &(VkImageViewCreateInfo) {
610 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
611 .image = srcImage,
612 .viewType = radv_meta_get_view_type(src_image),
613 .format = src_image->vk_format,
614 .subresourceRange = {
615 .aspectMask = src_res->aspectMask,
616 .baseMipLevel = src_res->mipLevel,
617 .levelCount = 1,
618 .baseArrayLayer = src_array_slice,
619 .layerCount = 1
620 },
621 });
622 meta_emit_blit(cmd_buffer,
623 src_image, &src_iview,
624 src_offset_0, src_offset_1,
625 dest_image, &dest_iview,
626 dest_offset_0, dest_offset_1,
627 dest_box,
628 filter);
629 }
630 }
631
632 radv_meta_restore(&saved_state, cmd_buffer);
633 }
634
635 void
636 radv_device_finish_meta_blit_state(struct radv_device *device)
637 {
638 struct radv_meta_state *state = &device->meta_state;
639
640 for (unsigned i = 0; i < NUM_META_FS_KEYS; ++i) {
641 radv_DestroyRenderPass(radv_device_to_handle(device),
642 state->blit.render_pass[i],
643 &state->alloc);
644 radv_DestroyPipeline(radv_device_to_handle(device),
645 state->blit.pipeline_1d_src[i],
646 &state->alloc);
647 radv_DestroyPipeline(radv_device_to_handle(device),
648 state->blit.pipeline_2d_src[i],
649 &state->alloc);
650 radv_DestroyPipeline(radv_device_to_handle(device),
651 state->blit.pipeline_3d_src[i],
652 &state->alloc);
653 }
654
655 radv_DestroyRenderPass(radv_device_to_handle(device),
656 state->blit.depth_only_rp, &state->alloc);
657 radv_DestroyPipeline(radv_device_to_handle(device),
658 state->blit.depth_only_1d_pipeline, &state->alloc);
659 radv_DestroyPipeline(radv_device_to_handle(device),
660 state->blit.depth_only_2d_pipeline, &state->alloc);
661 radv_DestroyPipeline(radv_device_to_handle(device),
662 state->blit.depth_only_3d_pipeline, &state->alloc);
663
664 radv_DestroyRenderPass(radv_device_to_handle(device),
665 state->blit.stencil_only_rp, &state->alloc);
666 radv_DestroyPipeline(radv_device_to_handle(device),
667 state->blit.stencil_only_1d_pipeline,
668 &state->alloc);
669 radv_DestroyPipeline(radv_device_to_handle(device),
670 state->blit.stencil_only_2d_pipeline,
671 &state->alloc);
672 radv_DestroyPipeline(radv_device_to_handle(device),
673 state->blit.stencil_only_3d_pipeline,
674 &state->alloc);
675
676 radv_DestroyPipelineLayout(radv_device_to_handle(device),
677 state->blit.pipeline_layout, &state->alloc);
678 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
679 state->blit.ds_layout, &state->alloc);
680 }
681
682 static VkFormat pipeline_formats[] = {
683 VK_FORMAT_R8G8B8A8_UNORM,
684 VK_FORMAT_R8G8B8A8_UINT,
685 VK_FORMAT_R8G8B8A8_SINT,
686 VK_FORMAT_A2R10G10B10_UINT_PACK32,
687 VK_FORMAT_A2R10G10B10_SINT_PACK32,
688 VK_FORMAT_R16G16B16A16_UNORM,
689 VK_FORMAT_R16G16B16A16_SNORM,
690 VK_FORMAT_R16G16B16A16_UINT,
691 VK_FORMAT_R16G16B16A16_SINT,
692 VK_FORMAT_R32_SFLOAT,
693 VK_FORMAT_R32G32_SFLOAT,
694 VK_FORMAT_R32G32B32A32_SFLOAT
695 };
696
697 static VkResult
698 radv_device_init_meta_blit_color(struct radv_device *device,
699 struct radv_shader_module *vs)
700 {
701 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
702 VkResult result;
703
704 fs_1d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_1D);
705 fs_2d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_2D);
706 fs_3d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_3D);
707
708 for (unsigned i = 0; i < ARRAY_SIZE(pipeline_formats); ++i) {
709 unsigned key = radv_format_meta_fs_key(pipeline_formats[i]);
710 result = radv_CreateRenderPass(radv_device_to_handle(device),
711 &(VkRenderPassCreateInfo) {
712 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
713 .attachmentCount = 1,
714 .pAttachments = &(VkAttachmentDescription) {
715 .format = pipeline_formats[i],
716 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
717 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
718 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
719 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
720 },
721 .subpassCount = 1,
722 .pSubpasses = &(VkSubpassDescription) {
723 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
724 .inputAttachmentCount = 0,
725 .colorAttachmentCount = 1,
726 .pColorAttachments = &(VkAttachmentReference) {
727 .attachment = 0,
728 .layout = VK_IMAGE_LAYOUT_GENERAL,
729 },
730 .pResolveAttachments = NULL,
731 .pDepthStencilAttachment = &(VkAttachmentReference) {
732 .attachment = VK_ATTACHMENT_UNUSED,
733 .layout = VK_IMAGE_LAYOUT_GENERAL,
734 },
735 .preserveAttachmentCount = 1,
736 .pPreserveAttachments = (uint32_t[]) { 0 },
737 },
738 .dependencyCount = 0,
739 }, &device->meta_state.alloc, &device->meta_state.blit.render_pass[key]);
740 if (result != VK_SUCCESS)
741 goto fail;
742
743 VkPipelineVertexInputStateCreateInfo vi_create_info = {
744 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
745 .vertexBindingDescriptionCount = 0,
746 .vertexAttributeDescriptionCount = 0,
747 };
748
749 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
750 {
751 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
752 .stage = VK_SHADER_STAGE_VERTEX_BIT,
753 .module = radv_shader_module_to_handle(vs),
754 .pName = "main",
755 .pSpecializationInfo = NULL
756 }, {
757 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
758 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
759 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
760 .pName = "main",
761 .pSpecializationInfo = NULL
762 },
763 };
764
765 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
766 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
767 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
768 .pStages = pipeline_shader_stages,
769 .pVertexInputState = &vi_create_info,
770 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
771 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
772 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
773 .primitiveRestartEnable = false,
774 },
775 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
776 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
777 .viewportCount = 1,
778 .scissorCount = 1,
779 },
780 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
781 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
782 .rasterizerDiscardEnable = false,
783 .polygonMode = VK_POLYGON_MODE_FILL,
784 .cullMode = VK_CULL_MODE_NONE,
785 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
786 },
787 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
788 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
789 .rasterizationSamples = 1,
790 .sampleShadingEnable = false,
791 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
792 },
793 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
794 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
795 .attachmentCount = 1,
796 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
797 { .colorWriteMask =
798 VK_COLOR_COMPONENT_A_BIT |
799 VK_COLOR_COMPONENT_R_BIT |
800 VK_COLOR_COMPONENT_G_BIT |
801 VK_COLOR_COMPONENT_B_BIT },
802 }
803 },
804 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
805 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
806 .dynamicStateCount = 4,
807 .pDynamicStates = (VkDynamicState[]) {
808 VK_DYNAMIC_STATE_VIEWPORT,
809 VK_DYNAMIC_STATE_SCISSOR,
810 VK_DYNAMIC_STATE_LINE_WIDTH,
811 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
812 },
813 },
814 .flags = 0,
815 .layout = device->meta_state.blit.pipeline_layout,
816 .renderPass = device->meta_state.blit.render_pass[key],
817 .subpass = 0,
818 };
819
820 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
821 .use_rectlist = true
822 };
823
824 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
825 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
826 radv_pipeline_cache_to_handle(&device->meta_state.cache),
827 &vk_pipeline_info, &radv_pipeline_info,
828 &device->meta_state.alloc, &device->meta_state.blit.pipeline_1d_src[key]);
829 if (result != VK_SUCCESS)
830 goto fail;
831
832 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
833 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
834 radv_pipeline_cache_to_handle(&device->meta_state.cache),
835 &vk_pipeline_info, &radv_pipeline_info,
836 &device->meta_state.alloc, &device->meta_state.blit.pipeline_2d_src[key]);
837 if (result != VK_SUCCESS)
838 goto fail;
839
840 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
841 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
842 radv_pipeline_cache_to_handle(&device->meta_state.cache),
843 &vk_pipeline_info, &radv_pipeline_info,
844 &device->meta_state.alloc, &device->meta_state.blit.pipeline_3d_src[key]);
845 if (result != VK_SUCCESS)
846 goto fail;
847
848 }
849
850 result = VK_SUCCESS;
851 fail:
852 ralloc_free(fs_1d.nir);
853 ralloc_free(fs_2d.nir);
854 ralloc_free(fs_3d.nir);
855 return result;
856 }
857
858 static VkResult
859 radv_device_init_meta_blit_depth(struct radv_device *device,
860 struct radv_shader_module *vs)
861 {
862 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
863 VkResult result;
864
865 fs_1d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_1D);
866 fs_2d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_2D);
867 fs_3d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_3D);
868
869 result = radv_CreateRenderPass(radv_device_to_handle(device),
870 &(VkRenderPassCreateInfo) {
871 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
872 .attachmentCount = 1,
873 .pAttachments = &(VkAttachmentDescription) {
874 .format = VK_FORMAT_D32_SFLOAT,
875 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
876 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
877 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
878 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
879 },
880 .subpassCount = 1,
881 .pSubpasses = &(VkSubpassDescription) {
882 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
883 .inputAttachmentCount = 0,
884 .colorAttachmentCount = 0,
885 .pColorAttachments = NULL,
886 .pResolveAttachments = NULL,
887 .pDepthStencilAttachment = &(VkAttachmentReference) {
888 .attachment = 0,
889 .layout = VK_IMAGE_LAYOUT_GENERAL,
890 },
891 .preserveAttachmentCount = 1,
892 .pPreserveAttachments = (uint32_t[]) { 0 },
893 },
894 .dependencyCount = 0,
895 }, &device->meta_state.alloc, &device->meta_state.blit.depth_only_rp);
896 if (result != VK_SUCCESS)
897 goto fail;
898
899 VkPipelineVertexInputStateCreateInfo vi_create_info = {
900 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
901 .vertexBindingDescriptionCount = 0,
902 .vertexAttributeDescriptionCount = 0,
903 };
904
905 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
906 {
907 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
908 .stage = VK_SHADER_STAGE_VERTEX_BIT,
909 .module = radv_shader_module_to_handle(vs),
910 .pName = "main",
911 .pSpecializationInfo = NULL
912 }, {
913 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
914 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
915 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
916 .pName = "main",
917 .pSpecializationInfo = NULL
918 },
919 };
920
921 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
922 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
923 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
924 .pStages = pipeline_shader_stages,
925 .pVertexInputState = &vi_create_info,
926 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
927 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
928 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
929 .primitiveRestartEnable = false,
930 },
931 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
932 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
933 .viewportCount = 1,
934 .scissorCount = 1,
935 },
936 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
937 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
938 .rasterizerDiscardEnable = false,
939 .polygonMode = VK_POLYGON_MODE_FILL,
940 .cullMode = VK_CULL_MODE_NONE,
941 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
942 },
943 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
944 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
945 .rasterizationSamples = 1,
946 .sampleShadingEnable = false,
947 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
948 },
949 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
950 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
951 .attachmentCount = 0,
952 .pAttachments = NULL,
953 },
954 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
955 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
956 .depthTestEnable = true,
957 .depthWriteEnable = true,
958 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
959 },
960 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
961 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
962 .dynamicStateCount = 9,
963 .pDynamicStates = (VkDynamicState[]) {
964 VK_DYNAMIC_STATE_VIEWPORT,
965 VK_DYNAMIC_STATE_SCISSOR,
966 VK_DYNAMIC_STATE_LINE_WIDTH,
967 VK_DYNAMIC_STATE_DEPTH_BIAS,
968 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
969 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
970 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
971 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
972 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
973 },
974 },
975 .flags = 0,
976 .layout = device->meta_state.blit.pipeline_layout,
977 .renderPass = device->meta_state.blit.depth_only_rp,
978 .subpass = 0,
979 };
980
981 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
982 .use_rectlist = true
983 };
984
985 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
986 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
987 radv_pipeline_cache_to_handle(&device->meta_state.cache),
988 &vk_pipeline_info, &radv_pipeline_info,
989 &device->meta_state.alloc, &device->meta_state.blit.depth_only_1d_pipeline);
990 if (result != VK_SUCCESS)
991 goto fail;
992
993 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
994 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
995 radv_pipeline_cache_to_handle(&device->meta_state.cache),
996 &vk_pipeline_info, &radv_pipeline_info,
997 &device->meta_state.alloc, &device->meta_state.blit.depth_only_2d_pipeline);
998 if (result != VK_SUCCESS)
999 goto fail;
1000
1001 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
1002 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1003 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1004 &vk_pipeline_info, &radv_pipeline_info,
1005 &device->meta_state.alloc, &device->meta_state.blit.depth_only_3d_pipeline);
1006 if (result != VK_SUCCESS)
1007 goto fail;
1008
1009 fail:
1010 ralloc_free(fs_1d.nir);
1011 ralloc_free(fs_2d.nir);
1012 ralloc_free(fs_3d.nir);
1013 return result;
1014 }
1015
1016 static VkResult
1017 radv_device_init_meta_blit_stencil(struct radv_device *device,
1018 struct radv_shader_module *vs)
1019 {
1020 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
1021 VkResult result;
1022
1023 fs_1d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_1D);
1024 fs_2d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_2D);
1025 fs_3d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_3D);
1026
1027 result = radv_CreateRenderPass(radv_device_to_handle(device),
1028 &(VkRenderPassCreateInfo) {
1029 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1030 .attachmentCount = 1,
1031 .pAttachments = &(VkAttachmentDescription) {
1032 .format = VK_FORMAT_S8_UINT,
1033 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1034 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1035 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
1036 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
1037 },
1038 .subpassCount = 1,
1039 .pSubpasses = &(VkSubpassDescription) {
1040 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1041 .inputAttachmentCount = 0,
1042 .colorAttachmentCount = 0,
1043 .pColorAttachments = NULL,
1044 .pResolveAttachments = NULL,
1045 .pDepthStencilAttachment = &(VkAttachmentReference) {
1046 .attachment = 0,
1047 .layout = VK_IMAGE_LAYOUT_GENERAL,
1048 },
1049 .preserveAttachmentCount = 1,
1050 .pPreserveAttachments = (uint32_t[]) { 0 },
1051 },
1052 .dependencyCount = 0,
1053 }, &device->meta_state.alloc, &device->meta_state.blit.stencil_only_rp);
1054 if (result != VK_SUCCESS)
1055 goto fail;
1056
1057 VkPipelineVertexInputStateCreateInfo vi_create_info = {
1058 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
1059 .vertexBindingDescriptionCount = 0,
1060 .vertexAttributeDescriptionCount = 0,
1061 };
1062
1063 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
1064 {
1065 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1066 .stage = VK_SHADER_STAGE_VERTEX_BIT,
1067 .module = radv_shader_module_to_handle(vs),
1068 .pName = "main",
1069 .pSpecializationInfo = NULL
1070 }, {
1071 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1072 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
1073 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
1074 .pName = "main",
1075 .pSpecializationInfo = NULL
1076 },
1077 };
1078
1079 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1080 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1081 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
1082 .pStages = pipeline_shader_stages,
1083 .pVertexInputState = &vi_create_info,
1084 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1085 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1086 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1087 .primitiveRestartEnable = false,
1088 },
1089 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
1090 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1091 .viewportCount = 1,
1092 .scissorCount = 1,
1093 },
1094 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1095 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1096 .rasterizerDiscardEnable = false,
1097 .polygonMode = VK_POLYGON_MODE_FILL,
1098 .cullMode = VK_CULL_MODE_NONE,
1099 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1100 },
1101 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1102 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1103 .rasterizationSamples = 1,
1104 .sampleShadingEnable = false,
1105 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1106 },
1107 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1108 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1109 .attachmentCount = 0,
1110 .pAttachments = NULL,
1111 },
1112 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1113 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1114 .depthTestEnable = false,
1115 .depthWriteEnable = false,
1116 .stencilTestEnable = true,
1117 .front = {
1118 .failOp = VK_STENCIL_OP_REPLACE,
1119 .passOp = VK_STENCIL_OP_REPLACE,
1120 .depthFailOp = VK_STENCIL_OP_REPLACE,
1121 .compareOp = VK_COMPARE_OP_ALWAYS,
1122 .compareMask = 0xff,
1123 .writeMask = 0xff,
1124 .reference = 0
1125 },
1126 .back = {
1127 .failOp = VK_STENCIL_OP_REPLACE,
1128 .passOp = VK_STENCIL_OP_REPLACE,
1129 .depthFailOp = VK_STENCIL_OP_REPLACE,
1130 .compareOp = VK_COMPARE_OP_ALWAYS,
1131 .compareMask = 0xff,
1132 .writeMask = 0xff,
1133 .reference = 0
1134 },
1135 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
1136 },
1137
1138 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1139 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1140 .dynamicStateCount = 6,
1141 .pDynamicStates = (VkDynamicState[]) {
1142 VK_DYNAMIC_STATE_VIEWPORT,
1143 VK_DYNAMIC_STATE_SCISSOR,
1144 VK_DYNAMIC_STATE_LINE_WIDTH,
1145 VK_DYNAMIC_STATE_DEPTH_BIAS,
1146 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1147 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1148 },
1149 },
1150 .flags = 0,
1151 .layout = device->meta_state.blit.pipeline_layout,
1152 .renderPass = device->meta_state.blit.stencil_only_rp,
1153 .subpass = 0,
1154 };
1155
1156 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1157 .use_rectlist = true
1158 };
1159
1160 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
1161 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1162 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1163 &vk_pipeline_info, &radv_pipeline_info,
1164 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_1d_pipeline);
1165 if (result != VK_SUCCESS)
1166 goto fail;
1167
1168 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
1169 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1170 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1171 &vk_pipeline_info, &radv_pipeline_info,
1172 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_2d_pipeline);
1173 if (result != VK_SUCCESS)
1174 goto fail;
1175
1176 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
1177 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1178 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1179 &vk_pipeline_info, &radv_pipeline_info,
1180 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_3d_pipeline);
1181 if (result != VK_SUCCESS)
1182 goto fail;
1183
1184 fail:
1185 ralloc_free(fs_1d.nir);
1186 ralloc_free(fs_2d.nir);
1187 ralloc_free(fs_3d.nir);
1188 return result;
1189 }
1190
1191 VkResult
1192 radv_device_init_meta_blit_state(struct radv_device *device)
1193 {
1194 VkResult result;
1195 struct radv_shader_module vs = {0};
1196
1197 VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1198 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1199 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1200 .bindingCount = 1,
1201 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1202 {
1203 .binding = 0,
1204 .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
1205 .descriptorCount = 1,
1206 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1207 .pImmutableSamplers = NULL
1208 },
1209 }
1210 };
1211 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1212 &ds_layout_info,
1213 &device->meta_state.alloc,
1214 &device->meta_state.blit.ds_layout);
1215 if (result != VK_SUCCESS)
1216 goto fail;
1217
1218 const VkPushConstantRange push_constant_range = {VK_SHADER_STAGE_VERTEX_BIT, 0, 20};
1219
1220 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1221 &(VkPipelineLayoutCreateInfo) {
1222 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1223 .setLayoutCount = 1,
1224 .pSetLayouts = &device->meta_state.blit.ds_layout,
1225 .pushConstantRangeCount = 1,
1226 .pPushConstantRanges = &push_constant_range,
1227 },
1228 &device->meta_state.alloc, &device->meta_state.blit.pipeline_layout);
1229 if (result != VK_SUCCESS)
1230 goto fail;
1231
1232 vs.nir = build_nir_vertex_shader();
1233
1234 result = radv_device_init_meta_blit_color(device, &vs);
1235 if (result != VK_SUCCESS)
1236 goto fail;
1237
1238 result = radv_device_init_meta_blit_depth(device, &vs);
1239 if (result != VK_SUCCESS)
1240 goto fail;
1241
1242 result = radv_device_init_meta_blit_stencil(device, &vs);
1243
1244 fail:
1245 ralloc_free(vs.nir);
1246 if (result != VK_SUCCESS)
1247 radv_device_finish_meta_blit_state(device);
1248 return result;
1249 }