radv: implement VK_AMD_shader_explicit_vertex_parameter
[mesa.git] / src / amd / vulkan / radv_meta_blit2d.c
1 /*
2 * Copyright © 2016 Red Hat
3 *
4 * based on anv driver:
5 * Copyright © 2016 Intel Corporation
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * IN THE SOFTWARE.
25 */
26
27 #include "radv_meta.h"
28 #include "nir/nir_builder.h"
29 #include "vk_format.h"
30
31 enum blit2d_src_type {
32 BLIT2D_SRC_TYPE_IMAGE,
33 BLIT2D_SRC_TYPE_IMAGE_3D,
34 BLIT2D_SRC_TYPE_BUFFER,
35 BLIT2D_NUM_SRC_TYPES,
36 };
37
38 static VkResult
39 blit2d_init_color_pipeline(struct radv_device *device,
40 enum blit2d_src_type src_type,
41 VkFormat format,
42 uint32_t log2_samples);
43
44 static VkResult
45 blit2d_init_depth_only_pipeline(struct radv_device *device,
46 enum blit2d_src_type src_type,
47 uint32_t log2_samples);
48
49 static VkResult
50 blit2d_init_stencil_only_pipeline(struct radv_device *device,
51 enum blit2d_src_type src_type,
52 uint32_t log2_samples);
53
54 static void
55 create_iview(struct radv_cmd_buffer *cmd_buffer,
56 struct radv_meta_blit2d_surf *surf,
57 struct radv_image_view *iview, VkFormat depth_format,
58 VkImageAspectFlagBits aspects)
59 {
60 VkFormat format;
61 VkImageViewType view_type = cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 ? VK_IMAGE_VIEW_TYPE_2D :
62 radv_meta_get_view_type(surf->image);
63
64 if (depth_format)
65 format = depth_format;
66 else
67 format = surf->format;
68
69 radv_image_view_init(iview, cmd_buffer->device,
70 &(VkImageViewCreateInfo) {
71 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
72 .image = radv_image_to_handle(surf->image),
73 .viewType = view_type,
74 .format = format,
75 .subresourceRange = {
76 .aspectMask = aspects,
77 .baseMipLevel = surf->level,
78 .levelCount = 1,
79 .baseArrayLayer = surf->layer,
80 .layerCount = 1
81 },
82 }, NULL);
83 }
84
85 static void
86 create_bview(struct radv_cmd_buffer *cmd_buffer,
87 struct radv_meta_blit2d_buffer *src,
88 struct radv_buffer_view *bview, VkFormat depth_format)
89 {
90 VkFormat format;
91
92 if (depth_format)
93 format = depth_format;
94 else
95 format = src->format;
96 radv_buffer_view_init(bview, cmd_buffer->device,
97 &(VkBufferViewCreateInfo) {
98 .sType = VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO,
99 .flags = 0,
100 .buffer = radv_buffer_to_handle(src->buffer),
101 .format = format,
102 .offset = src->offset,
103 .range = VK_WHOLE_SIZE,
104 });
105
106 }
107
108 struct blit2d_src_temps {
109 struct radv_image_view iview;
110 struct radv_buffer_view bview;
111 };
112
113 static void
114 blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
115 struct radv_meta_blit2d_surf *src_img,
116 struct radv_meta_blit2d_buffer *src_buf,
117 struct blit2d_src_temps *tmp,
118 enum blit2d_src_type src_type, VkFormat depth_format,
119 VkImageAspectFlagBits aspects,
120 uint32_t log2_samples)
121 {
122 struct radv_device *device = cmd_buffer->device;
123
124 if (src_type == BLIT2D_SRC_TYPE_BUFFER) {
125 create_bview(cmd_buffer, src_buf, &tmp->bview, depth_format);
126
127 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
128 device->meta_state.blit2d[log2_samples].p_layouts[src_type],
129 0, /* set */
130 1, /* descriptorWriteCount */
131 (VkWriteDescriptorSet[]) {
132 {
133 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
134 .dstBinding = 0,
135 .dstArrayElement = 0,
136 .descriptorCount = 1,
137 .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
138 .pTexelBufferView = (VkBufferView[]) { radv_buffer_view_to_handle(&tmp->bview) }
139 }
140 });
141
142 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
143 device->meta_state.blit2d[log2_samples].p_layouts[src_type],
144 VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4,
145 &src_buf->pitch);
146 } else {
147 create_iview(cmd_buffer, src_img, &tmp->iview, depth_format, aspects);
148
149 if (src_type == BLIT2D_SRC_TYPE_IMAGE_3D)
150 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
151 device->meta_state.blit2d[log2_samples].p_layouts[src_type],
152 VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4,
153 &src_img->layer);
154
155 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
156 device->meta_state.blit2d[log2_samples].p_layouts[src_type],
157 0, /* set */
158 1, /* descriptorWriteCount */
159 (VkWriteDescriptorSet[]) {
160 {
161 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
162 .dstBinding = 0,
163 .dstArrayElement = 0,
164 .descriptorCount = 1,
165 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
166 .pImageInfo = (VkDescriptorImageInfo[]) {
167 {
168 .sampler = VK_NULL_HANDLE,
169 .imageView = radv_image_view_to_handle(&tmp->iview),
170 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
171 },
172 }
173 }
174 });
175 }
176 }
177
178 struct blit2d_dst_temps {
179 VkImage image;
180 struct radv_image_view iview;
181 VkFramebuffer fb;
182 };
183
184 static void
185 blit2d_bind_dst(struct radv_cmd_buffer *cmd_buffer,
186 struct radv_meta_blit2d_surf *dst,
187 uint32_t width,
188 uint32_t height,
189 VkFormat depth_format,
190 struct blit2d_dst_temps *tmp,
191 VkImageAspectFlagBits aspects)
192 {
193 create_iview(cmd_buffer, dst, &tmp->iview, depth_format, aspects);
194
195 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer->device),
196 &(VkFramebufferCreateInfo) {
197 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
198 .attachmentCount = 1,
199 .pAttachments = (VkImageView[]) {
200 radv_image_view_to_handle(&tmp->iview),
201 },
202 .width = width,
203 .height = height,
204 .layers = 1
205 }, &cmd_buffer->pool->alloc, &tmp->fb);
206 }
207
208 static void
209 bind_pipeline(struct radv_cmd_buffer *cmd_buffer,
210 enum blit2d_src_type src_type, unsigned fs_key,
211 uint32_t log2_samples)
212 {
213 VkPipeline pipeline =
214 cmd_buffer->device->meta_state.blit2d[log2_samples].pipelines[src_type][fs_key];
215
216 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
217 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
218 }
219
220 static void
221 bind_depth_pipeline(struct radv_cmd_buffer *cmd_buffer,
222 enum blit2d_src_type src_type,
223 uint32_t log2_samples)
224 {
225 VkPipeline pipeline =
226 cmd_buffer->device->meta_state.blit2d[log2_samples].depth_only_pipeline[src_type];
227
228 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
229 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
230 }
231
232 static void
233 bind_stencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
234 enum blit2d_src_type src_type,
235 uint32_t log2_samples)
236 {
237 VkPipeline pipeline =
238 cmd_buffer->device->meta_state.blit2d[log2_samples].stencil_only_pipeline[src_type];
239
240 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
241 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
242 }
243
244 static void
245 radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
246 struct radv_meta_blit2d_surf *src_img,
247 struct radv_meta_blit2d_buffer *src_buf,
248 struct radv_meta_blit2d_surf *dst,
249 unsigned num_rects,
250 struct radv_meta_blit2d_rect *rects, enum blit2d_src_type src_type,
251 uint32_t log2_samples)
252 {
253 struct radv_device *device = cmd_buffer->device;
254
255 for (unsigned r = 0; r < num_rects; ++r) {
256 unsigned i;
257 for_each_bit(i, dst->aspect_mask) {
258 unsigned aspect_mask = 1u << i;
259 unsigned src_aspect_mask = aspect_mask;
260 VkFormat depth_format = 0;
261 if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT)
262 depth_format = vk_format_stencil_only(dst->image->vk_format);
263 else if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT)
264 depth_format = vk_format_depth_only(dst->image->vk_format);
265 else if (src_img)
266 src_aspect_mask = src_img->aspect_mask;
267
268 struct blit2d_src_temps src_temps;
269 blit2d_bind_src(cmd_buffer, src_img, src_buf, &src_temps, src_type, depth_format, src_aspect_mask, log2_samples);
270
271 struct blit2d_dst_temps dst_temps;
272 blit2d_bind_dst(cmd_buffer, dst, rects[r].dst_x + rects[r].width,
273 rects[r].dst_y + rects[r].height, depth_format, &dst_temps, aspect_mask);
274
275 float vertex_push_constants[4] = {
276 rects[r].src_x,
277 rects[r].src_y,
278 rects[r].src_x + rects[r].width,
279 rects[r].src_y + rects[r].height,
280 };
281
282 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
283 device->meta_state.blit2d[log2_samples].p_layouts[src_type],
284 VK_SHADER_STAGE_VERTEX_BIT, 0, 16,
285 vertex_push_constants);
286
287 if (aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT ||
288 aspect_mask == VK_IMAGE_ASPECT_PLANE_0_BIT ||
289 aspect_mask == VK_IMAGE_ASPECT_PLANE_1_BIT ||
290 aspect_mask == VK_IMAGE_ASPECT_PLANE_2_BIT) {
291 unsigned fs_key = radv_format_meta_fs_key(dst_temps.iview.vk_format);
292 unsigned dst_layout = radv_meta_dst_layout_from_layout(dst->current_layout);
293
294 if (device->meta_state.blit2d[log2_samples].pipelines[src_type][fs_key] == VK_NULL_HANDLE) {
295 VkResult ret = blit2d_init_color_pipeline(device, src_type, radv_fs_key_format_exemplars[fs_key], log2_samples);
296 if (ret != VK_SUCCESS) {
297 cmd_buffer->record_result = ret;
298 goto fail_pipeline;
299 }
300 }
301
302 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
303 &(VkRenderPassBeginInfo) {
304 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
305 .renderPass = device->meta_state.blit2d_render_passes[fs_key][dst_layout],
306 .framebuffer = dst_temps.fb,
307 .renderArea = {
308 .offset = { rects[r].dst_x, rects[r].dst_y, },
309 .extent = { rects[r].width, rects[r].height },
310 },
311 .clearValueCount = 0,
312 .pClearValues = NULL,
313 }, VK_SUBPASS_CONTENTS_INLINE);
314
315
316 bind_pipeline(cmd_buffer, src_type, fs_key, log2_samples);
317 } else if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
318 enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dst->current_layout);
319
320 if (device->meta_state.blit2d[log2_samples].depth_only_pipeline[src_type] == VK_NULL_HANDLE) {
321 VkResult ret = blit2d_init_depth_only_pipeline(device, src_type, log2_samples);
322 if (ret != VK_SUCCESS) {
323 cmd_buffer->record_result = ret;
324 goto fail_pipeline;
325 }
326 }
327
328 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
329 &(VkRenderPassBeginInfo) {
330 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
331 .renderPass = device->meta_state.blit2d_depth_only_rp[ds_layout],
332 .framebuffer = dst_temps.fb,
333 .renderArea = {
334 .offset = { rects[r].dst_x, rects[r].dst_y, },
335 .extent = { rects[r].width, rects[r].height },
336 },
337 .clearValueCount = 0,
338 .pClearValues = NULL,
339 }, VK_SUBPASS_CONTENTS_INLINE);
340
341
342 bind_depth_pipeline(cmd_buffer, src_type, log2_samples);
343
344 } else if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
345 enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dst->current_layout);
346
347 if (device->meta_state.blit2d[log2_samples].stencil_only_pipeline[src_type] == VK_NULL_HANDLE) {
348 VkResult ret = blit2d_init_stencil_only_pipeline(device, src_type, log2_samples);
349 if (ret != VK_SUCCESS) {
350 cmd_buffer->record_result = ret;
351 goto fail_pipeline;
352 }
353 }
354
355 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
356 &(VkRenderPassBeginInfo) {
357 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
358 .renderPass = device->meta_state.blit2d_stencil_only_rp[ds_layout],
359 .framebuffer = dst_temps.fb,
360 .renderArea = {
361 .offset = { rects[r].dst_x, rects[r].dst_y, },
362 .extent = { rects[r].width, rects[r].height },
363 },
364 .clearValueCount = 0,
365 .pClearValues = NULL,
366 }, VK_SUBPASS_CONTENTS_INLINE);
367
368
369 bind_stencil_pipeline(cmd_buffer, src_type, log2_samples);
370 } else
371 unreachable("Processing blit2d with multiple aspects.");
372
373 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
374 .x = rects[r].dst_x,
375 .y = rects[r].dst_y,
376 .width = rects[r].width,
377 .height = rects[r].height,
378 .minDepth = 0.0f,
379 .maxDepth = 1.0f
380 });
381
382 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
383 .offset = (VkOffset2D) { rects[r].dst_x, rects[r].dst_y },
384 .extent = (VkExtent2D) { rects[r].width, rects[r].height },
385 });
386
387
388
389 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
390 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
391
392 fail_pipeline:
393 /* At the point where we emit the draw call, all data from the
394 * descriptor sets, etc. has been used. We are free to delete it.
395 */
396 radv_DestroyFramebuffer(radv_device_to_handle(device),
397 dst_temps.fb,
398 &cmd_buffer->pool->alloc);
399 }
400 }
401 }
402
403 void
404 radv_meta_blit2d(struct radv_cmd_buffer *cmd_buffer,
405 struct radv_meta_blit2d_surf *src_img,
406 struct radv_meta_blit2d_buffer *src_buf,
407 struct radv_meta_blit2d_surf *dst,
408 unsigned num_rects,
409 struct radv_meta_blit2d_rect *rects)
410 {
411 bool use_3d = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
412 (src_img && src_img->image->type == VK_IMAGE_TYPE_3D);
413 enum blit2d_src_type src_type = src_buf ? BLIT2D_SRC_TYPE_BUFFER :
414 use_3d ? BLIT2D_SRC_TYPE_IMAGE_3D : BLIT2D_SRC_TYPE_IMAGE;
415 radv_meta_blit2d_normal_dst(cmd_buffer, src_img, src_buf, dst,
416 num_rects, rects, src_type,
417 src_img ? util_logbase2(src_img->image->info.samples) : 0);
418 }
419
420 static nir_shader *
421 build_nir_vertex_shader(void)
422 {
423 const struct glsl_type *vec4 = glsl_vec4_type();
424 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
425 nir_builder b;
426
427 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
428 b.shader->info.name = ralloc_strdup(b.shader, "meta_blit2d_vs");
429
430 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
431 vec4, "gl_Position");
432 pos_out->data.location = VARYING_SLOT_POS;
433
434 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
435 vec2, "v_tex_pos");
436 tex_pos_out->data.location = VARYING_SLOT_VAR0;
437 tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
438
439 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
440 nir_store_var(&b, pos_out, outvec, 0xf);
441
442 nir_intrinsic_instr *src_box = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
443 src_box->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
444 nir_intrinsic_set_base(src_box, 0);
445 nir_intrinsic_set_range(src_box, 16);
446 src_box->num_components = 4;
447 nir_ssa_dest_init(&src_box->instr, &src_box->dest, 4, 32, "src_box");
448 nir_builder_instr_insert(&b, &src_box->instr);
449
450 nir_intrinsic_instr *vertex_id = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_vertex_id_zero_base);
451 nir_ssa_dest_init(&vertex_id->instr, &vertex_id->dest, 1, 32, "vertexid");
452 nir_builder_instr_insert(&b, &vertex_id->instr);
453
454 /* vertex 0 - src_x, src_y */
455 /* vertex 1 - src_x, src_y+h */
456 /* vertex 2 - src_x+w, src_y */
457 /* so channel 0 is vertex_id != 2 ? src_x : src_x + w
458 channel 1 is vertex id != 1 ? src_y : src_y + w */
459
460 nir_ssa_def *c0cmp = nir_ine(&b, &vertex_id->dest.ssa,
461 nir_imm_int(&b, 2));
462 nir_ssa_def *c1cmp = nir_ine(&b, &vertex_id->dest.ssa,
463 nir_imm_int(&b, 1));
464
465 nir_ssa_def *comp[2];
466 comp[0] = nir_bcsel(&b, c0cmp,
467 nir_channel(&b, &src_box->dest.ssa, 0),
468 nir_channel(&b, &src_box->dest.ssa, 2));
469
470 comp[1] = nir_bcsel(&b, c1cmp,
471 nir_channel(&b, &src_box->dest.ssa, 1),
472 nir_channel(&b, &src_box->dest.ssa, 3));
473 nir_ssa_def *out_tex_vec = nir_vec(&b, comp, 2);
474 nir_store_var(&b, tex_pos_out, out_tex_vec, 0x3);
475 return b.shader;
476 }
477
478 typedef nir_ssa_def* (*texel_fetch_build_func)(struct nir_builder *,
479 struct radv_device *,
480 nir_ssa_def *, bool, bool);
481
482 static nir_ssa_def *
483 build_nir_texel_fetch(struct nir_builder *b, struct radv_device *device,
484 nir_ssa_def *tex_pos, bool is_3d, bool is_multisampled)
485 {
486 enum glsl_sampler_dim dim =
487 is_3d ? GLSL_SAMPLER_DIM_3D : is_multisampled ? GLSL_SAMPLER_DIM_MS : GLSL_SAMPLER_DIM_2D;
488 const struct glsl_type *sampler_type =
489 glsl_sampler_type(dim, false, false, GLSL_TYPE_UINT);
490 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
491 sampler_type, "s_tex");
492 sampler->data.descriptor_set = 0;
493 sampler->data.binding = 0;
494
495 nir_ssa_def *tex_pos_3d = NULL;
496 nir_intrinsic_instr *sample_idx = NULL;
497 if (is_3d) {
498 nir_intrinsic_instr *layer = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
499 nir_intrinsic_set_base(layer, 16);
500 nir_intrinsic_set_range(layer, 4);
501 layer->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
502 layer->num_components = 1;
503 nir_ssa_dest_init(&layer->instr, &layer->dest, 1, 32, "layer");
504 nir_builder_instr_insert(b, &layer->instr);
505
506 nir_ssa_def *chans[3];
507 chans[0] = nir_channel(b, tex_pos, 0);
508 chans[1] = nir_channel(b, tex_pos, 1);
509 chans[2] = &layer->dest.ssa;
510 tex_pos_3d = nir_vec(b, chans, 3);
511 }
512 if (is_multisampled) {
513 sample_idx = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_sample_id);
514 sample_idx->num_components = 1;
515 nir_ssa_dest_init(&sample_idx->instr, &sample_idx->dest, 1, 32, "sample_idx");
516 nir_builder_instr_insert(b, &sample_idx->instr);
517 }
518
519 nir_ssa_def *tex_deref = &nir_build_deref_var(b, sampler)->dest.ssa;
520
521 nir_tex_instr *tex = nir_tex_instr_create(b->shader, is_multisampled ? 4 : 3);
522 tex->sampler_dim = dim;
523 tex->op = is_multisampled ? nir_texop_txf_ms : nir_texop_txf;
524 tex->src[0].src_type = nir_tex_src_coord;
525 tex->src[0].src = nir_src_for_ssa(is_3d ? tex_pos_3d : tex_pos);
526 tex->src[1].src_type = is_multisampled ? nir_tex_src_ms_index : nir_tex_src_lod;
527 tex->src[1].src = nir_src_for_ssa(is_multisampled ? &sample_idx->dest.ssa : nir_imm_int(b, 0));
528 tex->src[2].src_type = nir_tex_src_texture_deref;
529 tex->src[2].src = nir_src_for_ssa(tex_deref);
530 if (is_multisampled) {
531 tex->src[3].src_type = nir_tex_src_lod;
532 tex->src[3].src = nir_src_for_ssa(nir_imm_int(b, 0));
533 }
534 tex->dest_type = nir_type_uint;
535 tex->is_array = false;
536 tex->coord_components = is_3d ? 3 : 2;
537
538 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
539 nir_builder_instr_insert(b, &tex->instr);
540
541 return &tex->dest.ssa;
542 }
543
544
545 static nir_ssa_def *
546 build_nir_buffer_fetch(struct nir_builder *b, struct radv_device *device,
547 nir_ssa_def *tex_pos, bool is_3d, bool is_multisampled)
548 {
549 const struct glsl_type *sampler_type =
550 glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_UINT);
551 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
552 sampler_type, "s_tex");
553 sampler->data.descriptor_set = 0;
554 sampler->data.binding = 0;
555
556 nir_intrinsic_instr *width = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
557 nir_intrinsic_set_base(width, 16);
558 nir_intrinsic_set_range(width, 4);
559 width->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
560 width->num_components = 1;
561 nir_ssa_dest_init(&width->instr, &width->dest, 1, 32, "width");
562 nir_builder_instr_insert(b, &width->instr);
563
564 nir_ssa_def *pos_x = nir_channel(b, tex_pos, 0);
565 nir_ssa_def *pos_y = nir_channel(b, tex_pos, 1);
566 pos_y = nir_imul(b, pos_y, &width->dest.ssa);
567 pos_x = nir_iadd(b, pos_x, pos_y);
568
569 nir_ssa_def *tex_deref = &nir_build_deref_var(b, sampler)->dest.ssa;
570
571 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 2);
572 tex->sampler_dim = GLSL_SAMPLER_DIM_BUF;
573 tex->op = nir_texop_txf;
574 tex->src[0].src_type = nir_tex_src_coord;
575 tex->src[0].src = nir_src_for_ssa(pos_x);
576 tex->src[1].src_type = nir_tex_src_texture_deref;
577 tex->src[1].src = nir_src_for_ssa(tex_deref);
578 tex->dest_type = nir_type_uint;
579 tex->is_array = false;
580 tex->coord_components = 1;
581
582 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
583 nir_builder_instr_insert(b, &tex->instr);
584
585 return &tex->dest.ssa;
586 }
587
588 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
589 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
590 .vertexBindingDescriptionCount = 0,
591 .vertexAttributeDescriptionCount = 0,
592 };
593
594 static nir_shader *
595 build_nir_copy_fragment_shader(struct radv_device *device,
596 texel_fetch_build_func txf_func, const char* name, bool is_3d,
597 bool is_multisampled)
598 {
599 const struct glsl_type *vec4 = glsl_vec4_type();
600 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
601 nir_builder b;
602
603 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
604 b.shader->info.name = ralloc_strdup(b.shader, name);
605
606 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
607 vec2, "v_tex_pos");
608 tex_pos_in->data.location = VARYING_SLOT_VAR0;
609
610 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
611 vec4, "f_color");
612 color_out->data.location = FRAG_RESULT_DATA0;
613
614 nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
615 nir_ssa_def *tex_pos = nir_channels(&b, pos_int, 0x3);
616
617 nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d, is_multisampled);
618 nir_store_var(&b, color_out, color, 0xf);
619
620 return b.shader;
621 }
622
623 static nir_shader *
624 build_nir_copy_fragment_shader_depth(struct radv_device *device,
625 texel_fetch_build_func txf_func, const char* name, bool is_3d,
626 bool is_multisampled)
627 {
628 const struct glsl_type *vec4 = glsl_vec4_type();
629 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
630 nir_builder b;
631
632 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
633 b.shader->info.name = ralloc_strdup(b.shader, name);
634
635 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
636 vec2, "v_tex_pos");
637 tex_pos_in->data.location = VARYING_SLOT_VAR0;
638
639 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
640 vec4, "f_color");
641 color_out->data.location = FRAG_RESULT_DEPTH;
642
643 nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
644 nir_ssa_def *tex_pos = nir_channels(&b, pos_int, 0x3);
645
646 nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d, is_multisampled);
647 nir_store_var(&b, color_out, color, 0x1);
648
649 return b.shader;
650 }
651
652 static nir_shader *
653 build_nir_copy_fragment_shader_stencil(struct radv_device *device,
654 texel_fetch_build_func txf_func, const char* name, bool is_3d,
655 bool is_multisampled)
656 {
657 const struct glsl_type *vec4 = glsl_vec4_type();
658 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
659 nir_builder b;
660
661 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
662 b.shader->info.name = ralloc_strdup(b.shader, name);
663
664 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
665 vec2, "v_tex_pos");
666 tex_pos_in->data.location = VARYING_SLOT_VAR0;
667
668 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
669 vec4, "f_color");
670 color_out->data.location = FRAG_RESULT_STENCIL;
671
672 nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
673 nir_ssa_def *tex_pos = nir_channels(&b, pos_int, 0x3);
674
675 nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d, is_multisampled);
676 nir_store_var(&b, color_out, color, 0x1);
677
678 return b.shader;
679 }
680
681 void
682 radv_device_finish_meta_blit2d_state(struct radv_device *device)
683 {
684 struct radv_meta_state *state = &device->meta_state;
685
686 for(unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
687 for (unsigned k = 0; k < RADV_META_DST_LAYOUT_COUNT; ++k) {
688 radv_DestroyRenderPass(radv_device_to_handle(device),
689 state->blit2d_render_passes[j][k],
690 &state->alloc);
691 }
692 }
693
694 for (enum radv_blit_ds_layout j = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; j < RADV_BLIT_DS_LAYOUT_COUNT; j++) {
695 radv_DestroyRenderPass(radv_device_to_handle(device),
696 state->blit2d_depth_only_rp[j], &state->alloc);
697 radv_DestroyRenderPass(radv_device_to_handle(device),
698 state->blit2d_stencil_only_rp[j], &state->alloc);
699 }
700
701 for (unsigned log2_samples = 0; log2_samples < MAX_SAMPLES_LOG2; ++log2_samples) {
702 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
703 radv_DestroyPipelineLayout(radv_device_to_handle(device),
704 state->blit2d[log2_samples].p_layouts[src],
705 &state->alloc);
706 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
707 state->blit2d[log2_samples].ds_layouts[src],
708 &state->alloc);
709
710 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
711 radv_DestroyPipeline(radv_device_to_handle(device),
712 state->blit2d[log2_samples].pipelines[src][j],
713 &state->alloc);
714 }
715
716 radv_DestroyPipeline(radv_device_to_handle(device),
717 state->blit2d[log2_samples].depth_only_pipeline[src],
718 &state->alloc);
719 radv_DestroyPipeline(radv_device_to_handle(device),
720 state->blit2d[log2_samples].stencil_only_pipeline[src],
721 &state->alloc);
722 }
723 }
724 }
725
726 static VkResult
727 blit2d_init_color_pipeline(struct radv_device *device,
728 enum blit2d_src_type src_type,
729 VkFormat format,
730 uint32_t log2_samples)
731 {
732 VkResult result;
733 unsigned fs_key = radv_format_meta_fs_key(format);
734 const char *name;
735
736 mtx_lock(&device->meta_state.mtx);
737 if (device->meta_state.blit2d[log2_samples].pipelines[src_type][fs_key]) {
738 mtx_unlock(&device->meta_state.mtx);
739 return VK_SUCCESS;
740 }
741
742 texel_fetch_build_func src_func;
743 switch(src_type) {
744 case BLIT2D_SRC_TYPE_IMAGE:
745 src_func = build_nir_texel_fetch;
746 name = "meta_blit2d_image_fs";
747 break;
748 case BLIT2D_SRC_TYPE_IMAGE_3D:
749 src_func = build_nir_texel_fetch;
750 name = "meta_blit3d_image_fs";
751 break;
752 case BLIT2D_SRC_TYPE_BUFFER:
753 src_func = build_nir_buffer_fetch;
754 name = "meta_blit2d_buffer_fs";
755 break;
756 default:
757 unreachable("unknown blit src type\n");
758 break;
759 }
760
761 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
762 struct radv_shader_module fs = { .nir = NULL };
763
764
765 fs.nir = build_nir_copy_fragment_shader(device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D, log2_samples > 0);
766 vi_create_info = &normal_vi_create_info;
767
768 struct radv_shader_module vs = {
769 .nir = build_nir_vertex_shader(),
770 };
771
772 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
773 {
774 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
775 .stage = VK_SHADER_STAGE_VERTEX_BIT,
776 .module = radv_shader_module_to_handle(&vs),
777 .pName = "main",
778 .pSpecializationInfo = NULL
779 }, {
780 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
781 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
782 .module = radv_shader_module_to_handle(&fs),
783 .pName = "main",
784 .pSpecializationInfo = NULL
785 },
786 };
787
788 for (unsigned dst_layout = 0; dst_layout < RADV_META_DST_LAYOUT_COUNT; ++dst_layout) {
789 if (!device->meta_state.blit2d_render_passes[fs_key][dst_layout]) {
790 VkImageLayout layout = radv_meta_dst_layout_to_layout(dst_layout);
791
792 result = radv_CreateRenderPass(radv_device_to_handle(device),
793 &(VkRenderPassCreateInfo) {
794 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
795 .attachmentCount = 1,
796 .pAttachments = &(VkAttachmentDescription) {
797 .format = format,
798 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
799 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
800 .initialLayout = layout,
801 .finalLayout = layout,
802 },
803 .subpassCount = 1,
804 .pSubpasses = &(VkSubpassDescription) {
805 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
806 .inputAttachmentCount = 0,
807 .colorAttachmentCount = 1,
808 .pColorAttachments = &(VkAttachmentReference) {
809 .attachment = 0,
810 .layout = layout,
811 },
812 .pResolveAttachments = NULL,
813 .pDepthStencilAttachment = &(VkAttachmentReference) {
814 .attachment = VK_ATTACHMENT_UNUSED,
815 .layout = layout,
816 },
817 .preserveAttachmentCount = 0,
818 .pPreserveAttachments = NULL,
819 },
820 .dependencyCount = 2,
821 .pDependencies = (VkSubpassDependency[]) {
822 {
823 .srcSubpass = VK_SUBPASS_EXTERNAL,
824 .dstSubpass = 0,
825 .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
826 .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
827 .srcAccessMask = 0,
828 .dstAccessMask = 0,
829 .dependencyFlags = 0
830 },
831 {
832 .srcSubpass = 0,
833 .dstSubpass = VK_SUBPASS_EXTERNAL,
834 .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
835 .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
836 .srcAccessMask = 0,
837 .dstAccessMask = 0,
838 .dependencyFlags = 0
839 }
840 },
841 }, &device->meta_state.alloc, &device->meta_state.blit2d_render_passes[fs_key][dst_layout]);
842 }
843 }
844
845 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
846 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
847 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
848 .pStages = pipeline_shader_stages,
849 .pVertexInputState = vi_create_info,
850 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
851 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
852 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
853 .primitiveRestartEnable = false,
854 },
855 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
856 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
857 .viewportCount = 1,
858 .scissorCount = 1,
859 },
860 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
861 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
862 .rasterizerDiscardEnable = false,
863 .polygonMode = VK_POLYGON_MODE_FILL,
864 .cullMode = VK_CULL_MODE_NONE,
865 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
866 },
867 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
868 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
869 .rasterizationSamples = 1 << log2_samples,
870 .sampleShadingEnable = log2_samples > 1,
871 .minSampleShading = 1.0,
872 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
873 },
874 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
875 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
876 .attachmentCount = 1,
877 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
878 { .colorWriteMask =
879 VK_COLOR_COMPONENT_A_BIT |
880 VK_COLOR_COMPONENT_R_BIT |
881 VK_COLOR_COMPONENT_G_BIT |
882 VK_COLOR_COMPONENT_B_BIT },
883 }
884 },
885 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
886 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
887 .dynamicStateCount = 9,
888 .pDynamicStates = (VkDynamicState[]) {
889 VK_DYNAMIC_STATE_VIEWPORT,
890 VK_DYNAMIC_STATE_SCISSOR,
891 VK_DYNAMIC_STATE_LINE_WIDTH,
892 VK_DYNAMIC_STATE_DEPTH_BIAS,
893 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
894 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
895 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
896 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
897 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
898 },
899 },
900 .flags = 0,
901 .layout = device->meta_state.blit2d[log2_samples].p_layouts[src_type],
902 .renderPass = device->meta_state.blit2d_render_passes[fs_key][0],
903 .subpass = 0,
904 };
905
906 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
907 .use_rectlist = true
908 };
909
910 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
911 radv_pipeline_cache_to_handle(&device->meta_state.cache),
912 &vk_pipeline_info, &radv_pipeline_info,
913 &device->meta_state.alloc,
914 &device->meta_state.blit2d[log2_samples].pipelines[src_type][fs_key]);
915
916
917 ralloc_free(vs.nir);
918 ralloc_free(fs.nir);
919
920 mtx_unlock(&device->meta_state.mtx);
921 return result;
922 }
923
924 static VkResult
925 blit2d_init_depth_only_pipeline(struct radv_device *device,
926 enum blit2d_src_type src_type,
927 uint32_t log2_samples)
928 {
929 VkResult result;
930 const char *name;
931
932 mtx_lock(&device->meta_state.mtx);
933 if (device->meta_state.blit2d[log2_samples].depth_only_pipeline[src_type]) {
934 mtx_unlock(&device->meta_state.mtx);
935 return VK_SUCCESS;
936 }
937
938 texel_fetch_build_func src_func;
939 switch(src_type) {
940 case BLIT2D_SRC_TYPE_IMAGE:
941 src_func = build_nir_texel_fetch;
942 name = "meta_blit2d_depth_image_fs";
943 break;
944 case BLIT2D_SRC_TYPE_IMAGE_3D:
945 src_func = build_nir_texel_fetch;
946 name = "meta_blit3d_depth_image_fs";
947 break;
948 case BLIT2D_SRC_TYPE_BUFFER:
949 src_func = build_nir_buffer_fetch;
950 name = "meta_blit2d_depth_buffer_fs";
951 break;
952 default:
953 unreachable("unknown blit src type\n");
954 break;
955 }
956
957 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
958 struct radv_shader_module fs = { .nir = NULL };
959
960 fs.nir = build_nir_copy_fragment_shader_depth(device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D, log2_samples > 0);
961 vi_create_info = &normal_vi_create_info;
962
963 struct radv_shader_module vs = {
964 .nir = build_nir_vertex_shader(),
965 };
966
967 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
968 {
969 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
970 .stage = VK_SHADER_STAGE_VERTEX_BIT,
971 .module = radv_shader_module_to_handle(&vs),
972 .pName = "main",
973 .pSpecializationInfo = NULL
974 }, {
975 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
976 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
977 .module = radv_shader_module_to_handle(&fs),
978 .pName = "main",
979 .pSpecializationInfo = NULL
980 },
981 };
982
983 for (enum radv_blit_ds_layout ds_layout = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; ds_layout < RADV_BLIT_DS_LAYOUT_COUNT; ds_layout++) {
984 if (!device->meta_state.blit2d_depth_only_rp[ds_layout]) {
985 VkImageLayout layout = radv_meta_blit_ds_to_layout(ds_layout);
986 result = radv_CreateRenderPass(radv_device_to_handle(device),
987 &(VkRenderPassCreateInfo) {
988 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
989 .attachmentCount = 1,
990 .pAttachments = &(VkAttachmentDescription) {
991 .format = VK_FORMAT_D32_SFLOAT,
992 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
993 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
994 .initialLayout = layout,
995 .finalLayout = layout,
996 },
997 .subpassCount = 1,
998 .pSubpasses = &(VkSubpassDescription) {
999 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1000 .inputAttachmentCount = 0,
1001 .colorAttachmentCount = 0,
1002 .pColorAttachments = NULL,
1003 .pResolveAttachments = NULL,
1004 .pDepthStencilAttachment = &(VkAttachmentReference) {
1005 .attachment = 0,
1006 .layout = layout,
1007 },
1008 .preserveAttachmentCount = 0,
1009 .pPreserveAttachments = NULL,
1010 },
1011 .dependencyCount = 2,
1012 .pDependencies = (VkSubpassDependency[]) {
1013 {
1014 .srcSubpass = VK_SUBPASS_EXTERNAL,
1015 .dstSubpass = 0,
1016 .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
1017 .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
1018 .srcAccessMask = 0,
1019 .dstAccessMask = 0,
1020 .dependencyFlags = 0
1021 },
1022 {
1023 .srcSubpass = 0,
1024 .dstSubpass = VK_SUBPASS_EXTERNAL,
1025 .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
1026 .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
1027 .srcAccessMask = 0,
1028 .dstAccessMask = 0,
1029 .dependencyFlags = 0
1030 }
1031 },
1032 }, &device->meta_state.alloc, &device->meta_state.blit2d_depth_only_rp[ds_layout]);
1033 }
1034 }
1035
1036 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1037 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1038 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
1039 .pStages = pipeline_shader_stages,
1040 .pVertexInputState = vi_create_info,
1041 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1042 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1043 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1044 .primitiveRestartEnable = false,
1045 },
1046 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
1047 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1048 .viewportCount = 1,
1049 .scissorCount = 1,
1050 },
1051 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1052 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1053 .rasterizerDiscardEnable = false,
1054 .polygonMode = VK_POLYGON_MODE_FILL,
1055 .cullMode = VK_CULL_MODE_NONE,
1056 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1057 },
1058 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1059 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1060 .rasterizationSamples = 1 << log2_samples,
1061 .sampleShadingEnable = false,
1062 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1063 },
1064 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1065 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1066 .attachmentCount = 0,
1067 .pAttachments = NULL,
1068 },
1069 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1070 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1071 .depthTestEnable = true,
1072 .depthWriteEnable = true,
1073 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
1074 },
1075 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1076 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1077 .dynamicStateCount = 9,
1078 .pDynamicStates = (VkDynamicState[]) {
1079 VK_DYNAMIC_STATE_VIEWPORT,
1080 VK_DYNAMIC_STATE_SCISSOR,
1081 VK_DYNAMIC_STATE_LINE_WIDTH,
1082 VK_DYNAMIC_STATE_DEPTH_BIAS,
1083 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1084 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1085 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
1086 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
1087 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
1088 },
1089 },
1090 .flags = 0,
1091 .layout = device->meta_state.blit2d[log2_samples].p_layouts[src_type],
1092 .renderPass = device->meta_state.blit2d_depth_only_rp[0],
1093 .subpass = 0,
1094 };
1095
1096 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1097 .use_rectlist = true
1098 };
1099
1100 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1101 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1102 &vk_pipeline_info, &radv_pipeline_info,
1103 &device->meta_state.alloc,
1104 &device->meta_state.blit2d[log2_samples].depth_only_pipeline[src_type]);
1105
1106
1107 ralloc_free(vs.nir);
1108 ralloc_free(fs.nir);
1109
1110 mtx_unlock(&device->meta_state.mtx);
1111 return result;
1112 }
1113
1114 static VkResult
1115 blit2d_init_stencil_only_pipeline(struct radv_device *device,
1116 enum blit2d_src_type src_type,
1117 uint32_t log2_samples)
1118 {
1119 VkResult result;
1120 const char *name;
1121
1122 mtx_lock(&device->meta_state.mtx);
1123 if (device->meta_state.blit2d[log2_samples].stencil_only_pipeline[src_type]) {
1124 mtx_unlock(&device->meta_state.mtx);
1125 return VK_SUCCESS;
1126 }
1127
1128 texel_fetch_build_func src_func;
1129 switch(src_type) {
1130 case BLIT2D_SRC_TYPE_IMAGE:
1131 src_func = build_nir_texel_fetch;
1132 name = "meta_blit2d_stencil_image_fs";
1133 break;
1134 case BLIT2D_SRC_TYPE_IMAGE_3D:
1135 src_func = build_nir_texel_fetch;
1136 name = "meta_blit3d_stencil_image_fs";
1137 break;
1138 case BLIT2D_SRC_TYPE_BUFFER:
1139 src_func = build_nir_buffer_fetch;
1140 name = "meta_blit2d_stencil_buffer_fs";
1141 break;
1142 default:
1143 unreachable("unknown blit src type\n");
1144 break;
1145 }
1146
1147 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
1148 struct radv_shader_module fs = { .nir = NULL };
1149
1150 fs.nir = build_nir_copy_fragment_shader_stencil(device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D, log2_samples > 0);
1151 vi_create_info = &normal_vi_create_info;
1152
1153 struct radv_shader_module vs = {
1154 .nir = build_nir_vertex_shader(),
1155 };
1156
1157 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
1158 {
1159 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1160 .stage = VK_SHADER_STAGE_VERTEX_BIT,
1161 .module = radv_shader_module_to_handle(&vs),
1162 .pName = "main",
1163 .pSpecializationInfo = NULL
1164 }, {
1165 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1166 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
1167 .module = radv_shader_module_to_handle(&fs),
1168 .pName = "main",
1169 .pSpecializationInfo = NULL
1170 },
1171 };
1172
1173 for (enum radv_blit_ds_layout ds_layout = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; ds_layout < RADV_BLIT_DS_LAYOUT_COUNT; ds_layout++) {
1174 if (!device->meta_state.blit2d_stencil_only_rp[ds_layout]) {
1175 VkImageLayout layout = radv_meta_blit_ds_to_layout(ds_layout);
1176 result = radv_CreateRenderPass(radv_device_to_handle(device),
1177 &(VkRenderPassCreateInfo) {
1178 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1179 .attachmentCount = 1,
1180 .pAttachments = &(VkAttachmentDescription) {
1181 .format = VK_FORMAT_S8_UINT,
1182 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1183 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1184 .initialLayout = layout,
1185 .finalLayout = layout,
1186 },
1187 .subpassCount = 1,
1188 .pSubpasses = &(VkSubpassDescription) {
1189 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1190 .inputAttachmentCount = 0,
1191 .colorAttachmentCount = 0,
1192 .pColorAttachments = NULL,
1193 .pResolveAttachments = NULL,
1194 .pDepthStencilAttachment = &(VkAttachmentReference) {
1195 .attachment = 0,
1196 .layout = layout,
1197 },
1198 .preserveAttachmentCount = 0,
1199 .pPreserveAttachments = NULL,
1200 },
1201 .dependencyCount = 2,
1202 .pDependencies = (VkSubpassDependency[]) {
1203 {
1204 .srcSubpass = VK_SUBPASS_EXTERNAL,
1205 .dstSubpass = 0,
1206 .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
1207 .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
1208 .srcAccessMask = 0,
1209 .dstAccessMask = 0,
1210 .dependencyFlags = 0
1211 },
1212 {
1213 .srcSubpass = 0,
1214 .dstSubpass = VK_SUBPASS_EXTERNAL,
1215 .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
1216 .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
1217 .srcAccessMask = 0,
1218 .dstAccessMask = 0,
1219 .dependencyFlags = 0
1220 }
1221 },
1222 }, &device->meta_state.alloc, &device->meta_state.blit2d_stencil_only_rp[ds_layout]);
1223 }
1224 }
1225
1226 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1227 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1228 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
1229 .pStages = pipeline_shader_stages,
1230 .pVertexInputState = vi_create_info,
1231 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1232 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1233 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1234 .primitiveRestartEnable = false,
1235 },
1236 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
1237 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1238 .viewportCount = 1,
1239 .scissorCount = 1,
1240 },
1241 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1242 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1243 .rasterizerDiscardEnable = false,
1244 .polygonMode = VK_POLYGON_MODE_FILL,
1245 .cullMode = VK_CULL_MODE_NONE,
1246 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1247 },
1248 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1249 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1250 .rasterizationSamples = 1 << log2_samples,
1251 .sampleShadingEnable = false,
1252 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1253 },
1254 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1255 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1256 .attachmentCount = 0,
1257 .pAttachments = NULL,
1258 },
1259 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1260 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1261 .depthTestEnable = false,
1262 .depthWriteEnable = false,
1263 .stencilTestEnable = true,
1264 .front = {
1265 .failOp = VK_STENCIL_OP_REPLACE,
1266 .passOp = VK_STENCIL_OP_REPLACE,
1267 .depthFailOp = VK_STENCIL_OP_REPLACE,
1268 .compareOp = VK_COMPARE_OP_ALWAYS,
1269 .compareMask = 0xff,
1270 .writeMask = 0xff,
1271 .reference = 0
1272 },
1273 .back = {
1274 .failOp = VK_STENCIL_OP_REPLACE,
1275 .passOp = VK_STENCIL_OP_REPLACE,
1276 .depthFailOp = VK_STENCIL_OP_REPLACE,
1277 .compareOp = VK_COMPARE_OP_ALWAYS,
1278 .compareMask = 0xff,
1279 .writeMask = 0xff,
1280 .reference = 0
1281 },
1282 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
1283 },
1284 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1285 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1286 .dynamicStateCount = 6,
1287 .pDynamicStates = (VkDynamicState[]) {
1288 VK_DYNAMIC_STATE_VIEWPORT,
1289 VK_DYNAMIC_STATE_SCISSOR,
1290 VK_DYNAMIC_STATE_LINE_WIDTH,
1291 VK_DYNAMIC_STATE_DEPTH_BIAS,
1292 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1293 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1294 },
1295 },
1296 .flags = 0,
1297 .layout = device->meta_state.blit2d[log2_samples].p_layouts[src_type],
1298 .renderPass = device->meta_state.blit2d_stencil_only_rp[0],
1299 .subpass = 0,
1300 };
1301
1302 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1303 .use_rectlist = true
1304 };
1305
1306 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1307 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1308 &vk_pipeline_info, &radv_pipeline_info,
1309 &device->meta_state.alloc,
1310 &device->meta_state.blit2d[log2_samples].stencil_only_pipeline[src_type]);
1311
1312
1313 ralloc_free(vs.nir);
1314 ralloc_free(fs.nir);
1315
1316 mtx_unlock(&device->meta_state.mtx);
1317 return result;
1318 }
1319
1320 static VkResult
1321 meta_blit2d_create_pipe_layout(struct radv_device *device,
1322 int idx,
1323 uint32_t log2_samples)
1324 {
1325 VkResult result;
1326 VkDescriptorType desc_type = (idx == BLIT2D_SRC_TYPE_BUFFER) ? VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER : VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE;
1327 const VkPushConstantRange push_constant_ranges[] = {
1328 {VK_SHADER_STAGE_VERTEX_BIT, 0, 16},
1329 {VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4},
1330 };
1331 int num_push_constant_range = (idx != BLIT2D_SRC_TYPE_IMAGE || log2_samples > 0) ? 2 : 1;
1332
1333 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1334 &(VkDescriptorSetLayoutCreateInfo) {
1335 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1336 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1337 .bindingCount = 1,
1338 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1339 {
1340 .binding = 0,
1341 .descriptorType = desc_type,
1342 .descriptorCount = 1,
1343 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1344 .pImmutableSamplers = NULL
1345 },
1346 }
1347 }, &device->meta_state.alloc, &device->meta_state.blit2d[log2_samples].ds_layouts[idx]);
1348 if (result != VK_SUCCESS)
1349 goto fail;
1350
1351 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1352 &(VkPipelineLayoutCreateInfo) {
1353 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1354 .setLayoutCount = 1,
1355 .pSetLayouts = &device->meta_state.blit2d[log2_samples].ds_layouts[idx],
1356 .pushConstantRangeCount = num_push_constant_range,
1357 .pPushConstantRanges = push_constant_ranges,
1358 },
1359 &device->meta_state.alloc, &device->meta_state.blit2d[log2_samples].p_layouts[idx]);
1360 if (result != VK_SUCCESS)
1361 goto fail;
1362 return VK_SUCCESS;
1363 fail:
1364 return result;
1365 }
1366
1367 VkResult
1368 radv_device_init_meta_blit2d_state(struct radv_device *device, bool on_demand)
1369 {
1370 VkResult result;
1371 bool create_3d = device->physical_device->rad_info.chip_class >= GFX9;
1372
1373 for (unsigned log2_samples = 0; log2_samples < MAX_SAMPLES_LOG2; log2_samples++) {
1374 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
1375 if (src == BLIT2D_SRC_TYPE_IMAGE_3D && !create_3d)
1376 continue;
1377
1378 /* Don't need to handle copies between buffers and multisample images. */
1379 if (src == BLIT2D_SRC_TYPE_BUFFER && log2_samples > 0)
1380 continue;
1381
1382 result = meta_blit2d_create_pipe_layout(device, src, log2_samples);
1383 if (result != VK_SUCCESS)
1384 goto fail;
1385
1386 if (on_demand)
1387 continue;
1388
1389 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
1390 result = blit2d_init_color_pipeline(device, src, radv_fs_key_format_exemplars[j], log2_samples);
1391 if (result != VK_SUCCESS)
1392 goto fail;
1393 }
1394
1395 result = blit2d_init_depth_only_pipeline(device, src, log2_samples);
1396 if (result != VK_SUCCESS)
1397 goto fail;
1398
1399 result = blit2d_init_stencil_only_pipeline(device, src, log2_samples);
1400 if (result != VK_SUCCESS)
1401 goto fail;
1402 }
1403 }
1404
1405 return VK_SUCCESS;
1406
1407 fail:
1408 radv_device_finish_meta_blit2d_state(device);
1409 return result;
1410 }