2 * Copyright © 2016 Red Hat
5 * Copyright © 2016 Intel Corporation
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "radv_meta.h"
28 #include "nir/nir_builder.h"
29 #include "vk_format.h"
31 enum blit2d_dst_type
{
32 /* We can bind this destination as a "normal" render target and render
33 * to it just like you would anywhere else.
35 BLIT2D_DST_TYPE_NORMAL
,
37 /* The destination has a 3-channel RGB format. Since we can't render to
38 * non-power-of-two textures, we have to bind it as a red texture and
39 * select the correct component for the given red pixel in the shader.
47 enum blit2d_src_type
{
48 BLIT2D_SRC_TYPE_IMAGE
,
49 BLIT2D_SRC_TYPE_BUFFER
,
54 create_iview(struct radv_cmd_buffer
*cmd_buffer
,
55 struct radv_meta_blit2d_surf
*surf
,
56 VkImageUsageFlags usage
,
57 struct radv_image_view
*iview
, VkFormat depth_format
)
62 format
= depth_format
;
64 format
= surf
->format
;
66 radv_image_view_init(iview
, cmd_buffer
->device
,
67 &(VkImageViewCreateInfo
) {
68 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
69 .image
= radv_image_to_handle(surf
->image
),
70 .viewType
= VK_IMAGE_VIEW_TYPE_2D
,
73 .aspectMask
= surf
->aspect_mask
,
74 .baseMipLevel
= surf
->level
,
76 .baseArrayLayer
= surf
->layer
,
79 }, cmd_buffer
, usage
);
83 create_bview(struct radv_cmd_buffer
*cmd_buffer
,
84 struct radv_meta_blit2d_buffer
*src
,
85 struct radv_buffer_view
*bview
, VkFormat depth_format
)
90 format
= depth_format
;
93 radv_buffer_view_init(bview
, cmd_buffer
->device
,
94 &(VkBufferViewCreateInfo
) {
95 .sType
= VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO
,
97 .buffer
= radv_buffer_to_handle(src
->buffer
),
99 .offset
= src
->offset
,
100 .range
= VK_WHOLE_SIZE
,
105 struct blit2d_src_temps
{
106 struct radv_image_view iview
;
109 struct radv_buffer_view bview
;
113 blit2d_bind_src(struct radv_cmd_buffer
*cmd_buffer
,
114 struct radv_meta_blit2d_surf
*src_img
,
115 struct radv_meta_blit2d_buffer
*src_buf
,
116 struct blit2d_src_temps
*tmp
,
117 enum blit2d_src_type src_type
, VkFormat depth_format
)
119 struct radv_device
*device
= cmd_buffer
->device
;
120 VkDevice vk_device
= radv_device_to_handle(cmd_buffer
->device
);
122 if (src_type
== BLIT2D_SRC_TYPE_BUFFER
) {
123 create_bview(cmd_buffer
, src_buf
, &tmp
->bview
, depth_format
);
125 radv_temp_descriptor_set_create(cmd_buffer
->device
, cmd_buffer
,
126 device
->meta_state
.blit2d
.ds_layouts
[src_type
],
129 radv_UpdateDescriptorSets(vk_device
,
131 (VkWriteDescriptorSet
[]) {
133 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
136 .dstArrayElement
= 0,
137 .descriptorCount
= 1,
138 .descriptorType
= VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
,
139 .pTexelBufferView
= (VkBufferView
[]) { radv_buffer_view_to_handle(&tmp
->bview
) }
143 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
144 device
->meta_state
.blit2d
.p_layouts
[src_type
],
145 VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 4,
148 create_iview(cmd_buffer
, src_img
, VK_IMAGE_USAGE_SAMPLED_BIT
, &tmp
->iview
,
151 radv_temp_descriptor_set_create(cmd_buffer
->device
, cmd_buffer
,
152 device
->meta_state
.blit2d
.ds_layouts
[src_type
],
155 radv_UpdateDescriptorSets(vk_device
,
157 (VkWriteDescriptorSet
[]) {
159 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
162 .dstArrayElement
= 0,
163 .descriptorCount
= 1,
164 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
165 .pImageInfo
= (VkDescriptorImageInfo
[]) {
167 .sampler
= VK_NULL_HANDLE
,
168 .imageView
= radv_image_view_to_handle(&tmp
->iview
),
169 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
177 radv_CmdBindDescriptorSets(radv_cmd_buffer_to_handle(cmd_buffer
),
178 VK_PIPELINE_BIND_POINT_GRAPHICS
,
179 device
->meta_state
.blit2d
.p_layouts
[src_type
], 0, 1,
184 blit2d_unbind_src(struct radv_cmd_buffer
*cmd_buffer
,
185 struct blit2d_src_temps
*tmp
,
186 enum blit2d_src_type src_type
)
188 radv_temp_descriptor_set_destroy(cmd_buffer
->device
, tmp
->set
);
191 struct blit2d_dst_temps
{
193 struct radv_image_view iview
;
198 blit2d_bind_dst(struct radv_cmd_buffer
*cmd_buffer
,
199 struct radv_meta_blit2d_surf
*dst
,
202 VkFormat depth_format
,
203 struct blit2d_dst_temps
*tmp
)
205 VkImageUsageFlagBits bits
;
207 if (dst
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
)
208 bits
= VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
;
210 bits
= VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
;
212 create_iview(cmd_buffer
, dst
, bits
,
213 &tmp
->iview
, depth_format
);
215 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer
->device
),
216 &(VkFramebufferCreateInfo
) {
217 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
218 .attachmentCount
= 1,
219 .pAttachments
= (VkImageView
[]) {
220 radv_image_view_to_handle(&tmp
->iview
),
225 }, &cmd_buffer
->pool
->alloc
, &tmp
->fb
);
229 blit2d_unbind_dst(struct radv_cmd_buffer
*cmd_buffer
,
230 struct blit2d_dst_temps
*tmp
)
232 VkDevice vk_device
= radv_device_to_handle(cmd_buffer
->device
);
233 radv_DestroyFramebuffer(vk_device
, tmp
->fb
, &cmd_buffer
->pool
->alloc
);
237 bind_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
238 enum blit2d_src_type src_type
, unsigned fs_key
)
240 VkPipeline pipeline
=
241 cmd_buffer
->device
->meta_state
.blit2d
.pipelines
[src_type
][fs_key
];
243 if (cmd_buffer
->state
.pipeline
!= radv_pipeline_from_handle(pipeline
)) {
244 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
245 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
250 bind_depth_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
251 enum blit2d_src_type src_type
)
253 VkPipeline pipeline
=
254 cmd_buffer
->device
->meta_state
.blit2d
.depth_only_pipeline
[src_type
];
256 if (cmd_buffer
->state
.pipeline
!= radv_pipeline_from_handle(pipeline
)) {
257 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
258 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
263 bind_stencil_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
264 enum blit2d_src_type src_type
)
266 VkPipeline pipeline
=
267 cmd_buffer
->device
->meta_state
.blit2d
.stencil_only_pipeline
[src_type
];
269 if (cmd_buffer
->state
.pipeline
!= radv_pipeline_from_handle(pipeline
)) {
270 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
271 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
276 radv_meta_blit2d_normal_dst(struct radv_cmd_buffer
*cmd_buffer
,
277 struct radv_meta_blit2d_surf
*src_img
,
278 struct radv_meta_blit2d_buffer
*src_buf
,
279 struct radv_meta_blit2d_surf
*dst
,
281 struct radv_meta_blit2d_rect
*rects
, enum blit2d_src_type src_type
)
283 struct radv_device
*device
= cmd_buffer
->device
;
285 for (unsigned r
= 0; r
< num_rects
; ++r
) {
286 VkFormat depth_format
= 0;
287 if (dst
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
)
288 depth_format
= vk_format_stencil_only(dst
->image
->vk_format
);
289 else if (dst
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
)
290 depth_format
= vk_format_depth_only(dst
->image
->vk_format
);
291 struct blit2d_src_temps src_temps
;
292 blit2d_bind_src(cmd_buffer
, src_img
, src_buf
, &src_temps
, src_type
, depth_format
);
295 struct blit2d_dst_temps dst_temps
;
296 blit2d_bind_dst(cmd_buffer
, dst
, rects
[r
].dst_x
+ rects
[r
].width
,
297 rects
[r
].dst_y
+ rects
[r
].height
, depth_format
, &dst_temps
);
299 struct blit_vb_data
{
304 unsigned vb_size
= 3 * sizeof(*vb_data
);
306 vb_data
[0] = (struct blit_vb_data
) {
317 vb_data
[1] = (struct blit_vb_data
) {
320 rects
[r
].dst_y
+ rects
[r
].height
,
324 rects
[r
].src_y
+ rects
[r
].height
,
328 vb_data
[2] = (struct blit_vb_data
) {
330 rects
[r
].dst_x
+ rects
[r
].width
,
334 rects
[r
].src_x
+ rects
[r
].width
,
340 radv_cmd_buffer_upload_data(cmd_buffer
, vb_size
, 16, vb_data
, &offset
);
342 struct radv_buffer vertex_buffer
= {
345 .bo
= cmd_buffer
->upload
.upload_bo
,
349 radv_CmdBindVertexBuffers(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1,
351 radv_buffer_to_handle(&vertex_buffer
),
358 if (dst
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
) {
359 unsigned fs_key
= radv_format_meta_fs_key(dst_temps
.iview
.vk_format
);
361 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
362 &(VkRenderPassBeginInfo
) {
363 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
364 .renderPass
= device
->meta_state
.blit2d
.render_passes
[fs_key
],
365 .framebuffer
= dst_temps
.fb
,
367 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
368 .extent
= { rects
[r
].width
, rects
[r
].height
},
370 .clearValueCount
= 0,
371 .pClearValues
= NULL
,
372 }, VK_SUBPASS_CONTENTS_INLINE
);
375 bind_pipeline(cmd_buffer
, src_type
, fs_key
);
376 } else if (dst
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
377 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
378 &(VkRenderPassBeginInfo
) {
379 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
380 .renderPass
= device
->meta_state
.blit2d
.depth_only_rp
,
381 .framebuffer
= dst_temps
.fb
,
383 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
384 .extent
= { rects
[r
].width
, rects
[r
].height
},
386 .clearValueCount
= 0,
387 .pClearValues
= NULL
,
388 }, VK_SUBPASS_CONTENTS_INLINE
);
391 bind_depth_pipeline(cmd_buffer
, src_type
);
393 } else if (dst
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
394 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
395 &(VkRenderPassBeginInfo
) {
396 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
397 .renderPass
= device
->meta_state
.blit2d
.stencil_only_rp
,
398 .framebuffer
= dst_temps
.fb
,
400 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
401 .extent
= { rects
[r
].width
, rects
[r
].height
},
403 .clearValueCount
= 0,
404 .pClearValues
= NULL
,
405 }, VK_SUBPASS_CONTENTS_INLINE
);
408 bind_stencil_pipeline(cmd_buffer
, src_type
);
411 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer
), 3, 1, 0, 0);
412 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
));
414 /* At the point where we emit the draw call, all data from the
415 * descriptor sets, etc. has been used. We are free to delete it.
417 blit2d_unbind_src(cmd_buffer
, &src_temps
, src_type
);
418 blit2d_unbind_dst(cmd_buffer
, &dst_temps
);
423 radv_meta_blit2d(struct radv_cmd_buffer
*cmd_buffer
,
424 struct radv_meta_blit2d_surf
*src_img
,
425 struct radv_meta_blit2d_buffer
*src_buf
,
426 struct radv_meta_blit2d_surf
*dst
,
428 struct radv_meta_blit2d_rect
*rects
)
430 enum blit2d_src_type src_type
= src_buf
? BLIT2D_SRC_TYPE_BUFFER
:
431 BLIT2D_SRC_TYPE_IMAGE
;
432 radv_meta_blit2d_normal_dst(cmd_buffer
, src_img
, src_buf
, dst
,
433 num_rects
, rects
, src_type
);
437 build_nir_vertex_shader(void)
439 const struct glsl_type
*vec4
= glsl_vec4_type();
440 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
443 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
444 b
.shader
->info
->name
= ralloc_strdup(b
.shader
, "meta_blit_vs");
446 nir_variable
*pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
448 pos_in
->data
.location
= VERT_ATTRIB_GENERIC0
;
449 nir_variable
*pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
450 vec4
, "gl_Position");
451 pos_out
->data
.location
= VARYING_SLOT_POS
;
452 nir_copy_var(&b
, pos_out
, pos_in
);
454 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
456 tex_pos_in
->data
.location
= VERT_ATTRIB_GENERIC1
;
457 nir_variable
*tex_pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
459 tex_pos_out
->data
.location
= VARYING_SLOT_VAR0
;
460 tex_pos_out
->data
.interpolation
= INTERP_MODE_SMOOTH
;
461 nir_copy_var(&b
, tex_pos_out
, tex_pos_in
);
466 typedef nir_ssa_def
* (*texel_fetch_build_func
)(struct nir_builder
*,
467 struct radv_device
*,
471 build_nir_texel_fetch(struct nir_builder
*b
, struct radv_device
*device
,
472 nir_ssa_def
*tex_pos
)
474 const struct glsl_type
*sampler_type
=
475 glsl_sampler_type(GLSL_SAMPLER_DIM_2D
, false, false, GLSL_TYPE_UINT
);
476 nir_variable
*sampler
= nir_variable_create(b
->shader
, nir_var_uniform
,
477 sampler_type
, "s_tex");
478 sampler
->data
.descriptor_set
= 0;
479 sampler
->data
.binding
= 0;
481 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, 2);
482 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
483 tex
->op
= nir_texop_txf
;
484 tex
->src
[0].src_type
= nir_tex_src_coord
;
485 tex
->src
[0].src
= nir_src_for_ssa(tex_pos
);
486 tex
->src
[1].src_type
= nir_tex_src_lod
;
487 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
488 tex
->dest_type
= nir_type_uint
;
489 tex
->is_array
= false;
490 tex
->coord_components
= 2;
491 tex
->texture
= nir_deref_var_create(tex
, sampler
);
494 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
495 nir_builder_instr_insert(b
, &tex
->instr
);
497 return &tex
->dest
.ssa
;
502 build_nir_buffer_fetch(struct nir_builder
*b
, struct radv_device
*device
,
503 nir_ssa_def
*tex_pos
)
505 const struct glsl_type
*sampler_type
=
506 glsl_sampler_type(GLSL_SAMPLER_DIM_BUF
, false, false, GLSL_TYPE_UINT
);
507 nir_variable
*sampler
= nir_variable_create(b
->shader
, nir_var_uniform
,
508 sampler_type
, "s_tex");
509 sampler
->data
.descriptor_set
= 0;
510 sampler
->data
.binding
= 0;
512 nir_intrinsic_instr
*width
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_push_constant
);
513 width
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, 0));
514 width
->num_components
= 1;
515 nir_ssa_dest_init(&width
->instr
, &width
->dest
, 1, 32, "width");
516 nir_builder_instr_insert(b
, &width
->instr
);
518 nir_ssa_def
*pos_x
= nir_channel(b
, tex_pos
, 0);
519 nir_ssa_def
*pos_y
= nir_channel(b
, tex_pos
, 1);
520 pos_y
= nir_imul(b
, pos_y
, &width
->dest
.ssa
);
521 pos_x
= nir_iadd(b
, pos_x
, pos_y
);
522 //pos_x = nir_iadd(b, pos_x, nir_imm_int(b, 100000));
524 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, 1);
525 tex
->sampler_dim
= GLSL_SAMPLER_DIM_BUF
;
526 tex
->op
= nir_texop_txf
;
527 tex
->src
[0].src_type
= nir_tex_src_coord
;
528 tex
->src
[0].src
= nir_src_for_ssa(pos_x
);
529 tex
->dest_type
= nir_type_uint
;
530 tex
->is_array
= false;
531 tex
->coord_components
= 1;
532 tex
->texture
= nir_deref_var_create(tex
, sampler
);
535 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
536 nir_builder_instr_insert(b
, &tex
->instr
);
538 return &tex
->dest
.ssa
;
541 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info
= {
542 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
543 .vertexBindingDescriptionCount
= 1,
544 .pVertexBindingDescriptions
= (VkVertexInputBindingDescription
[]) {
547 .stride
= 4 * sizeof(float),
548 .inputRate
= VK_VERTEX_INPUT_RATE_VERTEX
551 .vertexAttributeDescriptionCount
= 2,
552 .pVertexAttributeDescriptions
= (VkVertexInputAttributeDescription
[]) {
557 .format
= VK_FORMAT_R32G32_SFLOAT
,
561 /* Texture Coordinate */
564 .format
= VK_FORMAT_R32G32_SFLOAT
,
571 build_nir_copy_fragment_shader(struct radv_device
*device
,
572 texel_fetch_build_func txf_func
, const char* name
)
574 const struct glsl_type
*vec4
= glsl_vec4_type();
575 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
578 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
579 b
.shader
->info
->name
= ralloc_strdup(b
.shader
, name
);
581 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
583 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
585 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
587 color_out
->data
.location
= FRAG_RESULT_DATA0
;
589 nir_ssa_def
*pos_int
= nir_f2i(&b
, nir_load_var(&b
, tex_pos_in
));
590 unsigned swiz
[4] = { 0, 1 };
591 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
593 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
);
594 nir_store_var(&b
, color_out
, color
, 0xf);
600 build_nir_copy_fragment_shader_depth(struct radv_device
*device
,
601 texel_fetch_build_func txf_func
, const char* name
)
603 const struct glsl_type
*vec4
= glsl_vec4_type();
604 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
607 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
608 b
.shader
->info
->name
= ralloc_strdup(b
.shader
, name
);
610 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
612 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
614 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
616 color_out
->data
.location
= FRAG_RESULT_DEPTH
;
618 nir_ssa_def
*pos_int
= nir_f2i(&b
, nir_load_var(&b
, tex_pos_in
));
619 unsigned swiz
[4] = { 0, 1 };
620 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
622 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
);
623 nir_store_var(&b
, color_out
, color
, 0x1);
629 build_nir_copy_fragment_shader_stencil(struct radv_device
*device
,
630 texel_fetch_build_func txf_func
, const char* name
)
632 const struct glsl_type
*vec4
= glsl_vec4_type();
633 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
636 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
637 b
.shader
->info
->name
= ralloc_strdup(b
.shader
, name
);
639 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
641 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
643 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
645 color_out
->data
.location
= FRAG_RESULT_STENCIL
;
647 nir_ssa_def
*pos_int
= nir_f2i(&b
, nir_load_var(&b
, tex_pos_in
));
648 unsigned swiz
[4] = { 0, 1 };
649 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
651 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
);
652 nir_store_var(&b
, color_out
, color
, 0x1);
658 radv_device_finish_meta_blit2d_state(struct radv_device
*device
)
660 for(unsigned j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
661 if (device
->meta_state
.blit2d
.render_passes
[j
]) {
662 radv_DestroyRenderPass(radv_device_to_handle(device
),
663 device
->meta_state
.blit2d
.render_passes
[j
],
664 &device
->meta_state
.alloc
);
668 radv_DestroyRenderPass(radv_device_to_handle(device
),
669 device
->meta_state
.blit2d
.depth_only_rp
,
670 &device
->meta_state
.alloc
);
671 radv_DestroyRenderPass(radv_device_to_handle(device
),
672 device
->meta_state
.blit2d
.stencil_only_rp
,
673 &device
->meta_state
.alloc
);
675 for (unsigned src
= 0; src
< BLIT2D_NUM_SRC_TYPES
; src
++) {
676 if (device
->meta_state
.blit2d
.p_layouts
[src
]) {
677 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
678 device
->meta_state
.blit2d
.p_layouts
[src
],
679 &device
->meta_state
.alloc
);
682 if (device
->meta_state
.blit2d
.ds_layouts
[src
]) {
683 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
684 device
->meta_state
.blit2d
.ds_layouts
[src
],
685 &device
->meta_state
.alloc
);
688 for (unsigned j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
689 if (device
->meta_state
.blit2d
.pipelines
[src
][j
]) {
690 radv_DestroyPipeline(radv_device_to_handle(device
),
691 device
->meta_state
.blit2d
.pipelines
[src
][j
],
692 &device
->meta_state
.alloc
);
696 radv_DestroyPipeline(radv_device_to_handle(device
),
697 device
->meta_state
.blit2d
.depth_only_pipeline
[src
],
698 &device
->meta_state
.alloc
);
699 radv_DestroyPipeline(radv_device_to_handle(device
),
700 device
->meta_state
.blit2d
.stencil_only_pipeline
[src
],
701 &device
->meta_state
.alloc
);
706 blit2d_init_color_pipeline(struct radv_device
*device
,
707 enum blit2d_src_type src_type
,
711 unsigned fs_key
= radv_format_meta_fs_key(format
);
714 texel_fetch_build_func src_func
;
716 case BLIT2D_SRC_TYPE_IMAGE
:
717 src_func
= build_nir_texel_fetch
;
718 name
= "meta_blit2d_image_fs";
720 case BLIT2D_SRC_TYPE_BUFFER
:
721 src_func
= build_nir_buffer_fetch
;
722 name
= "meta_blit2d_buffer_fs";
725 unreachable("unknown blit src type\n");
729 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
730 struct radv_shader_module fs
= { .nir
= NULL
};
733 fs
.nir
= build_nir_copy_fragment_shader(device
, src_func
, name
);
734 vi_create_info
= &normal_vi_create_info
;
736 struct radv_shader_module vs
= {
737 .nir
= build_nir_vertex_shader(),
740 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
742 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
743 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
744 .module
= radv_shader_module_to_handle(&vs
),
746 .pSpecializationInfo
= NULL
748 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
749 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
750 .module
= radv_shader_module_to_handle(&fs
),
752 .pSpecializationInfo
= NULL
756 if (!device
->meta_state
.blit2d
.render_passes
[fs_key
]) {
757 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
758 &(VkRenderPassCreateInfo
) {
759 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
760 .attachmentCount
= 1,
761 .pAttachments
= &(VkAttachmentDescription
) {
763 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
764 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
765 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
766 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
769 .pSubpasses
= &(VkSubpassDescription
) {
770 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
771 .inputAttachmentCount
= 0,
772 .colorAttachmentCount
= 1,
773 .pColorAttachments
= &(VkAttachmentReference
) {
775 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
777 .pResolveAttachments
= NULL
,
778 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
779 .attachment
= VK_ATTACHMENT_UNUSED
,
780 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
782 .preserveAttachmentCount
= 1,
783 .pPreserveAttachments
= (uint32_t[]) { 0 },
785 .dependencyCount
= 0,
786 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.render_passes
[fs_key
]);
789 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
790 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
791 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
792 .pStages
= pipeline_shader_stages
,
793 .pVertexInputState
= vi_create_info
,
794 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
795 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
796 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
797 .primitiveRestartEnable
= false,
799 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
800 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
804 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
805 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
806 .rasterizerDiscardEnable
= false,
807 .polygonMode
= VK_POLYGON_MODE_FILL
,
808 .cullMode
= VK_CULL_MODE_NONE
,
809 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
811 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
812 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
813 .rasterizationSamples
= 1,
814 .sampleShadingEnable
= false,
815 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
817 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
818 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
819 .attachmentCount
= 1,
820 .pAttachments
= (VkPipelineColorBlendAttachmentState
[]) {
822 VK_COLOR_COMPONENT_A_BIT
|
823 VK_COLOR_COMPONENT_R_BIT
|
824 VK_COLOR_COMPONENT_G_BIT
|
825 VK_COLOR_COMPONENT_B_BIT
},
828 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
829 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
830 .dynamicStateCount
= 7,
831 .pDynamicStates
= (VkDynamicState
[]) {
832 VK_DYNAMIC_STATE_LINE_WIDTH
,
833 VK_DYNAMIC_STATE_DEPTH_BIAS
,
834 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
835 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
836 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
837 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
838 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
842 .layout
= device
->meta_state
.blit2d
.p_layouts
[src_type
],
843 .renderPass
= device
->meta_state
.blit2d
.render_passes
[fs_key
],
847 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
851 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
852 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
853 &vk_pipeline_info
, &radv_pipeline_info
,
854 &device
->meta_state
.alloc
,
855 &device
->meta_state
.blit2d
.pipelines
[src_type
][fs_key
]);
865 blit2d_init_depth_only_pipeline(struct radv_device
*device
,
866 enum blit2d_src_type src_type
)
871 texel_fetch_build_func src_func
;
873 case BLIT2D_SRC_TYPE_IMAGE
:
874 src_func
= build_nir_texel_fetch
;
875 name
= "meta_blit2d_depth_image_fs";
877 case BLIT2D_SRC_TYPE_BUFFER
:
878 src_func
= build_nir_buffer_fetch
;
879 name
= "meta_blit2d_depth_buffer_fs";
882 unreachable("unknown blit src type\n");
886 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
887 struct radv_shader_module fs
= { .nir
= NULL
};
889 fs
.nir
= build_nir_copy_fragment_shader_depth(device
, src_func
, name
);
890 vi_create_info
= &normal_vi_create_info
;
892 struct radv_shader_module vs
= {
893 .nir
= build_nir_vertex_shader(),
896 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
898 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
899 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
900 .module
= radv_shader_module_to_handle(&vs
),
902 .pSpecializationInfo
= NULL
904 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
905 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
906 .module
= radv_shader_module_to_handle(&fs
),
908 .pSpecializationInfo
= NULL
912 if (!device
->meta_state
.blit2d
.depth_only_rp
) {
913 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
914 &(VkRenderPassCreateInfo
) {
915 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
916 .attachmentCount
= 1,
917 .pAttachments
= &(VkAttachmentDescription
) {
919 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
920 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
921 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
922 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
925 .pSubpasses
= &(VkSubpassDescription
) {
926 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
927 .inputAttachmentCount
= 0,
928 .colorAttachmentCount
= 0,
929 .pColorAttachments
= NULL
,
930 .pResolveAttachments
= NULL
,
931 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
933 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
935 .preserveAttachmentCount
= 1,
936 .pPreserveAttachments
= (uint32_t[]) { 0 },
938 .dependencyCount
= 0,
939 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.depth_only_rp
);
942 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
943 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
944 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
945 .pStages
= pipeline_shader_stages
,
946 .pVertexInputState
= vi_create_info
,
947 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
948 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
949 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
950 .primitiveRestartEnable
= false,
952 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
953 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
957 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
958 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
959 .rasterizerDiscardEnable
= false,
960 .polygonMode
= VK_POLYGON_MODE_FILL
,
961 .cullMode
= VK_CULL_MODE_NONE
,
962 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
964 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
965 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
966 .rasterizationSamples
= 1,
967 .sampleShadingEnable
= false,
968 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
970 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
971 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
972 .attachmentCount
= 0,
973 .pAttachments
= NULL
,
975 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
976 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
977 .depthTestEnable
= true,
978 .depthWriteEnable
= true,
979 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
981 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
982 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
983 .dynamicStateCount
= 7,
984 .pDynamicStates
= (VkDynamicState
[]) {
985 VK_DYNAMIC_STATE_LINE_WIDTH
,
986 VK_DYNAMIC_STATE_DEPTH_BIAS
,
987 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
988 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
989 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
990 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
991 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
995 .layout
= device
->meta_state
.blit2d
.p_layouts
[src_type
],
996 .renderPass
= device
->meta_state
.blit2d
.depth_only_rp
,
1000 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
1001 .use_rectlist
= true
1004 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1005 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1006 &vk_pipeline_info
, &radv_pipeline_info
,
1007 &device
->meta_state
.alloc
,
1008 &device
->meta_state
.blit2d
.depth_only_pipeline
[src_type
]);
1011 ralloc_free(vs
.nir
);
1012 ralloc_free(fs
.nir
);
1018 blit2d_init_stencil_only_pipeline(struct radv_device
*device
,
1019 enum blit2d_src_type src_type
)
1024 texel_fetch_build_func src_func
;
1026 case BLIT2D_SRC_TYPE_IMAGE
:
1027 src_func
= build_nir_texel_fetch
;
1028 name
= "meta_blit2d_stencil_image_fs";
1030 case BLIT2D_SRC_TYPE_BUFFER
:
1031 src_func
= build_nir_buffer_fetch
;
1032 name
= "meta_blit2d_stencil_buffer_fs";
1035 unreachable("unknown blit src type\n");
1039 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
1040 struct radv_shader_module fs
= { .nir
= NULL
};
1042 fs
.nir
= build_nir_copy_fragment_shader_stencil(device
, src_func
, name
);
1043 vi_create_info
= &normal_vi_create_info
;
1045 struct radv_shader_module vs
= {
1046 .nir
= build_nir_vertex_shader(),
1049 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
1051 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1052 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
1053 .module
= radv_shader_module_to_handle(&vs
),
1055 .pSpecializationInfo
= NULL
1057 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1058 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1059 .module
= radv_shader_module_to_handle(&fs
),
1061 .pSpecializationInfo
= NULL
1065 if (!device
->meta_state
.blit2d
.stencil_only_rp
) {
1066 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
1067 &(VkRenderPassCreateInfo
) {
1068 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
1069 .attachmentCount
= 1,
1070 .pAttachments
= &(VkAttachmentDescription
) {
1072 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1073 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1074 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
1075 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
1078 .pSubpasses
= &(VkSubpassDescription
) {
1079 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
1080 .inputAttachmentCount
= 0,
1081 .colorAttachmentCount
= 0,
1082 .pColorAttachments
= NULL
,
1083 .pResolveAttachments
= NULL
,
1084 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
1086 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
1088 .preserveAttachmentCount
= 1,
1089 .pPreserveAttachments
= (uint32_t[]) { 0 },
1091 .dependencyCount
= 0,
1092 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.stencil_only_rp
);
1095 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
1096 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
1097 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
1098 .pStages
= pipeline_shader_stages
,
1099 .pVertexInputState
= vi_create_info
,
1100 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
1101 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
1102 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
1103 .primitiveRestartEnable
= false,
1105 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
1106 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
1110 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
1111 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
1112 .rasterizerDiscardEnable
= false,
1113 .polygonMode
= VK_POLYGON_MODE_FILL
,
1114 .cullMode
= VK_CULL_MODE_NONE
,
1115 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
1117 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
1118 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
1119 .rasterizationSamples
= 1,
1120 .sampleShadingEnable
= false,
1121 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
1123 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
1124 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
1125 .attachmentCount
= 0,
1126 .pAttachments
= NULL
,
1128 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
1129 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
1130 .depthTestEnable
= false,
1131 .depthWriteEnable
= false,
1132 .stencilTestEnable
= true,
1134 .failOp
= VK_STENCIL_OP_REPLACE
,
1135 .passOp
= VK_STENCIL_OP_REPLACE
,
1136 .depthFailOp
= VK_STENCIL_OP_REPLACE
,
1137 .compareOp
= VK_COMPARE_OP_ALWAYS
,
1138 .compareMask
= 0xff,
1143 .failOp
= VK_STENCIL_OP_REPLACE
,
1144 .passOp
= VK_STENCIL_OP_REPLACE
,
1145 .depthFailOp
= VK_STENCIL_OP_REPLACE
,
1146 .compareOp
= VK_COMPARE_OP_ALWAYS
,
1147 .compareMask
= 0xff,
1151 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
1153 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
1154 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
1155 .dynamicStateCount
= 4,
1156 .pDynamicStates
= (VkDynamicState
[]) {
1157 VK_DYNAMIC_STATE_LINE_WIDTH
,
1158 VK_DYNAMIC_STATE_DEPTH_BIAS
,
1159 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
1160 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
1164 .layout
= device
->meta_state
.blit2d
.p_layouts
[src_type
],
1165 .renderPass
= device
->meta_state
.blit2d
.stencil_only_rp
,
1169 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
1170 .use_rectlist
= true
1173 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1174 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1175 &vk_pipeline_info
, &radv_pipeline_info
,
1176 &device
->meta_state
.alloc
,
1177 &device
->meta_state
.blit2d
.stencil_only_pipeline
[src_type
]);
1180 ralloc_free(vs
.nir
);
1181 ralloc_free(fs
.nir
);
1186 static VkFormat pipeline_formats
[] = {
1187 VK_FORMAT_R8G8B8A8_UNORM
,
1188 VK_FORMAT_R8G8B8A8_UINT
,
1189 VK_FORMAT_R8G8B8A8_SINT
,
1190 VK_FORMAT_R16G16B16A16_UNORM
,
1191 VK_FORMAT_R16G16B16A16_SNORM
,
1192 VK_FORMAT_R16G16B16A16_UINT
,
1193 VK_FORMAT_R16G16B16A16_SINT
,
1194 VK_FORMAT_R32_SFLOAT
,
1195 VK_FORMAT_R32G32_SFLOAT
,
1196 VK_FORMAT_R32G32B32A32_SFLOAT
1200 radv_device_init_meta_blit2d_state(struct radv_device
*device
)
1204 zero(device
->meta_state
.blit2d
);
1206 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
1207 &(VkDescriptorSetLayoutCreateInfo
) {
1208 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
1210 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
1213 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
1214 .descriptorCount
= 1,
1215 .stageFlags
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1216 .pImmutableSamplers
= NULL
1219 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.ds_layouts
[BLIT2D_SRC_TYPE_IMAGE
]);
1220 if (result
!= VK_SUCCESS
)
1223 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1224 &(VkPipelineLayoutCreateInfo
) {
1225 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1226 .setLayoutCount
= 1,
1227 .pSetLayouts
= &device
->meta_state
.blit2d
.ds_layouts
[BLIT2D_SRC_TYPE_IMAGE
],
1229 &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.p_layouts
[BLIT2D_SRC_TYPE_IMAGE
]);
1230 if (result
!= VK_SUCCESS
)
1233 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
1234 &(VkDescriptorSetLayoutCreateInfo
) {
1235 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
1237 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
1240 .descriptorType
= VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
,
1241 .descriptorCount
= 1,
1242 .stageFlags
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1243 .pImmutableSamplers
= NULL
1246 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.ds_layouts
[BLIT2D_SRC_TYPE_BUFFER
]);
1247 if (result
!= VK_SUCCESS
)
1250 const VkPushConstantRange push_constant_range
= {VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 4};
1251 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1252 &(VkPipelineLayoutCreateInfo
) {
1253 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1254 .setLayoutCount
= 1,
1255 .pSetLayouts
= &device
->meta_state
.blit2d
.ds_layouts
[BLIT2D_SRC_TYPE_BUFFER
],
1256 .pushConstantRangeCount
= 1,
1257 .pPushConstantRanges
= &push_constant_range
,
1259 &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.p_layouts
[BLIT2D_SRC_TYPE_BUFFER
]);
1260 if (result
!= VK_SUCCESS
)
1263 for (unsigned src
= 0; src
< BLIT2D_NUM_SRC_TYPES
; src
++) {
1264 for (unsigned j
= 0; j
< ARRAY_SIZE(pipeline_formats
); ++j
) {
1265 result
= blit2d_init_color_pipeline(device
, src
, pipeline_formats
[j
]);
1266 if (result
!= VK_SUCCESS
)
1270 result
= blit2d_init_depth_only_pipeline(device
, src
);
1271 if (result
!= VK_SUCCESS
)
1274 result
= blit2d_init_stencil_only_pipeline(device
, src
);
1275 if (result
!= VK_SUCCESS
)
1282 radv_device_finish_meta_blit2d_state(device
);