vulkan/wsi: Do image creation in common code
[mesa.git] / src / amd / vulkan / radv_meta_blit2d.c
1 /*
2 * Copyright © 2016 Red Hat
3 *
4 * based on anv driver:
5 * Copyright © 2016 Intel Corporation
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * IN THE SOFTWARE.
25 */
26
27 #include "radv_meta.h"
28 #include "nir/nir_builder.h"
29 #include "vk_format.h"
30
31 enum blit2d_src_type {
32 BLIT2D_SRC_TYPE_IMAGE,
33 BLIT2D_SRC_TYPE_BUFFER,
34 BLIT2D_NUM_SRC_TYPES,
35 };
36
37 static void
38 create_iview(struct radv_cmd_buffer *cmd_buffer,
39 struct radv_meta_blit2d_surf *surf,
40 struct radv_image_view *iview, VkFormat depth_format,
41 VkImageAspectFlagBits aspects)
42 {
43 VkFormat format;
44
45 if (depth_format)
46 format = depth_format;
47 else
48 format = surf->format;
49
50 radv_image_view_init(iview, cmd_buffer->device,
51 &(VkImageViewCreateInfo) {
52 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
53 .image = radv_image_to_handle(surf->image),
54 .viewType = VK_IMAGE_VIEW_TYPE_2D,
55 .format = format,
56 .subresourceRange = {
57 .aspectMask = aspects,
58 .baseMipLevel = surf->level,
59 .levelCount = 1,
60 .baseArrayLayer = surf->layer,
61 .layerCount = 1
62 },
63 });
64 }
65
66 static void
67 create_bview(struct radv_cmd_buffer *cmd_buffer,
68 struct radv_meta_blit2d_buffer *src,
69 struct radv_buffer_view *bview, VkFormat depth_format)
70 {
71 VkFormat format;
72
73 if (depth_format)
74 format = depth_format;
75 else
76 format = src->format;
77 radv_buffer_view_init(bview, cmd_buffer->device,
78 &(VkBufferViewCreateInfo) {
79 .sType = VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO,
80 .flags = 0,
81 .buffer = radv_buffer_to_handle(src->buffer),
82 .format = format,
83 .offset = src->offset,
84 .range = VK_WHOLE_SIZE,
85 });
86
87 }
88
89 struct blit2d_src_temps {
90 struct radv_image_view iview;
91 struct radv_buffer_view bview;
92 };
93
94 static void
95 blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
96 struct radv_meta_blit2d_surf *src_img,
97 struct radv_meta_blit2d_buffer *src_buf,
98 struct blit2d_src_temps *tmp,
99 enum blit2d_src_type src_type, VkFormat depth_format,
100 VkImageAspectFlagBits aspects)
101 {
102 struct radv_device *device = cmd_buffer->device;
103
104 if (src_type == BLIT2D_SRC_TYPE_BUFFER) {
105 create_bview(cmd_buffer, src_buf, &tmp->bview, depth_format);
106
107 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
108 device->meta_state.blit2d.p_layouts[src_type],
109 0, /* set */
110 1, /* descriptorWriteCount */
111 (VkWriteDescriptorSet[]) {
112 {
113 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
114 .dstBinding = 0,
115 .dstArrayElement = 0,
116 .descriptorCount = 1,
117 .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
118 .pTexelBufferView = (VkBufferView[]) { radv_buffer_view_to_handle(&tmp->bview) }
119 }
120 });
121
122 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
123 device->meta_state.blit2d.p_layouts[src_type],
124 VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4,
125 &src_buf->pitch);
126 } else {
127 create_iview(cmd_buffer, src_img, &tmp->iview, depth_format, aspects);
128
129 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
130 device->meta_state.blit2d.p_layouts[src_type],
131 0, /* set */
132 1, /* descriptorWriteCount */
133 (VkWriteDescriptorSet[]) {
134 {
135 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
136 .dstBinding = 0,
137 .dstArrayElement = 0,
138 .descriptorCount = 1,
139 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
140 .pImageInfo = (VkDescriptorImageInfo[]) {
141 {
142 .sampler = VK_NULL_HANDLE,
143 .imageView = radv_image_view_to_handle(&tmp->iview),
144 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
145 },
146 }
147 }
148 });
149 }
150 }
151
152 struct blit2d_dst_temps {
153 VkImage image;
154 struct radv_image_view iview;
155 VkFramebuffer fb;
156 };
157
158 static void
159 blit2d_bind_dst(struct radv_cmd_buffer *cmd_buffer,
160 struct radv_meta_blit2d_surf *dst,
161 uint32_t width,
162 uint32_t height,
163 VkFormat depth_format,
164 struct blit2d_dst_temps *tmp,
165 VkImageAspectFlagBits aspects)
166 {
167 create_iview(cmd_buffer, dst, &tmp->iview, depth_format, aspects);
168
169 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer->device),
170 &(VkFramebufferCreateInfo) {
171 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
172 .attachmentCount = 1,
173 .pAttachments = (VkImageView[]) {
174 radv_image_view_to_handle(&tmp->iview),
175 },
176 .width = width,
177 .height = height,
178 .layers = 1
179 }, &cmd_buffer->pool->alloc, &tmp->fb);
180 }
181
182 static void
183 bind_pipeline(struct radv_cmd_buffer *cmd_buffer,
184 enum blit2d_src_type src_type, unsigned fs_key)
185 {
186 VkPipeline pipeline =
187 cmd_buffer->device->meta_state.blit2d.pipelines[src_type][fs_key];
188
189 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
190 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
191 }
192
193 static void
194 bind_depth_pipeline(struct radv_cmd_buffer *cmd_buffer,
195 enum blit2d_src_type src_type)
196 {
197 VkPipeline pipeline =
198 cmd_buffer->device->meta_state.blit2d.depth_only_pipeline[src_type];
199
200 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
201 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
202 }
203
204 static void
205 bind_stencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
206 enum blit2d_src_type src_type)
207 {
208 VkPipeline pipeline =
209 cmd_buffer->device->meta_state.blit2d.stencil_only_pipeline[src_type];
210
211 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
212 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
213 }
214
215 static void
216 radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
217 struct radv_meta_blit2d_surf *src_img,
218 struct radv_meta_blit2d_buffer *src_buf,
219 struct radv_meta_blit2d_surf *dst,
220 unsigned num_rects,
221 struct radv_meta_blit2d_rect *rects, enum blit2d_src_type src_type)
222 {
223 struct radv_device *device = cmd_buffer->device;
224
225 for (unsigned r = 0; r < num_rects; ++r) {
226 unsigned i;
227 for_each_bit(i, dst->aspect_mask) {
228 unsigned aspect_mask = 1u << i;
229 VkFormat depth_format = 0;
230 if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT)
231 depth_format = vk_format_stencil_only(dst->image->vk_format);
232 else if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT)
233 depth_format = vk_format_depth_only(dst->image->vk_format);
234 struct blit2d_src_temps src_temps;
235 blit2d_bind_src(cmd_buffer, src_img, src_buf, &src_temps, src_type, depth_format, aspect_mask);
236
237 struct blit2d_dst_temps dst_temps;
238 blit2d_bind_dst(cmd_buffer, dst, rects[r].dst_x + rects[r].width,
239 rects[r].dst_y + rects[r].height, depth_format, &dst_temps, aspect_mask);
240
241 float vertex_push_constants[4] = {
242 rects[r].src_x,
243 rects[r].src_y,
244 rects[r].src_x + rects[r].width,
245 rects[r].src_y + rects[r].height,
246 };
247
248 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
249 device->meta_state.blit2d.p_layouts[src_type],
250 VK_SHADER_STAGE_VERTEX_BIT, 0, 16,
251 vertex_push_constants);
252
253 if (aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT) {
254 unsigned fs_key = radv_format_meta_fs_key(dst_temps.iview.vk_format);
255
256 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
257 &(VkRenderPassBeginInfo) {
258 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
259 .renderPass = device->meta_state.blit2d.render_passes[fs_key],
260 .framebuffer = dst_temps.fb,
261 .renderArea = {
262 .offset = { rects[r].dst_x, rects[r].dst_y, },
263 .extent = { rects[r].width, rects[r].height },
264 },
265 .clearValueCount = 0,
266 .pClearValues = NULL,
267 }, VK_SUBPASS_CONTENTS_INLINE);
268
269
270 bind_pipeline(cmd_buffer, src_type, fs_key);
271 } else if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
272 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
273 &(VkRenderPassBeginInfo) {
274 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
275 .renderPass = device->meta_state.blit2d.depth_only_rp,
276 .framebuffer = dst_temps.fb,
277 .renderArea = {
278 .offset = { rects[r].dst_x, rects[r].dst_y, },
279 .extent = { rects[r].width, rects[r].height },
280 },
281 .clearValueCount = 0,
282 .pClearValues = NULL,
283 }, VK_SUBPASS_CONTENTS_INLINE);
284
285
286 bind_depth_pipeline(cmd_buffer, src_type);
287
288 } else if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
289 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
290 &(VkRenderPassBeginInfo) {
291 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
292 .renderPass = device->meta_state.blit2d.stencil_only_rp,
293 .framebuffer = dst_temps.fb,
294 .renderArea = {
295 .offset = { rects[r].dst_x, rects[r].dst_y, },
296 .extent = { rects[r].width, rects[r].height },
297 },
298 .clearValueCount = 0,
299 .pClearValues = NULL,
300 }, VK_SUBPASS_CONTENTS_INLINE);
301
302
303 bind_stencil_pipeline(cmd_buffer, src_type);
304 } else
305 unreachable("Processing blit2d with multiple aspects.");
306
307 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
308 .x = rects[r].dst_x,
309 .y = rects[r].dst_y,
310 .width = rects[r].width,
311 .height = rects[r].height,
312 .minDepth = 0.0f,
313 .maxDepth = 1.0f
314 });
315
316 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
317 .offset = (VkOffset2D) { rects[r].dst_x, rects[r].dst_y },
318 .extent = (VkExtent2D) { rects[r].width, rects[r].height },
319 });
320
321
322
323 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
324 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
325
326 /* At the point where we emit the draw call, all data from the
327 * descriptor sets, etc. has been used. We are free to delete it.
328 */
329 radv_DestroyFramebuffer(radv_device_to_handle(device),
330 dst_temps.fb,
331 &cmd_buffer->pool->alloc);
332 }
333 }
334 }
335
336 void
337 radv_meta_blit2d(struct radv_cmd_buffer *cmd_buffer,
338 struct radv_meta_blit2d_surf *src_img,
339 struct radv_meta_blit2d_buffer *src_buf,
340 struct radv_meta_blit2d_surf *dst,
341 unsigned num_rects,
342 struct radv_meta_blit2d_rect *rects)
343 {
344 enum blit2d_src_type src_type = src_buf ? BLIT2D_SRC_TYPE_BUFFER :
345 BLIT2D_SRC_TYPE_IMAGE;
346 radv_meta_blit2d_normal_dst(cmd_buffer, src_img, src_buf, dst,
347 num_rects, rects, src_type);
348 }
349
350 static nir_shader *
351 build_nir_vertex_shader(void)
352 {
353 const struct glsl_type *vec4 = glsl_vec4_type();
354 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
355 nir_builder b;
356
357 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
358 b.shader->info.name = ralloc_strdup(b.shader, "meta_blit2d_vs");
359
360 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
361 vec4, "gl_Position");
362 pos_out->data.location = VARYING_SLOT_POS;
363
364 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
365 vec2, "v_tex_pos");
366 tex_pos_out->data.location = VARYING_SLOT_VAR0;
367 tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
368
369 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
370 nir_store_var(&b, pos_out, outvec, 0xf);
371
372 nir_intrinsic_instr *src_box = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
373 src_box->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
374 nir_intrinsic_set_base(src_box, 0);
375 nir_intrinsic_set_range(src_box, 16);
376 src_box->num_components = 4;
377 nir_ssa_dest_init(&src_box->instr, &src_box->dest, 4, 32, "src_box");
378 nir_builder_instr_insert(&b, &src_box->instr);
379
380 nir_intrinsic_instr *vertex_id = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_vertex_id_zero_base);
381 nir_ssa_dest_init(&vertex_id->instr, &vertex_id->dest, 1, 32, "vertexid");
382 nir_builder_instr_insert(&b, &vertex_id->instr);
383
384 /* vertex 0 - src_x, src_y */
385 /* vertex 1 - src_x, src_y+h */
386 /* vertex 2 - src_x+w, src_y */
387 /* so channel 0 is vertex_id != 2 ? src_x : src_x + w
388 channel 1 is vertex id != 1 ? src_y : src_y + w */
389
390 nir_ssa_def *c0cmp = nir_ine(&b, &vertex_id->dest.ssa,
391 nir_imm_int(&b, 2));
392 nir_ssa_def *c1cmp = nir_ine(&b, &vertex_id->dest.ssa,
393 nir_imm_int(&b, 1));
394
395 nir_ssa_def *comp[2];
396 comp[0] = nir_bcsel(&b, c0cmp,
397 nir_channel(&b, &src_box->dest.ssa, 0),
398 nir_channel(&b, &src_box->dest.ssa, 2));
399
400 comp[1] = nir_bcsel(&b, c1cmp,
401 nir_channel(&b, &src_box->dest.ssa, 1),
402 nir_channel(&b, &src_box->dest.ssa, 3));
403 nir_ssa_def *out_tex_vec = nir_vec(&b, comp, 2);
404 nir_store_var(&b, tex_pos_out, out_tex_vec, 0x3);
405 return b.shader;
406 }
407
408 typedef nir_ssa_def* (*texel_fetch_build_func)(struct nir_builder *,
409 struct radv_device *,
410 nir_ssa_def *);
411
412 static nir_ssa_def *
413 build_nir_texel_fetch(struct nir_builder *b, struct radv_device *device,
414 nir_ssa_def *tex_pos)
415 {
416 const struct glsl_type *sampler_type =
417 glsl_sampler_type(GLSL_SAMPLER_DIM_2D, false, false, GLSL_TYPE_UINT);
418 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
419 sampler_type, "s_tex");
420 sampler->data.descriptor_set = 0;
421 sampler->data.binding = 0;
422
423 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 2);
424 tex->sampler_dim = GLSL_SAMPLER_DIM_2D;
425 tex->op = nir_texop_txf;
426 tex->src[0].src_type = nir_tex_src_coord;
427 tex->src[0].src = nir_src_for_ssa(tex_pos);
428 tex->src[1].src_type = nir_tex_src_lod;
429 tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
430 tex->dest_type = nir_type_uint;
431 tex->is_array = false;
432 tex->coord_components = 2;
433 tex->texture = nir_deref_var_create(tex, sampler);
434 tex->sampler = NULL;
435
436 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
437 nir_builder_instr_insert(b, &tex->instr);
438
439 return &tex->dest.ssa;
440 }
441
442
443 static nir_ssa_def *
444 build_nir_buffer_fetch(struct nir_builder *b, struct radv_device *device,
445 nir_ssa_def *tex_pos)
446 {
447 const struct glsl_type *sampler_type =
448 glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_UINT);
449 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
450 sampler_type, "s_tex");
451 sampler->data.descriptor_set = 0;
452 sampler->data.binding = 0;
453
454 nir_intrinsic_instr *width = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
455 nir_intrinsic_set_base(width, 16);
456 nir_intrinsic_set_range(width, 4);
457 width->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
458 width->num_components = 1;
459 nir_ssa_dest_init(&width->instr, &width->dest, 1, 32, "width");
460 nir_builder_instr_insert(b, &width->instr);
461
462 nir_ssa_def *pos_x = nir_channel(b, tex_pos, 0);
463 nir_ssa_def *pos_y = nir_channel(b, tex_pos, 1);
464 pos_y = nir_imul(b, pos_y, &width->dest.ssa);
465 pos_x = nir_iadd(b, pos_x, pos_y);
466 //pos_x = nir_iadd(b, pos_x, nir_imm_int(b, 100000));
467
468 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 1);
469 tex->sampler_dim = GLSL_SAMPLER_DIM_BUF;
470 tex->op = nir_texop_txf;
471 tex->src[0].src_type = nir_tex_src_coord;
472 tex->src[0].src = nir_src_for_ssa(pos_x);
473 tex->dest_type = nir_type_uint;
474 tex->is_array = false;
475 tex->coord_components = 1;
476 tex->texture = nir_deref_var_create(tex, sampler);
477 tex->sampler = NULL;
478
479 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
480 nir_builder_instr_insert(b, &tex->instr);
481
482 return &tex->dest.ssa;
483 }
484
485 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
486 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
487 .vertexBindingDescriptionCount = 0,
488 .vertexAttributeDescriptionCount = 0,
489 };
490
491 static nir_shader *
492 build_nir_copy_fragment_shader(struct radv_device *device,
493 texel_fetch_build_func txf_func, const char* name)
494 {
495 const struct glsl_type *vec4 = glsl_vec4_type();
496 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
497 nir_builder b;
498
499 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
500 b.shader->info.name = ralloc_strdup(b.shader, name);
501
502 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
503 vec2, "v_tex_pos");
504 tex_pos_in->data.location = VARYING_SLOT_VAR0;
505
506 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
507 vec4, "f_color");
508 color_out->data.location = FRAG_RESULT_DATA0;
509
510 nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
511 unsigned swiz[4] = { 0, 1 };
512 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
513
514 nir_ssa_def *color = txf_func(&b, device, tex_pos);
515 nir_store_var(&b, color_out, color, 0xf);
516
517 return b.shader;
518 }
519
520 static nir_shader *
521 build_nir_copy_fragment_shader_depth(struct radv_device *device,
522 texel_fetch_build_func txf_func, const char* name)
523 {
524 const struct glsl_type *vec4 = glsl_vec4_type();
525 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
526 nir_builder b;
527
528 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
529 b.shader->info.name = ralloc_strdup(b.shader, name);
530
531 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
532 vec2, "v_tex_pos");
533 tex_pos_in->data.location = VARYING_SLOT_VAR0;
534
535 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
536 vec4, "f_color");
537 color_out->data.location = FRAG_RESULT_DEPTH;
538
539 nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
540 unsigned swiz[4] = { 0, 1 };
541 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
542
543 nir_ssa_def *color = txf_func(&b, device, tex_pos);
544 nir_store_var(&b, color_out, color, 0x1);
545
546 return b.shader;
547 }
548
549 static nir_shader *
550 build_nir_copy_fragment_shader_stencil(struct radv_device *device,
551 texel_fetch_build_func txf_func, const char* name)
552 {
553 const struct glsl_type *vec4 = glsl_vec4_type();
554 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
555 nir_builder b;
556
557 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
558 b.shader->info.name = ralloc_strdup(b.shader, name);
559
560 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
561 vec2, "v_tex_pos");
562 tex_pos_in->data.location = VARYING_SLOT_VAR0;
563
564 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
565 vec4, "f_color");
566 color_out->data.location = FRAG_RESULT_STENCIL;
567
568 nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
569 unsigned swiz[4] = { 0, 1 };
570 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
571
572 nir_ssa_def *color = txf_func(&b, device, tex_pos);
573 nir_store_var(&b, color_out, color, 0x1);
574
575 return b.shader;
576 }
577
578 void
579 radv_device_finish_meta_blit2d_state(struct radv_device *device)
580 {
581 struct radv_meta_state *state = &device->meta_state;
582
583 for(unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
584 radv_DestroyRenderPass(radv_device_to_handle(device),
585 state->blit2d.render_passes[j],
586 &state->alloc);
587 }
588
589 radv_DestroyRenderPass(radv_device_to_handle(device),
590 state->blit2d.depth_only_rp, &state->alloc);
591 radv_DestroyRenderPass(radv_device_to_handle(device),
592 state->blit2d.stencil_only_rp, &state->alloc);
593
594 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
595 radv_DestroyPipelineLayout(radv_device_to_handle(device),
596 state->blit2d.p_layouts[src],
597 &state->alloc);
598 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
599 state->blit2d.ds_layouts[src],
600 &state->alloc);
601
602 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
603 radv_DestroyPipeline(radv_device_to_handle(device),
604 state->blit2d.pipelines[src][j],
605 &state->alloc);
606 }
607
608 radv_DestroyPipeline(radv_device_to_handle(device),
609 state->blit2d.depth_only_pipeline[src],
610 &state->alloc);
611 radv_DestroyPipeline(radv_device_to_handle(device),
612 state->blit2d.stencil_only_pipeline[src],
613 &state->alloc);
614 }
615 }
616
617 static VkResult
618 blit2d_init_color_pipeline(struct radv_device *device,
619 enum blit2d_src_type src_type,
620 VkFormat format)
621 {
622 VkResult result;
623 unsigned fs_key = radv_format_meta_fs_key(format);
624 const char *name;
625
626 texel_fetch_build_func src_func;
627 switch(src_type) {
628 case BLIT2D_SRC_TYPE_IMAGE:
629 src_func = build_nir_texel_fetch;
630 name = "meta_blit2d_image_fs";
631 break;
632 case BLIT2D_SRC_TYPE_BUFFER:
633 src_func = build_nir_buffer_fetch;
634 name = "meta_blit2d_buffer_fs";
635 break;
636 default:
637 unreachable("unknown blit src type\n");
638 break;
639 }
640
641 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
642 struct radv_shader_module fs = { .nir = NULL };
643
644
645 fs.nir = build_nir_copy_fragment_shader(device, src_func, name);
646 vi_create_info = &normal_vi_create_info;
647
648 struct radv_shader_module vs = {
649 .nir = build_nir_vertex_shader(),
650 };
651
652 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
653 {
654 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
655 .stage = VK_SHADER_STAGE_VERTEX_BIT,
656 .module = radv_shader_module_to_handle(&vs),
657 .pName = "main",
658 .pSpecializationInfo = NULL
659 }, {
660 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
661 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
662 .module = radv_shader_module_to_handle(&fs),
663 .pName = "main",
664 .pSpecializationInfo = NULL
665 },
666 };
667
668 if (!device->meta_state.blit2d.render_passes[fs_key]) {
669 result = radv_CreateRenderPass(radv_device_to_handle(device),
670 &(VkRenderPassCreateInfo) {
671 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
672 .attachmentCount = 1,
673 .pAttachments = &(VkAttachmentDescription) {
674 .format = format,
675 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
676 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
677 .initialLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
678 .finalLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
679 },
680 .subpassCount = 1,
681 .pSubpasses = &(VkSubpassDescription) {
682 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
683 .inputAttachmentCount = 0,
684 .colorAttachmentCount = 1,
685 .pColorAttachments = &(VkAttachmentReference) {
686 .attachment = 0,
687 .layout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
688 },
689 .pResolveAttachments = NULL,
690 .pDepthStencilAttachment = &(VkAttachmentReference) {
691 .attachment = VK_ATTACHMENT_UNUSED,
692 .layout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
693 },
694 .preserveAttachmentCount = 1,
695 .pPreserveAttachments = (uint32_t[]) { 0 },
696 },
697 .dependencyCount = 0,
698 }, &device->meta_state.alloc, &device->meta_state.blit2d.render_passes[fs_key]);
699 }
700
701 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
702 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
703 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
704 .pStages = pipeline_shader_stages,
705 .pVertexInputState = vi_create_info,
706 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
707 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
708 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
709 .primitiveRestartEnable = false,
710 },
711 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
712 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
713 .viewportCount = 1,
714 .scissorCount = 1,
715 },
716 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
717 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
718 .rasterizerDiscardEnable = false,
719 .polygonMode = VK_POLYGON_MODE_FILL,
720 .cullMode = VK_CULL_MODE_NONE,
721 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
722 },
723 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
724 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
725 .rasterizationSamples = 1,
726 .sampleShadingEnable = false,
727 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
728 },
729 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
730 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
731 .attachmentCount = 1,
732 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
733 { .colorWriteMask =
734 VK_COLOR_COMPONENT_A_BIT |
735 VK_COLOR_COMPONENT_R_BIT |
736 VK_COLOR_COMPONENT_G_BIT |
737 VK_COLOR_COMPONENT_B_BIT },
738 }
739 },
740 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
741 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
742 .dynamicStateCount = 9,
743 .pDynamicStates = (VkDynamicState[]) {
744 VK_DYNAMIC_STATE_VIEWPORT,
745 VK_DYNAMIC_STATE_SCISSOR,
746 VK_DYNAMIC_STATE_LINE_WIDTH,
747 VK_DYNAMIC_STATE_DEPTH_BIAS,
748 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
749 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
750 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
751 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
752 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
753 },
754 },
755 .flags = 0,
756 .layout = device->meta_state.blit2d.p_layouts[src_type],
757 .renderPass = device->meta_state.blit2d.render_passes[fs_key],
758 .subpass = 0,
759 };
760
761 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
762 .use_rectlist = true
763 };
764
765 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
766 radv_pipeline_cache_to_handle(&device->meta_state.cache),
767 &vk_pipeline_info, &radv_pipeline_info,
768 &device->meta_state.alloc,
769 &device->meta_state.blit2d.pipelines[src_type][fs_key]);
770
771
772 ralloc_free(vs.nir);
773 ralloc_free(fs.nir);
774
775 return result;
776 }
777
778 static VkResult
779 blit2d_init_depth_only_pipeline(struct radv_device *device,
780 enum blit2d_src_type src_type)
781 {
782 VkResult result;
783 const char *name;
784
785 texel_fetch_build_func src_func;
786 switch(src_type) {
787 case BLIT2D_SRC_TYPE_IMAGE:
788 src_func = build_nir_texel_fetch;
789 name = "meta_blit2d_depth_image_fs";
790 break;
791 case BLIT2D_SRC_TYPE_BUFFER:
792 src_func = build_nir_buffer_fetch;
793 name = "meta_blit2d_depth_buffer_fs";
794 break;
795 default:
796 unreachable("unknown blit src type\n");
797 break;
798 }
799
800 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
801 struct radv_shader_module fs = { .nir = NULL };
802
803 fs.nir = build_nir_copy_fragment_shader_depth(device, src_func, name);
804 vi_create_info = &normal_vi_create_info;
805
806 struct radv_shader_module vs = {
807 .nir = build_nir_vertex_shader(),
808 };
809
810 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
811 {
812 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
813 .stage = VK_SHADER_STAGE_VERTEX_BIT,
814 .module = radv_shader_module_to_handle(&vs),
815 .pName = "main",
816 .pSpecializationInfo = NULL
817 }, {
818 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
819 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
820 .module = radv_shader_module_to_handle(&fs),
821 .pName = "main",
822 .pSpecializationInfo = NULL
823 },
824 };
825
826 if (!device->meta_state.blit2d.depth_only_rp) {
827 result = radv_CreateRenderPass(radv_device_to_handle(device),
828 &(VkRenderPassCreateInfo) {
829 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
830 .attachmentCount = 1,
831 .pAttachments = &(VkAttachmentDescription) {
832 .format = VK_FORMAT_D32_SFLOAT,
833 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
834 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
835 .initialLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
836 .finalLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
837 },
838 .subpassCount = 1,
839 .pSubpasses = &(VkSubpassDescription) {
840 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
841 .inputAttachmentCount = 0,
842 .colorAttachmentCount = 0,
843 .pColorAttachments = NULL,
844 .pResolveAttachments = NULL,
845 .pDepthStencilAttachment = &(VkAttachmentReference) {
846 .attachment = 0,
847 .layout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
848 },
849 .preserveAttachmentCount = 1,
850 .pPreserveAttachments = (uint32_t[]) { 0 },
851 },
852 .dependencyCount = 0,
853 }, &device->meta_state.alloc, &device->meta_state.blit2d.depth_only_rp);
854 }
855
856 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
857 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
858 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
859 .pStages = pipeline_shader_stages,
860 .pVertexInputState = vi_create_info,
861 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
862 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
863 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
864 .primitiveRestartEnable = false,
865 },
866 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
867 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
868 .viewportCount = 1,
869 .scissorCount = 1,
870 },
871 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
872 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
873 .rasterizerDiscardEnable = false,
874 .polygonMode = VK_POLYGON_MODE_FILL,
875 .cullMode = VK_CULL_MODE_NONE,
876 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
877 },
878 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
879 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
880 .rasterizationSamples = 1,
881 .sampleShadingEnable = false,
882 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
883 },
884 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
885 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
886 .attachmentCount = 0,
887 .pAttachments = NULL,
888 },
889 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
890 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
891 .depthTestEnable = true,
892 .depthWriteEnable = true,
893 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
894 },
895 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
896 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
897 .dynamicStateCount = 9,
898 .pDynamicStates = (VkDynamicState[]) {
899 VK_DYNAMIC_STATE_VIEWPORT,
900 VK_DYNAMIC_STATE_SCISSOR,
901 VK_DYNAMIC_STATE_LINE_WIDTH,
902 VK_DYNAMIC_STATE_DEPTH_BIAS,
903 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
904 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
905 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
906 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
907 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
908 },
909 },
910 .flags = 0,
911 .layout = device->meta_state.blit2d.p_layouts[src_type],
912 .renderPass = device->meta_state.blit2d.depth_only_rp,
913 .subpass = 0,
914 };
915
916 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
917 .use_rectlist = true
918 };
919
920 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
921 radv_pipeline_cache_to_handle(&device->meta_state.cache),
922 &vk_pipeline_info, &radv_pipeline_info,
923 &device->meta_state.alloc,
924 &device->meta_state.blit2d.depth_only_pipeline[src_type]);
925
926
927 ralloc_free(vs.nir);
928 ralloc_free(fs.nir);
929
930 return result;
931 }
932
933 static VkResult
934 blit2d_init_stencil_only_pipeline(struct radv_device *device,
935 enum blit2d_src_type src_type)
936 {
937 VkResult result;
938 const char *name;
939
940 texel_fetch_build_func src_func;
941 switch(src_type) {
942 case BLIT2D_SRC_TYPE_IMAGE:
943 src_func = build_nir_texel_fetch;
944 name = "meta_blit2d_stencil_image_fs";
945 break;
946 case BLIT2D_SRC_TYPE_BUFFER:
947 src_func = build_nir_buffer_fetch;
948 name = "meta_blit2d_stencil_buffer_fs";
949 break;
950 default:
951 unreachable("unknown blit src type\n");
952 break;
953 }
954
955 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
956 struct radv_shader_module fs = { .nir = NULL };
957
958 fs.nir = build_nir_copy_fragment_shader_stencil(device, src_func, name);
959 vi_create_info = &normal_vi_create_info;
960
961 struct radv_shader_module vs = {
962 .nir = build_nir_vertex_shader(),
963 };
964
965 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
966 {
967 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
968 .stage = VK_SHADER_STAGE_VERTEX_BIT,
969 .module = radv_shader_module_to_handle(&vs),
970 .pName = "main",
971 .pSpecializationInfo = NULL
972 }, {
973 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
974 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
975 .module = radv_shader_module_to_handle(&fs),
976 .pName = "main",
977 .pSpecializationInfo = NULL
978 },
979 };
980
981 if (!device->meta_state.blit2d.stencil_only_rp) {
982 result = radv_CreateRenderPass(radv_device_to_handle(device),
983 &(VkRenderPassCreateInfo) {
984 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
985 .attachmentCount = 1,
986 .pAttachments = &(VkAttachmentDescription) {
987 .format = VK_FORMAT_S8_UINT,
988 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
989 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
990 .initialLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
991 .finalLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
992 },
993 .subpassCount = 1,
994 .pSubpasses = &(VkSubpassDescription) {
995 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
996 .inputAttachmentCount = 0,
997 .colorAttachmentCount = 0,
998 .pColorAttachments = NULL,
999 .pResolveAttachments = NULL,
1000 .pDepthStencilAttachment = &(VkAttachmentReference) {
1001 .attachment = 0,
1002 .layout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
1003 },
1004 .preserveAttachmentCount = 1,
1005 .pPreserveAttachments = (uint32_t[]) { 0 },
1006 },
1007 .dependencyCount = 0,
1008 }, &device->meta_state.alloc, &device->meta_state.blit2d.stencil_only_rp);
1009 }
1010
1011 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1012 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1013 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
1014 .pStages = pipeline_shader_stages,
1015 .pVertexInputState = vi_create_info,
1016 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1017 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1018 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1019 .primitiveRestartEnable = false,
1020 },
1021 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
1022 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1023 .viewportCount = 1,
1024 .scissorCount = 1,
1025 },
1026 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1027 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1028 .rasterizerDiscardEnable = false,
1029 .polygonMode = VK_POLYGON_MODE_FILL,
1030 .cullMode = VK_CULL_MODE_NONE,
1031 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1032 },
1033 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1034 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1035 .rasterizationSamples = 1,
1036 .sampleShadingEnable = false,
1037 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1038 },
1039 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1040 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1041 .attachmentCount = 0,
1042 .pAttachments = NULL,
1043 },
1044 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1045 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1046 .depthTestEnable = false,
1047 .depthWriteEnable = false,
1048 .stencilTestEnable = true,
1049 .front = {
1050 .failOp = VK_STENCIL_OP_REPLACE,
1051 .passOp = VK_STENCIL_OP_REPLACE,
1052 .depthFailOp = VK_STENCIL_OP_REPLACE,
1053 .compareOp = VK_COMPARE_OP_ALWAYS,
1054 .compareMask = 0xff,
1055 .writeMask = 0xff,
1056 .reference = 0
1057 },
1058 .back = {
1059 .failOp = VK_STENCIL_OP_REPLACE,
1060 .passOp = VK_STENCIL_OP_REPLACE,
1061 .depthFailOp = VK_STENCIL_OP_REPLACE,
1062 .compareOp = VK_COMPARE_OP_ALWAYS,
1063 .compareMask = 0xff,
1064 .writeMask = 0xff,
1065 .reference = 0
1066 },
1067 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
1068 },
1069 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1070 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1071 .dynamicStateCount = 6,
1072 .pDynamicStates = (VkDynamicState[]) {
1073 VK_DYNAMIC_STATE_VIEWPORT,
1074 VK_DYNAMIC_STATE_SCISSOR,
1075 VK_DYNAMIC_STATE_LINE_WIDTH,
1076 VK_DYNAMIC_STATE_DEPTH_BIAS,
1077 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1078 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1079 },
1080 },
1081 .flags = 0,
1082 .layout = device->meta_state.blit2d.p_layouts[src_type],
1083 .renderPass = device->meta_state.blit2d.stencil_only_rp,
1084 .subpass = 0,
1085 };
1086
1087 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1088 .use_rectlist = true
1089 };
1090
1091 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1092 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1093 &vk_pipeline_info, &radv_pipeline_info,
1094 &device->meta_state.alloc,
1095 &device->meta_state.blit2d.stencil_only_pipeline[src_type]);
1096
1097
1098 ralloc_free(vs.nir);
1099 ralloc_free(fs.nir);
1100
1101 return result;
1102 }
1103
1104 static VkFormat pipeline_formats[] = {
1105 VK_FORMAT_R8G8B8A8_UNORM,
1106 VK_FORMAT_R8G8B8A8_UINT,
1107 VK_FORMAT_R8G8B8A8_SINT,
1108 VK_FORMAT_A2R10G10B10_UINT_PACK32,
1109 VK_FORMAT_A2R10G10B10_SINT_PACK32,
1110 VK_FORMAT_R16G16B16A16_UNORM,
1111 VK_FORMAT_R16G16B16A16_SNORM,
1112 VK_FORMAT_R16G16B16A16_UINT,
1113 VK_FORMAT_R16G16B16A16_SINT,
1114 VK_FORMAT_R32_SFLOAT,
1115 VK_FORMAT_R32G32_SFLOAT,
1116 VK_FORMAT_R32G32B32A32_SFLOAT
1117 };
1118
1119 VkResult
1120 radv_device_init_meta_blit2d_state(struct radv_device *device)
1121 {
1122 VkResult result;
1123
1124 const VkPushConstantRange push_constant_ranges[] = {
1125 {VK_SHADER_STAGE_VERTEX_BIT, 0, 16},
1126 {VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4},
1127 };
1128 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1129 &(VkDescriptorSetLayoutCreateInfo) {
1130 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1131 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1132 .bindingCount = 1,
1133 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1134 {
1135 .binding = 0,
1136 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
1137 .descriptorCount = 1,
1138 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1139 .pImmutableSamplers = NULL
1140 },
1141 }
1142 }, &device->meta_state.alloc, &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_IMAGE]);
1143 if (result != VK_SUCCESS)
1144 goto fail;
1145
1146 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1147 &(VkPipelineLayoutCreateInfo) {
1148 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1149 .setLayoutCount = 1,
1150 .pSetLayouts = &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_IMAGE],
1151 .pushConstantRangeCount = 1,
1152 .pPushConstantRanges = push_constant_ranges,
1153 },
1154 &device->meta_state.alloc, &device->meta_state.blit2d.p_layouts[BLIT2D_SRC_TYPE_IMAGE]);
1155 if (result != VK_SUCCESS)
1156 goto fail;
1157
1158 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1159 &(VkDescriptorSetLayoutCreateInfo) {
1160 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1161 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1162 .bindingCount = 1,
1163 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1164 {
1165 .binding = 0,
1166 .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
1167 .descriptorCount = 1,
1168 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1169 .pImmutableSamplers = NULL
1170 },
1171 }
1172 }, &device->meta_state.alloc, &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_BUFFER]);
1173 if (result != VK_SUCCESS)
1174 goto fail;
1175
1176
1177 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1178 &(VkPipelineLayoutCreateInfo) {
1179 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1180 .setLayoutCount = 1,
1181 .pSetLayouts = &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_BUFFER],
1182 .pushConstantRangeCount = 2,
1183 .pPushConstantRanges = push_constant_ranges,
1184 },
1185 &device->meta_state.alloc, &device->meta_state.blit2d.p_layouts[BLIT2D_SRC_TYPE_BUFFER]);
1186 if (result != VK_SUCCESS)
1187 goto fail;
1188
1189 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
1190 for (unsigned j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
1191 result = blit2d_init_color_pipeline(device, src, pipeline_formats[j]);
1192 if (result != VK_SUCCESS)
1193 goto fail;
1194 }
1195
1196 result = blit2d_init_depth_only_pipeline(device, src);
1197 if (result != VK_SUCCESS)
1198 goto fail;
1199
1200 result = blit2d_init_stencil_only_pipeline(device, src);
1201 if (result != VK_SUCCESS)
1202 goto fail;
1203 }
1204
1205 return VK_SUCCESS;
1206
1207 fail:
1208 radv_device_finish_meta_blit2d_state(device);
1209 return result;
1210 }