2 * Copyright © 2016 Red Hat
5 * Copyright © 2016 Intel Corporation
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "radv_meta.h"
28 #include "nir/nir_builder.h"
29 #include "vk_format.h"
31 enum blit2d_src_type
{
32 BLIT2D_SRC_TYPE_IMAGE
,
33 BLIT2D_SRC_TYPE_BUFFER
,
38 create_iview(struct radv_cmd_buffer
*cmd_buffer
,
39 struct radv_meta_blit2d_surf
*surf
,
40 struct radv_image_view
*iview
, VkFormat depth_format
,
41 VkImageAspectFlagBits aspects
)
46 format
= depth_format
;
48 format
= surf
->format
;
50 radv_image_view_init(iview
, cmd_buffer
->device
,
51 &(VkImageViewCreateInfo
) {
52 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
53 .image
= radv_image_to_handle(surf
->image
),
54 .viewType
= VK_IMAGE_VIEW_TYPE_2D
,
57 .aspectMask
= aspects
,
58 .baseMipLevel
= surf
->level
,
60 .baseArrayLayer
= surf
->layer
,
67 create_bview(struct radv_cmd_buffer
*cmd_buffer
,
68 struct radv_meta_blit2d_buffer
*src
,
69 struct radv_buffer_view
*bview
, VkFormat depth_format
)
74 format
= depth_format
;
77 radv_buffer_view_init(bview
, cmd_buffer
->device
,
78 &(VkBufferViewCreateInfo
) {
79 .sType
= VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO
,
81 .buffer
= radv_buffer_to_handle(src
->buffer
),
83 .offset
= src
->offset
,
84 .range
= VK_WHOLE_SIZE
,
89 struct blit2d_src_temps
{
90 struct radv_image_view iview
;
91 struct radv_buffer_view bview
;
95 blit2d_bind_src(struct radv_cmd_buffer
*cmd_buffer
,
96 struct radv_meta_blit2d_surf
*src_img
,
97 struct radv_meta_blit2d_buffer
*src_buf
,
98 struct blit2d_src_temps
*tmp
,
99 enum blit2d_src_type src_type
, VkFormat depth_format
,
100 VkImageAspectFlagBits aspects
)
102 struct radv_device
*device
= cmd_buffer
->device
;
104 if (src_type
== BLIT2D_SRC_TYPE_BUFFER
) {
105 create_bview(cmd_buffer
, src_buf
, &tmp
->bview
, depth_format
);
107 radv_meta_push_descriptor_set(cmd_buffer
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
108 device
->meta_state
.blit2d
.p_layouts
[src_type
],
110 1, /* descriptorWriteCount */
111 (VkWriteDescriptorSet
[]) {
113 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
115 .dstArrayElement
= 0,
116 .descriptorCount
= 1,
117 .descriptorType
= VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
,
118 .pTexelBufferView
= (VkBufferView
[]) { radv_buffer_view_to_handle(&tmp
->bview
) }
122 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
123 device
->meta_state
.blit2d
.p_layouts
[src_type
],
124 VK_SHADER_STAGE_FRAGMENT_BIT
, 16, 4,
127 create_iview(cmd_buffer
, src_img
, &tmp
->iview
, depth_format
, aspects
);
129 radv_meta_push_descriptor_set(cmd_buffer
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
130 device
->meta_state
.blit2d
.p_layouts
[src_type
],
132 1, /* descriptorWriteCount */
133 (VkWriteDescriptorSet
[]) {
135 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
137 .dstArrayElement
= 0,
138 .descriptorCount
= 1,
139 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
140 .pImageInfo
= (VkDescriptorImageInfo
[]) {
142 .sampler
= VK_NULL_HANDLE
,
143 .imageView
= radv_image_view_to_handle(&tmp
->iview
),
144 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
152 struct blit2d_dst_temps
{
154 struct radv_image_view iview
;
159 blit2d_bind_dst(struct radv_cmd_buffer
*cmd_buffer
,
160 struct radv_meta_blit2d_surf
*dst
,
163 VkFormat depth_format
,
164 struct blit2d_dst_temps
*tmp
,
165 VkImageAspectFlagBits aspects
)
167 create_iview(cmd_buffer
, dst
, &tmp
->iview
, depth_format
, aspects
);
169 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer
->device
),
170 &(VkFramebufferCreateInfo
) {
171 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
172 .attachmentCount
= 1,
173 .pAttachments
= (VkImageView
[]) {
174 radv_image_view_to_handle(&tmp
->iview
),
179 }, &cmd_buffer
->pool
->alloc
, &tmp
->fb
);
183 blit2d_unbind_dst(struct radv_cmd_buffer
*cmd_buffer
,
184 struct blit2d_dst_temps
*tmp
)
186 VkDevice vk_device
= radv_device_to_handle(cmd_buffer
->device
);
187 radv_DestroyFramebuffer(vk_device
, tmp
->fb
, &cmd_buffer
->pool
->alloc
);
191 bind_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
192 enum blit2d_src_type src_type
, unsigned fs_key
)
194 VkPipeline pipeline
=
195 cmd_buffer
->device
->meta_state
.blit2d
.pipelines
[src_type
][fs_key
];
197 if (cmd_buffer
->state
.pipeline
!= radv_pipeline_from_handle(pipeline
)) {
198 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
199 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
204 bind_depth_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
205 enum blit2d_src_type src_type
)
207 VkPipeline pipeline
=
208 cmd_buffer
->device
->meta_state
.blit2d
.depth_only_pipeline
[src_type
];
210 if (cmd_buffer
->state
.pipeline
!= radv_pipeline_from_handle(pipeline
)) {
211 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
212 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
217 bind_stencil_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
218 enum blit2d_src_type src_type
)
220 VkPipeline pipeline
=
221 cmd_buffer
->device
->meta_state
.blit2d
.stencil_only_pipeline
[src_type
];
223 if (cmd_buffer
->state
.pipeline
!= radv_pipeline_from_handle(pipeline
)) {
224 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
225 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
230 radv_meta_blit2d_normal_dst(struct radv_cmd_buffer
*cmd_buffer
,
231 struct radv_meta_blit2d_surf
*src_img
,
232 struct radv_meta_blit2d_buffer
*src_buf
,
233 struct radv_meta_blit2d_surf
*dst
,
235 struct radv_meta_blit2d_rect
*rects
, enum blit2d_src_type src_type
)
237 struct radv_device
*device
= cmd_buffer
->device
;
239 for (unsigned r
= 0; r
< num_rects
; ++r
) {
241 for_each_bit(i
, dst
->aspect_mask
) {
242 unsigned aspect_mask
= 1u << i
;
243 VkFormat depth_format
= 0;
244 if (aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
)
245 depth_format
= vk_format_stencil_only(dst
->image
->vk_format
);
246 else if (aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
)
247 depth_format
= vk_format_depth_only(dst
->image
->vk_format
);
248 struct blit2d_src_temps src_temps
;
249 blit2d_bind_src(cmd_buffer
, src_img
, src_buf
, &src_temps
, src_type
, depth_format
, aspect_mask
);
251 struct blit2d_dst_temps dst_temps
;
252 blit2d_bind_dst(cmd_buffer
, dst
, rects
[r
].dst_x
+ rects
[r
].width
,
253 rects
[r
].dst_y
+ rects
[r
].height
, depth_format
, &dst_temps
, aspect_mask
);
255 float vertex_push_constants
[4] = {
258 rects
[r
].src_x
+ rects
[r
].width
,
259 rects
[r
].src_y
+ rects
[r
].height
,
262 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
263 device
->meta_state
.blit2d
.p_layouts
[src_type
],
264 VK_SHADER_STAGE_VERTEX_BIT
, 0, 16,
265 vertex_push_constants
);
267 if (aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
) {
268 unsigned fs_key
= radv_format_meta_fs_key(dst_temps
.iview
.vk_format
);
270 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
271 &(VkRenderPassBeginInfo
) {
272 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
273 .renderPass
= device
->meta_state
.blit2d
.render_passes
[fs_key
],
274 .framebuffer
= dst_temps
.fb
,
276 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
277 .extent
= { rects
[r
].width
, rects
[r
].height
},
279 .clearValueCount
= 0,
280 .pClearValues
= NULL
,
281 }, VK_SUBPASS_CONTENTS_INLINE
);
284 bind_pipeline(cmd_buffer
, src_type
, fs_key
);
285 } else if (aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
286 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
287 &(VkRenderPassBeginInfo
) {
288 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
289 .renderPass
= device
->meta_state
.blit2d
.depth_only_rp
,
290 .framebuffer
= dst_temps
.fb
,
292 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
293 .extent
= { rects
[r
].width
, rects
[r
].height
},
295 .clearValueCount
= 0,
296 .pClearValues
= NULL
,
297 }, VK_SUBPASS_CONTENTS_INLINE
);
300 bind_depth_pipeline(cmd_buffer
, src_type
);
302 } else if (aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
303 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
304 &(VkRenderPassBeginInfo
) {
305 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
306 .renderPass
= device
->meta_state
.blit2d
.stencil_only_rp
,
307 .framebuffer
= dst_temps
.fb
,
309 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
310 .extent
= { rects
[r
].width
, rects
[r
].height
},
312 .clearValueCount
= 0,
313 .pClearValues
= NULL
,
314 }, VK_SUBPASS_CONTENTS_INLINE
);
317 bind_stencil_pipeline(cmd_buffer
, src_type
);
319 unreachable("Processing blit2d with multiple aspects.");
321 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
324 .width
= rects
[r
].width
,
325 .height
= rects
[r
].height
,
330 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkRect2D
) {
331 .offset
= (VkOffset2D
) { rects
[r
].dst_x
, rects
[r
].dst_y
},
332 .extent
= (VkExtent2D
) { rects
[r
].width
, rects
[r
].height
},
337 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer
), 3, 1, 0, 0);
338 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
));
340 /* At the point where we emit the draw call, all data from the
341 * descriptor sets, etc. has been used. We are free to delete it.
343 blit2d_unbind_dst(cmd_buffer
, &dst_temps
);
349 radv_meta_blit2d(struct radv_cmd_buffer
*cmd_buffer
,
350 struct radv_meta_blit2d_surf
*src_img
,
351 struct radv_meta_blit2d_buffer
*src_buf
,
352 struct radv_meta_blit2d_surf
*dst
,
354 struct radv_meta_blit2d_rect
*rects
)
356 enum blit2d_src_type src_type
= src_buf
? BLIT2D_SRC_TYPE_BUFFER
:
357 BLIT2D_SRC_TYPE_IMAGE
;
358 radv_meta_blit2d_normal_dst(cmd_buffer
, src_img
, src_buf
, dst
,
359 num_rects
, rects
, src_type
);
363 build_nir_vertex_shader(void)
365 const struct glsl_type
*vec4
= glsl_vec4_type();
366 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
369 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
370 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "meta_blit2d_vs");
372 nir_variable
*pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
373 vec4
, "gl_Position");
374 pos_out
->data
.location
= VARYING_SLOT_POS
;
376 nir_variable
*tex_pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
378 tex_pos_out
->data
.location
= VARYING_SLOT_VAR0
;
379 tex_pos_out
->data
.interpolation
= INTERP_MODE_SMOOTH
;
381 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices(&b
);
382 nir_store_var(&b
, pos_out
, outvec
, 0xf);
384 nir_intrinsic_instr
*src_box
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
385 src_box
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
386 nir_intrinsic_set_base(src_box
, 0);
387 nir_intrinsic_set_range(src_box
, 16);
388 src_box
->num_components
= 4;
389 nir_ssa_dest_init(&src_box
->instr
, &src_box
->dest
, 4, 32, "src_box");
390 nir_builder_instr_insert(&b
, &src_box
->instr
);
392 nir_intrinsic_instr
*vertex_id
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_vertex_id_zero_base
);
393 nir_ssa_dest_init(&vertex_id
->instr
, &vertex_id
->dest
, 1, 32, "vertexid");
394 nir_builder_instr_insert(&b
, &vertex_id
->instr
);
396 /* vertex 0 - src_x, src_y */
397 /* vertex 1 - src_x, src_y+h */
398 /* vertex 2 - src_x+w, src_y */
399 /* so channel 0 is vertex_id != 2 ? src_x : src_x + w
400 channel 1 is vertex id != 1 ? src_y : src_y + w */
402 nir_ssa_def
*c0cmp
= nir_ine(&b
, &vertex_id
->dest
.ssa
,
404 nir_ssa_def
*c1cmp
= nir_ine(&b
, &vertex_id
->dest
.ssa
,
407 nir_ssa_def
*comp
[2];
408 comp
[0] = nir_bcsel(&b
, c0cmp
,
409 nir_channel(&b
, &src_box
->dest
.ssa
, 0),
410 nir_channel(&b
, &src_box
->dest
.ssa
, 2));
412 comp
[1] = nir_bcsel(&b
, c1cmp
,
413 nir_channel(&b
, &src_box
->dest
.ssa
, 1),
414 nir_channel(&b
, &src_box
->dest
.ssa
, 3));
415 nir_ssa_def
*out_tex_vec
= nir_vec(&b
, comp
, 2);
416 nir_store_var(&b
, tex_pos_out
, out_tex_vec
, 0x3);
420 typedef nir_ssa_def
* (*texel_fetch_build_func
)(struct nir_builder
*,
421 struct radv_device
*,
425 build_nir_texel_fetch(struct nir_builder
*b
, struct radv_device
*device
,
426 nir_ssa_def
*tex_pos
)
428 const struct glsl_type
*sampler_type
=
429 glsl_sampler_type(GLSL_SAMPLER_DIM_2D
, false, false, GLSL_TYPE_UINT
);
430 nir_variable
*sampler
= nir_variable_create(b
->shader
, nir_var_uniform
,
431 sampler_type
, "s_tex");
432 sampler
->data
.descriptor_set
= 0;
433 sampler
->data
.binding
= 0;
435 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, 2);
436 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
437 tex
->op
= nir_texop_txf
;
438 tex
->src
[0].src_type
= nir_tex_src_coord
;
439 tex
->src
[0].src
= nir_src_for_ssa(tex_pos
);
440 tex
->src
[1].src_type
= nir_tex_src_lod
;
441 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
442 tex
->dest_type
= nir_type_uint
;
443 tex
->is_array
= false;
444 tex
->coord_components
= 2;
445 tex
->texture
= nir_deref_var_create(tex
, sampler
);
448 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
449 nir_builder_instr_insert(b
, &tex
->instr
);
451 return &tex
->dest
.ssa
;
456 build_nir_buffer_fetch(struct nir_builder
*b
, struct radv_device
*device
,
457 nir_ssa_def
*tex_pos
)
459 const struct glsl_type
*sampler_type
=
460 glsl_sampler_type(GLSL_SAMPLER_DIM_BUF
, false, false, GLSL_TYPE_UINT
);
461 nir_variable
*sampler
= nir_variable_create(b
->shader
, nir_var_uniform
,
462 sampler_type
, "s_tex");
463 sampler
->data
.descriptor_set
= 0;
464 sampler
->data
.binding
= 0;
466 nir_intrinsic_instr
*width
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_push_constant
);
467 nir_intrinsic_set_base(width
, 16);
468 nir_intrinsic_set_range(width
, 4);
469 width
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, 0));
470 width
->num_components
= 1;
471 nir_ssa_dest_init(&width
->instr
, &width
->dest
, 1, 32, "width");
472 nir_builder_instr_insert(b
, &width
->instr
);
474 nir_ssa_def
*pos_x
= nir_channel(b
, tex_pos
, 0);
475 nir_ssa_def
*pos_y
= nir_channel(b
, tex_pos
, 1);
476 pos_y
= nir_imul(b
, pos_y
, &width
->dest
.ssa
);
477 pos_x
= nir_iadd(b
, pos_x
, pos_y
);
478 //pos_x = nir_iadd(b, pos_x, nir_imm_int(b, 100000));
480 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, 1);
481 tex
->sampler_dim
= GLSL_SAMPLER_DIM_BUF
;
482 tex
->op
= nir_texop_txf
;
483 tex
->src
[0].src_type
= nir_tex_src_coord
;
484 tex
->src
[0].src
= nir_src_for_ssa(pos_x
);
485 tex
->dest_type
= nir_type_uint
;
486 tex
->is_array
= false;
487 tex
->coord_components
= 1;
488 tex
->texture
= nir_deref_var_create(tex
, sampler
);
491 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
492 nir_builder_instr_insert(b
, &tex
->instr
);
494 return &tex
->dest
.ssa
;
497 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info
= {
498 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
499 .vertexBindingDescriptionCount
= 0,
500 .vertexAttributeDescriptionCount
= 0,
504 build_nir_copy_fragment_shader(struct radv_device
*device
,
505 texel_fetch_build_func txf_func
, const char* name
)
507 const struct glsl_type
*vec4
= glsl_vec4_type();
508 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
511 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
512 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, name
);
514 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
516 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
518 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
520 color_out
->data
.location
= FRAG_RESULT_DATA0
;
522 nir_ssa_def
*pos_int
= nir_f2i32(&b
, nir_load_var(&b
, tex_pos_in
));
523 unsigned swiz
[4] = { 0, 1 };
524 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
526 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
);
527 nir_store_var(&b
, color_out
, color
, 0xf);
533 build_nir_copy_fragment_shader_depth(struct radv_device
*device
,
534 texel_fetch_build_func txf_func
, const char* name
)
536 const struct glsl_type
*vec4
= glsl_vec4_type();
537 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
540 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
541 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, name
);
543 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
545 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
547 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
549 color_out
->data
.location
= FRAG_RESULT_DEPTH
;
551 nir_ssa_def
*pos_int
= nir_f2i32(&b
, nir_load_var(&b
, tex_pos_in
));
552 unsigned swiz
[4] = { 0, 1 };
553 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
555 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
);
556 nir_store_var(&b
, color_out
, color
, 0x1);
562 build_nir_copy_fragment_shader_stencil(struct radv_device
*device
,
563 texel_fetch_build_func txf_func
, const char* name
)
565 const struct glsl_type
*vec4
= glsl_vec4_type();
566 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
569 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
570 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, name
);
572 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
574 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
576 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
578 color_out
->data
.location
= FRAG_RESULT_STENCIL
;
580 nir_ssa_def
*pos_int
= nir_f2i32(&b
, nir_load_var(&b
, tex_pos_in
));
581 unsigned swiz
[4] = { 0, 1 };
582 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
584 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
);
585 nir_store_var(&b
, color_out
, color
, 0x1);
591 radv_device_finish_meta_blit2d_state(struct radv_device
*device
)
593 for(unsigned j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
594 if (device
->meta_state
.blit2d
.render_passes
[j
]) {
595 radv_DestroyRenderPass(radv_device_to_handle(device
),
596 device
->meta_state
.blit2d
.render_passes
[j
],
597 &device
->meta_state
.alloc
);
601 radv_DestroyRenderPass(radv_device_to_handle(device
),
602 device
->meta_state
.blit2d
.depth_only_rp
,
603 &device
->meta_state
.alloc
);
604 radv_DestroyRenderPass(radv_device_to_handle(device
),
605 device
->meta_state
.blit2d
.stencil_only_rp
,
606 &device
->meta_state
.alloc
);
608 for (unsigned src
= 0; src
< BLIT2D_NUM_SRC_TYPES
; src
++) {
609 if (device
->meta_state
.blit2d
.p_layouts
[src
]) {
610 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
611 device
->meta_state
.blit2d
.p_layouts
[src
],
612 &device
->meta_state
.alloc
);
615 if (device
->meta_state
.blit2d
.ds_layouts
[src
]) {
616 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
617 device
->meta_state
.blit2d
.ds_layouts
[src
],
618 &device
->meta_state
.alloc
);
621 for (unsigned j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
622 if (device
->meta_state
.blit2d
.pipelines
[src
][j
]) {
623 radv_DestroyPipeline(radv_device_to_handle(device
),
624 device
->meta_state
.blit2d
.pipelines
[src
][j
],
625 &device
->meta_state
.alloc
);
629 radv_DestroyPipeline(radv_device_to_handle(device
),
630 device
->meta_state
.blit2d
.depth_only_pipeline
[src
],
631 &device
->meta_state
.alloc
);
632 radv_DestroyPipeline(radv_device_to_handle(device
),
633 device
->meta_state
.blit2d
.stencil_only_pipeline
[src
],
634 &device
->meta_state
.alloc
);
639 blit2d_init_color_pipeline(struct radv_device
*device
,
640 enum blit2d_src_type src_type
,
644 unsigned fs_key
= radv_format_meta_fs_key(format
);
647 texel_fetch_build_func src_func
;
649 case BLIT2D_SRC_TYPE_IMAGE
:
650 src_func
= build_nir_texel_fetch
;
651 name
= "meta_blit2d_image_fs";
653 case BLIT2D_SRC_TYPE_BUFFER
:
654 src_func
= build_nir_buffer_fetch
;
655 name
= "meta_blit2d_buffer_fs";
658 unreachable("unknown blit src type\n");
662 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
663 struct radv_shader_module fs
= { .nir
= NULL
};
666 fs
.nir
= build_nir_copy_fragment_shader(device
, src_func
, name
);
667 vi_create_info
= &normal_vi_create_info
;
669 struct radv_shader_module vs
= {
670 .nir
= build_nir_vertex_shader(),
673 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
675 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
676 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
677 .module
= radv_shader_module_to_handle(&vs
),
679 .pSpecializationInfo
= NULL
681 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
682 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
683 .module
= radv_shader_module_to_handle(&fs
),
685 .pSpecializationInfo
= NULL
689 if (!device
->meta_state
.blit2d
.render_passes
[fs_key
]) {
690 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
691 &(VkRenderPassCreateInfo
) {
692 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
693 .attachmentCount
= 1,
694 .pAttachments
= &(VkAttachmentDescription
) {
696 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
697 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
698 .initialLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
699 .finalLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
702 .pSubpasses
= &(VkSubpassDescription
) {
703 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
704 .inputAttachmentCount
= 0,
705 .colorAttachmentCount
= 1,
706 .pColorAttachments
= &(VkAttachmentReference
) {
708 .layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
710 .pResolveAttachments
= NULL
,
711 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
712 .attachment
= VK_ATTACHMENT_UNUSED
,
713 .layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
715 .preserveAttachmentCount
= 1,
716 .pPreserveAttachments
= (uint32_t[]) { 0 },
718 .dependencyCount
= 0,
719 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.render_passes
[fs_key
]);
722 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
723 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
724 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
725 .pStages
= pipeline_shader_stages
,
726 .pVertexInputState
= vi_create_info
,
727 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
728 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
729 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
730 .primitiveRestartEnable
= false,
732 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
733 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
737 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
738 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
739 .rasterizerDiscardEnable
= false,
740 .polygonMode
= VK_POLYGON_MODE_FILL
,
741 .cullMode
= VK_CULL_MODE_NONE
,
742 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
744 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
745 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
746 .rasterizationSamples
= 1,
747 .sampleShadingEnable
= false,
748 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
750 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
751 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
752 .attachmentCount
= 1,
753 .pAttachments
= (VkPipelineColorBlendAttachmentState
[]) {
755 VK_COLOR_COMPONENT_A_BIT
|
756 VK_COLOR_COMPONENT_R_BIT
|
757 VK_COLOR_COMPONENT_G_BIT
|
758 VK_COLOR_COMPONENT_B_BIT
},
761 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
762 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
763 .dynamicStateCount
= 9,
764 .pDynamicStates
= (VkDynamicState
[]) {
765 VK_DYNAMIC_STATE_VIEWPORT
,
766 VK_DYNAMIC_STATE_SCISSOR
,
767 VK_DYNAMIC_STATE_LINE_WIDTH
,
768 VK_DYNAMIC_STATE_DEPTH_BIAS
,
769 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
770 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
771 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
772 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
773 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
777 .layout
= device
->meta_state
.blit2d
.p_layouts
[src_type
],
778 .renderPass
= device
->meta_state
.blit2d
.render_passes
[fs_key
],
782 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
786 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
787 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
788 &vk_pipeline_info
, &radv_pipeline_info
,
789 &device
->meta_state
.alloc
,
790 &device
->meta_state
.blit2d
.pipelines
[src_type
][fs_key
]);
800 blit2d_init_depth_only_pipeline(struct radv_device
*device
,
801 enum blit2d_src_type src_type
)
806 texel_fetch_build_func src_func
;
808 case BLIT2D_SRC_TYPE_IMAGE
:
809 src_func
= build_nir_texel_fetch
;
810 name
= "meta_blit2d_depth_image_fs";
812 case BLIT2D_SRC_TYPE_BUFFER
:
813 src_func
= build_nir_buffer_fetch
;
814 name
= "meta_blit2d_depth_buffer_fs";
817 unreachable("unknown blit src type\n");
821 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
822 struct radv_shader_module fs
= { .nir
= NULL
};
824 fs
.nir
= build_nir_copy_fragment_shader_depth(device
, src_func
, name
);
825 vi_create_info
= &normal_vi_create_info
;
827 struct radv_shader_module vs
= {
828 .nir
= build_nir_vertex_shader(),
831 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
833 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
834 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
835 .module
= radv_shader_module_to_handle(&vs
),
837 .pSpecializationInfo
= NULL
839 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
840 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
841 .module
= radv_shader_module_to_handle(&fs
),
843 .pSpecializationInfo
= NULL
847 if (!device
->meta_state
.blit2d
.depth_only_rp
) {
848 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
849 &(VkRenderPassCreateInfo
) {
850 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
851 .attachmentCount
= 1,
852 .pAttachments
= &(VkAttachmentDescription
) {
853 .format
= VK_FORMAT_D32_SFLOAT
,
854 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
855 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
856 .initialLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
857 .finalLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
860 .pSubpasses
= &(VkSubpassDescription
) {
861 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
862 .inputAttachmentCount
= 0,
863 .colorAttachmentCount
= 0,
864 .pColorAttachments
= NULL
,
865 .pResolveAttachments
= NULL
,
866 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
868 .layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
870 .preserveAttachmentCount
= 1,
871 .pPreserveAttachments
= (uint32_t[]) { 0 },
873 .dependencyCount
= 0,
874 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.depth_only_rp
);
877 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
878 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
879 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
880 .pStages
= pipeline_shader_stages
,
881 .pVertexInputState
= vi_create_info
,
882 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
883 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
884 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
885 .primitiveRestartEnable
= false,
887 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
888 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
892 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
893 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
894 .rasterizerDiscardEnable
= false,
895 .polygonMode
= VK_POLYGON_MODE_FILL
,
896 .cullMode
= VK_CULL_MODE_NONE
,
897 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
899 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
900 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
901 .rasterizationSamples
= 1,
902 .sampleShadingEnable
= false,
903 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
905 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
906 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
907 .attachmentCount
= 0,
908 .pAttachments
= NULL
,
910 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
911 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
912 .depthTestEnable
= true,
913 .depthWriteEnable
= true,
914 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
916 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
917 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
918 .dynamicStateCount
= 9,
919 .pDynamicStates
= (VkDynamicState
[]) {
920 VK_DYNAMIC_STATE_VIEWPORT
,
921 VK_DYNAMIC_STATE_SCISSOR
,
922 VK_DYNAMIC_STATE_LINE_WIDTH
,
923 VK_DYNAMIC_STATE_DEPTH_BIAS
,
924 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
925 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
926 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
927 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
928 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
932 .layout
= device
->meta_state
.blit2d
.p_layouts
[src_type
],
933 .renderPass
= device
->meta_state
.blit2d
.depth_only_rp
,
937 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
941 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
942 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
943 &vk_pipeline_info
, &radv_pipeline_info
,
944 &device
->meta_state
.alloc
,
945 &device
->meta_state
.blit2d
.depth_only_pipeline
[src_type
]);
955 blit2d_init_stencil_only_pipeline(struct radv_device
*device
,
956 enum blit2d_src_type src_type
)
961 texel_fetch_build_func src_func
;
963 case BLIT2D_SRC_TYPE_IMAGE
:
964 src_func
= build_nir_texel_fetch
;
965 name
= "meta_blit2d_stencil_image_fs";
967 case BLIT2D_SRC_TYPE_BUFFER
:
968 src_func
= build_nir_buffer_fetch
;
969 name
= "meta_blit2d_stencil_buffer_fs";
972 unreachable("unknown blit src type\n");
976 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
977 struct radv_shader_module fs
= { .nir
= NULL
};
979 fs
.nir
= build_nir_copy_fragment_shader_stencil(device
, src_func
, name
);
980 vi_create_info
= &normal_vi_create_info
;
982 struct radv_shader_module vs
= {
983 .nir
= build_nir_vertex_shader(),
986 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
988 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
989 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
990 .module
= radv_shader_module_to_handle(&vs
),
992 .pSpecializationInfo
= NULL
994 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
995 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
996 .module
= radv_shader_module_to_handle(&fs
),
998 .pSpecializationInfo
= NULL
1002 if (!device
->meta_state
.blit2d
.stencil_only_rp
) {
1003 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
1004 &(VkRenderPassCreateInfo
) {
1005 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
1006 .attachmentCount
= 1,
1007 .pAttachments
= &(VkAttachmentDescription
) {
1008 .format
= VK_FORMAT_S8_UINT
,
1009 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1010 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1011 .initialLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
1012 .finalLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
1015 .pSubpasses
= &(VkSubpassDescription
) {
1016 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
1017 .inputAttachmentCount
= 0,
1018 .colorAttachmentCount
= 0,
1019 .pColorAttachments
= NULL
,
1020 .pResolveAttachments
= NULL
,
1021 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
1023 .layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
1025 .preserveAttachmentCount
= 1,
1026 .pPreserveAttachments
= (uint32_t[]) { 0 },
1028 .dependencyCount
= 0,
1029 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.stencil_only_rp
);
1032 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
1033 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
1034 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
1035 .pStages
= pipeline_shader_stages
,
1036 .pVertexInputState
= vi_create_info
,
1037 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
1038 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
1039 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
1040 .primitiveRestartEnable
= false,
1042 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
1043 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
1047 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
1048 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
1049 .rasterizerDiscardEnable
= false,
1050 .polygonMode
= VK_POLYGON_MODE_FILL
,
1051 .cullMode
= VK_CULL_MODE_NONE
,
1052 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
1054 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
1055 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
1056 .rasterizationSamples
= 1,
1057 .sampleShadingEnable
= false,
1058 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
1060 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
1061 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
1062 .attachmentCount
= 0,
1063 .pAttachments
= NULL
,
1065 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
1066 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
1067 .depthTestEnable
= false,
1068 .depthWriteEnable
= false,
1069 .stencilTestEnable
= true,
1071 .failOp
= VK_STENCIL_OP_REPLACE
,
1072 .passOp
= VK_STENCIL_OP_REPLACE
,
1073 .depthFailOp
= VK_STENCIL_OP_REPLACE
,
1074 .compareOp
= VK_COMPARE_OP_ALWAYS
,
1075 .compareMask
= 0xff,
1080 .failOp
= VK_STENCIL_OP_REPLACE
,
1081 .passOp
= VK_STENCIL_OP_REPLACE
,
1082 .depthFailOp
= VK_STENCIL_OP_REPLACE
,
1083 .compareOp
= VK_COMPARE_OP_ALWAYS
,
1084 .compareMask
= 0xff,
1088 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
1090 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
1091 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
1092 .dynamicStateCount
= 6,
1093 .pDynamicStates
= (VkDynamicState
[]) {
1094 VK_DYNAMIC_STATE_VIEWPORT
,
1095 VK_DYNAMIC_STATE_SCISSOR
,
1096 VK_DYNAMIC_STATE_LINE_WIDTH
,
1097 VK_DYNAMIC_STATE_DEPTH_BIAS
,
1098 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
1099 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
1103 .layout
= device
->meta_state
.blit2d
.p_layouts
[src_type
],
1104 .renderPass
= device
->meta_state
.blit2d
.stencil_only_rp
,
1108 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
1109 .use_rectlist
= true
1112 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1113 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1114 &vk_pipeline_info
, &radv_pipeline_info
,
1115 &device
->meta_state
.alloc
,
1116 &device
->meta_state
.blit2d
.stencil_only_pipeline
[src_type
]);
1119 ralloc_free(vs
.nir
);
1120 ralloc_free(fs
.nir
);
1125 static VkFormat pipeline_formats
[] = {
1126 VK_FORMAT_R8G8B8A8_UNORM
,
1127 VK_FORMAT_R8G8B8A8_UINT
,
1128 VK_FORMAT_R8G8B8A8_SINT
,
1129 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
1130 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
1131 VK_FORMAT_R16G16B16A16_UNORM
,
1132 VK_FORMAT_R16G16B16A16_SNORM
,
1133 VK_FORMAT_R16G16B16A16_UINT
,
1134 VK_FORMAT_R16G16B16A16_SINT
,
1135 VK_FORMAT_R32_SFLOAT
,
1136 VK_FORMAT_R32G32_SFLOAT
,
1137 VK_FORMAT_R32G32B32A32_SFLOAT
1141 radv_device_init_meta_blit2d_state(struct radv_device
*device
)
1145 zero(device
->meta_state
.blit2d
);
1147 const VkPushConstantRange push_constant_ranges
[] = {
1148 {VK_SHADER_STAGE_VERTEX_BIT
, 0, 16},
1149 {VK_SHADER_STAGE_FRAGMENT_BIT
, 16, 4},
1151 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
1152 &(VkDescriptorSetLayoutCreateInfo
) {
1153 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
1154 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
1156 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
1159 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
1160 .descriptorCount
= 1,
1161 .stageFlags
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1162 .pImmutableSamplers
= NULL
1165 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.ds_layouts
[BLIT2D_SRC_TYPE_IMAGE
]);
1166 if (result
!= VK_SUCCESS
)
1169 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1170 &(VkPipelineLayoutCreateInfo
) {
1171 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1172 .setLayoutCount
= 1,
1173 .pSetLayouts
= &device
->meta_state
.blit2d
.ds_layouts
[BLIT2D_SRC_TYPE_IMAGE
],
1174 .pushConstantRangeCount
= 1,
1175 .pPushConstantRanges
= push_constant_ranges
,
1177 &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.p_layouts
[BLIT2D_SRC_TYPE_IMAGE
]);
1178 if (result
!= VK_SUCCESS
)
1181 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
1182 &(VkDescriptorSetLayoutCreateInfo
) {
1183 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
1184 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
1186 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
1189 .descriptorType
= VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
,
1190 .descriptorCount
= 1,
1191 .stageFlags
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1192 .pImmutableSamplers
= NULL
1195 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.ds_layouts
[BLIT2D_SRC_TYPE_BUFFER
]);
1196 if (result
!= VK_SUCCESS
)
1200 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1201 &(VkPipelineLayoutCreateInfo
) {
1202 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1203 .setLayoutCount
= 1,
1204 .pSetLayouts
= &device
->meta_state
.blit2d
.ds_layouts
[BLIT2D_SRC_TYPE_BUFFER
],
1205 .pushConstantRangeCount
= 2,
1206 .pPushConstantRanges
= push_constant_ranges
,
1208 &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.p_layouts
[BLIT2D_SRC_TYPE_BUFFER
]);
1209 if (result
!= VK_SUCCESS
)
1212 for (unsigned src
= 0; src
< BLIT2D_NUM_SRC_TYPES
; src
++) {
1213 for (unsigned j
= 0; j
< ARRAY_SIZE(pipeline_formats
); ++j
) {
1214 result
= blit2d_init_color_pipeline(device
, src
, pipeline_formats
[j
]);
1215 if (result
!= VK_SUCCESS
)
1219 result
= blit2d_init_depth_only_pipeline(device
, src
);
1220 if (result
!= VK_SUCCESS
)
1223 result
= blit2d_init_stencil_only_pipeline(device
, src
);
1224 if (result
!= VK_SUCCESS
)
1231 radv_device_finish_meta_blit2d_state(device
);