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[mesa.git] / src / amd / vulkan / radv_meta_blit2d.c
1 /*
2 * Copyright © 2016 Red Hat
3 *
4 * based on anv driver:
5 * Copyright © 2016 Intel Corporation
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * IN THE SOFTWARE.
25 */
26
27 #include "radv_meta.h"
28 #include "nir/nir_builder.h"
29 #include "vk_format.h"
30
31 enum blit2d_dst_type {
32 /* We can bind this destination as a "normal" render target and render
33 * to it just like you would anywhere else.
34 */
35 BLIT2D_DST_TYPE_NORMAL,
36
37 /* The destination has a 3-channel RGB format. Since we can't render to
38 * non-power-of-two textures, we have to bind it as a red texture and
39 * select the correct component for the given red pixel in the shader.
40 */
41 BLIT2D_DST_TYPE_RGB,
42
43 BLIT2D_NUM_DST_TYPES,
44 };
45
46
47 enum blit2d_src_type {
48 BLIT2D_SRC_TYPE_IMAGE,
49 BLIT2D_SRC_TYPE_BUFFER,
50 BLIT2D_NUM_SRC_TYPES,
51 };
52
53 static void
54 create_iview(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_meta_blit2d_surf *surf,
56 VkImageUsageFlags usage,
57 struct radv_image_view *iview, VkFormat depth_format)
58 {
59 VkFormat format;
60
61 if (depth_format)
62 format = depth_format;
63 else
64 format = surf->format;
65
66 radv_image_view_init(iview, cmd_buffer->device,
67 &(VkImageViewCreateInfo) {
68 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
69 .image = radv_image_to_handle(surf->image),
70 .viewType = VK_IMAGE_VIEW_TYPE_2D,
71 .format = format,
72 .subresourceRange = {
73 .aspectMask = surf->aspect_mask,
74 .baseMipLevel = surf->level,
75 .levelCount = 1,
76 .baseArrayLayer = surf->layer,
77 .layerCount = 1
78 },
79 }, cmd_buffer, usage);
80 }
81
82 static void
83 create_bview(struct radv_cmd_buffer *cmd_buffer,
84 struct radv_meta_blit2d_buffer *src,
85 struct radv_buffer_view *bview, VkFormat depth_format)
86 {
87 VkFormat format;
88
89 if (depth_format)
90 format = depth_format;
91 else
92 format = src->format;
93 radv_buffer_view_init(bview, cmd_buffer->device,
94 &(VkBufferViewCreateInfo) {
95 .sType = VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO,
96 .flags = 0,
97 .buffer = radv_buffer_to_handle(src->buffer),
98 .format = format,
99 .offset = src->offset,
100 .range = VK_WHOLE_SIZE,
101 }, cmd_buffer);
102
103 }
104
105 struct blit2d_src_temps {
106 struct radv_image_view iview;
107 struct radv_buffer_view bview;
108 };
109
110 static void
111 blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
112 struct radv_meta_blit2d_surf *src_img,
113 struct radv_meta_blit2d_buffer *src_buf,
114 struct blit2d_src_temps *tmp,
115 enum blit2d_src_type src_type, VkFormat depth_format)
116 {
117 struct radv_device *device = cmd_buffer->device;
118
119 if (src_type == BLIT2D_SRC_TYPE_BUFFER) {
120 create_bview(cmd_buffer, src_buf, &tmp->bview, depth_format);
121
122 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
123 device->meta_state.blit2d.p_layouts[src_type],
124 0, /* set */
125 1, /* descriptorWriteCount */
126 (VkWriteDescriptorSet[]) {
127 {
128 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
129 .dstBinding = 0,
130 .dstArrayElement = 0,
131 .descriptorCount = 1,
132 .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
133 .pTexelBufferView = (VkBufferView[]) { radv_buffer_view_to_handle(&tmp->bview) }
134 }
135 });
136
137 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
138 device->meta_state.blit2d.p_layouts[src_type],
139 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 4,
140 &src_buf->pitch);
141 } else {
142 create_iview(cmd_buffer, src_img, VK_IMAGE_USAGE_SAMPLED_BIT, &tmp->iview,
143 depth_format);
144
145 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
146 device->meta_state.blit2d.p_layouts[src_type],
147 0, /* set */
148 1, /* descriptorWriteCount */
149 (VkWriteDescriptorSet[]) {
150 {
151 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
152 .dstBinding = 0,
153 .dstArrayElement = 0,
154 .descriptorCount = 1,
155 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
156 .pImageInfo = (VkDescriptorImageInfo[]) {
157 {
158 .sampler = VK_NULL_HANDLE,
159 .imageView = radv_image_view_to_handle(&tmp->iview),
160 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
161 },
162 }
163 }
164 });
165 }
166 }
167
168 struct blit2d_dst_temps {
169 VkImage image;
170 struct radv_image_view iview;
171 VkFramebuffer fb;
172 };
173
174 static void
175 blit2d_bind_dst(struct radv_cmd_buffer *cmd_buffer,
176 struct radv_meta_blit2d_surf *dst,
177 uint32_t width,
178 uint32_t height,
179 VkFormat depth_format,
180 struct blit2d_dst_temps *tmp)
181 {
182 VkImageUsageFlagBits bits;
183
184 if (dst->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT)
185 bits = VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
186 else
187 bits = VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT;
188
189 create_iview(cmd_buffer, dst, bits,
190 &tmp->iview, depth_format);
191
192 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer->device),
193 &(VkFramebufferCreateInfo) {
194 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
195 .attachmentCount = 1,
196 .pAttachments = (VkImageView[]) {
197 radv_image_view_to_handle(&tmp->iview),
198 },
199 .width = width,
200 .height = height,
201 .layers = 1
202 }, &cmd_buffer->pool->alloc, &tmp->fb);
203 }
204
205 static void
206 blit2d_unbind_dst(struct radv_cmd_buffer *cmd_buffer,
207 struct blit2d_dst_temps *tmp)
208 {
209 VkDevice vk_device = radv_device_to_handle(cmd_buffer->device);
210 radv_DestroyFramebuffer(vk_device, tmp->fb, &cmd_buffer->pool->alloc);
211 }
212
213 static void
214 bind_pipeline(struct radv_cmd_buffer *cmd_buffer,
215 enum blit2d_src_type src_type, unsigned fs_key)
216 {
217 VkPipeline pipeline =
218 cmd_buffer->device->meta_state.blit2d.pipelines[src_type][fs_key];
219
220 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
221 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
222 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
223 }
224 }
225
226 static void
227 bind_depth_pipeline(struct radv_cmd_buffer *cmd_buffer,
228 enum blit2d_src_type src_type)
229 {
230 VkPipeline pipeline =
231 cmd_buffer->device->meta_state.blit2d.depth_only_pipeline[src_type];
232
233 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
234 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
235 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
236 }
237 }
238
239 static void
240 bind_stencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
241 enum blit2d_src_type src_type)
242 {
243 VkPipeline pipeline =
244 cmd_buffer->device->meta_state.blit2d.stencil_only_pipeline[src_type];
245
246 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
247 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
248 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
249 }
250 }
251
252 static void
253 radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
254 struct radv_meta_blit2d_surf *src_img,
255 struct radv_meta_blit2d_buffer *src_buf,
256 struct radv_meta_blit2d_surf *dst,
257 unsigned num_rects,
258 struct radv_meta_blit2d_rect *rects, enum blit2d_src_type src_type)
259 {
260 struct radv_device *device = cmd_buffer->device;
261
262 for (unsigned r = 0; r < num_rects; ++r) {
263 VkFormat depth_format = 0;
264 if (dst->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT)
265 depth_format = vk_format_stencil_only(dst->image->vk_format);
266 else if (dst->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT)
267 depth_format = vk_format_depth_only(dst->image->vk_format);
268 struct blit2d_src_temps src_temps;
269 blit2d_bind_src(cmd_buffer, src_img, src_buf, &src_temps, src_type, depth_format);
270
271 uint32_t offset = 0;
272 struct blit2d_dst_temps dst_temps;
273 blit2d_bind_dst(cmd_buffer, dst, rects[r].dst_x + rects[r].width,
274 rects[r].dst_y + rects[r].height, depth_format, &dst_temps);
275
276 struct blit_vb_data {
277 float tex_coord[2];
278 } vb_data[3];
279
280 unsigned vb_size = 3 * sizeof(*vb_data);
281
282 vb_data[0] = (struct blit_vb_data) {
283 .tex_coord = {
284 rects[r].src_x,
285 rects[r].src_y,
286 },
287 };
288
289 vb_data[1] = (struct blit_vb_data) {
290 .tex_coord = {
291 rects[r].src_x,
292 rects[r].src_y + rects[r].height,
293 },
294 };
295
296 vb_data[2] = (struct blit_vb_data) {
297 .tex_coord = {
298 rects[r].src_x + rects[r].width,
299 rects[r].src_y,
300 },
301 };
302
303
304 radv_cmd_buffer_upload_data(cmd_buffer, vb_size, 16, vb_data, &offset);
305
306 struct radv_buffer vertex_buffer = {
307 .device = device,
308 .size = vb_size,
309 .bo = cmd_buffer->upload.upload_bo,
310 .offset = offset,
311 };
312
313 radv_CmdBindVertexBuffers(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
314 (VkBuffer[]) {
315 radv_buffer_to_handle(&vertex_buffer),
316 },
317 (VkDeviceSize[]) {
318 0,
319 });
320
321
322 if (dst->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT) {
323 unsigned fs_key = radv_format_meta_fs_key(dst_temps.iview.vk_format);
324
325 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
326 &(VkRenderPassBeginInfo) {
327 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
328 .renderPass = device->meta_state.blit2d.render_passes[fs_key],
329 .framebuffer = dst_temps.fb,
330 .renderArea = {
331 .offset = { rects[r].dst_x, rects[r].dst_y, },
332 .extent = { rects[r].width, rects[r].height },
333 },
334 .clearValueCount = 0,
335 .pClearValues = NULL,
336 }, VK_SUBPASS_CONTENTS_INLINE);
337
338
339 bind_pipeline(cmd_buffer, src_type, fs_key);
340 } else if (dst->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
341 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
342 &(VkRenderPassBeginInfo) {
343 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
344 .renderPass = device->meta_state.blit2d.depth_only_rp,
345 .framebuffer = dst_temps.fb,
346 .renderArea = {
347 .offset = { rects[r].dst_x, rects[r].dst_y, },
348 .extent = { rects[r].width, rects[r].height },
349 },
350 .clearValueCount = 0,
351 .pClearValues = NULL,
352 }, VK_SUBPASS_CONTENTS_INLINE);
353
354
355 bind_depth_pipeline(cmd_buffer, src_type);
356
357 } else if (dst->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
358 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
359 &(VkRenderPassBeginInfo) {
360 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
361 .renderPass = device->meta_state.blit2d.stencil_only_rp,
362 .framebuffer = dst_temps.fb,
363 .renderArea = {
364 .offset = { rects[r].dst_x, rects[r].dst_y, },
365 .extent = { rects[r].width, rects[r].height },
366 },
367 .clearValueCount = 0,
368 .pClearValues = NULL,
369 }, VK_SUBPASS_CONTENTS_INLINE);
370
371
372 bind_stencil_pipeline(cmd_buffer, src_type);
373 }
374
375 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
376 .x = rects[r].dst_x,
377 .y = rects[r].dst_y,
378 .width = rects[r].width,
379 .height = rects[r].height,
380 .minDepth = 0.0f,
381 .maxDepth = 1.0f
382 });
383
384 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
385 .offset = (VkOffset2D) { rects[r].dst_x, rects[r].dst_y },
386 .extent = (VkExtent2D) { rects[r].width, rects[r].height },
387 });
388
389
390
391 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
392 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
393
394 /* At the point where we emit the draw call, all data from the
395 * descriptor sets, etc. has been used. We are free to delete it.
396 */
397 blit2d_unbind_dst(cmd_buffer, &dst_temps);
398 }
399 }
400
401 void
402 radv_meta_blit2d(struct radv_cmd_buffer *cmd_buffer,
403 struct radv_meta_blit2d_surf *src_img,
404 struct radv_meta_blit2d_buffer *src_buf,
405 struct radv_meta_blit2d_surf *dst,
406 unsigned num_rects,
407 struct radv_meta_blit2d_rect *rects)
408 {
409 enum blit2d_src_type src_type = src_buf ? BLIT2D_SRC_TYPE_BUFFER :
410 BLIT2D_SRC_TYPE_IMAGE;
411 radv_meta_blit2d_normal_dst(cmd_buffer, src_img, src_buf, dst,
412 num_rects, rects, src_type);
413 }
414
415 static nir_shader *
416 build_nir_vertex_shader(void)
417 {
418 const struct glsl_type *vec4 = glsl_vec4_type();
419 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
420 nir_builder b;
421
422 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
423 b.shader->info->name = ralloc_strdup(b.shader, "meta_blit_vs");
424
425 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
426 vec4, "gl_Position");
427 pos_out->data.location = VARYING_SLOT_POS;
428
429 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
430 vec2, "a_tex_pos");
431 tex_pos_in->data.location = VERT_ATTRIB_GENERIC0;
432 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
433 vec2, "v_tex_pos");
434 tex_pos_out->data.location = VARYING_SLOT_VAR0;
435 tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
436 nir_copy_var(&b, tex_pos_out, tex_pos_in);
437
438 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
439
440 nir_store_var(&b, pos_out, outvec, 0xf);
441 return b.shader;
442 }
443
444 typedef nir_ssa_def* (*texel_fetch_build_func)(struct nir_builder *,
445 struct radv_device *,
446 nir_ssa_def *);
447
448 static nir_ssa_def *
449 build_nir_texel_fetch(struct nir_builder *b, struct radv_device *device,
450 nir_ssa_def *tex_pos)
451 {
452 const struct glsl_type *sampler_type =
453 glsl_sampler_type(GLSL_SAMPLER_DIM_2D, false, false, GLSL_TYPE_UINT);
454 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
455 sampler_type, "s_tex");
456 sampler->data.descriptor_set = 0;
457 sampler->data.binding = 0;
458
459 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 2);
460 tex->sampler_dim = GLSL_SAMPLER_DIM_2D;
461 tex->op = nir_texop_txf;
462 tex->src[0].src_type = nir_tex_src_coord;
463 tex->src[0].src = nir_src_for_ssa(tex_pos);
464 tex->src[1].src_type = nir_tex_src_lod;
465 tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
466 tex->dest_type = nir_type_uint;
467 tex->is_array = false;
468 tex->coord_components = 2;
469 tex->texture = nir_deref_var_create(tex, sampler);
470 tex->sampler = NULL;
471
472 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
473 nir_builder_instr_insert(b, &tex->instr);
474
475 return &tex->dest.ssa;
476 }
477
478
479 static nir_ssa_def *
480 build_nir_buffer_fetch(struct nir_builder *b, struct radv_device *device,
481 nir_ssa_def *tex_pos)
482 {
483 const struct glsl_type *sampler_type =
484 glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_UINT);
485 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
486 sampler_type, "s_tex");
487 sampler->data.descriptor_set = 0;
488 sampler->data.binding = 0;
489
490 nir_intrinsic_instr *width = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
491 nir_intrinsic_set_base(width, 0);
492 nir_intrinsic_set_range(width, 4);
493 width->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
494 width->num_components = 1;
495 nir_ssa_dest_init(&width->instr, &width->dest, 1, 32, "width");
496 nir_builder_instr_insert(b, &width->instr);
497
498 nir_ssa_def *pos_x = nir_channel(b, tex_pos, 0);
499 nir_ssa_def *pos_y = nir_channel(b, tex_pos, 1);
500 pos_y = nir_imul(b, pos_y, &width->dest.ssa);
501 pos_x = nir_iadd(b, pos_x, pos_y);
502 //pos_x = nir_iadd(b, pos_x, nir_imm_int(b, 100000));
503
504 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 1);
505 tex->sampler_dim = GLSL_SAMPLER_DIM_BUF;
506 tex->op = nir_texop_txf;
507 tex->src[0].src_type = nir_tex_src_coord;
508 tex->src[0].src = nir_src_for_ssa(pos_x);
509 tex->dest_type = nir_type_uint;
510 tex->is_array = false;
511 tex->coord_components = 1;
512 tex->texture = nir_deref_var_create(tex, sampler);
513 tex->sampler = NULL;
514
515 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
516 nir_builder_instr_insert(b, &tex->instr);
517
518 return &tex->dest.ssa;
519 }
520
521 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
522 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
523 .vertexBindingDescriptionCount = 1,
524 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
525 {
526 .binding = 0,
527 .stride = 2 * sizeof(float),
528 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
529 },
530 },
531 .vertexAttributeDescriptionCount = 1,
532 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
533 {
534 /* Texture Coordinate */
535 .location = 0,
536 .binding = 0,
537 .format = VK_FORMAT_R32G32_SFLOAT,
538 .offset = 0
539 },
540 },
541 };
542
543 static nir_shader *
544 build_nir_copy_fragment_shader(struct radv_device *device,
545 texel_fetch_build_func txf_func, const char* name)
546 {
547 const struct glsl_type *vec4 = glsl_vec4_type();
548 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
549 nir_builder b;
550
551 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
552 b.shader->info->name = ralloc_strdup(b.shader, name);
553
554 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
555 vec2, "v_tex_pos");
556 tex_pos_in->data.location = VARYING_SLOT_VAR0;
557
558 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
559 vec4, "f_color");
560 color_out->data.location = FRAG_RESULT_DATA0;
561
562 nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
563 unsigned swiz[4] = { 0, 1 };
564 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
565
566 nir_ssa_def *color = txf_func(&b, device, tex_pos);
567 nir_store_var(&b, color_out, color, 0xf);
568
569 return b.shader;
570 }
571
572 static nir_shader *
573 build_nir_copy_fragment_shader_depth(struct radv_device *device,
574 texel_fetch_build_func txf_func, const char* name)
575 {
576 const struct glsl_type *vec4 = glsl_vec4_type();
577 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
578 nir_builder b;
579
580 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
581 b.shader->info->name = ralloc_strdup(b.shader, name);
582
583 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
584 vec2, "v_tex_pos");
585 tex_pos_in->data.location = VARYING_SLOT_VAR0;
586
587 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
588 vec4, "f_color");
589 color_out->data.location = FRAG_RESULT_DEPTH;
590
591 nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
592 unsigned swiz[4] = { 0, 1 };
593 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
594
595 nir_ssa_def *color = txf_func(&b, device, tex_pos);
596 nir_store_var(&b, color_out, color, 0x1);
597
598 return b.shader;
599 }
600
601 static nir_shader *
602 build_nir_copy_fragment_shader_stencil(struct radv_device *device,
603 texel_fetch_build_func txf_func, const char* name)
604 {
605 const struct glsl_type *vec4 = glsl_vec4_type();
606 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
607 nir_builder b;
608
609 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
610 b.shader->info->name = ralloc_strdup(b.shader, name);
611
612 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
613 vec2, "v_tex_pos");
614 tex_pos_in->data.location = VARYING_SLOT_VAR0;
615
616 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
617 vec4, "f_color");
618 color_out->data.location = FRAG_RESULT_STENCIL;
619
620 nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
621 unsigned swiz[4] = { 0, 1 };
622 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
623
624 nir_ssa_def *color = txf_func(&b, device, tex_pos);
625 nir_store_var(&b, color_out, color, 0x1);
626
627 return b.shader;
628 }
629
630 void
631 radv_device_finish_meta_blit2d_state(struct radv_device *device)
632 {
633 for(unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
634 if (device->meta_state.blit2d.render_passes[j]) {
635 radv_DestroyRenderPass(radv_device_to_handle(device),
636 device->meta_state.blit2d.render_passes[j],
637 &device->meta_state.alloc);
638 }
639 }
640
641 radv_DestroyRenderPass(radv_device_to_handle(device),
642 device->meta_state.blit2d.depth_only_rp,
643 &device->meta_state.alloc);
644 radv_DestroyRenderPass(radv_device_to_handle(device),
645 device->meta_state.blit2d.stencil_only_rp,
646 &device->meta_state.alloc);
647
648 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
649 if (device->meta_state.blit2d.p_layouts[src]) {
650 radv_DestroyPipelineLayout(radv_device_to_handle(device),
651 device->meta_state.blit2d.p_layouts[src],
652 &device->meta_state.alloc);
653 }
654
655 if (device->meta_state.blit2d.ds_layouts[src]) {
656 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
657 device->meta_state.blit2d.ds_layouts[src],
658 &device->meta_state.alloc);
659 }
660
661 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
662 if (device->meta_state.blit2d.pipelines[src][j]) {
663 radv_DestroyPipeline(radv_device_to_handle(device),
664 device->meta_state.blit2d.pipelines[src][j],
665 &device->meta_state.alloc);
666 }
667 }
668
669 radv_DestroyPipeline(radv_device_to_handle(device),
670 device->meta_state.blit2d.depth_only_pipeline[src],
671 &device->meta_state.alloc);
672 radv_DestroyPipeline(radv_device_to_handle(device),
673 device->meta_state.blit2d.stencil_only_pipeline[src],
674 &device->meta_state.alloc);
675 }
676 }
677
678 static VkResult
679 blit2d_init_color_pipeline(struct radv_device *device,
680 enum blit2d_src_type src_type,
681 VkFormat format)
682 {
683 VkResult result;
684 unsigned fs_key = radv_format_meta_fs_key(format);
685 const char *name;
686
687 texel_fetch_build_func src_func;
688 switch(src_type) {
689 case BLIT2D_SRC_TYPE_IMAGE:
690 src_func = build_nir_texel_fetch;
691 name = "meta_blit2d_image_fs";
692 break;
693 case BLIT2D_SRC_TYPE_BUFFER:
694 src_func = build_nir_buffer_fetch;
695 name = "meta_blit2d_buffer_fs";
696 break;
697 default:
698 unreachable("unknown blit src type\n");
699 break;
700 }
701
702 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
703 struct radv_shader_module fs = { .nir = NULL };
704
705
706 fs.nir = build_nir_copy_fragment_shader(device, src_func, name);
707 vi_create_info = &normal_vi_create_info;
708
709 struct radv_shader_module vs = {
710 .nir = build_nir_vertex_shader(),
711 };
712
713 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
714 {
715 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
716 .stage = VK_SHADER_STAGE_VERTEX_BIT,
717 .module = radv_shader_module_to_handle(&vs),
718 .pName = "main",
719 .pSpecializationInfo = NULL
720 }, {
721 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
722 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
723 .module = radv_shader_module_to_handle(&fs),
724 .pName = "main",
725 .pSpecializationInfo = NULL
726 },
727 };
728
729 if (!device->meta_state.blit2d.render_passes[fs_key]) {
730 result = radv_CreateRenderPass(radv_device_to_handle(device),
731 &(VkRenderPassCreateInfo) {
732 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
733 .attachmentCount = 1,
734 .pAttachments = &(VkAttachmentDescription) {
735 .format = format,
736 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
737 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
738 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
739 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
740 },
741 .subpassCount = 1,
742 .pSubpasses = &(VkSubpassDescription) {
743 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
744 .inputAttachmentCount = 0,
745 .colorAttachmentCount = 1,
746 .pColorAttachments = &(VkAttachmentReference) {
747 .attachment = 0,
748 .layout = VK_IMAGE_LAYOUT_GENERAL,
749 },
750 .pResolveAttachments = NULL,
751 .pDepthStencilAttachment = &(VkAttachmentReference) {
752 .attachment = VK_ATTACHMENT_UNUSED,
753 .layout = VK_IMAGE_LAYOUT_GENERAL,
754 },
755 .preserveAttachmentCount = 1,
756 .pPreserveAttachments = (uint32_t[]) { 0 },
757 },
758 .dependencyCount = 0,
759 }, &device->meta_state.alloc, &device->meta_state.blit2d.render_passes[fs_key]);
760 }
761
762 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
763 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
764 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
765 .pStages = pipeline_shader_stages,
766 .pVertexInputState = vi_create_info,
767 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
768 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
769 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
770 .primitiveRestartEnable = false,
771 },
772 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
773 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
774 .viewportCount = 1,
775 .scissorCount = 1,
776 },
777 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
778 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
779 .rasterizerDiscardEnable = false,
780 .polygonMode = VK_POLYGON_MODE_FILL,
781 .cullMode = VK_CULL_MODE_NONE,
782 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
783 },
784 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
785 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
786 .rasterizationSamples = 1,
787 .sampleShadingEnable = false,
788 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
789 },
790 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
791 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
792 .attachmentCount = 1,
793 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
794 { .colorWriteMask =
795 VK_COLOR_COMPONENT_A_BIT |
796 VK_COLOR_COMPONENT_R_BIT |
797 VK_COLOR_COMPONENT_G_BIT |
798 VK_COLOR_COMPONENT_B_BIT },
799 }
800 },
801 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
802 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
803 .dynamicStateCount = 9,
804 .pDynamicStates = (VkDynamicState[]) {
805 VK_DYNAMIC_STATE_VIEWPORT,
806 VK_DYNAMIC_STATE_SCISSOR,
807 VK_DYNAMIC_STATE_LINE_WIDTH,
808 VK_DYNAMIC_STATE_DEPTH_BIAS,
809 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
810 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
811 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
812 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
813 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
814 },
815 },
816 .flags = 0,
817 .layout = device->meta_state.blit2d.p_layouts[src_type],
818 .renderPass = device->meta_state.blit2d.render_passes[fs_key],
819 .subpass = 0,
820 };
821
822 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
823 .use_rectlist = true
824 };
825
826 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
827 radv_pipeline_cache_to_handle(&device->meta_state.cache),
828 &vk_pipeline_info, &radv_pipeline_info,
829 &device->meta_state.alloc,
830 &device->meta_state.blit2d.pipelines[src_type][fs_key]);
831
832
833 ralloc_free(vs.nir);
834 ralloc_free(fs.nir);
835
836 return result;
837 }
838
839 static VkResult
840 blit2d_init_depth_only_pipeline(struct radv_device *device,
841 enum blit2d_src_type src_type)
842 {
843 VkResult result;
844 const char *name;
845
846 texel_fetch_build_func src_func;
847 switch(src_type) {
848 case BLIT2D_SRC_TYPE_IMAGE:
849 src_func = build_nir_texel_fetch;
850 name = "meta_blit2d_depth_image_fs";
851 break;
852 case BLIT2D_SRC_TYPE_BUFFER:
853 src_func = build_nir_buffer_fetch;
854 name = "meta_blit2d_depth_buffer_fs";
855 break;
856 default:
857 unreachable("unknown blit src type\n");
858 break;
859 }
860
861 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
862 struct radv_shader_module fs = { .nir = NULL };
863
864 fs.nir = build_nir_copy_fragment_shader_depth(device, src_func, name);
865 vi_create_info = &normal_vi_create_info;
866
867 struct radv_shader_module vs = {
868 .nir = build_nir_vertex_shader(),
869 };
870
871 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
872 {
873 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
874 .stage = VK_SHADER_STAGE_VERTEX_BIT,
875 .module = radv_shader_module_to_handle(&vs),
876 .pName = "main",
877 .pSpecializationInfo = NULL
878 }, {
879 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
880 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
881 .module = radv_shader_module_to_handle(&fs),
882 .pName = "main",
883 .pSpecializationInfo = NULL
884 },
885 };
886
887 if (!device->meta_state.blit2d.depth_only_rp) {
888 result = radv_CreateRenderPass(radv_device_to_handle(device),
889 &(VkRenderPassCreateInfo) {
890 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
891 .attachmentCount = 1,
892 .pAttachments = &(VkAttachmentDescription) {
893 .format = 0,
894 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
895 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
896 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
897 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
898 },
899 .subpassCount = 1,
900 .pSubpasses = &(VkSubpassDescription) {
901 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
902 .inputAttachmentCount = 0,
903 .colorAttachmentCount = 0,
904 .pColorAttachments = NULL,
905 .pResolveAttachments = NULL,
906 .pDepthStencilAttachment = &(VkAttachmentReference) {
907 .attachment = 0,
908 .layout = VK_IMAGE_LAYOUT_GENERAL,
909 },
910 .preserveAttachmentCount = 1,
911 .pPreserveAttachments = (uint32_t[]) { 0 },
912 },
913 .dependencyCount = 0,
914 }, &device->meta_state.alloc, &device->meta_state.blit2d.depth_only_rp);
915 }
916
917 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
918 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
919 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
920 .pStages = pipeline_shader_stages,
921 .pVertexInputState = vi_create_info,
922 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
923 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
924 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
925 .primitiveRestartEnable = false,
926 },
927 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
928 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
929 .viewportCount = 1,
930 .scissorCount = 1,
931 },
932 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
933 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
934 .rasterizerDiscardEnable = false,
935 .polygonMode = VK_POLYGON_MODE_FILL,
936 .cullMode = VK_CULL_MODE_NONE,
937 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
938 },
939 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
940 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
941 .rasterizationSamples = 1,
942 .sampleShadingEnable = false,
943 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
944 },
945 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
946 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
947 .attachmentCount = 0,
948 .pAttachments = NULL,
949 },
950 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
951 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
952 .depthTestEnable = true,
953 .depthWriteEnable = true,
954 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
955 },
956 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
957 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
958 .dynamicStateCount = 9,
959 .pDynamicStates = (VkDynamicState[]) {
960 VK_DYNAMIC_STATE_VIEWPORT,
961 VK_DYNAMIC_STATE_SCISSOR,
962 VK_DYNAMIC_STATE_LINE_WIDTH,
963 VK_DYNAMIC_STATE_DEPTH_BIAS,
964 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
965 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
966 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
967 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
968 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
969 },
970 },
971 .flags = 0,
972 .layout = device->meta_state.blit2d.p_layouts[src_type],
973 .renderPass = device->meta_state.blit2d.depth_only_rp,
974 .subpass = 0,
975 };
976
977 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
978 .use_rectlist = true
979 };
980
981 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
982 radv_pipeline_cache_to_handle(&device->meta_state.cache),
983 &vk_pipeline_info, &radv_pipeline_info,
984 &device->meta_state.alloc,
985 &device->meta_state.blit2d.depth_only_pipeline[src_type]);
986
987
988 ralloc_free(vs.nir);
989 ralloc_free(fs.nir);
990
991 return result;
992 }
993
994 static VkResult
995 blit2d_init_stencil_only_pipeline(struct radv_device *device,
996 enum blit2d_src_type src_type)
997 {
998 VkResult result;
999 const char *name;
1000
1001 texel_fetch_build_func src_func;
1002 switch(src_type) {
1003 case BLIT2D_SRC_TYPE_IMAGE:
1004 src_func = build_nir_texel_fetch;
1005 name = "meta_blit2d_stencil_image_fs";
1006 break;
1007 case BLIT2D_SRC_TYPE_BUFFER:
1008 src_func = build_nir_buffer_fetch;
1009 name = "meta_blit2d_stencil_buffer_fs";
1010 break;
1011 default:
1012 unreachable("unknown blit src type\n");
1013 break;
1014 }
1015
1016 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
1017 struct radv_shader_module fs = { .nir = NULL };
1018
1019 fs.nir = build_nir_copy_fragment_shader_stencil(device, src_func, name);
1020 vi_create_info = &normal_vi_create_info;
1021
1022 struct radv_shader_module vs = {
1023 .nir = build_nir_vertex_shader(),
1024 };
1025
1026 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
1027 {
1028 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1029 .stage = VK_SHADER_STAGE_VERTEX_BIT,
1030 .module = radv_shader_module_to_handle(&vs),
1031 .pName = "main",
1032 .pSpecializationInfo = NULL
1033 }, {
1034 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1035 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
1036 .module = radv_shader_module_to_handle(&fs),
1037 .pName = "main",
1038 .pSpecializationInfo = NULL
1039 },
1040 };
1041
1042 if (!device->meta_state.blit2d.stencil_only_rp) {
1043 result = radv_CreateRenderPass(radv_device_to_handle(device),
1044 &(VkRenderPassCreateInfo) {
1045 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1046 .attachmentCount = 1,
1047 .pAttachments = &(VkAttachmentDescription) {
1048 .format = 0,
1049 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1050 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1051 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
1052 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
1053 },
1054 .subpassCount = 1,
1055 .pSubpasses = &(VkSubpassDescription) {
1056 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1057 .inputAttachmentCount = 0,
1058 .colorAttachmentCount = 0,
1059 .pColorAttachments = NULL,
1060 .pResolveAttachments = NULL,
1061 .pDepthStencilAttachment = &(VkAttachmentReference) {
1062 .attachment = 0,
1063 .layout = VK_IMAGE_LAYOUT_GENERAL,
1064 },
1065 .preserveAttachmentCount = 1,
1066 .pPreserveAttachments = (uint32_t[]) { 0 },
1067 },
1068 .dependencyCount = 0,
1069 }, &device->meta_state.alloc, &device->meta_state.blit2d.stencil_only_rp);
1070 }
1071
1072 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1073 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1074 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
1075 .pStages = pipeline_shader_stages,
1076 .pVertexInputState = vi_create_info,
1077 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1078 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1079 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1080 .primitiveRestartEnable = false,
1081 },
1082 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
1083 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1084 .viewportCount = 1,
1085 .scissorCount = 1,
1086 },
1087 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1088 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1089 .rasterizerDiscardEnable = false,
1090 .polygonMode = VK_POLYGON_MODE_FILL,
1091 .cullMode = VK_CULL_MODE_NONE,
1092 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1093 },
1094 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1095 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1096 .rasterizationSamples = 1,
1097 .sampleShadingEnable = false,
1098 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1099 },
1100 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1101 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1102 .attachmentCount = 0,
1103 .pAttachments = NULL,
1104 },
1105 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1106 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1107 .depthTestEnable = false,
1108 .depthWriteEnable = false,
1109 .stencilTestEnable = true,
1110 .front = {
1111 .failOp = VK_STENCIL_OP_REPLACE,
1112 .passOp = VK_STENCIL_OP_REPLACE,
1113 .depthFailOp = VK_STENCIL_OP_REPLACE,
1114 .compareOp = VK_COMPARE_OP_ALWAYS,
1115 .compareMask = 0xff,
1116 .writeMask = 0xff,
1117 .reference = 0
1118 },
1119 .back = {
1120 .failOp = VK_STENCIL_OP_REPLACE,
1121 .passOp = VK_STENCIL_OP_REPLACE,
1122 .depthFailOp = VK_STENCIL_OP_REPLACE,
1123 .compareOp = VK_COMPARE_OP_ALWAYS,
1124 .compareMask = 0xff,
1125 .writeMask = 0xff,
1126 .reference = 0
1127 },
1128 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
1129 },
1130 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1131 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1132 .dynamicStateCount = 6,
1133 .pDynamicStates = (VkDynamicState[]) {
1134 VK_DYNAMIC_STATE_VIEWPORT,
1135 VK_DYNAMIC_STATE_SCISSOR,
1136 VK_DYNAMIC_STATE_LINE_WIDTH,
1137 VK_DYNAMIC_STATE_DEPTH_BIAS,
1138 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1139 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1140 },
1141 },
1142 .flags = 0,
1143 .layout = device->meta_state.blit2d.p_layouts[src_type],
1144 .renderPass = device->meta_state.blit2d.stencil_only_rp,
1145 .subpass = 0,
1146 };
1147
1148 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1149 .use_rectlist = true
1150 };
1151
1152 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1153 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1154 &vk_pipeline_info, &radv_pipeline_info,
1155 &device->meta_state.alloc,
1156 &device->meta_state.blit2d.stencil_only_pipeline[src_type]);
1157
1158
1159 ralloc_free(vs.nir);
1160 ralloc_free(fs.nir);
1161
1162 return result;
1163 }
1164
1165 static VkFormat pipeline_formats[] = {
1166 VK_FORMAT_R8G8B8A8_UNORM,
1167 VK_FORMAT_R8G8B8A8_UINT,
1168 VK_FORMAT_R8G8B8A8_SINT,
1169 VK_FORMAT_R16G16B16A16_UNORM,
1170 VK_FORMAT_R16G16B16A16_SNORM,
1171 VK_FORMAT_R16G16B16A16_UINT,
1172 VK_FORMAT_R16G16B16A16_SINT,
1173 VK_FORMAT_R32_SFLOAT,
1174 VK_FORMAT_R32G32_SFLOAT,
1175 VK_FORMAT_R32G32B32A32_SFLOAT
1176 };
1177
1178 VkResult
1179 radv_device_init_meta_blit2d_state(struct radv_device *device)
1180 {
1181 VkResult result;
1182
1183 zero(device->meta_state.blit2d);
1184
1185 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1186 &(VkDescriptorSetLayoutCreateInfo) {
1187 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1188 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1189 .bindingCount = 1,
1190 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1191 {
1192 .binding = 0,
1193 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
1194 .descriptorCount = 1,
1195 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1196 .pImmutableSamplers = NULL
1197 },
1198 }
1199 }, &device->meta_state.alloc, &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_IMAGE]);
1200 if (result != VK_SUCCESS)
1201 goto fail;
1202
1203 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1204 &(VkPipelineLayoutCreateInfo) {
1205 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1206 .setLayoutCount = 1,
1207 .pSetLayouts = &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_IMAGE],
1208 },
1209 &device->meta_state.alloc, &device->meta_state.blit2d.p_layouts[BLIT2D_SRC_TYPE_IMAGE]);
1210 if (result != VK_SUCCESS)
1211 goto fail;
1212
1213 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1214 &(VkDescriptorSetLayoutCreateInfo) {
1215 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1216 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1217 .bindingCount = 1,
1218 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1219 {
1220 .binding = 0,
1221 .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
1222 .descriptorCount = 1,
1223 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1224 .pImmutableSamplers = NULL
1225 },
1226 }
1227 }, &device->meta_state.alloc, &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_BUFFER]);
1228 if (result != VK_SUCCESS)
1229 goto fail;
1230
1231 const VkPushConstantRange push_constant_range = {VK_SHADER_STAGE_FRAGMENT_BIT, 0, 4};
1232 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1233 &(VkPipelineLayoutCreateInfo) {
1234 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1235 .setLayoutCount = 1,
1236 .pSetLayouts = &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_BUFFER],
1237 .pushConstantRangeCount = 1,
1238 .pPushConstantRanges = &push_constant_range,
1239 },
1240 &device->meta_state.alloc, &device->meta_state.blit2d.p_layouts[BLIT2D_SRC_TYPE_BUFFER]);
1241 if (result != VK_SUCCESS)
1242 goto fail;
1243
1244 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
1245 for (unsigned j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
1246 result = blit2d_init_color_pipeline(device, src, pipeline_formats[j]);
1247 if (result != VK_SUCCESS)
1248 goto fail;
1249 }
1250
1251 result = blit2d_init_depth_only_pipeline(device, src);
1252 if (result != VK_SUCCESS)
1253 goto fail;
1254
1255 result = blit2d_init_stencil_only_pipeline(device, src);
1256 if (result != VK_SUCCESS)
1257 goto fail;
1258 }
1259
1260 return VK_SUCCESS;
1261
1262 fail:
1263 radv_device_finish_meta_blit2d_state(device);
1264 return result;
1265 }