2 * Copyright © 2016 Red Hat
5 * Copyright © 2016 Intel Corporation
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "radv_meta.h"
28 #include "nir/nir_builder.h"
29 #include "vk_format.h"
31 enum blit2d_src_type
{
32 BLIT2D_SRC_TYPE_IMAGE
,
33 BLIT2D_SRC_TYPE_IMAGE_3D
,
34 BLIT2D_SRC_TYPE_BUFFER
,
39 create_iview(struct radv_cmd_buffer
*cmd_buffer
,
40 struct radv_meta_blit2d_surf
*surf
,
41 struct radv_image_view
*iview
, VkFormat depth_format
,
42 VkImageAspectFlagBits aspects
)
45 VkImageViewType view_type
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
< GFX9
? VK_IMAGE_VIEW_TYPE_2D
:
46 radv_meta_get_view_type(surf
->image
);
49 format
= depth_format
;
51 format
= surf
->format
;
53 radv_image_view_init(iview
, cmd_buffer
->device
,
54 &(VkImageViewCreateInfo
) {
55 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
56 .image
= radv_image_to_handle(surf
->image
),
57 .viewType
= view_type
,
60 .aspectMask
= aspects
,
61 .baseMipLevel
= surf
->level
,
63 .baseArrayLayer
= surf
->layer
,
70 create_bview(struct radv_cmd_buffer
*cmd_buffer
,
71 struct radv_meta_blit2d_buffer
*src
,
72 struct radv_buffer_view
*bview
, VkFormat depth_format
)
77 format
= depth_format
;
80 radv_buffer_view_init(bview
, cmd_buffer
->device
,
81 &(VkBufferViewCreateInfo
) {
82 .sType
= VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO
,
84 .buffer
= radv_buffer_to_handle(src
->buffer
),
86 .offset
= src
->offset
,
87 .range
= VK_WHOLE_SIZE
,
92 struct blit2d_src_temps
{
93 struct radv_image_view iview
;
94 struct radv_buffer_view bview
;
98 blit2d_bind_src(struct radv_cmd_buffer
*cmd_buffer
,
99 struct radv_meta_blit2d_surf
*src_img
,
100 struct radv_meta_blit2d_buffer
*src_buf
,
101 struct blit2d_src_temps
*tmp
,
102 enum blit2d_src_type src_type
, VkFormat depth_format
,
103 VkImageAspectFlagBits aspects
,
104 uint32_t log2_samples
)
106 struct radv_device
*device
= cmd_buffer
->device
;
108 if (src_type
== BLIT2D_SRC_TYPE_BUFFER
) {
109 create_bview(cmd_buffer
, src_buf
, &tmp
->bview
, depth_format
);
111 radv_meta_push_descriptor_set(cmd_buffer
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
112 device
->meta_state
.blit2d
[log2_samples
].p_layouts
[src_type
],
114 1, /* descriptorWriteCount */
115 (VkWriteDescriptorSet
[]) {
117 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
119 .dstArrayElement
= 0,
120 .descriptorCount
= 1,
121 .descriptorType
= VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
,
122 .pTexelBufferView
= (VkBufferView
[]) { radv_buffer_view_to_handle(&tmp
->bview
) }
126 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
127 device
->meta_state
.blit2d
[log2_samples
].p_layouts
[src_type
],
128 VK_SHADER_STAGE_FRAGMENT_BIT
, 16, 4,
131 create_iview(cmd_buffer
, src_img
, &tmp
->iview
, depth_format
, aspects
);
133 if (src_type
== BLIT2D_SRC_TYPE_IMAGE_3D
)
134 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
135 device
->meta_state
.blit2d
[log2_samples
].p_layouts
[src_type
],
136 VK_SHADER_STAGE_FRAGMENT_BIT
, 16, 4,
139 radv_meta_push_descriptor_set(cmd_buffer
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
140 device
->meta_state
.blit2d
[log2_samples
].p_layouts
[src_type
],
142 1, /* descriptorWriteCount */
143 (VkWriteDescriptorSet
[]) {
145 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
147 .dstArrayElement
= 0,
148 .descriptorCount
= 1,
149 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
150 .pImageInfo
= (VkDescriptorImageInfo
[]) {
152 .sampler
= VK_NULL_HANDLE
,
153 .imageView
= radv_image_view_to_handle(&tmp
->iview
),
154 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
162 struct blit2d_dst_temps
{
164 struct radv_image_view iview
;
169 blit2d_bind_dst(struct radv_cmd_buffer
*cmd_buffer
,
170 struct radv_meta_blit2d_surf
*dst
,
173 VkFormat depth_format
,
174 struct blit2d_dst_temps
*tmp
,
175 VkImageAspectFlagBits aspects
)
177 create_iview(cmd_buffer
, dst
, &tmp
->iview
, depth_format
, aspects
);
179 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer
->device
),
180 &(VkFramebufferCreateInfo
) {
181 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
182 .attachmentCount
= 1,
183 .pAttachments
= (VkImageView
[]) {
184 radv_image_view_to_handle(&tmp
->iview
),
189 }, &cmd_buffer
->pool
->alloc
, &tmp
->fb
);
193 bind_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
194 enum blit2d_src_type src_type
, unsigned fs_key
,
195 uint32_t log2_samples
)
197 VkPipeline pipeline
=
198 cmd_buffer
->device
->meta_state
.blit2d
[log2_samples
].pipelines
[src_type
][fs_key
];
200 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
201 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
205 bind_depth_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
206 enum blit2d_src_type src_type
,
207 uint32_t log2_samples
)
209 VkPipeline pipeline
=
210 cmd_buffer
->device
->meta_state
.blit2d
[log2_samples
].depth_only_pipeline
[src_type
];
212 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
213 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
217 bind_stencil_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
218 enum blit2d_src_type src_type
,
219 uint32_t log2_samples
)
221 VkPipeline pipeline
=
222 cmd_buffer
->device
->meta_state
.blit2d
[log2_samples
].stencil_only_pipeline
[src_type
];
224 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
225 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
229 radv_meta_blit2d_normal_dst(struct radv_cmd_buffer
*cmd_buffer
,
230 struct radv_meta_blit2d_surf
*src_img
,
231 struct radv_meta_blit2d_buffer
*src_buf
,
232 struct radv_meta_blit2d_surf
*dst
,
234 struct radv_meta_blit2d_rect
*rects
, enum blit2d_src_type src_type
,
235 uint32_t log2_samples
)
237 struct radv_device
*device
= cmd_buffer
->device
;
239 for (unsigned r
= 0; r
< num_rects
; ++r
) {
241 for_each_bit(i
, dst
->aspect_mask
) {
242 unsigned aspect_mask
= 1u << i
;
243 VkFormat depth_format
= 0;
244 if (aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
)
245 depth_format
= vk_format_stencil_only(dst
->image
->vk_format
);
246 else if (aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
)
247 depth_format
= vk_format_depth_only(dst
->image
->vk_format
);
248 struct blit2d_src_temps src_temps
;
249 blit2d_bind_src(cmd_buffer
, src_img
, src_buf
, &src_temps
, src_type
, depth_format
, aspect_mask
, log2_samples
);
251 struct blit2d_dst_temps dst_temps
;
252 blit2d_bind_dst(cmd_buffer
, dst
, rects
[r
].dst_x
+ rects
[r
].width
,
253 rects
[r
].dst_y
+ rects
[r
].height
, depth_format
, &dst_temps
, aspect_mask
);
255 float vertex_push_constants
[4] = {
258 rects
[r
].src_x
+ rects
[r
].width
,
259 rects
[r
].src_y
+ rects
[r
].height
,
262 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
263 device
->meta_state
.blit2d
[log2_samples
].p_layouts
[src_type
],
264 VK_SHADER_STAGE_VERTEX_BIT
, 0, 16,
265 vertex_push_constants
);
267 if (aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
) {
268 unsigned fs_key
= radv_format_meta_fs_key(dst_temps
.iview
.vk_format
);
269 unsigned dst_layout
= radv_meta_dst_layout_from_layout(dst
->current_layout
);
271 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
272 &(VkRenderPassBeginInfo
) {
273 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
274 .renderPass
= device
->meta_state
.blit2d_render_passes
[fs_key
][dst_layout
],
275 .framebuffer
= dst_temps
.fb
,
277 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
278 .extent
= { rects
[r
].width
, rects
[r
].height
},
280 .clearValueCount
= 0,
281 .pClearValues
= NULL
,
282 }, VK_SUBPASS_CONTENTS_INLINE
);
285 bind_pipeline(cmd_buffer
, src_type
, fs_key
, log2_samples
);
286 } else if (aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
287 enum radv_blit_ds_layout ds_layout
= radv_meta_blit_ds_to_type(dst
->current_layout
);
288 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
289 &(VkRenderPassBeginInfo
) {
290 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
291 .renderPass
= device
->meta_state
.blit2d_depth_only_rp
[ds_layout
],
292 .framebuffer
= dst_temps
.fb
,
294 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
295 .extent
= { rects
[r
].width
, rects
[r
].height
},
297 .clearValueCount
= 0,
298 .pClearValues
= NULL
,
299 }, VK_SUBPASS_CONTENTS_INLINE
);
302 bind_depth_pipeline(cmd_buffer
, src_type
, log2_samples
);
304 } else if (aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
305 enum radv_blit_ds_layout ds_layout
= radv_meta_blit_ds_to_type(dst
->current_layout
);
306 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
307 &(VkRenderPassBeginInfo
) {
308 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
309 .renderPass
= device
->meta_state
.blit2d_stencil_only_rp
[ds_layout
],
310 .framebuffer
= dst_temps
.fb
,
312 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
313 .extent
= { rects
[r
].width
, rects
[r
].height
},
315 .clearValueCount
= 0,
316 .pClearValues
= NULL
,
317 }, VK_SUBPASS_CONTENTS_INLINE
);
320 bind_stencil_pipeline(cmd_buffer
, src_type
, log2_samples
);
322 unreachable("Processing blit2d with multiple aspects.");
324 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
327 .width
= rects
[r
].width
,
328 .height
= rects
[r
].height
,
333 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkRect2D
) {
334 .offset
= (VkOffset2D
) { rects
[r
].dst_x
, rects
[r
].dst_y
},
335 .extent
= (VkExtent2D
) { rects
[r
].width
, rects
[r
].height
},
340 if (log2_samples
> 0) {
341 for (uint32_t sample
= 0; sample
< src_img
->image
->info
.samples
; sample
++) {
342 uint32_t sample_mask
= 1 << sample
;
343 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
344 device
->meta_state
.blit2d
[log2_samples
].p_layouts
[src_type
],
345 VK_SHADER_STAGE_FRAGMENT_BIT
, 20, 4,
348 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
349 device
->meta_state
.blit2d
[log2_samples
].p_layouts
[src_type
],
350 VK_SHADER_STAGE_FRAGMENT_BIT
, 24, 4,
353 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer
), 3, 1, 0, 0);
357 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer
), 3, 1, 0, 0);
358 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
));
360 /* At the point where we emit the draw call, all data from the
361 * descriptor sets, etc. has been used. We are free to delete it.
363 radv_DestroyFramebuffer(radv_device_to_handle(device
),
365 &cmd_buffer
->pool
->alloc
);
371 radv_meta_blit2d(struct radv_cmd_buffer
*cmd_buffer
,
372 struct radv_meta_blit2d_surf
*src_img
,
373 struct radv_meta_blit2d_buffer
*src_buf
,
374 struct radv_meta_blit2d_surf
*dst
,
376 struct radv_meta_blit2d_rect
*rects
)
378 bool use_3d
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
379 (src_img
&& src_img
->image
->type
== VK_IMAGE_TYPE_3D
);
380 enum blit2d_src_type src_type
= src_buf
? BLIT2D_SRC_TYPE_BUFFER
:
381 use_3d
? BLIT2D_SRC_TYPE_IMAGE_3D
: BLIT2D_SRC_TYPE_IMAGE
;
382 radv_meta_blit2d_normal_dst(cmd_buffer
, src_img
, src_buf
, dst
,
383 num_rects
, rects
, src_type
,
384 src_img
? util_logbase2(src_img
->image
->info
.samples
) : 0);
388 build_nir_vertex_shader(void)
390 const struct glsl_type
*vec4
= glsl_vec4_type();
391 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
394 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
395 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "meta_blit2d_vs");
397 nir_variable
*pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
398 vec4
, "gl_Position");
399 pos_out
->data
.location
= VARYING_SLOT_POS
;
401 nir_variable
*tex_pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
403 tex_pos_out
->data
.location
= VARYING_SLOT_VAR0
;
404 tex_pos_out
->data
.interpolation
= INTERP_MODE_SMOOTH
;
406 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices(&b
);
407 nir_store_var(&b
, pos_out
, outvec
, 0xf);
409 nir_intrinsic_instr
*src_box
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
410 src_box
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
411 nir_intrinsic_set_base(src_box
, 0);
412 nir_intrinsic_set_range(src_box
, 16);
413 src_box
->num_components
= 4;
414 nir_ssa_dest_init(&src_box
->instr
, &src_box
->dest
, 4, 32, "src_box");
415 nir_builder_instr_insert(&b
, &src_box
->instr
);
417 nir_intrinsic_instr
*vertex_id
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_vertex_id_zero_base
);
418 nir_ssa_dest_init(&vertex_id
->instr
, &vertex_id
->dest
, 1, 32, "vertexid");
419 nir_builder_instr_insert(&b
, &vertex_id
->instr
);
421 /* vertex 0 - src_x, src_y */
422 /* vertex 1 - src_x, src_y+h */
423 /* vertex 2 - src_x+w, src_y */
424 /* so channel 0 is vertex_id != 2 ? src_x : src_x + w
425 channel 1 is vertex id != 1 ? src_y : src_y + w */
427 nir_ssa_def
*c0cmp
= nir_ine(&b
, &vertex_id
->dest
.ssa
,
429 nir_ssa_def
*c1cmp
= nir_ine(&b
, &vertex_id
->dest
.ssa
,
432 nir_ssa_def
*comp
[2];
433 comp
[0] = nir_bcsel(&b
, c0cmp
,
434 nir_channel(&b
, &src_box
->dest
.ssa
, 0),
435 nir_channel(&b
, &src_box
->dest
.ssa
, 2));
437 comp
[1] = nir_bcsel(&b
, c1cmp
,
438 nir_channel(&b
, &src_box
->dest
.ssa
, 1),
439 nir_channel(&b
, &src_box
->dest
.ssa
, 3));
440 nir_ssa_def
*out_tex_vec
= nir_vec(&b
, comp
, 2);
441 nir_store_var(&b
, tex_pos_out
, out_tex_vec
, 0x3);
445 typedef nir_ssa_def
* (*texel_fetch_build_func
)(struct nir_builder
*,
446 struct radv_device
*,
447 nir_ssa_def
*, bool, bool);
450 build_nir_texel_fetch(struct nir_builder
*b
, struct radv_device
*device
,
451 nir_ssa_def
*tex_pos
, bool is_3d
, bool is_multisampled
)
453 enum glsl_sampler_dim dim
=
454 is_3d
? GLSL_SAMPLER_DIM_3D
: is_multisampled
? GLSL_SAMPLER_DIM_MS
: GLSL_SAMPLER_DIM_2D
;
455 const struct glsl_type
*sampler_type
=
456 glsl_sampler_type(dim
, false, false, GLSL_TYPE_UINT
);
457 nir_variable
*sampler
= nir_variable_create(b
->shader
, nir_var_uniform
,
458 sampler_type
, "s_tex");
459 sampler
->data
.descriptor_set
= 0;
460 sampler
->data
.binding
= 0;
462 nir_ssa_def
*tex_pos_3d
= NULL
;
463 nir_intrinsic_instr
*sample_idx
= NULL
;
465 nir_intrinsic_instr
*layer
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_push_constant
);
466 nir_intrinsic_set_base(layer
, 16);
467 nir_intrinsic_set_range(layer
, 4);
468 layer
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, 0));
469 layer
->num_components
= 1;
470 nir_ssa_dest_init(&layer
->instr
, &layer
->dest
, 1, 32, "layer");
471 nir_builder_instr_insert(b
, &layer
->instr
);
473 nir_ssa_def
*chans
[3];
474 chans
[0] = nir_channel(b
, tex_pos
, 0);
475 chans
[1] = nir_channel(b
, tex_pos
, 1);
476 chans
[2] = &layer
->dest
.ssa
;
477 tex_pos_3d
= nir_vec(b
, chans
, 3);
479 if (is_multisampled
) {
480 sample_idx
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_push_constant
);
481 nir_intrinsic_set_base(sample_idx
, 20);
482 nir_intrinsic_set_range(sample_idx
, 4);
483 sample_idx
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, 0));
484 sample_idx
->num_components
= 1;
485 nir_ssa_dest_init(&sample_idx
->instr
, &sample_idx
->dest
, 1, 32, "sample_idx");
486 nir_builder_instr_insert(b
, &sample_idx
->instr
);
488 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, is_multisampled
? 3 : 2);
489 tex
->sampler_dim
= dim
;
490 tex
->op
= is_multisampled
? nir_texop_txf_ms
: nir_texop_txf
;
491 tex
->src
[0].src_type
= nir_tex_src_coord
;
492 tex
->src
[0].src
= nir_src_for_ssa(is_3d
? tex_pos_3d
: tex_pos
);
493 tex
->src
[1].src_type
= is_multisampled
? nir_tex_src_ms_index
: nir_tex_src_lod
;
494 tex
->src
[1].src
= nir_src_for_ssa(is_multisampled
? &sample_idx
->dest
.ssa
: nir_imm_int(b
, 0));
495 if (is_multisampled
) {
496 tex
->src
[2].src_type
= nir_tex_src_lod
;
497 tex
->src
[2].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
499 tex
->dest_type
= nir_type_uint
;
500 tex
->is_array
= false;
501 tex
->coord_components
= is_3d
? 3 : 2;
502 tex
->texture
= nir_deref_var_create(tex
, sampler
);
505 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
506 nir_builder_instr_insert(b
, &tex
->instr
);
508 return &tex
->dest
.ssa
;
513 build_nir_buffer_fetch(struct nir_builder
*b
, struct radv_device
*device
,
514 nir_ssa_def
*tex_pos
, bool is_3d
, bool is_multisampled
)
516 const struct glsl_type
*sampler_type
=
517 glsl_sampler_type(GLSL_SAMPLER_DIM_BUF
, false, false, GLSL_TYPE_UINT
);
518 nir_variable
*sampler
= nir_variable_create(b
->shader
, nir_var_uniform
,
519 sampler_type
, "s_tex");
520 sampler
->data
.descriptor_set
= 0;
521 sampler
->data
.binding
= 0;
523 nir_intrinsic_instr
*width
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_push_constant
);
524 nir_intrinsic_set_base(width
, 16);
525 nir_intrinsic_set_range(width
, 4);
526 width
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, 0));
527 width
->num_components
= 1;
528 nir_ssa_dest_init(&width
->instr
, &width
->dest
, 1, 32, "width");
529 nir_builder_instr_insert(b
, &width
->instr
);
531 nir_ssa_def
*pos_x
= nir_channel(b
, tex_pos
, 0);
532 nir_ssa_def
*pos_y
= nir_channel(b
, tex_pos
, 1);
533 pos_y
= nir_imul(b
, pos_y
, &width
->dest
.ssa
);
534 pos_x
= nir_iadd(b
, pos_x
, pos_y
);
535 //pos_x = nir_iadd(b, pos_x, nir_imm_int(b, 100000));
537 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, 1);
538 tex
->sampler_dim
= GLSL_SAMPLER_DIM_BUF
;
539 tex
->op
= nir_texop_txf
;
540 tex
->src
[0].src_type
= nir_tex_src_coord
;
541 tex
->src
[0].src
= nir_src_for_ssa(pos_x
);
542 tex
->dest_type
= nir_type_uint
;
543 tex
->is_array
= false;
544 tex
->coord_components
= 1;
545 tex
->texture
= nir_deref_var_create(tex
, sampler
);
548 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
549 nir_builder_instr_insert(b
, &tex
->instr
);
551 return &tex
->dest
.ssa
;
554 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info
= {
555 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
556 .vertexBindingDescriptionCount
= 0,
557 .vertexAttributeDescriptionCount
= 0,
561 build_nir_store_sample_mask(struct nir_builder
*b
)
563 nir_intrinsic_instr
*sample_mask
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_push_constant
);
564 nir_intrinsic_set_base(sample_mask
, 24);
565 nir_intrinsic_set_range(sample_mask
, 4);
566 sample_mask
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, 0));
567 sample_mask
->num_components
= 1;
568 nir_ssa_dest_init(&sample_mask
->instr
, &sample_mask
->dest
, 1, 32, "sample_mask");
569 nir_builder_instr_insert(b
, &sample_mask
->instr
);
571 const struct glsl_type
*sample_mask_out_type
= glsl_uint_type();
573 nir_variable
*sample_mask_out
=
574 nir_variable_create(b
->shader
, nir_var_shader_out
,
575 sample_mask_out_type
, "sample_mask_out");
576 sample_mask_out
->data
.location
= FRAG_RESULT_SAMPLE_MASK
;
578 nir_store_var(b
, sample_mask_out
, &sample_mask
->dest
.ssa
, 0x1);
582 build_nir_copy_fragment_shader(struct radv_device
*device
,
583 texel_fetch_build_func txf_func
, const char* name
, bool is_3d
,
584 bool is_multisampled
)
586 const struct glsl_type
*vec4
= glsl_vec4_type();
587 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
590 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
591 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, name
);
593 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
595 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
597 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
599 color_out
->data
.location
= FRAG_RESULT_DATA0
;
601 if (is_multisampled
) {
602 build_nir_store_sample_mask(&b
);
605 nir_ssa_def
*pos_int
= nir_f2i32(&b
, nir_load_var(&b
, tex_pos_in
));
606 unsigned swiz
[4] = { 0, 1 };
607 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
609 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
, is_3d
, is_multisampled
);
610 nir_store_var(&b
, color_out
, color
, 0xf);
616 build_nir_copy_fragment_shader_depth(struct radv_device
*device
,
617 texel_fetch_build_func txf_func
, const char* name
, bool is_3d
,
618 bool is_multisampled
)
620 const struct glsl_type
*vec4
= glsl_vec4_type();
621 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
624 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
625 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, name
);
627 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
629 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
631 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
633 color_out
->data
.location
= FRAG_RESULT_DEPTH
;
635 if (is_multisampled
) {
636 build_nir_store_sample_mask(&b
);
639 nir_ssa_def
*pos_int
= nir_f2i32(&b
, nir_load_var(&b
, tex_pos_in
));
640 unsigned swiz
[4] = { 0, 1 };
641 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
643 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
, is_3d
, is_multisampled
);
644 nir_store_var(&b
, color_out
, color
, 0x1);
650 build_nir_copy_fragment_shader_stencil(struct radv_device
*device
,
651 texel_fetch_build_func txf_func
, const char* name
, bool is_3d
,
652 bool is_multisampled
)
654 const struct glsl_type
*vec4
= glsl_vec4_type();
655 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
658 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
659 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, name
);
661 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
663 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
665 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
667 color_out
->data
.location
= FRAG_RESULT_STENCIL
;
669 if (is_multisampled
) {
670 build_nir_store_sample_mask(&b
);
673 nir_ssa_def
*pos_int
= nir_f2i32(&b
, nir_load_var(&b
, tex_pos_in
));
674 unsigned swiz
[4] = { 0, 1 };
675 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
677 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
, is_3d
, is_multisampled
);
678 nir_store_var(&b
, color_out
, color
, 0x1);
684 radv_device_finish_meta_blit2d_state(struct radv_device
*device
)
686 struct radv_meta_state
*state
= &device
->meta_state
;
688 for(unsigned j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
689 for (unsigned k
= 0; k
< RADV_META_DST_LAYOUT_COUNT
; ++k
) {
690 radv_DestroyRenderPass(radv_device_to_handle(device
),
691 state
->blit2d_render_passes
[j
][k
],
696 for (enum radv_blit_ds_layout j
= RADV_BLIT_DS_LAYOUT_TILE_ENABLE
; j
< RADV_BLIT_DS_LAYOUT_COUNT
; j
++) {
697 radv_DestroyRenderPass(radv_device_to_handle(device
),
698 state
->blit2d_depth_only_rp
[j
], &state
->alloc
);
699 radv_DestroyRenderPass(radv_device_to_handle(device
),
700 state
->blit2d_stencil_only_rp
[j
], &state
->alloc
);
703 for (unsigned log2_samples
= 0; log2_samples
< 1 + MAX_SAMPLES_LOG2
; ++log2_samples
) {
704 for (unsigned src
= 0; src
< BLIT2D_NUM_SRC_TYPES
; src
++) {
705 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
706 state
->blit2d
[log2_samples
].p_layouts
[src
],
708 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
709 state
->blit2d
[log2_samples
].ds_layouts
[src
],
712 for (unsigned j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
713 radv_DestroyPipeline(radv_device_to_handle(device
),
714 state
->blit2d
[log2_samples
].pipelines
[src
][j
],
718 radv_DestroyPipeline(radv_device_to_handle(device
),
719 state
->blit2d
[log2_samples
].depth_only_pipeline
[src
],
721 radv_DestroyPipeline(radv_device_to_handle(device
),
722 state
->blit2d
[log2_samples
].stencil_only_pipeline
[src
],
729 blit2d_init_color_pipeline(struct radv_device
*device
,
730 enum blit2d_src_type src_type
,
732 uint32_t log2_samples
)
735 unsigned fs_key
= radv_format_meta_fs_key(format
);
738 texel_fetch_build_func src_func
;
740 case BLIT2D_SRC_TYPE_IMAGE
:
741 src_func
= build_nir_texel_fetch
;
742 name
= "meta_blit2d_image_fs";
744 case BLIT2D_SRC_TYPE_IMAGE_3D
:
745 src_func
= build_nir_texel_fetch
;
746 name
= "meta_blit3d_image_fs";
748 case BLIT2D_SRC_TYPE_BUFFER
:
749 src_func
= build_nir_buffer_fetch
;
750 name
= "meta_blit2d_buffer_fs";
753 unreachable("unknown blit src type\n");
757 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
758 struct radv_shader_module fs
= { .nir
= NULL
};
761 fs
.nir
= build_nir_copy_fragment_shader(device
, src_func
, name
, src_type
== BLIT2D_SRC_TYPE_IMAGE_3D
, log2_samples
> 0);
762 vi_create_info
= &normal_vi_create_info
;
764 struct radv_shader_module vs
= {
765 .nir
= build_nir_vertex_shader(),
768 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
770 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
771 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
772 .module
= radv_shader_module_to_handle(&vs
),
774 .pSpecializationInfo
= NULL
776 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
777 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
778 .module
= radv_shader_module_to_handle(&fs
),
780 .pSpecializationInfo
= NULL
784 for (unsigned dst_layout
= 0; dst_layout
< RADV_META_DST_LAYOUT_COUNT
; ++dst_layout
) {
785 if (!device
->meta_state
.blit2d_render_passes
[fs_key
][dst_layout
]) {
786 VkImageLayout layout
= radv_meta_dst_layout_to_layout(dst_layout
);
788 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
789 &(VkRenderPassCreateInfo
) {
790 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
791 .attachmentCount
= 1,
792 .pAttachments
= &(VkAttachmentDescription
) {
794 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
795 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
796 .initialLayout
= layout
,
797 .finalLayout
= layout
,
800 .pSubpasses
= &(VkSubpassDescription
) {
801 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
802 .inputAttachmentCount
= 0,
803 .colorAttachmentCount
= 1,
804 .pColorAttachments
= &(VkAttachmentReference
) {
808 .pResolveAttachments
= NULL
,
809 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
810 .attachment
= VK_ATTACHMENT_UNUSED
,
813 .preserveAttachmentCount
= 1,
814 .pPreserveAttachments
= (uint32_t[]) { 0 },
816 .dependencyCount
= 0,
817 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d_render_passes
[fs_key
][dst_layout
]);
821 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
822 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
823 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
824 .pStages
= pipeline_shader_stages
,
825 .pVertexInputState
= vi_create_info
,
826 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
827 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
828 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
829 .primitiveRestartEnable
= false,
831 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
832 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
836 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
837 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
838 .rasterizerDiscardEnable
= false,
839 .polygonMode
= VK_POLYGON_MODE_FILL
,
840 .cullMode
= VK_CULL_MODE_NONE
,
841 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
843 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
844 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
845 .rasterizationSamples
= 1 << log2_samples
,
846 .sampleShadingEnable
= false,
847 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
849 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
850 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
851 .attachmentCount
= 1,
852 .pAttachments
= (VkPipelineColorBlendAttachmentState
[]) {
854 VK_COLOR_COMPONENT_A_BIT
|
855 VK_COLOR_COMPONENT_R_BIT
|
856 VK_COLOR_COMPONENT_G_BIT
|
857 VK_COLOR_COMPONENT_B_BIT
},
860 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
861 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
862 .dynamicStateCount
= 9,
863 .pDynamicStates
= (VkDynamicState
[]) {
864 VK_DYNAMIC_STATE_VIEWPORT
,
865 VK_DYNAMIC_STATE_SCISSOR
,
866 VK_DYNAMIC_STATE_LINE_WIDTH
,
867 VK_DYNAMIC_STATE_DEPTH_BIAS
,
868 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
869 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
870 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
871 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
872 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
876 .layout
= device
->meta_state
.blit2d
[log2_samples
].p_layouts
[src_type
],
877 .renderPass
= device
->meta_state
.blit2d_render_passes
[fs_key
][0],
881 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
885 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
886 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
887 &vk_pipeline_info
, &radv_pipeline_info
,
888 &device
->meta_state
.alloc
,
889 &device
->meta_state
.blit2d
[log2_samples
].pipelines
[src_type
][fs_key
]);
899 blit2d_init_depth_only_pipeline(struct radv_device
*device
,
900 enum blit2d_src_type src_type
,
901 uint32_t log2_samples
)
906 texel_fetch_build_func src_func
;
908 case BLIT2D_SRC_TYPE_IMAGE
:
909 src_func
= build_nir_texel_fetch
;
910 name
= "meta_blit2d_depth_image_fs";
912 case BLIT2D_SRC_TYPE_IMAGE_3D
:
913 src_func
= build_nir_texel_fetch
;
914 name
= "meta_blit3d_depth_image_fs";
916 case BLIT2D_SRC_TYPE_BUFFER
:
917 src_func
= build_nir_buffer_fetch
;
918 name
= "meta_blit2d_depth_buffer_fs";
921 unreachable("unknown blit src type\n");
925 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
926 struct radv_shader_module fs
= { .nir
= NULL
};
928 fs
.nir
= build_nir_copy_fragment_shader_depth(device
, src_func
, name
, src_type
== BLIT2D_SRC_TYPE_IMAGE_3D
, log2_samples
> 0);
929 vi_create_info
= &normal_vi_create_info
;
931 struct radv_shader_module vs
= {
932 .nir
= build_nir_vertex_shader(),
935 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
937 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
938 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
939 .module
= radv_shader_module_to_handle(&vs
),
941 .pSpecializationInfo
= NULL
943 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
944 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
945 .module
= radv_shader_module_to_handle(&fs
),
947 .pSpecializationInfo
= NULL
951 for (enum radv_blit_ds_layout ds_layout
= RADV_BLIT_DS_LAYOUT_TILE_ENABLE
; ds_layout
< RADV_BLIT_DS_LAYOUT_COUNT
; ds_layout
++) {
952 if (!device
->meta_state
.blit2d_depth_only_rp
[ds_layout
]) {
953 VkImageLayout layout
= radv_meta_blit_ds_to_layout(ds_layout
);
954 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
955 &(VkRenderPassCreateInfo
) {
956 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
957 .attachmentCount
= 1,
958 .pAttachments
= &(VkAttachmentDescription
) {
959 .format
= VK_FORMAT_D32_SFLOAT
,
960 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
961 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
962 .initialLayout
= layout
,
963 .finalLayout
= layout
,
966 .pSubpasses
= &(VkSubpassDescription
) {
967 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
968 .inputAttachmentCount
= 0,
969 .colorAttachmentCount
= 0,
970 .pColorAttachments
= NULL
,
971 .pResolveAttachments
= NULL
,
972 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
976 .preserveAttachmentCount
= 1,
977 .pPreserveAttachments
= (uint32_t[]) { 0 },
979 .dependencyCount
= 0,
980 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d_depth_only_rp
[ds_layout
]);
984 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
985 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
986 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
987 .pStages
= pipeline_shader_stages
,
988 .pVertexInputState
= vi_create_info
,
989 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
990 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
991 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
992 .primitiveRestartEnable
= false,
994 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
995 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
999 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
1000 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
1001 .rasterizerDiscardEnable
= false,
1002 .polygonMode
= VK_POLYGON_MODE_FILL
,
1003 .cullMode
= VK_CULL_MODE_NONE
,
1004 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
1006 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
1007 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
1008 .rasterizationSamples
= 1 << log2_samples
,
1009 .sampleShadingEnable
= false,
1010 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
1012 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
1013 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
1014 .attachmentCount
= 0,
1015 .pAttachments
= NULL
,
1017 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
1018 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
1019 .depthTestEnable
= true,
1020 .depthWriteEnable
= true,
1021 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
1023 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
1024 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
1025 .dynamicStateCount
= 9,
1026 .pDynamicStates
= (VkDynamicState
[]) {
1027 VK_DYNAMIC_STATE_VIEWPORT
,
1028 VK_DYNAMIC_STATE_SCISSOR
,
1029 VK_DYNAMIC_STATE_LINE_WIDTH
,
1030 VK_DYNAMIC_STATE_DEPTH_BIAS
,
1031 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
1032 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
1033 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
1034 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
1035 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
1039 .layout
= device
->meta_state
.blit2d
[log2_samples
].p_layouts
[src_type
],
1040 .renderPass
= device
->meta_state
.blit2d_depth_only_rp
[0],
1044 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
1045 .use_rectlist
= true
1048 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1049 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1050 &vk_pipeline_info
, &radv_pipeline_info
,
1051 &device
->meta_state
.alloc
,
1052 &device
->meta_state
.blit2d
[log2_samples
].depth_only_pipeline
[src_type
]);
1055 ralloc_free(vs
.nir
);
1056 ralloc_free(fs
.nir
);
1062 blit2d_init_stencil_only_pipeline(struct radv_device
*device
,
1063 enum blit2d_src_type src_type
,
1064 uint32_t log2_samples
)
1069 texel_fetch_build_func src_func
;
1071 case BLIT2D_SRC_TYPE_IMAGE
:
1072 src_func
= build_nir_texel_fetch
;
1073 name
= "meta_blit2d_stencil_image_fs";
1075 case BLIT2D_SRC_TYPE_IMAGE_3D
:
1076 src_func
= build_nir_texel_fetch
;
1077 name
= "meta_blit3d_stencil_image_fs";
1079 case BLIT2D_SRC_TYPE_BUFFER
:
1080 src_func
= build_nir_buffer_fetch
;
1081 name
= "meta_blit2d_stencil_buffer_fs";
1084 unreachable("unknown blit src type\n");
1088 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
1089 struct radv_shader_module fs
= { .nir
= NULL
};
1091 fs
.nir
= build_nir_copy_fragment_shader_stencil(device
, src_func
, name
, src_type
== BLIT2D_SRC_TYPE_IMAGE_3D
, log2_samples
> 0);
1092 vi_create_info
= &normal_vi_create_info
;
1094 struct radv_shader_module vs
= {
1095 .nir
= build_nir_vertex_shader(),
1098 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
1100 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1101 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
1102 .module
= radv_shader_module_to_handle(&vs
),
1104 .pSpecializationInfo
= NULL
1106 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1107 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1108 .module
= radv_shader_module_to_handle(&fs
),
1110 .pSpecializationInfo
= NULL
1114 for (enum radv_blit_ds_layout ds_layout
= RADV_BLIT_DS_LAYOUT_TILE_ENABLE
; ds_layout
< RADV_BLIT_DS_LAYOUT_COUNT
; ds_layout
++) {
1115 if (!device
->meta_state
.blit2d_stencil_only_rp
[ds_layout
]) {
1116 VkImageLayout layout
= radv_meta_blit_ds_to_layout(ds_layout
);
1117 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
1118 &(VkRenderPassCreateInfo
) {
1119 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
1120 .attachmentCount
= 1,
1121 .pAttachments
= &(VkAttachmentDescription
) {
1122 .format
= VK_FORMAT_S8_UINT
,
1123 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1124 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1125 .initialLayout
= layout
,
1126 .finalLayout
= layout
,
1129 .pSubpasses
= &(VkSubpassDescription
) {
1130 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
1131 .inputAttachmentCount
= 0,
1132 .colorAttachmentCount
= 0,
1133 .pColorAttachments
= NULL
,
1134 .pResolveAttachments
= NULL
,
1135 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
1139 .preserveAttachmentCount
= 1,
1140 .pPreserveAttachments
= (uint32_t[]) { 0 },
1142 .dependencyCount
= 0,
1143 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d_stencil_only_rp
[ds_layout
]);
1147 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
1148 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
1149 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
1150 .pStages
= pipeline_shader_stages
,
1151 .pVertexInputState
= vi_create_info
,
1152 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
1153 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
1154 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
1155 .primitiveRestartEnable
= false,
1157 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
1158 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
1162 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
1163 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
1164 .rasterizerDiscardEnable
= false,
1165 .polygonMode
= VK_POLYGON_MODE_FILL
,
1166 .cullMode
= VK_CULL_MODE_NONE
,
1167 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
1169 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
1170 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
1171 .rasterizationSamples
= 1 << log2_samples
,
1172 .sampleShadingEnable
= false,
1173 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
1175 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
1176 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
1177 .attachmentCount
= 0,
1178 .pAttachments
= NULL
,
1180 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
1181 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
1182 .depthTestEnable
= false,
1183 .depthWriteEnable
= false,
1184 .stencilTestEnable
= true,
1186 .failOp
= VK_STENCIL_OP_REPLACE
,
1187 .passOp
= VK_STENCIL_OP_REPLACE
,
1188 .depthFailOp
= VK_STENCIL_OP_REPLACE
,
1189 .compareOp
= VK_COMPARE_OP_ALWAYS
,
1190 .compareMask
= 0xff,
1195 .failOp
= VK_STENCIL_OP_REPLACE
,
1196 .passOp
= VK_STENCIL_OP_REPLACE
,
1197 .depthFailOp
= VK_STENCIL_OP_REPLACE
,
1198 .compareOp
= VK_COMPARE_OP_ALWAYS
,
1199 .compareMask
= 0xff,
1203 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
1205 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
1206 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
1207 .dynamicStateCount
= 6,
1208 .pDynamicStates
= (VkDynamicState
[]) {
1209 VK_DYNAMIC_STATE_VIEWPORT
,
1210 VK_DYNAMIC_STATE_SCISSOR
,
1211 VK_DYNAMIC_STATE_LINE_WIDTH
,
1212 VK_DYNAMIC_STATE_DEPTH_BIAS
,
1213 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
1214 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
1218 .layout
= device
->meta_state
.blit2d
[log2_samples
].p_layouts
[src_type
],
1219 .renderPass
= device
->meta_state
.blit2d_stencil_only_rp
[0],
1223 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
1224 .use_rectlist
= true
1227 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1228 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1229 &vk_pipeline_info
, &radv_pipeline_info
,
1230 &device
->meta_state
.alloc
,
1231 &device
->meta_state
.blit2d
[log2_samples
].stencil_only_pipeline
[src_type
]);
1234 ralloc_free(vs
.nir
);
1235 ralloc_free(fs
.nir
);
1240 static VkFormat pipeline_formats
[] = {
1241 VK_FORMAT_R8G8B8A8_UNORM
,
1242 VK_FORMAT_R8G8B8A8_UINT
,
1243 VK_FORMAT_R8G8B8A8_SINT
,
1244 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
1245 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
1246 VK_FORMAT_R16G16B16A16_UNORM
,
1247 VK_FORMAT_R16G16B16A16_SNORM
,
1248 VK_FORMAT_R16G16B16A16_UINT
,
1249 VK_FORMAT_R16G16B16A16_SINT
,
1250 VK_FORMAT_R32_SFLOAT
,
1251 VK_FORMAT_R32G32_SFLOAT
,
1252 VK_FORMAT_R32G32B32A32_SFLOAT
1256 meta_blit2d_create_pipe_layout(struct radv_device
*device
,
1258 uint32_t log2_samples
)
1261 VkDescriptorType desc_type
= (idx
== BLIT2D_SRC_TYPE_BUFFER
) ? VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
: VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
;
1262 const VkPushConstantRange push_constant_ranges
[] = {
1263 {VK_SHADER_STAGE_VERTEX_BIT
, 0, 16},
1264 {VK_SHADER_STAGE_FRAGMENT_BIT
, 16, 12},
1266 int num_push_constant_range
= (idx
!= BLIT2D_SRC_TYPE_IMAGE
|| log2_samples
> 0) ? 2 : 1;
1268 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
1269 &(VkDescriptorSetLayoutCreateInfo
) {
1270 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
1271 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
1273 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
1276 .descriptorType
= desc_type
,
1277 .descriptorCount
= 1,
1278 .stageFlags
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1279 .pImmutableSamplers
= NULL
1282 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
[log2_samples
].ds_layouts
[idx
]);
1283 if (result
!= VK_SUCCESS
)
1286 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1287 &(VkPipelineLayoutCreateInfo
) {
1288 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1289 .setLayoutCount
= 1,
1290 .pSetLayouts
= &device
->meta_state
.blit2d
[log2_samples
].ds_layouts
[idx
],
1291 .pushConstantRangeCount
= num_push_constant_range
,
1292 .pPushConstantRanges
= push_constant_ranges
,
1294 &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
[log2_samples
].p_layouts
[idx
]);
1295 if (result
!= VK_SUCCESS
)
1303 radv_device_init_meta_blit2d_state(struct radv_device
*device
)
1306 bool create_3d
= device
->physical_device
->rad_info
.chip_class
>= GFX9
;
1308 for (unsigned log2_samples
= 0; log2_samples
< 1 + MAX_SAMPLES_LOG2
; log2_samples
++) {
1309 for (unsigned src
= 0; src
< BLIT2D_NUM_SRC_TYPES
; src
++) {
1310 if (src
== BLIT2D_SRC_TYPE_IMAGE_3D
&& !create_3d
)
1313 /* Don't need to handle copies between buffers and multisample images. */
1314 if (src
== BLIT2D_SRC_TYPE_BUFFER
&& log2_samples
> 0)
1317 result
= meta_blit2d_create_pipe_layout(device
, src
, log2_samples
);
1318 if (result
!= VK_SUCCESS
)
1321 for (unsigned j
= 0; j
< ARRAY_SIZE(pipeline_formats
); ++j
) {
1322 result
= blit2d_init_color_pipeline(device
, src
, pipeline_formats
[j
], log2_samples
);
1323 if (result
!= VK_SUCCESS
)
1327 result
= blit2d_init_depth_only_pipeline(device
, src
, log2_samples
);
1328 if (result
!= VK_SUCCESS
)
1331 result
= blit2d_init_stencil_only_pipeline(device
, src
, log2_samples
);
1332 if (result
!= VK_SUCCESS
)
1340 radv_device_finish_meta_blit2d_state(device
);