radv: change base aligmment for allocated memory.
[mesa.git] / src / amd / vulkan / radv_meta_blit2d.c
1 /*
2 * Copyright © 2016 Red Hat
3 *
4 * based on anv driver:
5 * Copyright © 2016 Intel Corporation
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * IN THE SOFTWARE.
25 */
26
27 #include "radv_meta.h"
28 #include "nir/nir_builder.h"
29
30 enum blit2d_dst_type {
31 /* We can bind this destination as a "normal" render target and render
32 * to it just like you would anywhere else.
33 */
34 BLIT2D_DST_TYPE_NORMAL,
35
36 /* The destination has a 3-channel RGB format. Since we can't render to
37 * non-power-of-two textures, we have to bind it as a red texture and
38 * select the correct component for the given red pixel in the shader.
39 */
40 BLIT2D_DST_TYPE_RGB,
41
42 BLIT2D_NUM_DST_TYPES,
43 };
44
45
46 enum blit2d_src_type {
47 BLIT2D_SRC_TYPE_IMAGE,
48 BLIT2D_SRC_TYPE_BUFFER,
49 BLIT2D_NUM_SRC_TYPES,
50 };
51
52 static void
53 create_iview(struct radv_cmd_buffer *cmd_buffer,
54 struct radv_meta_blit2d_surf *surf,
55 VkImageUsageFlags usage,
56 struct radv_image_view *iview, VkFormat depth_format)
57 {
58 VkFormat format;
59
60 if (depth_format)
61 format = depth_format;
62 else
63 format = surf->format;
64
65 radv_image_view_init(iview, cmd_buffer->device,
66 &(VkImageViewCreateInfo) {
67 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
68 .image = radv_image_to_handle(surf->image),
69 .viewType = VK_IMAGE_VIEW_TYPE_2D,
70 .format = format,
71 .subresourceRange = {
72 .aspectMask = surf->aspect_mask,
73 .baseMipLevel = surf->level,
74 .levelCount = 1,
75 .baseArrayLayer = surf->layer,
76 .layerCount = 1
77 },
78 }, cmd_buffer, usage);
79 }
80
81 static void
82 create_bview(struct radv_cmd_buffer *cmd_buffer,
83 struct radv_meta_blit2d_buffer *src,
84 struct radv_buffer_view *bview, VkFormat depth_format)
85 {
86 VkFormat format;
87
88 if (depth_format)
89 format = depth_format;
90 else
91 format = src->format;
92 radv_buffer_view_init(bview, cmd_buffer->device,
93 &(VkBufferViewCreateInfo) {
94 .sType = VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO,
95 .flags = 0,
96 .buffer = radv_buffer_to_handle(src->buffer),
97 .format = format,
98 .offset = src->offset,
99 .range = VK_WHOLE_SIZE,
100 }, cmd_buffer);
101
102 }
103
104 struct blit2d_src_temps {
105 struct radv_image_view iview;
106
107 VkDescriptorSet set;
108 struct radv_buffer_view bview;
109 };
110
111 static void
112 blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
113 struct radv_meta_blit2d_surf *src_img,
114 struct radv_meta_blit2d_buffer *src_buf,
115 struct blit2d_src_temps *tmp,
116 enum blit2d_src_type src_type, VkFormat depth_format)
117 {
118 struct radv_device *device = cmd_buffer->device;
119 VkDevice vk_device = radv_device_to_handle(cmd_buffer->device);
120
121 if (src_type == BLIT2D_SRC_TYPE_BUFFER) {
122 create_bview(cmd_buffer, src_buf, &tmp->bview, depth_format);
123
124 radv_temp_descriptor_set_create(cmd_buffer->device, cmd_buffer,
125 device->meta_state.blit2d.ds_layouts[src_type],
126 &tmp->set);
127
128 radv_UpdateDescriptorSets(vk_device,
129 1, /* writeCount */
130 (VkWriteDescriptorSet[]) {
131 {
132 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
133 .dstSet = tmp->set,
134 .dstBinding = 0,
135 .dstArrayElement = 0,
136 .descriptorCount = 1,
137 .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
138 .pTexelBufferView = (VkBufferView[]) { radv_buffer_view_to_handle(&tmp->bview) }
139 }
140 }, 0, NULL);
141
142 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
143 device->meta_state.blit2d.p_layouts[src_type],
144 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 4,
145 &src_buf->pitch);
146 } else {
147 create_iview(cmd_buffer, src_img, VK_IMAGE_USAGE_SAMPLED_BIT, &tmp->iview,
148 depth_format);
149
150 radv_temp_descriptor_set_create(cmd_buffer->device, cmd_buffer,
151 device->meta_state.blit2d.ds_layouts[src_type],
152 &tmp->set);
153
154 radv_UpdateDescriptorSets(vk_device,
155 1, /* writeCount */
156 (VkWriteDescriptorSet[]) {
157 {
158 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
159 .dstSet = tmp->set,
160 .dstBinding = 0,
161 .dstArrayElement = 0,
162 .descriptorCount = 1,
163 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
164 .pImageInfo = (VkDescriptorImageInfo[]) {
165 {
166 .sampler = VK_NULL_HANDLE,
167 .imageView = radv_image_view_to_handle(&tmp->iview),
168 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
169 },
170 }
171 }
172 }, 0, NULL);
173
174 }
175
176 radv_CmdBindDescriptorSets(radv_cmd_buffer_to_handle(cmd_buffer),
177 VK_PIPELINE_BIND_POINT_GRAPHICS,
178 device->meta_state.blit2d.p_layouts[src_type], 0, 1,
179 &tmp->set, 0, NULL);
180 }
181
182 static void
183 blit2d_unbind_src(struct radv_cmd_buffer *cmd_buffer,
184 struct blit2d_src_temps *tmp,
185 enum blit2d_src_type src_type)
186 {
187 radv_temp_descriptor_set_destroy(cmd_buffer->device, tmp->set);
188 }
189
190 struct blit2d_dst_temps {
191 VkImage image;
192 struct radv_image_view iview;
193 VkFramebuffer fb;
194 };
195
196 static void
197 blit2d_bind_dst(struct radv_cmd_buffer *cmd_buffer,
198 struct radv_meta_blit2d_surf *dst,
199 uint32_t width,
200 uint32_t height,
201 VkFormat depth_format,
202 struct blit2d_dst_temps *tmp)
203 {
204 VkImageUsageFlagBits bits;
205
206 if (dst->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT)
207 bits = VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
208 else
209 bits = VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT;
210
211 create_iview(cmd_buffer, dst, bits,
212 &tmp->iview, depth_format);
213
214 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer->device),
215 &(VkFramebufferCreateInfo) {
216 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
217 .attachmentCount = 1,
218 .pAttachments = (VkImageView[]) {
219 radv_image_view_to_handle(&tmp->iview),
220 },
221 .width = width,
222 .height = height,
223 .layers = 1
224 }, &cmd_buffer->pool->alloc, &tmp->fb);
225 }
226
227 static void
228 blit2d_unbind_dst(struct radv_cmd_buffer *cmd_buffer,
229 struct blit2d_dst_temps *tmp)
230 {
231 VkDevice vk_device = radv_device_to_handle(cmd_buffer->device);
232 radv_DestroyFramebuffer(vk_device, tmp->fb, &cmd_buffer->pool->alloc);
233 }
234
235 static void
236 bind_pipeline(struct radv_cmd_buffer *cmd_buffer,
237 enum blit2d_src_type src_type, unsigned fs_key)
238 {
239 VkPipeline pipeline =
240 cmd_buffer->device->meta_state.blit2d.pipelines[src_type][fs_key];
241
242 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
243 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
244 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
245 }
246 }
247
248 static void
249 bind_depth_pipeline(struct radv_cmd_buffer *cmd_buffer,
250 enum blit2d_src_type src_type)
251 {
252 VkPipeline pipeline =
253 cmd_buffer->device->meta_state.blit2d.depth_only_pipeline[src_type];
254
255 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
256 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
257 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
258 }
259 }
260
261 static void
262 bind_stencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
263 enum blit2d_src_type src_type)
264 {
265 VkPipeline pipeline =
266 cmd_buffer->device->meta_state.blit2d.stencil_only_pipeline[src_type];
267
268 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
269 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
270 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
271 }
272 }
273
274 static void
275 radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
276 struct radv_meta_blit2d_surf *src_img,
277 struct radv_meta_blit2d_buffer *src_buf,
278 struct radv_meta_blit2d_surf *dst,
279 unsigned num_rects,
280 struct radv_meta_blit2d_rect *rects, enum blit2d_src_type src_type)
281 {
282 struct radv_device *device = cmd_buffer->device;
283
284 for (unsigned r = 0; r < num_rects; ++r) {
285 VkFormat depth_format = 0;
286 if (dst->aspect_mask != VK_IMAGE_ASPECT_COLOR_BIT)
287 depth_format = dst->image->vk_format;
288 struct blit2d_src_temps src_temps;
289 blit2d_bind_src(cmd_buffer, src_img, src_buf, &src_temps, src_type, depth_format);
290
291 uint32_t offset = 0;
292 struct blit2d_dst_temps dst_temps;
293 blit2d_bind_dst(cmd_buffer, dst, rects[r].dst_x + rects[r].width,
294 rects[r].dst_y + rects[r].height, depth_format, &dst_temps);
295
296 struct blit_vb_data {
297 float pos[2];
298 float tex_coord[2];
299 } vb_data[3];
300
301 unsigned vb_size = 3 * sizeof(*vb_data);
302
303 vb_data[0] = (struct blit_vb_data) {
304 .pos = {
305 rects[r].dst_x,
306 rects[r].dst_y,
307 },
308 .tex_coord = {
309 rects[r].src_x,
310 rects[r].src_y,
311 },
312 };
313
314 vb_data[1] = (struct blit_vb_data) {
315 .pos = {
316 rects[r].dst_x,
317 rects[r].dst_y + rects[r].height,
318 },
319 .tex_coord = {
320 rects[r].src_x,
321 rects[r].src_y + rects[r].height,
322 },
323 };
324
325 vb_data[2] = (struct blit_vb_data) {
326 .pos = {
327 rects[r].dst_x + rects[r].width,
328 rects[r].dst_y,
329 },
330 .tex_coord = {
331 rects[r].src_x + rects[r].width,
332 rects[r].src_y,
333 },
334 };
335
336
337 radv_cmd_buffer_upload_data(cmd_buffer, vb_size, 16, vb_data, &offset);
338
339 struct radv_buffer vertex_buffer = {
340 .device = device,
341 .size = vb_size,
342 .bo = cmd_buffer->upload.upload_bo,
343 .offset = offset,
344 };
345
346 radv_CmdBindVertexBuffers(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
347 (VkBuffer[]) {
348 radv_buffer_to_handle(&vertex_buffer),
349 },
350 (VkDeviceSize[]) {
351 0,
352 });
353
354
355 if (dst->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT) {
356 unsigned fs_key = radv_format_meta_fs_key(dst_temps.iview.vk_format);
357
358 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
359 &(VkRenderPassBeginInfo) {
360 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
361 .renderPass = device->meta_state.blit2d.render_passes[fs_key],
362 .framebuffer = dst_temps.fb,
363 .renderArea = {
364 .offset = { rects[r].dst_x, rects[r].dst_y, },
365 .extent = { rects[r].width, rects[r].height },
366 },
367 .clearValueCount = 0,
368 .pClearValues = NULL,
369 }, VK_SUBPASS_CONTENTS_INLINE);
370
371
372 bind_pipeline(cmd_buffer, src_type, fs_key);
373 } else if (dst->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
374 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
375 &(VkRenderPassBeginInfo) {
376 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
377 .renderPass = device->meta_state.blit2d.depth_only_rp,
378 .framebuffer = dst_temps.fb,
379 .renderArea = {
380 .offset = { rects[r].dst_x, rects[r].dst_y, },
381 .extent = { rects[r].width, rects[r].height },
382 },
383 .clearValueCount = 0,
384 .pClearValues = NULL,
385 }, VK_SUBPASS_CONTENTS_INLINE);
386
387
388 bind_depth_pipeline(cmd_buffer, src_type);
389
390 } else if (dst->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
391 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
392 &(VkRenderPassBeginInfo) {
393 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
394 .renderPass = device->meta_state.blit2d.stencil_only_rp,
395 .framebuffer = dst_temps.fb,
396 .renderArea = {
397 .offset = { rects[r].dst_x, rects[r].dst_y, },
398 .extent = { rects[r].width, rects[r].height },
399 },
400 .clearValueCount = 0,
401 .pClearValues = NULL,
402 }, VK_SUBPASS_CONTENTS_INLINE);
403
404
405 bind_stencil_pipeline(cmd_buffer, src_type);
406 }
407
408 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
409 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
410
411 /* At the point where we emit the draw call, all data from the
412 * descriptor sets, etc. has been used. We are free to delete it.
413 */
414 blit2d_unbind_src(cmd_buffer, &src_temps, src_type);
415 blit2d_unbind_dst(cmd_buffer, &dst_temps);
416 }
417 }
418
419 void
420 radv_meta_blit2d(struct radv_cmd_buffer *cmd_buffer,
421 struct radv_meta_blit2d_surf *src_img,
422 struct radv_meta_blit2d_buffer *src_buf,
423 struct radv_meta_blit2d_surf *dst,
424 unsigned num_rects,
425 struct radv_meta_blit2d_rect *rects)
426 {
427 enum blit2d_src_type src_type = src_buf ? BLIT2D_SRC_TYPE_BUFFER :
428 BLIT2D_SRC_TYPE_IMAGE;
429 radv_meta_blit2d_normal_dst(cmd_buffer, src_img, src_buf, dst,
430 num_rects, rects, src_type);
431 }
432
433 static nir_shader *
434 build_nir_vertex_shader(void)
435 {
436 const struct glsl_type *vec4 = glsl_vec4_type();
437 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
438 nir_builder b;
439
440 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
441 b.shader->info->name = ralloc_strdup(b.shader, "meta_blit_vs");
442
443 nir_variable *pos_in = nir_variable_create(b.shader, nir_var_shader_in,
444 vec4, "a_pos");
445 pos_in->data.location = VERT_ATTRIB_GENERIC0;
446 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
447 vec4, "gl_Position");
448 pos_out->data.location = VARYING_SLOT_POS;
449 nir_copy_var(&b, pos_out, pos_in);
450
451 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
452 vec2, "a_tex_pos");
453 tex_pos_in->data.location = VERT_ATTRIB_GENERIC1;
454 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
455 vec2, "v_tex_pos");
456 tex_pos_out->data.location = VARYING_SLOT_VAR0;
457 tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
458 nir_copy_var(&b, tex_pos_out, tex_pos_in);
459
460 return b.shader;
461 }
462
463 typedef nir_ssa_def* (*texel_fetch_build_func)(struct nir_builder *,
464 struct radv_device *,
465 nir_ssa_def *);
466
467 static nir_ssa_def *
468 build_nir_texel_fetch(struct nir_builder *b, struct radv_device *device,
469 nir_ssa_def *tex_pos)
470 {
471 const struct glsl_type *sampler_type =
472 glsl_sampler_type(GLSL_SAMPLER_DIM_2D, false, false, GLSL_TYPE_UINT);
473 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
474 sampler_type, "s_tex");
475 sampler->data.descriptor_set = 0;
476 sampler->data.binding = 0;
477
478 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 2);
479 tex->sampler_dim = GLSL_SAMPLER_DIM_2D;
480 tex->op = nir_texop_txf;
481 tex->src[0].src_type = nir_tex_src_coord;
482 tex->src[0].src = nir_src_for_ssa(tex_pos);
483 tex->src[1].src_type = nir_tex_src_lod;
484 tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
485 tex->dest_type = nir_type_uint;
486 tex->is_array = false;
487 tex->coord_components = 2;
488 tex->texture = nir_deref_var_create(tex, sampler);
489 tex->sampler = NULL;
490
491 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
492 nir_builder_instr_insert(b, &tex->instr);
493
494 return &tex->dest.ssa;
495 }
496
497
498 static nir_ssa_def *
499 build_nir_buffer_fetch(struct nir_builder *b, struct radv_device *device,
500 nir_ssa_def *tex_pos)
501 {
502 const struct glsl_type *sampler_type =
503 glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_UINT);
504 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
505 sampler_type, "s_tex");
506 sampler->data.descriptor_set = 0;
507 sampler->data.binding = 0;
508
509 nir_intrinsic_instr *width = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
510 width->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
511 width->num_components = 1;
512 nir_ssa_dest_init(&width->instr, &width->dest, 1, 32, "width");
513 nir_builder_instr_insert(b, &width->instr);
514
515 nir_ssa_def *pos_x = nir_channel(b, tex_pos, 0);
516 nir_ssa_def *pos_y = nir_channel(b, tex_pos, 1);
517 pos_y = nir_imul(b, pos_y, &width->dest.ssa);
518 pos_x = nir_iadd(b, pos_x, pos_y);
519 //pos_x = nir_iadd(b, pos_x, nir_imm_int(b, 100000));
520
521 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 1);
522 tex->sampler_dim = GLSL_SAMPLER_DIM_BUF;
523 tex->op = nir_texop_txf;
524 tex->src[0].src_type = nir_tex_src_coord;
525 tex->src[0].src = nir_src_for_ssa(pos_x);
526 tex->dest_type = nir_type_uint;
527 tex->is_array = false;
528 tex->coord_components = 1;
529 tex->texture = nir_deref_var_create(tex, sampler);
530 tex->sampler = NULL;
531
532 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
533 nir_builder_instr_insert(b, &tex->instr);
534
535 return &tex->dest.ssa;
536 }
537
538 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
539 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
540 .vertexBindingDescriptionCount = 1,
541 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
542 {
543 .binding = 0,
544 .stride = 4 * sizeof(float),
545 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
546 },
547 },
548 .vertexAttributeDescriptionCount = 2,
549 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
550 {
551 /* Position */
552 .location = 0,
553 .binding = 0,
554 .format = VK_FORMAT_R32G32_SFLOAT,
555 .offset = 0
556 },
557 {
558 /* Texture Coordinate */
559 .location = 1,
560 .binding = 0,
561 .format = VK_FORMAT_R32G32_SFLOAT,
562 .offset = 8
563 },
564 },
565 };
566
567 static nir_shader *
568 build_nir_copy_fragment_shader(struct radv_device *device,
569 texel_fetch_build_func txf_func, const char* name)
570 {
571 const struct glsl_type *vec4 = glsl_vec4_type();
572 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
573 nir_builder b;
574
575 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
576 b.shader->info->name = ralloc_strdup(b.shader, name);
577
578 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
579 vec2, "v_tex_pos");
580 tex_pos_in->data.location = VARYING_SLOT_VAR0;
581
582 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
583 vec4, "f_color");
584 color_out->data.location = FRAG_RESULT_DATA0;
585
586 nir_ssa_def *pos_int = nir_f2i(&b, nir_load_var(&b, tex_pos_in));
587 unsigned swiz[4] = { 0, 1 };
588 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
589
590 nir_ssa_def *color = txf_func(&b, device, tex_pos);
591 nir_store_var(&b, color_out, color, 0xf);
592
593 return b.shader;
594 }
595
596 static nir_shader *
597 build_nir_copy_fragment_shader_depth(struct radv_device *device,
598 texel_fetch_build_func txf_func, const char* name)
599 {
600 const struct glsl_type *vec4 = glsl_vec4_type();
601 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
602 nir_builder b;
603
604 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
605 b.shader->info->name = ralloc_strdup(b.shader, name);
606
607 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
608 vec2, "v_tex_pos");
609 tex_pos_in->data.location = VARYING_SLOT_VAR0;
610
611 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
612 vec4, "f_color");
613 color_out->data.location = FRAG_RESULT_DEPTH;
614
615 nir_ssa_def *pos_int = nir_f2i(&b, nir_load_var(&b, tex_pos_in));
616 unsigned swiz[4] = { 0, 1 };
617 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
618
619 nir_ssa_def *color = txf_func(&b, device, tex_pos);
620 nir_store_var(&b, color_out, color, 0x1);
621
622 return b.shader;
623 }
624
625 static nir_shader *
626 build_nir_copy_fragment_shader_stencil(struct radv_device *device,
627 texel_fetch_build_func txf_func, const char* name)
628 {
629 const struct glsl_type *vec4 = glsl_vec4_type();
630 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
631 nir_builder b;
632
633 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
634 b.shader->info->name = ralloc_strdup(b.shader, name);
635
636 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
637 vec2, "v_tex_pos");
638 tex_pos_in->data.location = VARYING_SLOT_VAR0;
639
640 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
641 vec4, "f_color");
642 color_out->data.location = FRAG_RESULT_STENCIL;
643
644 nir_ssa_def *pos_int = nir_f2i(&b, nir_load_var(&b, tex_pos_in));
645 unsigned swiz[4] = { 0, 1 };
646 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
647
648 nir_ssa_def *color = txf_func(&b, device, tex_pos);
649 nir_store_var(&b, color_out, color, 0x1);
650
651 return b.shader;
652 }
653
654 void
655 radv_device_finish_meta_blit2d_state(struct radv_device *device)
656 {
657 for(unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
658 if (device->meta_state.blit2d.render_passes[j]) {
659 radv_DestroyRenderPass(radv_device_to_handle(device),
660 device->meta_state.blit2d.render_passes[j],
661 &device->meta_state.alloc);
662 }
663 }
664
665 radv_DestroyRenderPass(radv_device_to_handle(device),
666 device->meta_state.blit2d.depth_only_rp,
667 &device->meta_state.alloc);
668 radv_DestroyRenderPass(radv_device_to_handle(device),
669 device->meta_state.blit2d.stencil_only_rp,
670 &device->meta_state.alloc);
671
672 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
673 if (device->meta_state.blit2d.p_layouts[src]) {
674 radv_DestroyPipelineLayout(radv_device_to_handle(device),
675 device->meta_state.blit2d.p_layouts[src],
676 &device->meta_state.alloc);
677 }
678
679 if (device->meta_state.blit2d.ds_layouts[src]) {
680 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
681 device->meta_state.blit2d.ds_layouts[src],
682 &device->meta_state.alloc);
683 }
684
685 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
686 if (device->meta_state.blit2d.pipelines[src][j]) {
687 radv_DestroyPipeline(radv_device_to_handle(device),
688 device->meta_state.blit2d.pipelines[src][j],
689 &device->meta_state.alloc);
690 }
691 }
692
693 radv_DestroyPipeline(radv_device_to_handle(device),
694 device->meta_state.blit2d.depth_only_pipeline[src],
695 &device->meta_state.alloc);
696 radv_DestroyPipeline(radv_device_to_handle(device),
697 device->meta_state.blit2d.stencil_only_pipeline[src],
698 &device->meta_state.alloc);
699 }
700 }
701
702 static VkResult
703 blit2d_init_color_pipeline(struct radv_device *device,
704 enum blit2d_src_type src_type,
705 VkFormat format)
706 {
707 VkResult result;
708 unsigned fs_key = radv_format_meta_fs_key(format);
709 const char *name;
710
711 texel_fetch_build_func src_func;
712 switch(src_type) {
713 case BLIT2D_SRC_TYPE_IMAGE:
714 src_func = build_nir_texel_fetch;
715 name = "meta_blit2d_image_fs";
716 break;
717 case BLIT2D_SRC_TYPE_BUFFER:
718 src_func = build_nir_buffer_fetch;
719 name = "meta_blit2d_buffer_fs";
720 break;
721 default:
722 unreachable("unknown blit src type\n");
723 break;
724 }
725
726 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
727 struct radv_shader_module fs = { .nir = NULL };
728
729
730 fs.nir = build_nir_copy_fragment_shader(device, src_func, name);
731 vi_create_info = &normal_vi_create_info;
732
733 struct radv_shader_module vs = {
734 .nir = build_nir_vertex_shader(),
735 };
736
737 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
738 {
739 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
740 .stage = VK_SHADER_STAGE_VERTEX_BIT,
741 .module = radv_shader_module_to_handle(&vs),
742 .pName = "main",
743 .pSpecializationInfo = NULL
744 }, {
745 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
746 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
747 .module = radv_shader_module_to_handle(&fs),
748 .pName = "main",
749 .pSpecializationInfo = NULL
750 },
751 };
752
753 if (!device->meta_state.blit2d.render_passes[fs_key]) {
754 result = radv_CreateRenderPass(radv_device_to_handle(device),
755 &(VkRenderPassCreateInfo) {
756 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
757 .attachmentCount = 1,
758 .pAttachments = &(VkAttachmentDescription) {
759 .format = format,
760 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
761 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
762 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
763 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
764 },
765 .subpassCount = 1,
766 .pSubpasses = &(VkSubpassDescription) {
767 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
768 .inputAttachmentCount = 0,
769 .colorAttachmentCount = 1,
770 .pColorAttachments = &(VkAttachmentReference) {
771 .attachment = 0,
772 .layout = VK_IMAGE_LAYOUT_GENERAL,
773 },
774 .pResolveAttachments = NULL,
775 .pDepthStencilAttachment = &(VkAttachmentReference) {
776 .attachment = VK_ATTACHMENT_UNUSED,
777 .layout = VK_IMAGE_LAYOUT_GENERAL,
778 },
779 .preserveAttachmentCount = 1,
780 .pPreserveAttachments = (uint32_t[]) { 0 },
781 },
782 .dependencyCount = 0,
783 }, &device->meta_state.alloc, &device->meta_state.blit2d.render_passes[fs_key]);
784 }
785
786 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
787 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
788 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
789 .pStages = pipeline_shader_stages,
790 .pVertexInputState = vi_create_info,
791 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
792 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
793 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
794 .primitiveRestartEnable = false,
795 },
796 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
797 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
798 .viewportCount = 0,
799 .scissorCount = 0,
800 },
801 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
802 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
803 .rasterizerDiscardEnable = false,
804 .polygonMode = VK_POLYGON_MODE_FILL,
805 .cullMode = VK_CULL_MODE_NONE,
806 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
807 },
808 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
809 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
810 .rasterizationSamples = 1,
811 .sampleShadingEnable = false,
812 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
813 },
814 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
815 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
816 .attachmentCount = 1,
817 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
818 { .colorWriteMask =
819 VK_COLOR_COMPONENT_A_BIT |
820 VK_COLOR_COMPONENT_R_BIT |
821 VK_COLOR_COMPONENT_G_BIT |
822 VK_COLOR_COMPONENT_B_BIT },
823 }
824 },
825 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
826 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
827 .dynamicStateCount = 7,
828 .pDynamicStates = (VkDynamicState[]) {
829 VK_DYNAMIC_STATE_LINE_WIDTH,
830 VK_DYNAMIC_STATE_DEPTH_BIAS,
831 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
832 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
833 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
834 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
835 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
836 },
837 },
838 .flags = 0,
839 .layout = device->meta_state.blit2d.p_layouts[src_type],
840 .renderPass = device->meta_state.blit2d.render_passes[fs_key],
841 .subpass = 0,
842 };
843
844 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
845 .use_rectlist = true
846 };
847
848 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
849 radv_pipeline_cache_to_handle(&device->meta_state.cache),
850 &vk_pipeline_info, &radv_pipeline_info,
851 &device->meta_state.alloc,
852 &device->meta_state.blit2d.pipelines[src_type][fs_key]);
853
854
855 ralloc_free(vs.nir);
856 ralloc_free(fs.nir);
857
858 return result;
859 }
860
861 static VkResult
862 blit2d_init_depth_only_pipeline(struct radv_device *device,
863 enum blit2d_src_type src_type)
864 {
865 VkResult result;
866 const char *name;
867
868 texel_fetch_build_func src_func;
869 switch(src_type) {
870 case BLIT2D_SRC_TYPE_IMAGE:
871 src_func = build_nir_texel_fetch;
872 name = "meta_blit2d_depth_image_fs";
873 break;
874 case BLIT2D_SRC_TYPE_BUFFER:
875 src_func = build_nir_buffer_fetch;
876 name = "meta_blit2d_depth_buffer_fs";
877 break;
878 default:
879 unreachable("unknown blit src type\n");
880 break;
881 }
882
883 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
884 struct radv_shader_module fs = { .nir = NULL };
885
886 fs.nir = build_nir_copy_fragment_shader_depth(device, src_func, name);
887 vi_create_info = &normal_vi_create_info;
888
889 struct radv_shader_module vs = {
890 .nir = build_nir_vertex_shader(),
891 };
892
893 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
894 {
895 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
896 .stage = VK_SHADER_STAGE_VERTEX_BIT,
897 .module = radv_shader_module_to_handle(&vs),
898 .pName = "main",
899 .pSpecializationInfo = NULL
900 }, {
901 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
902 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
903 .module = radv_shader_module_to_handle(&fs),
904 .pName = "main",
905 .pSpecializationInfo = NULL
906 },
907 };
908
909 if (!device->meta_state.blit2d.depth_only_rp) {
910 result = radv_CreateRenderPass(radv_device_to_handle(device),
911 &(VkRenderPassCreateInfo) {
912 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
913 .attachmentCount = 1,
914 .pAttachments = &(VkAttachmentDescription) {
915 .format = 0,
916 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
917 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
918 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
919 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
920 },
921 .subpassCount = 1,
922 .pSubpasses = &(VkSubpassDescription) {
923 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
924 .inputAttachmentCount = 0,
925 .colorAttachmentCount = 0,
926 .pColorAttachments = NULL,
927 .pResolveAttachments = NULL,
928 .pDepthStencilAttachment = &(VkAttachmentReference) {
929 .attachment = 0,
930 .layout = VK_IMAGE_LAYOUT_GENERAL,
931 },
932 .preserveAttachmentCount = 1,
933 .pPreserveAttachments = (uint32_t[]) { 0 },
934 },
935 .dependencyCount = 0,
936 }, &device->meta_state.alloc, &device->meta_state.blit2d.depth_only_rp);
937 }
938
939 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
940 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
941 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
942 .pStages = pipeline_shader_stages,
943 .pVertexInputState = vi_create_info,
944 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
945 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
946 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
947 .primitiveRestartEnable = false,
948 },
949 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
950 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
951 .viewportCount = 0,
952 .scissorCount = 0,
953 },
954 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
955 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
956 .rasterizerDiscardEnable = false,
957 .polygonMode = VK_POLYGON_MODE_FILL,
958 .cullMode = VK_CULL_MODE_NONE,
959 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
960 },
961 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
962 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
963 .rasterizationSamples = 1,
964 .sampleShadingEnable = false,
965 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
966 },
967 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
968 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
969 .attachmentCount = 0,
970 .pAttachments = NULL,
971 },
972 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
973 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
974 .depthTestEnable = true,
975 .depthWriteEnable = true,
976 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
977 },
978 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
979 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
980 .dynamicStateCount = 7,
981 .pDynamicStates = (VkDynamicState[]) {
982 VK_DYNAMIC_STATE_LINE_WIDTH,
983 VK_DYNAMIC_STATE_DEPTH_BIAS,
984 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
985 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
986 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
987 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
988 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
989 },
990 },
991 .flags = 0,
992 .layout = device->meta_state.blit2d.p_layouts[src_type],
993 .renderPass = device->meta_state.blit2d.depth_only_rp,
994 .subpass = 0,
995 };
996
997 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
998 .use_rectlist = true
999 };
1000
1001 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1002 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1003 &vk_pipeline_info, &radv_pipeline_info,
1004 &device->meta_state.alloc,
1005 &device->meta_state.blit2d.depth_only_pipeline[src_type]);
1006
1007
1008 ralloc_free(vs.nir);
1009 ralloc_free(fs.nir);
1010
1011 return result;
1012 }
1013
1014 static VkResult
1015 blit2d_init_stencil_only_pipeline(struct radv_device *device,
1016 enum blit2d_src_type src_type)
1017 {
1018 VkResult result;
1019 const char *name;
1020
1021 texel_fetch_build_func src_func;
1022 switch(src_type) {
1023 case BLIT2D_SRC_TYPE_IMAGE:
1024 src_func = build_nir_texel_fetch;
1025 name = "meta_blit2d_stencil_image_fs";
1026 break;
1027 case BLIT2D_SRC_TYPE_BUFFER:
1028 src_func = build_nir_buffer_fetch;
1029 name = "meta_blit2d_stencil_buffer_fs";
1030 break;
1031 default:
1032 unreachable("unknown blit src type\n");
1033 break;
1034 }
1035
1036 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
1037 struct radv_shader_module fs = { .nir = NULL };
1038
1039 fs.nir = build_nir_copy_fragment_shader_stencil(device, src_func, name);
1040 vi_create_info = &normal_vi_create_info;
1041
1042 struct radv_shader_module vs = {
1043 .nir = build_nir_vertex_shader(),
1044 };
1045
1046 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
1047 {
1048 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1049 .stage = VK_SHADER_STAGE_VERTEX_BIT,
1050 .module = radv_shader_module_to_handle(&vs),
1051 .pName = "main",
1052 .pSpecializationInfo = NULL
1053 }, {
1054 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1055 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
1056 .module = radv_shader_module_to_handle(&fs),
1057 .pName = "main",
1058 .pSpecializationInfo = NULL
1059 },
1060 };
1061
1062 if (!device->meta_state.blit2d.stencil_only_rp) {
1063 result = radv_CreateRenderPass(radv_device_to_handle(device),
1064 &(VkRenderPassCreateInfo) {
1065 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1066 .attachmentCount = 1,
1067 .pAttachments = &(VkAttachmentDescription) {
1068 .format = 0,
1069 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1070 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1071 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
1072 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
1073 },
1074 .subpassCount = 1,
1075 .pSubpasses = &(VkSubpassDescription) {
1076 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1077 .inputAttachmentCount = 0,
1078 .colorAttachmentCount = 0,
1079 .pColorAttachments = NULL,
1080 .pResolveAttachments = NULL,
1081 .pDepthStencilAttachment = &(VkAttachmentReference) {
1082 .attachment = 0,
1083 .layout = VK_IMAGE_LAYOUT_GENERAL,
1084 },
1085 .preserveAttachmentCount = 1,
1086 .pPreserveAttachments = (uint32_t[]) { 0 },
1087 },
1088 .dependencyCount = 0,
1089 }, &device->meta_state.alloc, &device->meta_state.blit2d.stencil_only_rp);
1090 }
1091
1092 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1093 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1094 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
1095 .pStages = pipeline_shader_stages,
1096 .pVertexInputState = vi_create_info,
1097 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1098 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1099 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1100 .primitiveRestartEnable = false,
1101 },
1102 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
1103 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1104 .viewportCount = 0,
1105 .scissorCount = 0,
1106 },
1107 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1108 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1109 .rasterizerDiscardEnable = false,
1110 .polygonMode = VK_POLYGON_MODE_FILL,
1111 .cullMode = VK_CULL_MODE_NONE,
1112 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1113 },
1114 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1115 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1116 .rasterizationSamples = 1,
1117 .sampleShadingEnable = false,
1118 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1119 },
1120 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1121 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1122 .attachmentCount = 0,
1123 .pAttachments = NULL,
1124 },
1125 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1126 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1127 .depthTestEnable = false,
1128 .depthWriteEnable = false,
1129 .stencilTestEnable = true,
1130 .front = {
1131 .failOp = VK_STENCIL_OP_REPLACE,
1132 .passOp = VK_STENCIL_OP_REPLACE,
1133 .depthFailOp = VK_STENCIL_OP_REPLACE,
1134 .compareOp = VK_COMPARE_OP_ALWAYS,
1135 .compareMask = 0xff,
1136 .writeMask = 0xff,
1137 .reference = 0
1138 },
1139 .back = {
1140 .failOp = VK_STENCIL_OP_REPLACE,
1141 .passOp = VK_STENCIL_OP_REPLACE,
1142 .depthFailOp = VK_STENCIL_OP_REPLACE,
1143 .compareOp = VK_COMPARE_OP_ALWAYS,
1144 .compareMask = 0xff,
1145 .writeMask = 0xff,
1146 .reference = 0
1147 },
1148 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
1149 },
1150 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1151 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1152 .dynamicStateCount = 4,
1153 .pDynamicStates = (VkDynamicState[]) {
1154 VK_DYNAMIC_STATE_LINE_WIDTH,
1155 VK_DYNAMIC_STATE_DEPTH_BIAS,
1156 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1157 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1158 },
1159 },
1160 .flags = 0,
1161 .layout = device->meta_state.blit2d.p_layouts[src_type],
1162 .renderPass = device->meta_state.blit2d.stencil_only_rp,
1163 .subpass = 0,
1164 };
1165
1166 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1167 .use_rectlist = true
1168 };
1169
1170 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1171 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1172 &vk_pipeline_info, &radv_pipeline_info,
1173 &device->meta_state.alloc,
1174 &device->meta_state.blit2d.stencil_only_pipeline[src_type]);
1175
1176
1177 ralloc_free(vs.nir);
1178 ralloc_free(fs.nir);
1179
1180 return result;
1181 }
1182
1183 static VkFormat pipeline_formats[] = {
1184 VK_FORMAT_R8G8B8A8_UNORM,
1185 VK_FORMAT_R8G8B8A8_UINT,
1186 VK_FORMAT_R8G8B8A8_SINT,
1187 VK_FORMAT_R16G16B16A16_UNORM,
1188 VK_FORMAT_R16G16B16A16_SNORM,
1189 VK_FORMAT_R16G16B16A16_UINT,
1190 VK_FORMAT_R16G16B16A16_SINT,
1191 VK_FORMAT_R32_SFLOAT,
1192 VK_FORMAT_R32G32_SFLOAT,
1193 VK_FORMAT_R32G32B32A32_SFLOAT
1194 };
1195
1196 VkResult
1197 radv_device_init_meta_blit2d_state(struct radv_device *device)
1198 {
1199 VkResult result;
1200
1201 zero(device->meta_state.blit2d);
1202
1203 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1204 &(VkDescriptorSetLayoutCreateInfo) {
1205 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1206 .bindingCount = 1,
1207 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1208 {
1209 .binding = 0,
1210 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
1211 .descriptorCount = 1,
1212 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1213 .pImmutableSamplers = NULL
1214 },
1215 }
1216 }, &device->meta_state.alloc, &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_IMAGE]);
1217 if (result != VK_SUCCESS)
1218 goto fail;
1219
1220 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1221 &(VkPipelineLayoutCreateInfo) {
1222 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1223 .setLayoutCount = 1,
1224 .pSetLayouts = &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_IMAGE],
1225 },
1226 &device->meta_state.alloc, &device->meta_state.blit2d.p_layouts[BLIT2D_SRC_TYPE_IMAGE]);
1227 if (result != VK_SUCCESS)
1228 goto fail;
1229
1230 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1231 &(VkDescriptorSetLayoutCreateInfo) {
1232 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1233 .bindingCount = 1,
1234 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1235 {
1236 .binding = 0,
1237 .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
1238 .descriptorCount = 1,
1239 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1240 .pImmutableSamplers = NULL
1241 },
1242 }
1243 }, &device->meta_state.alloc, &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_BUFFER]);
1244 if (result != VK_SUCCESS)
1245 goto fail;
1246
1247 const VkPushConstantRange push_constant_range = {VK_SHADER_STAGE_FRAGMENT_BIT, 0, 4};
1248 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1249 &(VkPipelineLayoutCreateInfo) {
1250 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1251 .setLayoutCount = 1,
1252 .pSetLayouts = &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_BUFFER],
1253 .pushConstantRangeCount = 1,
1254 .pPushConstantRanges = &push_constant_range,
1255 },
1256 &device->meta_state.alloc, &device->meta_state.blit2d.p_layouts[BLIT2D_SRC_TYPE_BUFFER]);
1257 if (result != VK_SUCCESS)
1258 goto fail;
1259
1260 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
1261 for (unsigned j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
1262 result = blit2d_init_color_pipeline(device, src, pipeline_formats[j]);
1263 if (result != VK_SUCCESS)
1264 goto fail;
1265 }
1266
1267 result = blit2d_init_depth_only_pipeline(device, src);
1268 if (result != VK_SUCCESS)
1269 goto fail;
1270
1271 result = blit2d_init_stencil_only_pipeline(device, src);
1272 if (result != VK_SUCCESS)
1273 goto fail;
1274 }
1275
1276 return VK_SUCCESS;
1277
1278 fail:
1279 radv_device_finish_meta_blit2d_state(device);
1280 return result;
1281 }