2 * Copyright © 2016 Red Hat
5 * Copyright © 2016 Intel Corporation
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "radv_meta.h"
28 #include "nir/nir_builder.h"
30 enum blit2d_dst_type
{
31 /* We can bind this destination as a "normal" render target and render
32 * to it just like you would anywhere else.
34 BLIT2D_DST_TYPE_NORMAL
,
36 /* The destination has a 3-channel RGB format. Since we can't render to
37 * non-power-of-two textures, we have to bind it as a red texture and
38 * select the correct component for the given red pixel in the shader.
46 enum blit2d_src_type
{
47 BLIT2D_SRC_TYPE_IMAGE
,
48 BLIT2D_SRC_TYPE_BUFFER
,
53 create_iview(struct radv_cmd_buffer
*cmd_buffer
,
54 struct radv_meta_blit2d_surf
*surf
,
55 VkImageUsageFlags usage
,
56 struct radv_image_view
*iview
, VkFormat depth_format
)
61 format
= depth_format
;
63 format
= surf
->format
;
65 radv_image_view_init(iview
, cmd_buffer
->device
,
66 &(VkImageViewCreateInfo
) {
67 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
68 .image
= radv_image_to_handle(surf
->image
),
69 .viewType
= VK_IMAGE_VIEW_TYPE_2D
,
72 .aspectMask
= surf
->aspect_mask
,
73 .baseMipLevel
= surf
->level
,
75 .baseArrayLayer
= surf
->layer
,
78 }, cmd_buffer
, usage
);
82 create_bview(struct radv_cmd_buffer
*cmd_buffer
,
83 struct radv_meta_blit2d_buffer
*src
,
84 struct radv_buffer_view
*bview
, VkFormat depth_format
)
89 format
= depth_format
;
92 radv_buffer_view_init(bview
, cmd_buffer
->device
,
93 &(VkBufferViewCreateInfo
) {
94 .sType
= VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO
,
96 .buffer
= radv_buffer_to_handle(src
->buffer
),
98 .offset
= src
->offset
,
99 .range
= VK_WHOLE_SIZE
,
104 struct blit2d_src_temps
{
105 struct radv_image_view iview
;
108 struct radv_buffer_view bview
;
112 blit2d_bind_src(struct radv_cmd_buffer
*cmd_buffer
,
113 struct radv_meta_blit2d_surf
*src_img
,
114 struct radv_meta_blit2d_buffer
*src_buf
,
115 struct blit2d_src_temps
*tmp
,
116 enum blit2d_src_type src_type
, VkFormat depth_format
)
118 struct radv_device
*device
= cmd_buffer
->device
;
119 VkDevice vk_device
= radv_device_to_handle(cmd_buffer
->device
);
121 if (src_type
== BLIT2D_SRC_TYPE_BUFFER
) {
122 create_bview(cmd_buffer
, src_buf
, &tmp
->bview
, depth_format
);
124 radv_temp_descriptor_set_create(cmd_buffer
->device
, cmd_buffer
,
125 device
->meta_state
.blit2d
.ds_layouts
[src_type
],
128 radv_UpdateDescriptorSets(vk_device
,
130 (VkWriteDescriptorSet
[]) {
132 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
135 .dstArrayElement
= 0,
136 .descriptorCount
= 1,
137 .descriptorType
= VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
,
138 .pTexelBufferView
= (VkBufferView
[]) { radv_buffer_view_to_handle(&tmp
->bview
) }
142 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
143 device
->meta_state
.blit2d
.p_layouts
[src_type
],
144 VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 4,
147 create_iview(cmd_buffer
, src_img
, VK_IMAGE_USAGE_SAMPLED_BIT
, &tmp
->iview
,
150 radv_temp_descriptor_set_create(cmd_buffer
->device
, cmd_buffer
,
151 device
->meta_state
.blit2d
.ds_layouts
[src_type
],
154 radv_UpdateDescriptorSets(vk_device
,
156 (VkWriteDescriptorSet
[]) {
158 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
161 .dstArrayElement
= 0,
162 .descriptorCount
= 1,
163 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
164 .pImageInfo
= (VkDescriptorImageInfo
[]) {
166 .sampler
= VK_NULL_HANDLE
,
167 .imageView
= radv_image_view_to_handle(&tmp
->iview
),
168 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
176 radv_CmdBindDescriptorSets(radv_cmd_buffer_to_handle(cmd_buffer
),
177 VK_PIPELINE_BIND_POINT_GRAPHICS
,
178 device
->meta_state
.blit2d
.p_layouts
[src_type
], 0, 1,
183 blit2d_unbind_src(struct radv_cmd_buffer
*cmd_buffer
,
184 struct blit2d_src_temps
*tmp
,
185 enum blit2d_src_type src_type
)
187 radv_temp_descriptor_set_destroy(cmd_buffer
->device
, tmp
->set
);
190 struct blit2d_dst_temps
{
192 struct radv_image_view iview
;
197 blit2d_bind_dst(struct radv_cmd_buffer
*cmd_buffer
,
198 struct radv_meta_blit2d_surf
*dst
,
201 VkFormat depth_format
,
202 struct blit2d_dst_temps
*tmp
)
204 VkImageUsageFlagBits bits
;
206 if (dst
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
)
207 bits
= VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
;
209 bits
= VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
;
211 create_iview(cmd_buffer
, dst
, bits
,
212 &tmp
->iview
, depth_format
);
214 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer
->device
),
215 &(VkFramebufferCreateInfo
) {
216 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
217 .attachmentCount
= 1,
218 .pAttachments
= (VkImageView
[]) {
219 radv_image_view_to_handle(&tmp
->iview
),
224 }, &cmd_buffer
->pool
->alloc
, &tmp
->fb
);
228 blit2d_unbind_dst(struct radv_cmd_buffer
*cmd_buffer
,
229 struct blit2d_dst_temps
*tmp
)
231 VkDevice vk_device
= radv_device_to_handle(cmd_buffer
->device
);
232 radv_DestroyFramebuffer(vk_device
, tmp
->fb
, &cmd_buffer
->pool
->alloc
);
236 bind_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
237 enum blit2d_src_type src_type
, unsigned fs_key
)
239 VkPipeline pipeline
=
240 cmd_buffer
->device
->meta_state
.blit2d
.pipelines
[src_type
][fs_key
];
242 if (cmd_buffer
->state
.pipeline
!= radv_pipeline_from_handle(pipeline
)) {
243 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
244 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
249 bind_depth_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
250 enum blit2d_src_type src_type
)
252 VkPipeline pipeline
=
253 cmd_buffer
->device
->meta_state
.blit2d
.depth_only_pipeline
[src_type
];
255 if (cmd_buffer
->state
.pipeline
!= radv_pipeline_from_handle(pipeline
)) {
256 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
257 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
262 bind_stencil_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
263 enum blit2d_src_type src_type
)
265 VkPipeline pipeline
=
266 cmd_buffer
->device
->meta_state
.blit2d
.stencil_only_pipeline
[src_type
];
268 if (cmd_buffer
->state
.pipeline
!= radv_pipeline_from_handle(pipeline
)) {
269 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
270 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
275 radv_meta_blit2d_normal_dst(struct radv_cmd_buffer
*cmd_buffer
,
276 struct radv_meta_blit2d_surf
*src_img
,
277 struct radv_meta_blit2d_buffer
*src_buf
,
278 struct radv_meta_blit2d_surf
*dst
,
280 struct radv_meta_blit2d_rect
*rects
, enum blit2d_src_type src_type
)
282 struct radv_device
*device
= cmd_buffer
->device
;
284 for (unsigned r
= 0; r
< num_rects
; ++r
) {
285 VkFormat depth_format
= 0;
286 if (dst
->aspect_mask
!= VK_IMAGE_ASPECT_COLOR_BIT
)
287 depth_format
= dst
->image
->vk_format
;
288 struct blit2d_src_temps src_temps
;
289 blit2d_bind_src(cmd_buffer
, src_img
, src_buf
, &src_temps
, src_type
, depth_format
);
292 struct blit2d_dst_temps dst_temps
;
293 blit2d_bind_dst(cmd_buffer
, dst
, rects
[r
].dst_x
+ rects
[r
].width
,
294 rects
[r
].dst_y
+ rects
[r
].height
, depth_format
, &dst_temps
);
296 struct blit_vb_data
{
301 unsigned vb_size
= 3 * sizeof(*vb_data
);
303 vb_data
[0] = (struct blit_vb_data
) {
314 vb_data
[1] = (struct blit_vb_data
) {
317 rects
[r
].dst_y
+ rects
[r
].height
,
321 rects
[r
].src_y
+ rects
[r
].height
,
325 vb_data
[2] = (struct blit_vb_data
) {
327 rects
[r
].dst_x
+ rects
[r
].width
,
331 rects
[r
].src_x
+ rects
[r
].width
,
337 radv_cmd_buffer_upload_data(cmd_buffer
, vb_size
, 16, vb_data
, &offset
);
339 struct radv_buffer vertex_buffer
= {
342 .bo
= cmd_buffer
->upload
.upload_bo
,
346 radv_CmdBindVertexBuffers(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1,
348 radv_buffer_to_handle(&vertex_buffer
),
355 if (dst
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
) {
356 unsigned fs_key
= radv_format_meta_fs_key(dst_temps
.iview
.vk_format
);
358 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
359 &(VkRenderPassBeginInfo
) {
360 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
361 .renderPass
= device
->meta_state
.blit2d
.render_passes
[fs_key
],
362 .framebuffer
= dst_temps
.fb
,
364 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
365 .extent
= { rects
[r
].width
, rects
[r
].height
},
367 .clearValueCount
= 0,
368 .pClearValues
= NULL
,
369 }, VK_SUBPASS_CONTENTS_INLINE
);
372 bind_pipeline(cmd_buffer
, src_type
, fs_key
);
373 } else if (dst
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
374 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
375 &(VkRenderPassBeginInfo
) {
376 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
377 .renderPass
= device
->meta_state
.blit2d
.depth_only_rp
,
378 .framebuffer
= dst_temps
.fb
,
380 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
381 .extent
= { rects
[r
].width
, rects
[r
].height
},
383 .clearValueCount
= 0,
384 .pClearValues
= NULL
,
385 }, VK_SUBPASS_CONTENTS_INLINE
);
388 bind_depth_pipeline(cmd_buffer
, src_type
);
390 } else if (dst
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
391 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
392 &(VkRenderPassBeginInfo
) {
393 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
394 .renderPass
= device
->meta_state
.blit2d
.stencil_only_rp
,
395 .framebuffer
= dst_temps
.fb
,
397 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
398 .extent
= { rects
[r
].width
, rects
[r
].height
},
400 .clearValueCount
= 0,
401 .pClearValues
= NULL
,
402 }, VK_SUBPASS_CONTENTS_INLINE
);
405 bind_stencil_pipeline(cmd_buffer
, src_type
);
408 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer
), 3, 1, 0, 0);
409 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
));
411 /* At the point where we emit the draw call, all data from the
412 * descriptor sets, etc. has been used. We are free to delete it.
414 blit2d_unbind_src(cmd_buffer
, &src_temps
, src_type
);
415 blit2d_unbind_dst(cmd_buffer
, &dst_temps
);
420 radv_meta_blit2d(struct radv_cmd_buffer
*cmd_buffer
,
421 struct radv_meta_blit2d_surf
*src_img
,
422 struct radv_meta_blit2d_buffer
*src_buf
,
423 struct radv_meta_blit2d_surf
*dst
,
425 struct radv_meta_blit2d_rect
*rects
)
427 enum blit2d_src_type src_type
= src_buf
? BLIT2D_SRC_TYPE_BUFFER
:
428 BLIT2D_SRC_TYPE_IMAGE
;
429 radv_meta_blit2d_normal_dst(cmd_buffer
, src_img
, src_buf
, dst
,
430 num_rects
, rects
, src_type
);
434 build_nir_vertex_shader(void)
436 const struct glsl_type
*vec4
= glsl_vec4_type();
437 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
440 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
441 b
.shader
->info
->name
= ralloc_strdup(b
.shader
, "meta_blit_vs");
443 nir_variable
*pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
445 pos_in
->data
.location
= VERT_ATTRIB_GENERIC0
;
446 nir_variable
*pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
447 vec4
, "gl_Position");
448 pos_out
->data
.location
= VARYING_SLOT_POS
;
449 nir_copy_var(&b
, pos_out
, pos_in
);
451 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
453 tex_pos_in
->data
.location
= VERT_ATTRIB_GENERIC1
;
454 nir_variable
*tex_pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
456 tex_pos_out
->data
.location
= VARYING_SLOT_VAR0
;
457 tex_pos_out
->data
.interpolation
= INTERP_MODE_SMOOTH
;
458 nir_copy_var(&b
, tex_pos_out
, tex_pos_in
);
463 typedef nir_ssa_def
* (*texel_fetch_build_func
)(struct nir_builder
*,
464 struct radv_device
*,
468 build_nir_texel_fetch(struct nir_builder
*b
, struct radv_device
*device
,
469 nir_ssa_def
*tex_pos
)
471 const struct glsl_type
*sampler_type
=
472 glsl_sampler_type(GLSL_SAMPLER_DIM_2D
, false, false, GLSL_TYPE_UINT
);
473 nir_variable
*sampler
= nir_variable_create(b
->shader
, nir_var_uniform
,
474 sampler_type
, "s_tex");
475 sampler
->data
.descriptor_set
= 0;
476 sampler
->data
.binding
= 0;
478 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, 2);
479 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
480 tex
->op
= nir_texop_txf
;
481 tex
->src
[0].src_type
= nir_tex_src_coord
;
482 tex
->src
[0].src
= nir_src_for_ssa(tex_pos
);
483 tex
->src
[1].src_type
= nir_tex_src_lod
;
484 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
485 tex
->dest_type
= nir_type_uint
;
486 tex
->is_array
= false;
487 tex
->coord_components
= 2;
488 tex
->texture
= nir_deref_var_create(tex
, sampler
);
491 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
492 nir_builder_instr_insert(b
, &tex
->instr
);
494 return &tex
->dest
.ssa
;
499 build_nir_buffer_fetch(struct nir_builder
*b
, struct radv_device
*device
,
500 nir_ssa_def
*tex_pos
)
502 const struct glsl_type
*sampler_type
=
503 glsl_sampler_type(GLSL_SAMPLER_DIM_BUF
, false, false, GLSL_TYPE_UINT
);
504 nir_variable
*sampler
= nir_variable_create(b
->shader
, nir_var_uniform
,
505 sampler_type
, "s_tex");
506 sampler
->data
.descriptor_set
= 0;
507 sampler
->data
.binding
= 0;
509 nir_intrinsic_instr
*width
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_push_constant
);
510 width
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, 0));
511 width
->num_components
= 1;
512 nir_ssa_dest_init(&width
->instr
, &width
->dest
, 1, 32, "width");
513 nir_builder_instr_insert(b
, &width
->instr
);
515 nir_ssa_def
*pos_x
= nir_channel(b
, tex_pos
, 0);
516 nir_ssa_def
*pos_y
= nir_channel(b
, tex_pos
, 1);
517 pos_y
= nir_imul(b
, pos_y
, &width
->dest
.ssa
);
518 pos_x
= nir_iadd(b
, pos_x
, pos_y
);
519 //pos_x = nir_iadd(b, pos_x, nir_imm_int(b, 100000));
521 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, 1);
522 tex
->sampler_dim
= GLSL_SAMPLER_DIM_BUF
;
523 tex
->op
= nir_texop_txf
;
524 tex
->src
[0].src_type
= nir_tex_src_coord
;
525 tex
->src
[0].src
= nir_src_for_ssa(pos_x
);
526 tex
->dest_type
= nir_type_uint
;
527 tex
->is_array
= false;
528 tex
->coord_components
= 1;
529 tex
->texture
= nir_deref_var_create(tex
, sampler
);
532 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
533 nir_builder_instr_insert(b
, &tex
->instr
);
535 return &tex
->dest
.ssa
;
538 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info
= {
539 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
540 .vertexBindingDescriptionCount
= 1,
541 .pVertexBindingDescriptions
= (VkVertexInputBindingDescription
[]) {
544 .stride
= 4 * sizeof(float),
545 .inputRate
= VK_VERTEX_INPUT_RATE_VERTEX
548 .vertexAttributeDescriptionCount
= 2,
549 .pVertexAttributeDescriptions
= (VkVertexInputAttributeDescription
[]) {
554 .format
= VK_FORMAT_R32G32_SFLOAT
,
558 /* Texture Coordinate */
561 .format
= VK_FORMAT_R32G32_SFLOAT
,
568 build_nir_copy_fragment_shader(struct radv_device
*device
,
569 texel_fetch_build_func txf_func
, const char* name
)
571 const struct glsl_type
*vec4
= glsl_vec4_type();
572 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
575 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
576 b
.shader
->info
->name
= ralloc_strdup(b
.shader
, name
);
578 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
580 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
582 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
584 color_out
->data
.location
= FRAG_RESULT_DATA0
;
586 nir_ssa_def
*pos_int
= nir_f2i(&b
, nir_load_var(&b
, tex_pos_in
));
587 unsigned swiz
[4] = { 0, 1 };
588 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
590 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
);
591 nir_store_var(&b
, color_out
, color
, 0xf);
597 build_nir_copy_fragment_shader_depth(struct radv_device
*device
,
598 texel_fetch_build_func txf_func
, const char* name
)
600 const struct glsl_type
*vec4
= glsl_vec4_type();
601 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
604 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
605 b
.shader
->info
->name
= ralloc_strdup(b
.shader
, name
);
607 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
609 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
611 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
613 color_out
->data
.location
= FRAG_RESULT_DEPTH
;
615 nir_ssa_def
*pos_int
= nir_f2i(&b
, nir_load_var(&b
, tex_pos_in
));
616 unsigned swiz
[4] = { 0, 1 };
617 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
619 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
);
620 nir_store_var(&b
, color_out
, color
, 0x1);
626 build_nir_copy_fragment_shader_stencil(struct radv_device
*device
,
627 texel_fetch_build_func txf_func
, const char* name
)
629 const struct glsl_type
*vec4
= glsl_vec4_type();
630 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
633 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
634 b
.shader
->info
->name
= ralloc_strdup(b
.shader
, name
);
636 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
638 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
640 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
642 color_out
->data
.location
= FRAG_RESULT_STENCIL
;
644 nir_ssa_def
*pos_int
= nir_f2i(&b
, nir_load_var(&b
, tex_pos_in
));
645 unsigned swiz
[4] = { 0, 1 };
646 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
648 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
);
649 nir_store_var(&b
, color_out
, color
, 0x1);
655 radv_device_finish_meta_blit2d_state(struct radv_device
*device
)
657 for(unsigned j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
658 if (device
->meta_state
.blit2d
.render_passes
[j
]) {
659 radv_DestroyRenderPass(radv_device_to_handle(device
),
660 device
->meta_state
.blit2d
.render_passes
[j
],
661 &device
->meta_state
.alloc
);
665 radv_DestroyRenderPass(radv_device_to_handle(device
),
666 device
->meta_state
.blit2d
.depth_only_rp
,
667 &device
->meta_state
.alloc
);
668 radv_DestroyRenderPass(radv_device_to_handle(device
),
669 device
->meta_state
.blit2d
.stencil_only_rp
,
670 &device
->meta_state
.alloc
);
672 for (unsigned src
= 0; src
< BLIT2D_NUM_SRC_TYPES
; src
++) {
673 if (device
->meta_state
.blit2d
.p_layouts
[src
]) {
674 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
675 device
->meta_state
.blit2d
.p_layouts
[src
],
676 &device
->meta_state
.alloc
);
679 if (device
->meta_state
.blit2d
.ds_layouts
[src
]) {
680 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
681 device
->meta_state
.blit2d
.ds_layouts
[src
],
682 &device
->meta_state
.alloc
);
685 for (unsigned j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
686 if (device
->meta_state
.blit2d
.pipelines
[src
][j
]) {
687 radv_DestroyPipeline(radv_device_to_handle(device
),
688 device
->meta_state
.blit2d
.pipelines
[src
][j
],
689 &device
->meta_state
.alloc
);
693 radv_DestroyPipeline(radv_device_to_handle(device
),
694 device
->meta_state
.blit2d
.depth_only_pipeline
[src
],
695 &device
->meta_state
.alloc
);
696 radv_DestroyPipeline(radv_device_to_handle(device
),
697 device
->meta_state
.blit2d
.stencil_only_pipeline
[src
],
698 &device
->meta_state
.alloc
);
703 blit2d_init_color_pipeline(struct radv_device
*device
,
704 enum blit2d_src_type src_type
,
708 unsigned fs_key
= radv_format_meta_fs_key(format
);
711 texel_fetch_build_func src_func
;
713 case BLIT2D_SRC_TYPE_IMAGE
:
714 src_func
= build_nir_texel_fetch
;
715 name
= "meta_blit2d_image_fs";
717 case BLIT2D_SRC_TYPE_BUFFER
:
718 src_func
= build_nir_buffer_fetch
;
719 name
= "meta_blit2d_buffer_fs";
722 unreachable("unknown blit src type\n");
726 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
727 struct radv_shader_module fs
= { .nir
= NULL
};
730 fs
.nir
= build_nir_copy_fragment_shader(device
, src_func
, name
);
731 vi_create_info
= &normal_vi_create_info
;
733 struct radv_shader_module vs
= {
734 .nir
= build_nir_vertex_shader(),
737 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
739 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
740 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
741 .module
= radv_shader_module_to_handle(&vs
),
743 .pSpecializationInfo
= NULL
745 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
746 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
747 .module
= radv_shader_module_to_handle(&fs
),
749 .pSpecializationInfo
= NULL
753 if (!device
->meta_state
.blit2d
.render_passes
[fs_key
]) {
754 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
755 &(VkRenderPassCreateInfo
) {
756 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
757 .attachmentCount
= 1,
758 .pAttachments
= &(VkAttachmentDescription
) {
760 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
761 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
762 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
763 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
766 .pSubpasses
= &(VkSubpassDescription
) {
767 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
768 .inputAttachmentCount
= 0,
769 .colorAttachmentCount
= 1,
770 .pColorAttachments
= &(VkAttachmentReference
) {
772 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
774 .pResolveAttachments
= NULL
,
775 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
776 .attachment
= VK_ATTACHMENT_UNUSED
,
777 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
779 .preserveAttachmentCount
= 1,
780 .pPreserveAttachments
= (uint32_t[]) { 0 },
782 .dependencyCount
= 0,
783 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.render_passes
[fs_key
]);
786 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
787 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
788 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
789 .pStages
= pipeline_shader_stages
,
790 .pVertexInputState
= vi_create_info
,
791 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
792 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
793 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
794 .primitiveRestartEnable
= false,
796 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
797 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
801 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
802 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
803 .rasterizerDiscardEnable
= false,
804 .polygonMode
= VK_POLYGON_MODE_FILL
,
805 .cullMode
= VK_CULL_MODE_NONE
,
806 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
808 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
809 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
810 .rasterizationSamples
= 1,
811 .sampleShadingEnable
= false,
812 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
814 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
815 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
816 .attachmentCount
= 1,
817 .pAttachments
= (VkPipelineColorBlendAttachmentState
[]) {
819 VK_COLOR_COMPONENT_A_BIT
|
820 VK_COLOR_COMPONENT_R_BIT
|
821 VK_COLOR_COMPONENT_G_BIT
|
822 VK_COLOR_COMPONENT_B_BIT
},
825 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
826 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
827 .dynamicStateCount
= 7,
828 .pDynamicStates
= (VkDynamicState
[]) {
829 VK_DYNAMIC_STATE_LINE_WIDTH
,
830 VK_DYNAMIC_STATE_DEPTH_BIAS
,
831 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
832 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
833 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
834 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
835 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
839 .layout
= device
->meta_state
.blit2d
.p_layouts
[src_type
],
840 .renderPass
= device
->meta_state
.blit2d
.render_passes
[fs_key
],
844 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
848 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
849 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
850 &vk_pipeline_info
, &radv_pipeline_info
,
851 &device
->meta_state
.alloc
,
852 &device
->meta_state
.blit2d
.pipelines
[src_type
][fs_key
]);
862 blit2d_init_depth_only_pipeline(struct radv_device
*device
,
863 enum blit2d_src_type src_type
)
868 texel_fetch_build_func src_func
;
870 case BLIT2D_SRC_TYPE_IMAGE
:
871 src_func
= build_nir_texel_fetch
;
872 name
= "meta_blit2d_depth_image_fs";
874 case BLIT2D_SRC_TYPE_BUFFER
:
875 src_func
= build_nir_buffer_fetch
;
876 name
= "meta_blit2d_depth_buffer_fs";
879 unreachable("unknown blit src type\n");
883 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
884 struct radv_shader_module fs
= { .nir
= NULL
};
886 fs
.nir
= build_nir_copy_fragment_shader_depth(device
, src_func
, name
);
887 vi_create_info
= &normal_vi_create_info
;
889 struct radv_shader_module vs
= {
890 .nir
= build_nir_vertex_shader(),
893 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
895 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
896 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
897 .module
= radv_shader_module_to_handle(&vs
),
899 .pSpecializationInfo
= NULL
901 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
902 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
903 .module
= radv_shader_module_to_handle(&fs
),
905 .pSpecializationInfo
= NULL
909 if (!device
->meta_state
.blit2d
.depth_only_rp
) {
910 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
911 &(VkRenderPassCreateInfo
) {
912 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
913 .attachmentCount
= 1,
914 .pAttachments
= &(VkAttachmentDescription
) {
916 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
917 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
918 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
919 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
922 .pSubpasses
= &(VkSubpassDescription
) {
923 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
924 .inputAttachmentCount
= 0,
925 .colorAttachmentCount
= 0,
926 .pColorAttachments
= NULL
,
927 .pResolveAttachments
= NULL
,
928 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
930 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
932 .preserveAttachmentCount
= 1,
933 .pPreserveAttachments
= (uint32_t[]) { 0 },
935 .dependencyCount
= 0,
936 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.depth_only_rp
);
939 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
940 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
941 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
942 .pStages
= pipeline_shader_stages
,
943 .pVertexInputState
= vi_create_info
,
944 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
945 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
946 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
947 .primitiveRestartEnable
= false,
949 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
950 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
954 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
955 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
956 .rasterizerDiscardEnable
= false,
957 .polygonMode
= VK_POLYGON_MODE_FILL
,
958 .cullMode
= VK_CULL_MODE_NONE
,
959 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
961 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
962 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
963 .rasterizationSamples
= 1,
964 .sampleShadingEnable
= false,
965 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
967 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
968 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
969 .attachmentCount
= 0,
970 .pAttachments
= NULL
,
972 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
973 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
974 .depthTestEnable
= true,
975 .depthWriteEnable
= true,
976 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
978 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
979 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
980 .dynamicStateCount
= 7,
981 .pDynamicStates
= (VkDynamicState
[]) {
982 VK_DYNAMIC_STATE_LINE_WIDTH
,
983 VK_DYNAMIC_STATE_DEPTH_BIAS
,
984 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
985 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
986 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
987 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
988 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
992 .layout
= device
->meta_state
.blit2d
.p_layouts
[src_type
],
993 .renderPass
= device
->meta_state
.blit2d
.depth_only_rp
,
997 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
1001 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1002 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1003 &vk_pipeline_info
, &radv_pipeline_info
,
1004 &device
->meta_state
.alloc
,
1005 &device
->meta_state
.blit2d
.depth_only_pipeline
[src_type
]);
1008 ralloc_free(vs
.nir
);
1009 ralloc_free(fs
.nir
);
1015 blit2d_init_stencil_only_pipeline(struct radv_device
*device
,
1016 enum blit2d_src_type src_type
)
1021 texel_fetch_build_func src_func
;
1023 case BLIT2D_SRC_TYPE_IMAGE
:
1024 src_func
= build_nir_texel_fetch
;
1025 name
= "meta_blit2d_stencil_image_fs";
1027 case BLIT2D_SRC_TYPE_BUFFER
:
1028 src_func
= build_nir_buffer_fetch
;
1029 name
= "meta_blit2d_stencil_buffer_fs";
1032 unreachable("unknown blit src type\n");
1036 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
1037 struct radv_shader_module fs
= { .nir
= NULL
};
1039 fs
.nir
= build_nir_copy_fragment_shader_stencil(device
, src_func
, name
);
1040 vi_create_info
= &normal_vi_create_info
;
1042 struct radv_shader_module vs
= {
1043 .nir
= build_nir_vertex_shader(),
1046 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
1048 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1049 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
1050 .module
= radv_shader_module_to_handle(&vs
),
1052 .pSpecializationInfo
= NULL
1054 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1055 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1056 .module
= radv_shader_module_to_handle(&fs
),
1058 .pSpecializationInfo
= NULL
1062 if (!device
->meta_state
.blit2d
.stencil_only_rp
) {
1063 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
1064 &(VkRenderPassCreateInfo
) {
1065 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
1066 .attachmentCount
= 1,
1067 .pAttachments
= &(VkAttachmentDescription
) {
1069 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1070 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1071 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
1072 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
1075 .pSubpasses
= &(VkSubpassDescription
) {
1076 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
1077 .inputAttachmentCount
= 0,
1078 .colorAttachmentCount
= 0,
1079 .pColorAttachments
= NULL
,
1080 .pResolveAttachments
= NULL
,
1081 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
1083 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
1085 .preserveAttachmentCount
= 1,
1086 .pPreserveAttachments
= (uint32_t[]) { 0 },
1088 .dependencyCount
= 0,
1089 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.stencil_only_rp
);
1092 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
1093 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
1094 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
1095 .pStages
= pipeline_shader_stages
,
1096 .pVertexInputState
= vi_create_info
,
1097 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
1098 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
1099 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
1100 .primitiveRestartEnable
= false,
1102 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
1103 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
1107 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
1108 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
1109 .rasterizerDiscardEnable
= false,
1110 .polygonMode
= VK_POLYGON_MODE_FILL
,
1111 .cullMode
= VK_CULL_MODE_NONE
,
1112 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
1114 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
1115 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
1116 .rasterizationSamples
= 1,
1117 .sampleShadingEnable
= false,
1118 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
1120 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
1121 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
1122 .attachmentCount
= 0,
1123 .pAttachments
= NULL
,
1125 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
1126 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
1127 .depthTestEnable
= false,
1128 .depthWriteEnable
= false,
1129 .stencilTestEnable
= true,
1131 .failOp
= VK_STENCIL_OP_REPLACE
,
1132 .passOp
= VK_STENCIL_OP_REPLACE
,
1133 .depthFailOp
= VK_STENCIL_OP_REPLACE
,
1134 .compareOp
= VK_COMPARE_OP_ALWAYS
,
1135 .compareMask
= 0xff,
1140 .failOp
= VK_STENCIL_OP_REPLACE
,
1141 .passOp
= VK_STENCIL_OP_REPLACE
,
1142 .depthFailOp
= VK_STENCIL_OP_REPLACE
,
1143 .compareOp
= VK_COMPARE_OP_ALWAYS
,
1144 .compareMask
= 0xff,
1148 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
1150 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
1151 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
1152 .dynamicStateCount
= 4,
1153 .pDynamicStates
= (VkDynamicState
[]) {
1154 VK_DYNAMIC_STATE_LINE_WIDTH
,
1155 VK_DYNAMIC_STATE_DEPTH_BIAS
,
1156 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
1157 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
1161 .layout
= device
->meta_state
.blit2d
.p_layouts
[src_type
],
1162 .renderPass
= device
->meta_state
.blit2d
.stencil_only_rp
,
1166 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
1167 .use_rectlist
= true
1170 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1171 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1172 &vk_pipeline_info
, &radv_pipeline_info
,
1173 &device
->meta_state
.alloc
,
1174 &device
->meta_state
.blit2d
.stencil_only_pipeline
[src_type
]);
1177 ralloc_free(vs
.nir
);
1178 ralloc_free(fs
.nir
);
1183 static VkFormat pipeline_formats
[] = {
1184 VK_FORMAT_R8G8B8A8_UNORM
,
1185 VK_FORMAT_R8G8B8A8_UINT
,
1186 VK_FORMAT_R8G8B8A8_SINT
,
1187 VK_FORMAT_R16G16B16A16_UNORM
,
1188 VK_FORMAT_R16G16B16A16_SNORM
,
1189 VK_FORMAT_R16G16B16A16_UINT
,
1190 VK_FORMAT_R16G16B16A16_SINT
,
1191 VK_FORMAT_R32_SFLOAT
,
1192 VK_FORMAT_R32G32_SFLOAT
,
1193 VK_FORMAT_R32G32B32A32_SFLOAT
1197 radv_device_init_meta_blit2d_state(struct radv_device
*device
)
1201 zero(device
->meta_state
.blit2d
);
1203 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
1204 &(VkDescriptorSetLayoutCreateInfo
) {
1205 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
1207 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
1210 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
1211 .descriptorCount
= 1,
1212 .stageFlags
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1213 .pImmutableSamplers
= NULL
1216 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.ds_layouts
[BLIT2D_SRC_TYPE_IMAGE
]);
1217 if (result
!= VK_SUCCESS
)
1220 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1221 &(VkPipelineLayoutCreateInfo
) {
1222 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1223 .setLayoutCount
= 1,
1224 .pSetLayouts
= &device
->meta_state
.blit2d
.ds_layouts
[BLIT2D_SRC_TYPE_IMAGE
],
1226 &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.p_layouts
[BLIT2D_SRC_TYPE_IMAGE
]);
1227 if (result
!= VK_SUCCESS
)
1230 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
1231 &(VkDescriptorSetLayoutCreateInfo
) {
1232 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
1234 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
1237 .descriptorType
= VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
,
1238 .descriptorCount
= 1,
1239 .stageFlags
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1240 .pImmutableSamplers
= NULL
1243 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.ds_layouts
[BLIT2D_SRC_TYPE_BUFFER
]);
1244 if (result
!= VK_SUCCESS
)
1247 const VkPushConstantRange push_constant_range
= {VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 4};
1248 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1249 &(VkPipelineLayoutCreateInfo
) {
1250 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1251 .setLayoutCount
= 1,
1252 .pSetLayouts
= &device
->meta_state
.blit2d
.ds_layouts
[BLIT2D_SRC_TYPE_BUFFER
],
1253 .pushConstantRangeCount
= 1,
1254 .pPushConstantRanges
= &push_constant_range
,
1256 &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.p_layouts
[BLIT2D_SRC_TYPE_BUFFER
]);
1257 if (result
!= VK_SUCCESS
)
1260 for (unsigned src
= 0; src
< BLIT2D_NUM_SRC_TYPES
; src
++) {
1261 for (unsigned j
= 0; j
< ARRAY_SIZE(pipeline_formats
); ++j
) {
1262 result
= blit2d_init_color_pipeline(device
, src
, pipeline_formats
[j
]);
1263 if (result
!= VK_SUCCESS
)
1267 result
= blit2d_init_depth_only_pipeline(device
, src
);
1268 if (result
!= VK_SUCCESS
)
1271 result
= blit2d_init_stencil_only_pipeline(device
, src
);
1272 if (result
!= VK_SUCCESS
)
1279 radv_device_finish_meta_blit2d_state(device
);