2 * Copyright © 2016 Red Hat
5 * Copyright © 2016 Intel Corporation
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "radv_meta.h"
28 #include "nir/nir_builder.h"
29 #include "vk_format.h"
31 enum blit2d_dst_type
{
32 /* We can bind this destination as a "normal" render target and render
33 * to it just like you would anywhere else.
35 BLIT2D_DST_TYPE_NORMAL
,
37 /* The destination has a 3-channel RGB format. Since we can't render to
38 * non-power-of-two textures, we have to bind it as a red texture and
39 * select the correct component for the given red pixel in the shader.
47 enum blit2d_src_type
{
48 BLIT2D_SRC_TYPE_IMAGE
,
49 BLIT2D_SRC_TYPE_BUFFER
,
54 create_iview(struct radv_cmd_buffer
*cmd_buffer
,
55 struct radv_meta_blit2d_surf
*surf
,
56 struct radv_image_view
*iview
, VkFormat depth_format
)
61 format
= depth_format
;
63 format
= surf
->format
;
65 radv_image_view_init(iview
, cmd_buffer
->device
,
66 &(VkImageViewCreateInfo
) {
67 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
68 .image
= radv_image_to_handle(surf
->image
),
69 .viewType
= VK_IMAGE_VIEW_TYPE_2D
,
72 .aspectMask
= surf
->aspect_mask
,
73 .baseMipLevel
= surf
->level
,
75 .baseArrayLayer
= surf
->layer
,
82 create_bview(struct radv_cmd_buffer
*cmd_buffer
,
83 struct radv_meta_blit2d_buffer
*src
,
84 struct radv_buffer_view
*bview
, VkFormat depth_format
)
89 format
= depth_format
;
92 radv_buffer_view_init(bview
, cmd_buffer
->device
,
93 &(VkBufferViewCreateInfo
) {
94 .sType
= VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO
,
96 .buffer
= radv_buffer_to_handle(src
->buffer
),
98 .offset
= src
->offset
,
99 .range
= VK_WHOLE_SIZE
,
104 struct blit2d_src_temps
{
105 struct radv_image_view iview
;
106 struct radv_buffer_view bview
;
110 blit2d_bind_src(struct radv_cmd_buffer
*cmd_buffer
,
111 struct radv_meta_blit2d_surf
*src_img
,
112 struct radv_meta_blit2d_buffer
*src_buf
,
113 struct blit2d_src_temps
*tmp
,
114 enum blit2d_src_type src_type
, VkFormat depth_format
)
116 struct radv_device
*device
= cmd_buffer
->device
;
118 if (src_type
== BLIT2D_SRC_TYPE_BUFFER
) {
119 create_bview(cmd_buffer
, src_buf
, &tmp
->bview
, depth_format
);
121 radv_meta_push_descriptor_set(cmd_buffer
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
122 device
->meta_state
.blit2d
.p_layouts
[src_type
],
124 1, /* descriptorWriteCount */
125 (VkWriteDescriptorSet
[]) {
127 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
129 .dstArrayElement
= 0,
130 .descriptorCount
= 1,
131 .descriptorType
= VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
,
132 .pTexelBufferView
= (VkBufferView
[]) { radv_buffer_view_to_handle(&tmp
->bview
) }
136 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
137 device
->meta_state
.blit2d
.p_layouts
[src_type
],
138 VK_SHADER_STAGE_FRAGMENT_BIT
, 16, 4,
141 create_iview(cmd_buffer
, src_img
, &tmp
->iview
, depth_format
);
143 radv_meta_push_descriptor_set(cmd_buffer
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
144 device
->meta_state
.blit2d
.p_layouts
[src_type
],
146 1, /* descriptorWriteCount */
147 (VkWriteDescriptorSet
[]) {
149 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
151 .dstArrayElement
= 0,
152 .descriptorCount
= 1,
153 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
154 .pImageInfo
= (VkDescriptorImageInfo
[]) {
156 .sampler
= VK_NULL_HANDLE
,
157 .imageView
= radv_image_view_to_handle(&tmp
->iview
),
158 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
166 struct blit2d_dst_temps
{
168 struct radv_image_view iview
;
173 blit2d_bind_dst(struct radv_cmd_buffer
*cmd_buffer
,
174 struct radv_meta_blit2d_surf
*dst
,
177 VkFormat depth_format
,
178 struct blit2d_dst_temps
*tmp
)
180 create_iview(cmd_buffer
, dst
, &tmp
->iview
, depth_format
);
182 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer
->device
),
183 &(VkFramebufferCreateInfo
) {
184 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
185 .attachmentCount
= 1,
186 .pAttachments
= (VkImageView
[]) {
187 radv_image_view_to_handle(&tmp
->iview
),
192 }, &cmd_buffer
->pool
->alloc
, &tmp
->fb
);
196 blit2d_unbind_dst(struct radv_cmd_buffer
*cmd_buffer
,
197 struct blit2d_dst_temps
*tmp
)
199 VkDevice vk_device
= radv_device_to_handle(cmd_buffer
->device
);
200 radv_DestroyFramebuffer(vk_device
, tmp
->fb
, &cmd_buffer
->pool
->alloc
);
204 bind_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
205 enum blit2d_src_type src_type
, unsigned fs_key
)
207 VkPipeline pipeline
=
208 cmd_buffer
->device
->meta_state
.blit2d
.pipelines
[src_type
][fs_key
];
210 if (cmd_buffer
->state
.pipeline
!= radv_pipeline_from_handle(pipeline
)) {
211 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
212 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
217 bind_depth_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
218 enum blit2d_src_type src_type
)
220 VkPipeline pipeline
=
221 cmd_buffer
->device
->meta_state
.blit2d
.depth_only_pipeline
[src_type
];
223 if (cmd_buffer
->state
.pipeline
!= radv_pipeline_from_handle(pipeline
)) {
224 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
225 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
230 bind_stencil_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
231 enum blit2d_src_type src_type
)
233 VkPipeline pipeline
=
234 cmd_buffer
->device
->meta_state
.blit2d
.stencil_only_pipeline
[src_type
];
236 if (cmd_buffer
->state
.pipeline
!= radv_pipeline_from_handle(pipeline
)) {
237 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
238 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
243 radv_meta_blit2d_normal_dst(struct radv_cmd_buffer
*cmd_buffer
,
244 struct radv_meta_blit2d_surf
*src_img
,
245 struct radv_meta_blit2d_buffer
*src_buf
,
246 struct radv_meta_blit2d_surf
*dst
,
248 struct radv_meta_blit2d_rect
*rects
, enum blit2d_src_type src_type
)
250 struct radv_device
*device
= cmd_buffer
->device
;
252 for (unsigned r
= 0; r
< num_rects
; ++r
) {
253 VkFormat depth_format
= 0;
254 if (dst
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
)
255 depth_format
= vk_format_stencil_only(dst
->image
->vk_format
);
256 else if (dst
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
)
257 depth_format
= vk_format_depth_only(dst
->image
->vk_format
);
258 struct blit2d_src_temps src_temps
;
259 blit2d_bind_src(cmd_buffer
, src_img
, src_buf
, &src_temps
, src_type
, depth_format
);
261 struct blit2d_dst_temps dst_temps
;
262 blit2d_bind_dst(cmd_buffer
, dst
, rects
[r
].dst_x
+ rects
[r
].width
,
263 rects
[r
].dst_y
+ rects
[r
].height
, depth_format
, &dst_temps
);
265 float vertex_push_constants
[4] = {
268 rects
[r
].src_x
+ rects
[r
].width
,
269 rects
[r
].src_y
+ rects
[r
].height
,
272 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
273 device
->meta_state
.blit2d
.p_layouts
[src_type
],
274 VK_SHADER_STAGE_VERTEX_BIT
, 0, 16,
275 vertex_push_constants
);
277 if (dst
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
) {
278 unsigned fs_key
= radv_format_meta_fs_key(dst_temps
.iview
.vk_format
);
280 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
281 &(VkRenderPassBeginInfo
) {
282 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
283 .renderPass
= device
->meta_state
.blit2d
.render_passes
[fs_key
],
284 .framebuffer
= dst_temps
.fb
,
286 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
287 .extent
= { rects
[r
].width
, rects
[r
].height
},
289 .clearValueCount
= 0,
290 .pClearValues
= NULL
,
291 }, VK_SUBPASS_CONTENTS_INLINE
);
294 bind_pipeline(cmd_buffer
, src_type
, fs_key
);
295 } else if (dst
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
296 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
297 &(VkRenderPassBeginInfo
) {
298 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
299 .renderPass
= device
->meta_state
.blit2d
.depth_only_rp
,
300 .framebuffer
= dst_temps
.fb
,
302 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
303 .extent
= { rects
[r
].width
, rects
[r
].height
},
305 .clearValueCount
= 0,
306 .pClearValues
= NULL
,
307 }, VK_SUBPASS_CONTENTS_INLINE
);
310 bind_depth_pipeline(cmd_buffer
, src_type
);
312 } else if (dst
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
313 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
314 &(VkRenderPassBeginInfo
) {
315 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
316 .renderPass
= device
->meta_state
.blit2d
.stencil_only_rp
,
317 .framebuffer
= dst_temps
.fb
,
319 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
320 .extent
= { rects
[r
].width
, rects
[r
].height
},
322 .clearValueCount
= 0,
323 .pClearValues
= NULL
,
324 }, VK_SUBPASS_CONTENTS_INLINE
);
327 bind_stencil_pipeline(cmd_buffer
, src_type
);
330 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
333 .width
= rects
[r
].width
,
334 .height
= rects
[r
].height
,
339 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkRect2D
) {
340 .offset
= (VkOffset2D
) { rects
[r
].dst_x
, rects
[r
].dst_y
},
341 .extent
= (VkExtent2D
) { rects
[r
].width
, rects
[r
].height
},
346 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer
), 3, 1, 0, 0);
347 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
));
349 /* At the point where we emit the draw call, all data from the
350 * descriptor sets, etc. has been used. We are free to delete it.
352 blit2d_unbind_dst(cmd_buffer
, &dst_temps
);
357 radv_meta_blit2d(struct radv_cmd_buffer
*cmd_buffer
,
358 struct radv_meta_blit2d_surf
*src_img
,
359 struct radv_meta_blit2d_buffer
*src_buf
,
360 struct radv_meta_blit2d_surf
*dst
,
362 struct radv_meta_blit2d_rect
*rects
)
364 enum blit2d_src_type src_type
= src_buf
? BLIT2D_SRC_TYPE_BUFFER
:
365 BLIT2D_SRC_TYPE_IMAGE
;
366 radv_meta_blit2d_normal_dst(cmd_buffer
, src_img
, src_buf
, dst
,
367 num_rects
, rects
, src_type
);
371 build_nir_vertex_shader(void)
373 const struct glsl_type
*vec4
= glsl_vec4_type();
374 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
377 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
378 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "meta_blit2d_vs");
380 nir_variable
*pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
381 vec4
, "gl_Position");
382 pos_out
->data
.location
= VARYING_SLOT_POS
;
384 nir_variable
*tex_pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
386 tex_pos_out
->data
.location
= VARYING_SLOT_VAR0
;
387 tex_pos_out
->data
.interpolation
= INTERP_MODE_SMOOTH
;
389 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices(&b
);
390 nir_store_var(&b
, pos_out
, outvec
, 0xf);
392 nir_intrinsic_instr
*src_box
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
393 src_box
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
394 nir_intrinsic_set_base(src_box
, 0);
395 nir_intrinsic_set_range(src_box
, 16);
396 src_box
->num_components
= 4;
397 nir_ssa_dest_init(&src_box
->instr
, &src_box
->dest
, 4, 32, "src_box");
398 nir_builder_instr_insert(&b
, &src_box
->instr
);
400 nir_intrinsic_instr
*vertex_id
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_vertex_id_zero_base
);
401 nir_ssa_dest_init(&vertex_id
->instr
, &vertex_id
->dest
, 1, 32, "vertexid");
402 nir_builder_instr_insert(&b
, &vertex_id
->instr
);
404 /* vertex 0 - src_x, src_y */
405 /* vertex 1 - src_x, src_y+h */
406 /* vertex 2 - src_x+w, src_y */
407 /* so channel 0 is vertex_id != 2 ? src_x : src_x + w
408 channel 1 is vertex id != 1 ? src_y : src_y + w */
410 nir_ssa_def
*c0cmp
= nir_ine(&b
, &vertex_id
->dest
.ssa
,
412 nir_ssa_def
*c1cmp
= nir_ine(&b
, &vertex_id
->dest
.ssa
,
415 nir_ssa_def
*comp
[2];
416 comp
[0] = nir_bcsel(&b
, c0cmp
,
417 nir_channel(&b
, &src_box
->dest
.ssa
, 0),
418 nir_channel(&b
, &src_box
->dest
.ssa
, 2));
420 comp
[1] = nir_bcsel(&b
, c1cmp
,
421 nir_channel(&b
, &src_box
->dest
.ssa
, 1),
422 nir_channel(&b
, &src_box
->dest
.ssa
, 3));
423 nir_ssa_def
*out_tex_vec
= nir_vec(&b
, comp
, 2);
424 nir_store_var(&b
, tex_pos_out
, out_tex_vec
, 0x3);
428 typedef nir_ssa_def
* (*texel_fetch_build_func
)(struct nir_builder
*,
429 struct radv_device
*,
433 build_nir_texel_fetch(struct nir_builder
*b
, struct radv_device
*device
,
434 nir_ssa_def
*tex_pos
)
436 const struct glsl_type
*sampler_type
=
437 glsl_sampler_type(GLSL_SAMPLER_DIM_2D
, false, false, GLSL_TYPE_UINT
);
438 nir_variable
*sampler
= nir_variable_create(b
->shader
, nir_var_uniform
,
439 sampler_type
, "s_tex");
440 sampler
->data
.descriptor_set
= 0;
441 sampler
->data
.binding
= 0;
443 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, 2);
444 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
445 tex
->op
= nir_texop_txf
;
446 tex
->src
[0].src_type
= nir_tex_src_coord
;
447 tex
->src
[0].src
= nir_src_for_ssa(tex_pos
);
448 tex
->src
[1].src_type
= nir_tex_src_lod
;
449 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
450 tex
->dest_type
= nir_type_uint
;
451 tex
->is_array
= false;
452 tex
->coord_components
= 2;
453 tex
->texture
= nir_deref_var_create(tex
, sampler
);
456 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
457 nir_builder_instr_insert(b
, &tex
->instr
);
459 return &tex
->dest
.ssa
;
464 build_nir_buffer_fetch(struct nir_builder
*b
, struct radv_device
*device
,
465 nir_ssa_def
*tex_pos
)
467 const struct glsl_type
*sampler_type
=
468 glsl_sampler_type(GLSL_SAMPLER_DIM_BUF
, false, false, GLSL_TYPE_UINT
);
469 nir_variable
*sampler
= nir_variable_create(b
->shader
, nir_var_uniform
,
470 sampler_type
, "s_tex");
471 sampler
->data
.descriptor_set
= 0;
472 sampler
->data
.binding
= 0;
474 nir_intrinsic_instr
*width
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_push_constant
);
475 nir_intrinsic_set_base(width
, 16);
476 nir_intrinsic_set_range(width
, 4);
477 width
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, 0));
478 width
->num_components
= 1;
479 nir_ssa_dest_init(&width
->instr
, &width
->dest
, 1, 32, "width");
480 nir_builder_instr_insert(b
, &width
->instr
);
482 nir_ssa_def
*pos_x
= nir_channel(b
, tex_pos
, 0);
483 nir_ssa_def
*pos_y
= nir_channel(b
, tex_pos
, 1);
484 pos_y
= nir_imul(b
, pos_y
, &width
->dest
.ssa
);
485 pos_x
= nir_iadd(b
, pos_x
, pos_y
);
486 //pos_x = nir_iadd(b, pos_x, nir_imm_int(b, 100000));
488 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, 1);
489 tex
->sampler_dim
= GLSL_SAMPLER_DIM_BUF
;
490 tex
->op
= nir_texop_txf
;
491 tex
->src
[0].src_type
= nir_tex_src_coord
;
492 tex
->src
[0].src
= nir_src_for_ssa(pos_x
);
493 tex
->dest_type
= nir_type_uint
;
494 tex
->is_array
= false;
495 tex
->coord_components
= 1;
496 tex
->texture
= nir_deref_var_create(tex
, sampler
);
499 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
500 nir_builder_instr_insert(b
, &tex
->instr
);
502 return &tex
->dest
.ssa
;
505 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info
= {
506 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
507 .vertexBindingDescriptionCount
= 0,
508 .vertexAttributeDescriptionCount
= 0,
512 build_nir_copy_fragment_shader(struct radv_device
*device
,
513 texel_fetch_build_func txf_func
, const char* name
)
515 const struct glsl_type
*vec4
= glsl_vec4_type();
516 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
519 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
520 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, name
);
522 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
524 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
526 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
528 color_out
->data
.location
= FRAG_RESULT_DATA0
;
530 nir_ssa_def
*pos_int
= nir_f2i32(&b
, nir_load_var(&b
, tex_pos_in
));
531 unsigned swiz
[4] = { 0, 1 };
532 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
534 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
);
535 nir_store_var(&b
, color_out
, color
, 0xf);
541 build_nir_copy_fragment_shader_depth(struct radv_device
*device
,
542 texel_fetch_build_func txf_func
, const char* name
)
544 const struct glsl_type
*vec4
= glsl_vec4_type();
545 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
548 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
549 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, name
);
551 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
553 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
555 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
557 color_out
->data
.location
= FRAG_RESULT_DEPTH
;
559 nir_ssa_def
*pos_int
= nir_f2i32(&b
, nir_load_var(&b
, tex_pos_in
));
560 unsigned swiz
[4] = { 0, 1 };
561 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
563 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
);
564 nir_store_var(&b
, color_out
, color
, 0x1);
570 build_nir_copy_fragment_shader_stencil(struct radv_device
*device
,
571 texel_fetch_build_func txf_func
, const char* name
)
573 const struct glsl_type
*vec4
= glsl_vec4_type();
574 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
577 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
578 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, name
);
580 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
582 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
584 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
586 color_out
->data
.location
= FRAG_RESULT_STENCIL
;
588 nir_ssa_def
*pos_int
= nir_f2i32(&b
, nir_load_var(&b
, tex_pos_in
));
589 unsigned swiz
[4] = { 0, 1 };
590 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
592 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
);
593 nir_store_var(&b
, color_out
, color
, 0x1);
599 radv_device_finish_meta_blit2d_state(struct radv_device
*device
)
601 for(unsigned j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
602 if (device
->meta_state
.blit2d
.render_passes
[j
]) {
603 radv_DestroyRenderPass(radv_device_to_handle(device
),
604 device
->meta_state
.blit2d
.render_passes
[j
],
605 &device
->meta_state
.alloc
);
609 radv_DestroyRenderPass(radv_device_to_handle(device
),
610 device
->meta_state
.blit2d
.depth_only_rp
,
611 &device
->meta_state
.alloc
);
612 radv_DestroyRenderPass(radv_device_to_handle(device
),
613 device
->meta_state
.blit2d
.stencil_only_rp
,
614 &device
->meta_state
.alloc
);
616 for (unsigned src
= 0; src
< BLIT2D_NUM_SRC_TYPES
; src
++) {
617 if (device
->meta_state
.blit2d
.p_layouts
[src
]) {
618 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
619 device
->meta_state
.blit2d
.p_layouts
[src
],
620 &device
->meta_state
.alloc
);
623 if (device
->meta_state
.blit2d
.ds_layouts
[src
]) {
624 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
625 device
->meta_state
.blit2d
.ds_layouts
[src
],
626 &device
->meta_state
.alloc
);
629 for (unsigned j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
630 if (device
->meta_state
.blit2d
.pipelines
[src
][j
]) {
631 radv_DestroyPipeline(radv_device_to_handle(device
),
632 device
->meta_state
.blit2d
.pipelines
[src
][j
],
633 &device
->meta_state
.alloc
);
637 radv_DestroyPipeline(radv_device_to_handle(device
),
638 device
->meta_state
.blit2d
.depth_only_pipeline
[src
],
639 &device
->meta_state
.alloc
);
640 radv_DestroyPipeline(radv_device_to_handle(device
),
641 device
->meta_state
.blit2d
.stencil_only_pipeline
[src
],
642 &device
->meta_state
.alloc
);
647 blit2d_init_color_pipeline(struct radv_device
*device
,
648 enum blit2d_src_type src_type
,
652 unsigned fs_key
= radv_format_meta_fs_key(format
);
655 texel_fetch_build_func src_func
;
657 case BLIT2D_SRC_TYPE_IMAGE
:
658 src_func
= build_nir_texel_fetch
;
659 name
= "meta_blit2d_image_fs";
661 case BLIT2D_SRC_TYPE_BUFFER
:
662 src_func
= build_nir_buffer_fetch
;
663 name
= "meta_blit2d_buffer_fs";
666 unreachable("unknown blit src type\n");
670 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
671 struct radv_shader_module fs
= { .nir
= NULL
};
674 fs
.nir
= build_nir_copy_fragment_shader(device
, src_func
, name
);
675 vi_create_info
= &normal_vi_create_info
;
677 struct radv_shader_module vs
= {
678 .nir
= build_nir_vertex_shader(),
681 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
683 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
684 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
685 .module
= radv_shader_module_to_handle(&vs
),
687 .pSpecializationInfo
= NULL
689 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
690 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
691 .module
= radv_shader_module_to_handle(&fs
),
693 .pSpecializationInfo
= NULL
697 if (!device
->meta_state
.blit2d
.render_passes
[fs_key
]) {
698 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
699 &(VkRenderPassCreateInfo
) {
700 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
701 .attachmentCount
= 1,
702 .pAttachments
= &(VkAttachmentDescription
) {
704 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
705 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
706 .initialLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
707 .finalLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
710 .pSubpasses
= &(VkSubpassDescription
) {
711 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
712 .inputAttachmentCount
= 0,
713 .colorAttachmentCount
= 1,
714 .pColorAttachments
= &(VkAttachmentReference
) {
716 .layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
718 .pResolveAttachments
= NULL
,
719 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
720 .attachment
= VK_ATTACHMENT_UNUSED
,
721 .layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
723 .preserveAttachmentCount
= 1,
724 .pPreserveAttachments
= (uint32_t[]) { 0 },
726 .dependencyCount
= 0,
727 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.render_passes
[fs_key
]);
730 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
731 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
732 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
733 .pStages
= pipeline_shader_stages
,
734 .pVertexInputState
= vi_create_info
,
735 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
736 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
737 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
738 .primitiveRestartEnable
= false,
740 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
741 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
745 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
746 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
747 .rasterizerDiscardEnable
= false,
748 .polygonMode
= VK_POLYGON_MODE_FILL
,
749 .cullMode
= VK_CULL_MODE_NONE
,
750 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
752 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
753 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
754 .rasterizationSamples
= 1,
755 .sampleShadingEnable
= false,
756 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
758 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
759 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
760 .attachmentCount
= 1,
761 .pAttachments
= (VkPipelineColorBlendAttachmentState
[]) {
763 VK_COLOR_COMPONENT_A_BIT
|
764 VK_COLOR_COMPONENT_R_BIT
|
765 VK_COLOR_COMPONENT_G_BIT
|
766 VK_COLOR_COMPONENT_B_BIT
},
769 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
770 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
771 .dynamicStateCount
= 9,
772 .pDynamicStates
= (VkDynamicState
[]) {
773 VK_DYNAMIC_STATE_VIEWPORT
,
774 VK_DYNAMIC_STATE_SCISSOR
,
775 VK_DYNAMIC_STATE_LINE_WIDTH
,
776 VK_DYNAMIC_STATE_DEPTH_BIAS
,
777 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
778 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
779 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
780 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
781 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
785 .layout
= device
->meta_state
.blit2d
.p_layouts
[src_type
],
786 .renderPass
= device
->meta_state
.blit2d
.render_passes
[fs_key
],
790 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
794 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
795 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
796 &vk_pipeline_info
, &radv_pipeline_info
,
797 &device
->meta_state
.alloc
,
798 &device
->meta_state
.blit2d
.pipelines
[src_type
][fs_key
]);
808 blit2d_init_depth_only_pipeline(struct radv_device
*device
,
809 enum blit2d_src_type src_type
)
814 texel_fetch_build_func src_func
;
816 case BLIT2D_SRC_TYPE_IMAGE
:
817 src_func
= build_nir_texel_fetch
;
818 name
= "meta_blit2d_depth_image_fs";
820 case BLIT2D_SRC_TYPE_BUFFER
:
821 src_func
= build_nir_buffer_fetch
;
822 name
= "meta_blit2d_depth_buffer_fs";
825 unreachable("unknown blit src type\n");
829 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
830 struct radv_shader_module fs
= { .nir
= NULL
};
832 fs
.nir
= build_nir_copy_fragment_shader_depth(device
, src_func
, name
);
833 vi_create_info
= &normal_vi_create_info
;
835 struct radv_shader_module vs
= {
836 .nir
= build_nir_vertex_shader(),
839 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
841 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
842 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
843 .module
= radv_shader_module_to_handle(&vs
),
845 .pSpecializationInfo
= NULL
847 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
848 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
849 .module
= radv_shader_module_to_handle(&fs
),
851 .pSpecializationInfo
= NULL
855 if (!device
->meta_state
.blit2d
.depth_only_rp
) {
856 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
857 &(VkRenderPassCreateInfo
) {
858 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
859 .attachmentCount
= 1,
860 .pAttachments
= &(VkAttachmentDescription
) {
861 .format
= VK_FORMAT_D32_SFLOAT
,
862 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
863 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
864 .initialLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
865 .finalLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
868 .pSubpasses
= &(VkSubpassDescription
) {
869 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
870 .inputAttachmentCount
= 0,
871 .colorAttachmentCount
= 0,
872 .pColorAttachments
= NULL
,
873 .pResolveAttachments
= NULL
,
874 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
876 .layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
878 .preserveAttachmentCount
= 1,
879 .pPreserveAttachments
= (uint32_t[]) { 0 },
881 .dependencyCount
= 0,
882 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.depth_only_rp
);
885 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
886 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
887 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
888 .pStages
= pipeline_shader_stages
,
889 .pVertexInputState
= vi_create_info
,
890 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
891 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
892 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
893 .primitiveRestartEnable
= false,
895 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
896 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
900 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
901 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
902 .rasterizerDiscardEnable
= false,
903 .polygonMode
= VK_POLYGON_MODE_FILL
,
904 .cullMode
= VK_CULL_MODE_NONE
,
905 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
907 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
908 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
909 .rasterizationSamples
= 1,
910 .sampleShadingEnable
= false,
911 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
913 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
914 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
915 .attachmentCount
= 0,
916 .pAttachments
= NULL
,
918 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
919 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
920 .depthTestEnable
= true,
921 .depthWriteEnable
= true,
922 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
924 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
925 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
926 .dynamicStateCount
= 9,
927 .pDynamicStates
= (VkDynamicState
[]) {
928 VK_DYNAMIC_STATE_VIEWPORT
,
929 VK_DYNAMIC_STATE_SCISSOR
,
930 VK_DYNAMIC_STATE_LINE_WIDTH
,
931 VK_DYNAMIC_STATE_DEPTH_BIAS
,
932 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
933 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
934 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
935 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
936 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
940 .layout
= device
->meta_state
.blit2d
.p_layouts
[src_type
],
941 .renderPass
= device
->meta_state
.blit2d
.depth_only_rp
,
945 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
949 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
950 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
951 &vk_pipeline_info
, &radv_pipeline_info
,
952 &device
->meta_state
.alloc
,
953 &device
->meta_state
.blit2d
.depth_only_pipeline
[src_type
]);
963 blit2d_init_stencil_only_pipeline(struct radv_device
*device
,
964 enum blit2d_src_type src_type
)
969 texel_fetch_build_func src_func
;
971 case BLIT2D_SRC_TYPE_IMAGE
:
972 src_func
= build_nir_texel_fetch
;
973 name
= "meta_blit2d_stencil_image_fs";
975 case BLIT2D_SRC_TYPE_BUFFER
:
976 src_func
= build_nir_buffer_fetch
;
977 name
= "meta_blit2d_stencil_buffer_fs";
980 unreachable("unknown blit src type\n");
984 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
985 struct radv_shader_module fs
= { .nir
= NULL
};
987 fs
.nir
= build_nir_copy_fragment_shader_stencil(device
, src_func
, name
);
988 vi_create_info
= &normal_vi_create_info
;
990 struct radv_shader_module vs
= {
991 .nir
= build_nir_vertex_shader(),
994 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
996 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
997 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
998 .module
= radv_shader_module_to_handle(&vs
),
1000 .pSpecializationInfo
= NULL
1002 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1003 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1004 .module
= radv_shader_module_to_handle(&fs
),
1006 .pSpecializationInfo
= NULL
1010 if (!device
->meta_state
.blit2d
.stencil_only_rp
) {
1011 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
1012 &(VkRenderPassCreateInfo
) {
1013 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
1014 .attachmentCount
= 1,
1015 .pAttachments
= &(VkAttachmentDescription
) {
1016 .format
= VK_FORMAT_S8_UINT
,
1017 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1018 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1019 .initialLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
1020 .finalLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
1023 .pSubpasses
= &(VkSubpassDescription
) {
1024 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
1025 .inputAttachmentCount
= 0,
1026 .colorAttachmentCount
= 0,
1027 .pColorAttachments
= NULL
,
1028 .pResolveAttachments
= NULL
,
1029 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
1031 .layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
1033 .preserveAttachmentCount
= 1,
1034 .pPreserveAttachments
= (uint32_t[]) { 0 },
1036 .dependencyCount
= 0,
1037 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.stencil_only_rp
);
1040 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
1041 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
1042 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
1043 .pStages
= pipeline_shader_stages
,
1044 .pVertexInputState
= vi_create_info
,
1045 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
1046 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
1047 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
1048 .primitiveRestartEnable
= false,
1050 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
1051 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
1055 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
1056 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
1057 .rasterizerDiscardEnable
= false,
1058 .polygonMode
= VK_POLYGON_MODE_FILL
,
1059 .cullMode
= VK_CULL_MODE_NONE
,
1060 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
1062 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
1063 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
1064 .rasterizationSamples
= 1,
1065 .sampleShadingEnable
= false,
1066 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
1068 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
1069 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
1070 .attachmentCount
= 0,
1071 .pAttachments
= NULL
,
1073 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
1074 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
1075 .depthTestEnable
= false,
1076 .depthWriteEnable
= false,
1077 .stencilTestEnable
= true,
1079 .failOp
= VK_STENCIL_OP_REPLACE
,
1080 .passOp
= VK_STENCIL_OP_REPLACE
,
1081 .depthFailOp
= VK_STENCIL_OP_REPLACE
,
1082 .compareOp
= VK_COMPARE_OP_ALWAYS
,
1083 .compareMask
= 0xff,
1088 .failOp
= VK_STENCIL_OP_REPLACE
,
1089 .passOp
= VK_STENCIL_OP_REPLACE
,
1090 .depthFailOp
= VK_STENCIL_OP_REPLACE
,
1091 .compareOp
= VK_COMPARE_OP_ALWAYS
,
1092 .compareMask
= 0xff,
1096 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
1098 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
1099 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
1100 .dynamicStateCount
= 6,
1101 .pDynamicStates
= (VkDynamicState
[]) {
1102 VK_DYNAMIC_STATE_VIEWPORT
,
1103 VK_DYNAMIC_STATE_SCISSOR
,
1104 VK_DYNAMIC_STATE_LINE_WIDTH
,
1105 VK_DYNAMIC_STATE_DEPTH_BIAS
,
1106 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
1107 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
1111 .layout
= device
->meta_state
.blit2d
.p_layouts
[src_type
],
1112 .renderPass
= device
->meta_state
.blit2d
.stencil_only_rp
,
1116 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
1117 .use_rectlist
= true
1120 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1121 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1122 &vk_pipeline_info
, &radv_pipeline_info
,
1123 &device
->meta_state
.alloc
,
1124 &device
->meta_state
.blit2d
.stencil_only_pipeline
[src_type
]);
1127 ralloc_free(vs
.nir
);
1128 ralloc_free(fs
.nir
);
1133 static VkFormat pipeline_formats
[] = {
1134 VK_FORMAT_R8G8B8A8_UNORM
,
1135 VK_FORMAT_R8G8B8A8_UINT
,
1136 VK_FORMAT_R8G8B8A8_SINT
,
1137 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
1138 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
1139 VK_FORMAT_R16G16B16A16_UNORM
,
1140 VK_FORMAT_R16G16B16A16_SNORM
,
1141 VK_FORMAT_R16G16B16A16_UINT
,
1142 VK_FORMAT_R16G16B16A16_SINT
,
1143 VK_FORMAT_R32_SFLOAT
,
1144 VK_FORMAT_R32G32_SFLOAT
,
1145 VK_FORMAT_R32G32B32A32_SFLOAT
1149 radv_device_init_meta_blit2d_state(struct radv_device
*device
)
1153 zero(device
->meta_state
.blit2d
);
1155 const VkPushConstantRange push_constant_ranges
[] = {
1156 {VK_SHADER_STAGE_VERTEX_BIT
, 0, 16},
1157 {VK_SHADER_STAGE_FRAGMENT_BIT
, 16, 4},
1159 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
1160 &(VkDescriptorSetLayoutCreateInfo
) {
1161 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
1162 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
1164 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
1167 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
1168 .descriptorCount
= 1,
1169 .stageFlags
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1170 .pImmutableSamplers
= NULL
1173 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.ds_layouts
[BLIT2D_SRC_TYPE_IMAGE
]);
1174 if (result
!= VK_SUCCESS
)
1177 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1178 &(VkPipelineLayoutCreateInfo
) {
1179 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1180 .setLayoutCount
= 1,
1181 .pSetLayouts
= &device
->meta_state
.blit2d
.ds_layouts
[BLIT2D_SRC_TYPE_IMAGE
],
1182 .pushConstantRangeCount
= 1,
1183 .pPushConstantRanges
= push_constant_ranges
,
1185 &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.p_layouts
[BLIT2D_SRC_TYPE_IMAGE
]);
1186 if (result
!= VK_SUCCESS
)
1189 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
1190 &(VkDescriptorSetLayoutCreateInfo
) {
1191 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
1192 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
1194 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
1197 .descriptorType
= VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
,
1198 .descriptorCount
= 1,
1199 .stageFlags
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1200 .pImmutableSamplers
= NULL
1203 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.ds_layouts
[BLIT2D_SRC_TYPE_BUFFER
]);
1204 if (result
!= VK_SUCCESS
)
1208 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1209 &(VkPipelineLayoutCreateInfo
) {
1210 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1211 .setLayoutCount
= 1,
1212 .pSetLayouts
= &device
->meta_state
.blit2d
.ds_layouts
[BLIT2D_SRC_TYPE_BUFFER
],
1213 .pushConstantRangeCount
= 2,
1214 .pPushConstantRanges
= push_constant_ranges
,
1216 &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.p_layouts
[BLIT2D_SRC_TYPE_BUFFER
]);
1217 if (result
!= VK_SUCCESS
)
1220 for (unsigned src
= 0; src
< BLIT2D_NUM_SRC_TYPES
; src
++) {
1221 for (unsigned j
= 0; j
< ARRAY_SIZE(pipeline_formats
); ++j
) {
1222 result
= blit2d_init_color_pipeline(device
, src
, pipeline_formats
[j
]);
1223 if (result
!= VK_SUCCESS
)
1227 result
= blit2d_init_depth_only_pipeline(device
, src
);
1228 if (result
!= VK_SUCCESS
)
1231 result
= blit2d_init_stencil_only_pipeline(device
, src
);
1232 if (result
!= VK_SUCCESS
)
1239 radv_device_finish_meta_blit2d_state(device
);