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[mesa.git] / src / amd / vulkan / radv_meta_blit2d.c
1 /*
2 * Copyright © 2016 Red Hat
3 *
4 * based on anv driver:
5 * Copyright © 2016 Intel Corporation
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * IN THE SOFTWARE.
25 */
26
27 #include "radv_meta.h"
28 #include "nir/nir_builder.h"
29 #include "vk_format.h"
30
31 enum blit2d_dst_type {
32 /* We can bind this destination as a "normal" render target and render
33 * to it just like you would anywhere else.
34 */
35 BLIT2D_DST_TYPE_NORMAL,
36
37 /* The destination has a 3-channel RGB format. Since we can't render to
38 * non-power-of-two textures, we have to bind it as a red texture and
39 * select the correct component for the given red pixel in the shader.
40 */
41 BLIT2D_DST_TYPE_RGB,
42
43 BLIT2D_NUM_DST_TYPES,
44 };
45
46
47 enum blit2d_src_type {
48 BLIT2D_SRC_TYPE_IMAGE,
49 BLIT2D_SRC_TYPE_BUFFER,
50 BLIT2D_NUM_SRC_TYPES,
51 };
52
53 static void
54 create_iview(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_meta_blit2d_surf *surf,
56 VkImageUsageFlags usage,
57 struct radv_image_view *iview, VkFormat depth_format)
58 {
59 VkFormat format;
60
61 if (depth_format)
62 format = depth_format;
63 else
64 format = surf->format;
65
66 radv_image_view_init(iview, cmd_buffer->device,
67 &(VkImageViewCreateInfo) {
68 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
69 .image = radv_image_to_handle(surf->image),
70 .viewType = VK_IMAGE_VIEW_TYPE_2D,
71 .format = format,
72 .subresourceRange = {
73 .aspectMask = surf->aspect_mask,
74 .baseMipLevel = surf->level,
75 .levelCount = 1,
76 .baseArrayLayer = surf->layer,
77 .layerCount = 1
78 },
79 }, cmd_buffer, usage);
80 }
81
82 static void
83 create_bview(struct radv_cmd_buffer *cmd_buffer,
84 struct radv_meta_blit2d_buffer *src,
85 struct radv_buffer_view *bview, VkFormat depth_format)
86 {
87 VkFormat format;
88
89 if (depth_format)
90 format = depth_format;
91 else
92 format = src->format;
93 radv_buffer_view_init(bview, cmd_buffer->device,
94 &(VkBufferViewCreateInfo) {
95 .sType = VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO,
96 .flags = 0,
97 .buffer = radv_buffer_to_handle(src->buffer),
98 .format = format,
99 .offset = src->offset,
100 .range = VK_WHOLE_SIZE,
101 }, cmd_buffer);
102
103 }
104
105 struct blit2d_src_temps {
106 struct radv_image_view iview;
107 struct radv_buffer_view bview;
108 };
109
110 static void
111 blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
112 struct radv_meta_blit2d_surf *src_img,
113 struct radv_meta_blit2d_buffer *src_buf,
114 struct blit2d_src_temps *tmp,
115 enum blit2d_src_type src_type, VkFormat depth_format)
116 {
117 struct radv_device *device = cmd_buffer->device;
118
119 if (src_type == BLIT2D_SRC_TYPE_BUFFER) {
120 create_bview(cmd_buffer, src_buf, &tmp->bview, depth_format);
121
122 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
123 device->meta_state.blit2d.p_layouts[src_type],
124 0, /* set */
125 1, /* descriptorWriteCount */
126 (VkWriteDescriptorSet[]) {
127 {
128 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
129 .dstBinding = 0,
130 .dstArrayElement = 0,
131 .descriptorCount = 1,
132 .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
133 .pTexelBufferView = (VkBufferView[]) { radv_buffer_view_to_handle(&tmp->bview) }
134 }
135 });
136
137 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
138 device->meta_state.blit2d.p_layouts[src_type],
139 VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4,
140 &src_buf->pitch);
141 } else {
142 create_iview(cmd_buffer, src_img, VK_IMAGE_USAGE_SAMPLED_BIT, &tmp->iview,
143 depth_format);
144
145 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
146 device->meta_state.blit2d.p_layouts[src_type],
147 0, /* set */
148 1, /* descriptorWriteCount */
149 (VkWriteDescriptorSet[]) {
150 {
151 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
152 .dstBinding = 0,
153 .dstArrayElement = 0,
154 .descriptorCount = 1,
155 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
156 .pImageInfo = (VkDescriptorImageInfo[]) {
157 {
158 .sampler = VK_NULL_HANDLE,
159 .imageView = radv_image_view_to_handle(&tmp->iview),
160 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
161 },
162 }
163 }
164 });
165 }
166 }
167
168 struct blit2d_dst_temps {
169 VkImage image;
170 struct radv_image_view iview;
171 VkFramebuffer fb;
172 };
173
174 static void
175 blit2d_bind_dst(struct radv_cmd_buffer *cmd_buffer,
176 struct radv_meta_blit2d_surf *dst,
177 uint32_t width,
178 uint32_t height,
179 VkFormat depth_format,
180 struct blit2d_dst_temps *tmp)
181 {
182 VkImageUsageFlagBits bits;
183
184 if (dst->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT)
185 bits = VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
186 else
187 bits = VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT;
188
189 create_iview(cmd_buffer, dst, bits,
190 &tmp->iview, depth_format);
191
192 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer->device),
193 &(VkFramebufferCreateInfo) {
194 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
195 .attachmentCount = 1,
196 .pAttachments = (VkImageView[]) {
197 radv_image_view_to_handle(&tmp->iview),
198 },
199 .width = width,
200 .height = height,
201 .layers = 1
202 }, &cmd_buffer->pool->alloc, &tmp->fb);
203 }
204
205 static void
206 blit2d_unbind_dst(struct radv_cmd_buffer *cmd_buffer,
207 struct blit2d_dst_temps *tmp)
208 {
209 VkDevice vk_device = radv_device_to_handle(cmd_buffer->device);
210 radv_DestroyFramebuffer(vk_device, tmp->fb, &cmd_buffer->pool->alloc);
211 }
212
213 static void
214 bind_pipeline(struct radv_cmd_buffer *cmd_buffer,
215 enum blit2d_src_type src_type, unsigned fs_key)
216 {
217 VkPipeline pipeline =
218 cmd_buffer->device->meta_state.blit2d.pipelines[src_type][fs_key];
219
220 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
221 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
222 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
223 }
224 }
225
226 static void
227 bind_depth_pipeline(struct radv_cmd_buffer *cmd_buffer,
228 enum blit2d_src_type src_type)
229 {
230 VkPipeline pipeline =
231 cmd_buffer->device->meta_state.blit2d.depth_only_pipeline[src_type];
232
233 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
234 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
235 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
236 }
237 }
238
239 static void
240 bind_stencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
241 enum blit2d_src_type src_type)
242 {
243 VkPipeline pipeline =
244 cmd_buffer->device->meta_state.blit2d.stencil_only_pipeline[src_type];
245
246 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
247 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
248 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
249 }
250 }
251
252 static void
253 radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
254 struct radv_meta_blit2d_surf *src_img,
255 struct radv_meta_blit2d_buffer *src_buf,
256 struct radv_meta_blit2d_surf *dst,
257 unsigned num_rects,
258 struct radv_meta_blit2d_rect *rects, enum blit2d_src_type src_type)
259 {
260 struct radv_device *device = cmd_buffer->device;
261
262 for (unsigned r = 0; r < num_rects; ++r) {
263 VkFormat depth_format = 0;
264 if (dst->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT)
265 depth_format = vk_format_stencil_only(dst->image->vk_format);
266 else if (dst->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT)
267 depth_format = vk_format_depth_only(dst->image->vk_format);
268 struct blit2d_src_temps src_temps;
269 blit2d_bind_src(cmd_buffer, src_img, src_buf, &src_temps, src_type, depth_format);
270
271 struct blit2d_dst_temps dst_temps;
272 blit2d_bind_dst(cmd_buffer, dst, rects[r].dst_x + rects[r].width,
273 rects[r].dst_y + rects[r].height, depth_format, &dst_temps);
274
275 float vertex_push_constants[4] = {
276 rects[r].src_x,
277 rects[r].src_y,
278 rects[r].src_x + rects[r].width,
279 rects[r].src_y + rects[r].height,
280 };
281
282 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
283 device->meta_state.blit2d.p_layouts[src_type],
284 VK_SHADER_STAGE_VERTEX_BIT, 0, 16,
285 vertex_push_constants);
286
287 if (dst->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT) {
288 unsigned fs_key = radv_format_meta_fs_key(dst_temps.iview.vk_format);
289
290 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
291 &(VkRenderPassBeginInfo) {
292 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
293 .renderPass = device->meta_state.blit2d.render_passes[fs_key],
294 .framebuffer = dst_temps.fb,
295 .renderArea = {
296 .offset = { rects[r].dst_x, rects[r].dst_y, },
297 .extent = { rects[r].width, rects[r].height },
298 },
299 .clearValueCount = 0,
300 .pClearValues = NULL,
301 }, VK_SUBPASS_CONTENTS_INLINE);
302
303
304 bind_pipeline(cmd_buffer, src_type, fs_key);
305 } else if (dst->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
306 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
307 &(VkRenderPassBeginInfo) {
308 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
309 .renderPass = device->meta_state.blit2d.depth_only_rp,
310 .framebuffer = dst_temps.fb,
311 .renderArea = {
312 .offset = { rects[r].dst_x, rects[r].dst_y, },
313 .extent = { rects[r].width, rects[r].height },
314 },
315 .clearValueCount = 0,
316 .pClearValues = NULL,
317 }, VK_SUBPASS_CONTENTS_INLINE);
318
319
320 bind_depth_pipeline(cmd_buffer, src_type);
321
322 } else if (dst->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
323 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
324 &(VkRenderPassBeginInfo) {
325 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
326 .renderPass = device->meta_state.blit2d.stencil_only_rp,
327 .framebuffer = dst_temps.fb,
328 .renderArea = {
329 .offset = { rects[r].dst_x, rects[r].dst_y, },
330 .extent = { rects[r].width, rects[r].height },
331 },
332 .clearValueCount = 0,
333 .pClearValues = NULL,
334 }, VK_SUBPASS_CONTENTS_INLINE);
335
336
337 bind_stencil_pipeline(cmd_buffer, src_type);
338 }
339
340 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
341 .x = rects[r].dst_x,
342 .y = rects[r].dst_y,
343 .width = rects[r].width,
344 .height = rects[r].height,
345 .minDepth = 0.0f,
346 .maxDepth = 1.0f
347 });
348
349 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
350 .offset = (VkOffset2D) { rects[r].dst_x, rects[r].dst_y },
351 .extent = (VkExtent2D) { rects[r].width, rects[r].height },
352 });
353
354
355
356 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
357 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
358
359 /* At the point where we emit the draw call, all data from the
360 * descriptor sets, etc. has been used. We are free to delete it.
361 */
362 blit2d_unbind_dst(cmd_buffer, &dst_temps);
363 }
364 }
365
366 void
367 radv_meta_blit2d(struct radv_cmd_buffer *cmd_buffer,
368 struct radv_meta_blit2d_surf *src_img,
369 struct radv_meta_blit2d_buffer *src_buf,
370 struct radv_meta_blit2d_surf *dst,
371 unsigned num_rects,
372 struct radv_meta_blit2d_rect *rects)
373 {
374 enum blit2d_src_type src_type = src_buf ? BLIT2D_SRC_TYPE_BUFFER :
375 BLIT2D_SRC_TYPE_IMAGE;
376 radv_meta_blit2d_normal_dst(cmd_buffer, src_img, src_buf, dst,
377 num_rects, rects, src_type);
378 }
379
380 static nir_shader *
381 build_nir_vertex_shader(void)
382 {
383 const struct glsl_type *vec4 = glsl_vec4_type();
384 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
385 nir_builder b;
386
387 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
388 b.shader->info->name = ralloc_strdup(b.shader, "meta_blit2d_vs");
389
390 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
391 vec4, "gl_Position");
392 pos_out->data.location = VARYING_SLOT_POS;
393
394 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
395 vec2, "v_tex_pos");
396 tex_pos_out->data.location = VARYING_SLOT_VAR0;
397 tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
398
399 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
400 nir_store_var(&b, pos_out, outvec, 0xf);
401
402 nir_intrinsic_instr *src_box = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
403 src_box->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
404 nir_intrinsic_set_base(src_box, 0);
405 nir_intrinsic_set_range(src_box, 16);
406 src_box->num_components = 4;
407 nir_ssa_dest_init(&src_box->instr, &src_box->dest, 4, 32, "src_box");
408 nir_builder_instr_insert(&b, &src_box->instr);
409
410 nir_intrinsic_instr *vertex_id = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_vertex_id_zero_base);
411 nir_ssa_dest_init(&vertex_id->instr, &vertex_id->dest, 1, 32, "vertexid");
412 nir_builder_instr_insert(&b, &vertex_id->instr);
413
414 /* vertex 0 - src_x, src_y */
415 /* vertex 1 - src_x, src_y+h */
416 /* vertex 2 - src_x+w, src_y */
417 /* so channel 0 is vertex_id != 2 ? src_x : src_x + w
418 channel 1 is vertex id != 1 ? src_y : src_y + w */
419
420 nir_ssa_def *c0cmp = nir_ine(&b, &vertex_id->dest.ssa,
421 nir_imm_int(&b, 2));
422 nir_ssa_def *c1cmp = nir_ine(&b, &vertex_id->dest.ssa,
423 nir_imm_int(&b, 1));
424
425 nir_ssa_def *comp[2];
426 comp[0] = nir_bcsel(&b, c0cmp,
427 nir_channel(&b, &src_box->dest.ssa, 0),
428 nir_channel(&b, &src_box->dest.ssa, 2));
429
430 comp[1] = nir_bcsel(&b, c1cmp,
431 nir_channel(&b, &src_box->dest.ssa, 1),
432 nir_channel(&b, &src_box->dest.ssa, 3));
433 nir_ssa_def *out_tex_vec = nir_vec(&b, comp, 2);
434 nir_store_var(&b, tex_pos_out, out_tex_vec, 0x3);
435 return b.shader;
436 }
437
438 typedef nir_ssa_def* (*texel_fetch_build_func)(struct nir_builder *,
439 struct radv_device *,
440 nir_ssa_def *);
441
442 static nir_ssa_def *
443 build_nir_texel_fetch(struct nir_builder *b, struct radv_device *device,
444 nir_ssa_def *tex_pos)
445 {
446 const struct glsl_type *sampler_type =
447 glsl_sampler_type(GLSL_SAMPLER_DIM_2D, false, false, GLSL_TYPE_UINT);
448 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
449 sampler_type, "s_tex");
450 sampler->data.descriptor_set = 0;
451 sampler->data.binding = 0;
452
453 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 2);
454 tex->sampler_dim = GLSL_SAMPLER_DIM_2D;
455 tex->op = nir_texop_txf;
456 tex->src[0].src_type = nir_tex_src_coord;
457 tex->src[0].src = nir_src_for_ssa(tex_pos);
458 tex->src[1].src_type = nir_tex_src_lod;
459 tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
460 tex->dest_type = nir_type_uint;
461 tex->is_array = false;
462 tex->coord_components = 2;
463 tex->texture = nir_deref_var_create(tex, sampler);
464 tex->sampler = NULL;
465
466 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
467 nir_builder_instr_insert(b, &tex->instr);
468
469 return &tex->dest.ssa;
470 }
471
472
473 static nir_ssa_def *
474 build_nir_buffer_fetch(struct nir_builder *b, struct radv_device *device,
475 nir_ssa_def *tex_pos)
476 {
477 const struct glsl_type *sampler_type =
478 glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_UINT);
479 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
480 sampler_type, "s_tex");
481 sampler->data.descriptor_set = 0;
482 sampler->data.binding = 0;
483
484 nir_intrinsic_instr *width = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
485 nir_intrinsic_set_base(width, 16);
486 nir_intrinsic_set_range(width, 4);
487 width->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
488 width->num_components = 1;
489 nir_ssa_dest_init(&width->instr, &width->dest, 1, 32, "width");
490 nir_builder_instr_insert(b, &width->instr);
491
492 nir_ssa_def *pos_x = nir_channel(b, tex_pos, 0);
493 nir_ssa_def *pos_y = nir_channel(b, tex_pos, 1);
494 pos_y = nir_imul(b, pos_y, &width->dest.ssa);
495 pos_x = nir_iadd(b, pos_x, pos_y);
496 //pos_x = nir_iadd(b, pos_x, nir_imm_int(b, 100000));
497
498 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 1);
499 tex->sampler_dim = GLSL_SAMPLER_DIM_BUF;
500 tex->op = nir_texop_txf;
501 tex->src[0].src_type = nir_tex_src_coord;
502 tex->src[0].src = nir_src_for_ssa(pos_x);
503 tex->dest_type = nir_type_uint;
504 tex->is_array = false;
505 tex->coord_components = 1;
506 tex->texture = nir_deref_var_create(tex, sampler);
507 tex->sampler = NULL;
508
509 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
510 nir_builder_instr_insert(b, &tex->instr);
511
512 return &tex->dest.ssa;
513 }
514
515 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
516 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
517 .vertexBindingDescriptionCount = 0,
518 .vertexAttributeDescriptionCount = 0,
519 };
520
521 static nir_shader *
522 build_nir_copy_fragment_shader(struct radv_device *device,
523 texel_fetch_build_func txf_func, const char* name)
524 {
525 const struct glsl_type *vec4 = glsl_vec4_type();
526 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
527 nir_builder b;
528
529 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
530 b.shader->info->name = ralloc_strdup(b.shader, name);
531
532 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
533 vec2, "v_tex_pos");
534 tex_pos_in->data.location = VARYING_SLOT_VAR0;
535
536 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
537 vec4, "f_color");
538 color_out->data.location = FRAG_RESULT_DATA0;
539
540 nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
541 unsigned swiz[4] = { 0, 1 };
542 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
543
544 nir_ssa_def *color = txf_func(&b, device, tex_pos);
545 nir_store_var(&b, color_out, color, 0xf);
546
547 return b.shader;
548 }
549
550 static nir_shader *
551 build_nir_copy_fragment_shader_depth(struct radv_device *device,
552 texel_fetch_build_func txf_func, const char* name)
553 {
554 const struct glsl_type *vec4 = glsl_vec4_type();
555 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
556 nir_builder b;
557
558 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
559 b.shader->info->name = ralloc_strdup(b.shader, name);
560
561 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
562 vec2, "v_tex_pos");
563 tex_pos_in->data.location = VARYING_SLOT_VAR0;
564
565 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
566 vec4, "f_color");
567 color_out->data.location = FRAG_RESULT_DEPTH;
568
569 nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
570 unsigned swiz[4] = { 0, 1 };
571 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
572
573 nir_ssa_def *color = txf_func(&b, device, tex_pos);
574 nir_store_var(&b, color_out, color, 0x1);
575
576 return b.shader;
577 }
578
579 static nir_shader *
580 build_nir_copy_fragment_shader_stencil(struct radv_device *device,
581 texel_fetch_build_func txf_func, const char* name)
582 {
583 const struct glsl_type *vec4 = glsl_vec4_type();
584 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
585 nir_builder b;
586
587 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
588 b.shader->info->name = ralloc_strdup(b.shader, name);
589
590 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
591 vec2, "v_tex_pos");
592 tex_pos_in->data.location = VARYING_SLOT_VAR0;
593
594 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
595 vec4, "f_color");
596 color_out->data.location = FRAG_RESULT_STENCIL;
597
598 nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
599 unsigned swiz[4] = { 0, 1 };
600 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
601
602 nir_ssa_def *color = txf_func(&b, device, tex_pos);
603 nir_store_var(&b, color_out, color, 0x1);
604
605 return b.shader;
606 }
607
608 void
609 radv_device_finish_meta_blit2d_state(struct radv_device *device)
610 {
611 for(unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
612 if (device->meta_state.blit2d.render_passes[j]) {
613 radv_DestroyRenderPass(radv_device_to_handle(device),
614 device->meta_state.blit2d.render_passes[j],
615 &device->meta_state.alloc);
616 }
617 }
618
619 radv_DestroyRenderPass(radv_device_to_handle(device),
620 device->meta_state.blit2d.depth_only_rp,
621 &device->meta_state.alloc);
622 radv_DestroyRenderPass(radv_device_to_handle(device),
623 device->meta_state.blit2d.stencil_only_rp,
624 &device->meta_state.alloc);
625
626 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
627 if (device->meta_state.blit2d.p_layouts[src]) {
628 radv_DestroyPipelineLayout(radv_device_to_handle(device),
629 device->meta_state.blit2d.p_layouts[src],
630 &device->meta_state.alloc);
631 }
632
633 if (device->meta_state.blit2d.ds_layouts[src]) {
634 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
635 device->meta_state.blit2d.ds_layouts[src],
636 &device->meta_state.alloc);
637 }
638
639 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
640 if (device->meta_state.blit2d.pipelines[src][j]) {
641 radv_DestroyPipeline(radv_device_to_handle(device),
642 device->meta_state.blit2d.pipelines[src][j],
643 &device->meta_state.alloc);
644 }
645 }
646
647 radv_DestroyPipeline(radv_device_to_handle(device),
648 device->meta_state.blit2d.depth_only_pipeline[src],
649 &device->meta_state.alloc);
650 radv_DestroyPipeline(radv_device_to_handle(device),
651 device->meta_state.blit2d.stencil_only_pipeline[src],
652 &device->meta_state.alloc);
653 }
654 }
655
656 static VkResult
657 blit2d_init_color_pipeline(struct radv_device *device,
658 enum blit2d_src_type src_type,
659 VkFormat format)
660 {
661 VkResult result;
662 unsigned fs_key = radv_format_meta_fs_key(format);
663 const char *name;
664
665 texel_fetch_build_func src_func;
666 switch(src_type) {
667 case BLIT2D_SRC_TYPE_IMAGE:
668 src_func = build_nir_texel_fetch;
669 name = "meta_blit2d_image_fs";
670 break;
671 case BLIT2D_SRC_TYPE_BUFFER:
672 src_func = build_nir_buffer_fetch;
673 name = "meta_blit2d_buffer_fs";
674 break;
675 default:
676 unreachable("unknown blit src type\n");
677 break;
678 }
679
680 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
681 struct radv_shader_module fs = { .nir = NULL };
682
683
684 fs.nir = build_nir_copy_fragment_shader(device, src_func, name);
685 vi_create_info = &normal_vi_create_info;
686
687 struct radv_shader_module vs = {
688 .nir = build_nir_vertex_shader(),
689 };
690
691 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
692 {
693 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
694 .stage = VK_SHADER_STAGE_VERTEX_BIT,
695 .module = radv_shader_module_to_handle(&vs),
696 .pName = "main",
697 .pSpecializationInfo = NULL
698 }, {
699 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
700 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
701 .module = radv_shader_module_to_handle(&fs),
702 .pName = "main",
703 .pSpecializationInfo = NULL
704 },
705 };
706
707 if (!device->meta_state.blit2d.render_passes[fs_key]) {
708 result = radv_CreateRenderPass(radv_device_to_handle(device),
709 &(VkRenderPassCreateInfo) {
710 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
711 .attachmentCount = 1,
712 .pAttachments = &(VkAttachmentDescription) {
713 .format = format,
714 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
715 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
716 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
717 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
718 },
719 .subpassCount = 1,
720 .pSubpasses = &(VkSubpassDescription) {
721 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
722 .inputAttachmentCount = 0,
723 .colorAttachmentCount = 1,
724 .pColorAttachments = &(VkAttachmentReference) {
725 .attachment = 0,
726 .layout = VK_IMAGE_LAYOUT_GENERAL,
727 },
728 .pResolveAttachments = NULL,
729 .pDepthStencilAttachment = &(VkAttachmentReference) {
730 .attachment = VK_ATTACHMENT_UNUSED,
731 .layout = VK_IMAGE_LAYOUT_GENERAL,
732 },
733 .preserveAttachmentCount = 1,
734 .pPreserveAttachments = (uint32_t[]) { 0 },
735 },
736 .dependencyCount = 0,
737 }, &device->meta_state.alloc, &device->meta_state.blit2d.render_passes[fs_key]);
738 }
739
740 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
741 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
742 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
743 .pStages = pipeline_shader_stages,
744 .pVertexInputState = vi_create_info,
745 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
746 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
747 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
748 .primitiveRestartEnable = false,
749 },
750 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
751 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
752 .viewportCount = 1,
753 .scissorCount = 1,
754 },
755 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
756 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
757 .rasterizerDiscardEnable = false,
758 .polygonMode = VK_POLYGON_MODE_FILL,
759 .cullMode = VK_CULL_MODE_NONE,
760 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
761 },
762 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
763 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
764 .rasterizationSamples = 1,
765 .sampleShadingEnable = false,
766 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
767 },
768 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
769 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
770 .attachmentCount = 1,
771 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
772 { .colorWriteMask =
773 VK_COLOR_COMPONENT_A_BIT |
774 VK_COLOR_COMPONENT_R_BIT |
775 VK_COLOR_COMPONENT_G_BIT |
776 VK_COLOR_COMPONENT_B_BIT },
777 }
778 },
779 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
780 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
781 .dynamicStateCount = 9,
782 .pDynamicStates = (VkDynamicState[]) {
783 VK_DYNAMIC_STATE_VIEWPORT,
784 VK_DYNAMIC_STATE_SCISSOR,
785 VK_DYNAMIC_STATE_LINE_WIDTH,
786 VK_DYNAMIC_STATE_DEPTH_BIAS,
787 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
788 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
789 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
790 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
791 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
792 },
793 },
794 .flags = 0,
795 .layout = device->meta_state.blit2d.p_layouts[src_type],
796 .renderPass = device->meta_state.blit2d.render_passes[fs_key],
797 .subpass = 0,
798 };
799
800 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
801 .use_rectlist = true
802 };
803
804 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
805 radv_pipeline_cache_to_handle(&device->meta_state.cache),
806 &vk_pipeline_info, &radv_pipeline_info,
807 &device->meta_state.alloc,
808 &device->meta_state.blit2d.pipelines[src_type][fs_key]);
809
810
811 ralloc_free(vs.nir);
812 ralloc_free(fs.nir);
813
814 return result;
815 }
816
817 static VkResult
818 blit2d_init_depth_only_pipeline(struct radv_device *device,
819 enum blit2d_src_type src_type)
820 {
821 VkResult result;
822 const char *name;
823
824 texel_fetch_build_func src_func;
825 switch(src_type) {
826 case BLIT2D_SRC_TYPE_IMAGE:
827 src_func = build_nir_texel_fetch;
828 name = "meta_blit2d_depth_image_fs";
829 break;
830 case BLIT2D_SRC_TYPE_BUFFER:
831 src_func = build_nir_buffer_fetch;
832 name = "meta_blit2d_depth_buffer_fs";
833 break;
834 default:
835 unreachable("unknown blit src type\n");
836 break;
837 }
838
839 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
840 struct radv_shader_module fs = { .nir = NULL };
841
842 fs.nir = build_nir_copy_fragment_shader_depth(device, src_func, name);
843 vi_create_info = &normal_vi_create_info;
844
845 struct radv_shader_module vs = {
846 .nir = build_nir_vertex_shader(),
847 };
848
849 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
850 {
851 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
852 .stage = VK_SHADER_STAGE_VERTEX_BIT,
853 .module = radv_shader_module_to_handle(&vs),
854 .pName = "main",
855 .pSpecializationInfo = NULL
856 }, {
857 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
858 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
859 .module = radv_shader_module_to_handle(&fs),
860 .pName = "main",
861 .pSpecializationInfo = NULL
862 },
863 };
864
865 if (!device->meta_state.blit2d.depth_only_rp) {
866 result = radv_CreateRenderPass(radv_device_to_handle(device),
867 &(VkRenderPassCreateInfo) {
868 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
869 .attachmentCount = 1,
870 .pAttachments = &(VkAttachmentDescription) {
871 .format = 0,
872 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
873 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
874 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
875 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
876 },
877 .subpassCount = 1,
878 .pSubpasses = &(VkSubpassDescription) {
879 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
880 .inputAttachmentCount = 0,
881 .colorAttachmentCount = 0,
882 .pColorAttachments = NULL,
883 .pResolveAttachments = NULL,
884 .pDepthStencilAttachment = &(VkAttachmentReference) {
885 .attachment = 0,
886 .layout = VK_IMAGE_LAYOUT_GENERAL,
887 },
888 .preserveAttachmentCount = 1,
889 .pPreserveAttachments = (uint32_t[]) { 0 },
890 },
891 .dependencyCount = 0,
892 }, &device->meta_state.alloc, &device->meta_state.blit2d.depth_only_rp);
893 }
894
895 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
896 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
897 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
898 .pStages = pipeline_shader_stages,
899 .pVertexInputState = vi_create_info,
900 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
901 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
902 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
903 .primitiveRestartEnable = false,
904 },
905 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
906 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
907 .viewportCount = 1,
908 .scissorCount = 1,
909 },
910 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
911 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
912 .rasterizerDiscardEnable = false,
913 .polygonMode = VK_POLYGON_MODE_FILL,
914 .cullMode = VK_CULL_MODE_NONE,
915 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
916 },
917 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
918 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
919 .rasterizationSamples = 1,
920 .sampleShadingEnable = false,
921 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
922 },
923 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
924 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
925 .attachmentCount = 0,
926 .pAttachments = NULL,
927 },
928 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
929 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
930 .depthTestEnable = true,
931 .depthWriteEnable = true,
932 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
933 },
934 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
935 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
936 .dynamicStateCount = 9,
937 .pDynamicStates = (VkDynamicState[]) {
938 VK_DYNAMIC_STATE_VIEWPORT,
939 VK_DYNAMIC_STATE_SCISSOR,
940 VK_DYNAMIC_STATE_LINE_WIDTH,
941 VK_DYNAMIC_STATE_DEPTH_BIAS,
942 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
943 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
944 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
945 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
946 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
947 },
948 },
949 .flags = 0,
950 .layout = device->meta_state.blit2d.p_layouts[src_type],
951 .renderPass = device->meta_state.blit2d.depth_only_rp,
952 .subpass = 0,
953 };
954
955 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
956 .use_rectlist = true
957 };
958
959 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
960 radv_pipeline_cache_to_handle(&device->meta_state.cache),
961 &vk_pipeline_info, &radv_pipeline_info,
962 &device->meta_state.alloc,
963 &device->meta_state.blit2d.depth_only_pipeline[src_type]);
964
965
966 ralloc_free(vs.nir);
967 ralloc_free(fs.nir);
968
969 return result;
970 }
971
972 static VkResult
973 blit2d_init_stencil_only_pipeline(struct radv_device *device,
974 enum blit2d_src_type src_type)
975 {
976 VkResult result;
977 const char *name;
978
979 texel_fetch_build_func src_func;
980 switch(src_type) {
981 case BLIT2D_SRC_TYPE_IMAGE:
982 src_func = build_nir_texel_fetch;
983 name = "meta_blit2d_stencil_image_fs";
984 break;
985 case BLIT2D_SRC_TYPE_BUFFER:
986 src_func = build_nir_buffer_fetch;
987 name = "meta_blit2d_stencil_buffer_fs";
988 break;
989 default:
990 unreachable("unknown blit src type\n");
991 break;
992 }
993
994 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
995 struct radv_shader_module fs = { .nir = NULL };
996
997 fs.nir = build_nir_copy_fragment_shader_stencil(device, src_func, name);
998 vi_create_info = &normal_vi_create_info;
999
1000 struct radv_shader_module vs = {
1001 .nir = build_nir_vertex_shader(),
1002 };
1003
1004 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
1005 {
1006 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1007 .stage = VK_SHADER_STAGE_VERTEX_BIT,
1008 .module = radv_shader_module_to_handle(&vs),
1009 .pName = "main",
1010 .pSpecializationInfo = NULL
1011 }, {
1012 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1013 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
1014 .module = radv_shader_module_to_handle(&fs),
1015 .pName = "main",
1016 .pSpecializationInfo = NULL
1017 },
1018 };
1019
1020 if (!device->meta_state.blit2d.stencil_only_rp) {
1021 result = radv_CreateRenderPass(radv_device_to_handle(device),
1022 &(VkRenderPassCreateInfo) {
1023 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1024 .attachmentCount = 1,
1025 .pAttachments = &(VkAttachmentDescription) {
1026 .format = 0,
1027 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1028 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1029 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
1030 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
1031 },
1032 .subpassCount = 1,
1033 .pSubpasses = &(VkSubpassDescription) {
1034 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1035 .inputAttachmentCount = 0,
1036 .colorAttachmentCount = 0,
1037 .pColorAttachments = NULL,
1038 .pResolveAttachments = NULL,
1039 .pDepthStencilAttachment = &(VkAttachmentReference) {
1040 .attachment = 0,
1041 .layout = VK_IMAGE_LAYOUT_GENERAL,
1042 },
1043 .preserveAttachmentCount = 1,
1044 .pPreserveAttachments = (uint32_t[]) { 0 },
1045 },
1046 .dependencyCount = 0,
1047 }, &device->meta_state.alloc, &device->meta_state.blit2d.stencil_only_rp);
1048 }
1049
1050 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1051 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1052 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
1053 .pStages = pipeline_shader_stages,
1054 .pVertexInputState = vi_create_info,
1055 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1056 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1057 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1058 .primitiveRestartEnable = false,
1059 },
1060 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
1061 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1062 .viewportCount = 1,
1063 .scissorCount = 1,
1064 },
1065 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1066 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1067 .rasterizerDiscardEnable = false,
1068 .polygonMode = VK_POLYGON_MODE_FILL,
1069 .cullMode = VK_CULL_MODE_NONE,
1070 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1071 },
1072 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1073 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1074 .rasterizationSamples = 1,
1075 .sampleShadingEnable = false,
1076 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1077 },
1078 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1079 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1080 .attachmentCount = 0,
1081 .pAttachments = NULL,
1082 },
1083 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1084 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1085 .depthTestEnable = false,
1086 .depthWriteEnable = false,
1087 .stencilTestEnable = true,
1088 .front = {
1089 .failOp = VK_STENCIL_OP_REPLACE,
1090 .passOp = VK_STENCIL_OP_REPLACE,
1091 .depthFailOp = VK_STENCIL_OP_REPLACE,
1092 .compareOp = VK_COMPARE_OP_ALWAYS,
1093 .compareMask = 0xff,
1094 .writeMask = 0xff,
1095 .reference = 0
1096 },
1097 .back = {
1098 .failOp = VK_STENCIL_OP_REPLACE,
1099 .passOp = VK_STENCIL_OP_REPLACE,
1100 .depthFailOp = VK_STENCIL_OP_REPLACE,
1101 .compareOp = VK_COMPARE_OP_ALWAYS,
1102 .compareMask = 0xff,
1103 .writeMask = 0xff,
1104 .reference = 0
1105 },
1106 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
1107 },
1108 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1109 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1110 .dynamicStateCount = 6,
1111 .pDynamicStates = (VkDynamicState[]) {
1112 VK_DYNAMIC_STATE_VIEWPORT,
1113 VK_DYNAMIC_STATE_SCISSOR,
1114 VK_DYNAMIC_STATE_LINE_WIDTH,
1115 VK_DYNAMIC_STATE_DEPTH_BIAS,
1116 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1117 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1118 },
1119 },
1120 .flags = 0,
1121 .layout = device->meta_state.blit2d.p_layouts[src_type],
1122 .renderPass = device->meta_state.blit2d.stencil_only_rp,
1123 .subpass = 0,
1124 };
1125
1126 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1127 .use_rectlist = true
1128 };
1129
1130 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1131 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1132 &vk_pipeline_info, &radv_pipeline_info,
1133 &device->meta_state.alloc,
1134 &device->meta_state.blit2d.stencil_only_pipeline[src_type]);
1135
1136
1137 ralloc_free(vs.nir);
1138 ralloc_free(fs.nir);
1139
1140 return result;
1141 }
1142
1143 static VkFormat pipeline_formats[] = {
1144 VK_FORMAT_R8G8B8A8_UNORM,
1145 VK_FORMAT_R8G8B8A8_UINT,
1146 VK_FORMAT_R8G8B8A8_SINT,
1147 VK_FORMAT_R16G16B16A16_UNORM,
1148 VK_FORMAT_R16G16B16A16_SNORM,
1149 VK_FORMAT_R16G16B16A16_UINT,
1150 VK_FORMAT_R16G16B16A16_SINT,
1151 VK_FORMAT_R32_SFLOAT,
1152 VK_FORMAT_R32G32_SFLOAT,
1153 VK_FORMAT_R32G32B32A32_SFLOAT
1154 };
1155
1156 VkResult
1157 radv_device_init_meta_blit2d_state(struct radv_device *device)
1158 {
1159 VkResult result;
1160
1161 zero(device->meta_state.blit2d);
1162
1163 const VkPushConstantRange push_constant_ranges[] = {
1164 {VK_SHADER_STAGE_VERTEX_BIT, 0, 16},
1165 {VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4},
1166 };
1167 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1168 &(VkDescriptorSetLayoutCreateInfo) {
1169 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1170 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1171 .bindingCount = 1,
1172 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1173 {
1174 .binding = 0,
1175 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
1176 .descriptorCount = 1,
1177 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1178 .pImmutableSamplers = NULL
1179 },
1180 }
1181 }, &device->meta_state.alloc, &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_IMAGE]);
1182 if (result != VK_SUCCESS)
1183 goto fail;
1184
1185 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1186 &(VkPipelineLayoutCreateInfo) {
1187 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1188 .setLayoutCount = 1,
1189 .pSetLayouts = &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_IMAGE],
1190 .pushConstantRangeCount = 1,
1191 .pPushConstantRanges = push_constant_ranges,
1192 },
1193 &device->meta_state.alloc, &device->meta_state.blit2d.p_layouts[BLIT2D_SRC_TYPE_IMAGE]);
1194 if (result != VK_SUCCESS)
1195 goto fail;
1196
1197 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1198 &(VkDescriptorSetLayoutCreateInfo) {
1199 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1200 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1201 .bindingCount = 1,
1202 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1203 {
1204 .binding = 0,
1205 .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
1206 .descriptorCount = 1,
1207 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1208 .pImmutableSamplers = NULL
1209 },
1210 }
1211 }, &device->meta_state.alloc, &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_BUFFER]);
1212 if (result != VK_SUCCESS)
1213 goto fail;
1214
1215
1216 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1217 &(VkPipelineLayoutCreateInfo) {
1218 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1219 .setLayoutCount = 1,
1220 .pSetLayouts = &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_BUFFER],
1221 .pushConstantRangeCount = 2,
1222 .pPushConstantRanges = push_constant_ranges,
1223 },
1224 &device->meta_state.alloc, &device->meta_state.blit2d.p_layouts[BLIT2D_SRC_TYPE_BUFFER]);
1225 if (result != VK_SUCCESS)
1226 goto fail;
1227
1228 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
1229 for (unsigned j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
1230 result = blit2d_init_color_pipeline(device, src, pipeline_formats[j]);
1231 if (result != VK_SUCCESS)
1232 goto fail;
1233 }
1234
1235 result = blit2d_init_depth_only_pipeline(device, src);
1236 if (result != VK_SUCCESS)
1237 goto fail;
1238
1239 result = blit2d_init_stencil_only_pipeline(device, src);
1240 if (result != VK_SUCCESS)
1241 goto fail;
1242 }
1243
1244 return VK_SUCCESS;
1245
1246 fail:
1247 radv_device_finish_meta_blit2d_state(device);
1248 return result;
1249 }