2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "radv_meta.h"
25 #include "nir/nir_builder.h"
28 * GFX queue: Compute shader implementation of image->buffer copy
29 * Compute queue: implementation also of buffer->image, image->image, and image clear.
32 /* GFX9 needs to use a 3D sampler to access 3D resources, so the shader has the options
36 build_nir_itob_compute_shader(struct radv_device
*dev
, bool is_3d
)
39 enum glsl_sampler_dim dim
= is_3d
? GLSL_SAMPLER_DIM_3D
: GLSL_SAMPLER_DIM_2D
;
40 const struct glsl_type
*sampler_type
= glsl_sampler_type(dim
,
44 const struct glsl_type
*img_type
= glsl_sampler_type(GLSL_SAMPLER_DIM_BUF
,
48 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_COMPUTE
, NULL
);
49 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, is_3d
? "meta_itob_cs_3d" : "meta_itob_cs");
50 b
.shader
->info
.cs
.local_size
[0] = 16;
51 b
.shader
->info
.cs
.local_size
[1] = 16;
52 b
.shader
->info
.cs
.local_size
[2] = 1;
53 nir_variable
*input_img
= nir_variable_create(b
.shader
, nir_var_uniform
,
54 sampler_type
, "s_tex");
55 input_img
->data
.descriptor_set
= 0;
56 input_img
->data
.binding
= 0;
58 nir_variable
*output_img
= nir_variable_create(b
.shader
, nir_var_uniform
,
60 output_img
->data
.descriptor_set
= 0;
61 output_img
->data
.binding
= 1;
63 nir_ssa_def
*invoc_id
= nir_load_system_value(&b
, nir_intrinsic_load_local_invocation_id
, 0);
64 nir_ssa_def
*wg_id
= nir_load_system_value(&b
, nir_intrinsic_load_work_group_id
, 0);
65 nir_ssa_def
*block_size
= nir_imm_ivec4(&b
,
66 b
.shader
->info
.cs
.local_size
[0],
67 b
.shader
->info
.cs
.local_size
[1],
68 b
.shader
->info
.cs
.local_size
[2], 0);
70 nir_ssa_def
*global_id
= nir_iadd(&b
, nir_imul(&b
, wg_id
, block_size
), invoc_id
);
74 nir_intrinsic_instr
*offset
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
75 nir_intrinsic_set_base(offset
, 0);
76 nir_intrinsic_set_range(offset
, 16);
77 offset
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
78 offset
->num_components
= is_3d
? 3 : 2;
79 nir_ssa_dest_init(&offset
->instr
, &offset
->dest
, is_3d
? 3 : 2, 32, "offset");
80 nir_builder_instr_insert(&b
, &offset
->instr
);
82 nir_intrinsic_instr
*stride
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
83 nir_intrinsic_set_base(stride
, 0);
84 nir_intrinsic_set_range(stride
, 16);
85 stride
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 12));
86 stride
->num_components
= 1;
87 nir_ssa_dest_init(&stride
->instr
, &stride
->dest
, 1, 32, "stride");
88 nir_builder_instr_insert(&b
, &stride
->instr
);
90 nir_ssa_def
*img_coord
= nir_iadd(&b
, global_id
, &offset
->dest
.ssa
);
91 nir_tex_instr
*tex
= nir_tex_instr_create(b
.shader
, 2);
92 tex
->sampler_dim
= dim
;
93 tex
->op
= nir_texop_txf
;
94 tex
->src
[0].src_type
= nir_tex_src_coord
;
95 tex
->src
[0].src
= nir_src_for_ssa(nir_channels(&b
, img_coord
, is_3d
? 0x7 : 0x3));
96 tex
->src
[1].src_type
= nir_tex_src_lod
;
97 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(&b
, 0));
98 tex
->dest_type
= nir_type_float
;
99 tex
->is_array
= false;
100 tex
->coord_components
= is_3d
? 3 : 2;
101 tex
->texture
= nir_deref_var_create(tex
, input_img
);
104 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
105 nir_builder_instr_insert(&b
, &tex
->instr
);
107 nir_ssa_def
*pos_x
= nir_channel(&b
, global_id
, 0);
108 nir_ssa_def
*pos_y
= nir_channel(&b
, global_id
, 1);
110 nir_ssa_def
*tmp
= nir_imul(&b
, pos_y
, &stride
->dest
.ssa
);
111 tmp
= nir_iadd(&b
, tmp
, pos_x
);
113 nir_ssa_def
*coord
= nir_vec4(&b
, tmp
, tmp
, tmp
, tmp
);
115 nir_ssa_def
*outval
= &tex
->dest
.ssa
;
116 nir_intrinsic_instr
*store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_image_var_store
);
117 store
->src
[0] = nir_src_for_ssa(coord
);
118 store
->src
[1] = nir_src_for_ssa(nir_ssa_undef(&b
, 1, 32));
119 store
->src
[2] = nir_src_for_ssa(outval
);
120 store
->variables
[0] = nir_deref_var_create(store
, output_img
);
122 nir_builder_instr_insert(&b
, &store
->instr
);
126 /* Image to buffer - don't write use image accessors */
128 radv_device_init_meta_itob_state(struct radv_device
*device
)
131 struct radv_shader_module cs
= { .nir
= NULL
};
132 struct radv_shader_module cs_3d
= { .nir
= NULL
};
134 cs
.nir
= build_nir_itob_compute_shader(device
, false);
135 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
136 cs_3d
.nir
= build_nir_itob_compute_shader(device
, true);
139 * two descriptors one for the image being sampled
140 * one for the buffer being written.
142 VkDescriptorSetLayoutCreateInfo ds_create_info
= {
143 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
144 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
146 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
149 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
150 .descriptorCount
= 1,
151 .stageFlags
= VK_SHADER_STAGE_COMPUTE_BIT
,
152 .pImmutableSamplers
= NULL
156 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
,
157 .descriptorCount
= 1,
158 .stageFlags
= VK_SHADER_STAGE_COMPUTE_BIT
,
159 .pImmutableSamplers
= NULL
164 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
166 &device
->meta_state
.alloc
,
167 &device
->meta_state
.itob
.img_ds_layout
);
168 if (result
!= VK_SUCCESS
)
172 VkPipelineLayoutCreateInfo pl_create_info
= {
173 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
175 .pSetLayouts
= &device
->meta_state
.itob
.img_ds_layout
,
176 .pushConstantRangeCount
= 1,
177 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_COMPUTE_BIT
, 0, 16},
180 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
182 &device
->meta_state
.alloc
,
183 &device
->meta_state
.itob
.img_p_layout
);
184 if (result
!= VK_SUCCESS
)
189 VkPipelineShaderStageCreateInfo pipeline_shader_stage
= {
190 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
191 .stage
= VK_SHADER_STAGE_COMPUTE_BIT
,
192 .module
= radv_shader_module_to_handle(&cs
),
194 .pSpecializationInfo
= NULL
,
197 VkComputePipelineCreateInfo vk_pipeline_info
= {
198 .sType
= VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
,
199 .stage
= pipeline_shader_stage
,
201 .layout
= device
->meta_state
.itob
.img_p_layout
,
204 result
= radv_CreateComputePipelines(radv_device_to_handle(device
),
205 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
206 1, &vk_pipeline_info
, NULL
,
207 &device
->meta_state
.itob
.pipeline
);
208 if (result
!= VK_SUCCESS
)
211 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
212 VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d
= {
213 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
214 .stage
= VK_SHADER_STAGE_COMPUTE_BIT
,
215 .module
= radv_shader_module_to_handle(&cs_3d
),
217 .pSpecializationInfo
= NULL
,
220 VkComputePipelineCreateInfo vk_pipeline_info_3d
= {
221 .sType
= VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
,
222 .stage
= pipeline_shader_stage_3d
,
224 .layout
= device
->meta_state
.itob
.img_p_layout
,
227 result
= radv_CreateComputePipelines(radv_device_to_handle(device
),
228 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
229 1, &vk_pipeline_info_3d
, NULL
,
230 &device
->meta_state
.itob
.pipeline_3d
);
231 if (result
!= VK_SUCCESS
)
233 ralloc_free(cs_3d
.nir
);
240 ralloc_free(cs_3d
.nir
);
245 radv_device_finish_meta_itob_state(struct radv_device
*device
)
247 struct radv_meta_state
*state
= &device
->meta_state
;
249 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
250 state
->itob
.img_p_layout
, &state
->alloc
);
251 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
252 state
->itob
.img_ds_layout
,
254 radv_DestroyPipeline(radv_device_to_handle(device
),
255 state
->itob
.pipeline
, &state
->alloc
);
256 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
257 radv_DestroyPipeline(radv_device_to_handle(device
),
258 state
->itob
.pipeline_3d
, &state
->alloc
);
262 build_nir_btoi_compute_shader(struct radv_device
*dev
, bool is_3d
)
265 enum glsl_sampler_dim dim
= is_3d
? GLSL_SAMPLER_DIM_3D
: GLSL_SAMPLER_DIM_2D
;
266 const struct glsl_type
*buf_type
= glsl_sampler_type(GLSL_SAMPLER_DIM_BUF
,
270 const struct glsl_type
*img_type
= glsl_sampler_type(dim
,
274 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_COMPUTE
, NULL
);
275 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, is_3d
? "meta_btoi_cs_3d" : "meta_btoi_cs");
276 b
.shader
->info
.cs
.local_size
[0] = 16;
277 b
.shader
->info
.cs
.local_size
[1] = 16;
278 b
.shader
->info
.cs
.local_size
[2] = 1;
279 nir_variable
*input_img
= nir_variable_create(b
.shader
, nir_var_uniform
,
281 input_img
->data
.descriptor_set
= 0;
282 input_img
->data
.binding
= 0;
284 nir_variable
*output_img
= nir_variable_create(b
.shader
, nir_var_uniform
,
285 img_type
, "out_img");
286 output_img
->data
.descriptor_set
= 0;
287 output_img
->data
.binding
= 1;
289 nir_ssa_def
*invoc_id
= nir_load_system_value(&b
, nir_intrinsic_load_local_invocation_id
, 0);
290 nir_ssa_def
*wg_id
= nir_load_system_value(&b
, nir_intrinsic_load_work_group_id
, 0);
291 nir_ssa_def
*block_size
= nir_imm_ivec4(&b
,
292 b
.shader
->info
.cs
.local_size
[0],
293 b
.shader
->info
.cs
.local_size
[1],
294 b
.shader
->info
.cs
.local_size
[2], 0);
296 nir_ssa_def
*global_id
= nir_iadd(&b
, nir_imul(&b
, wg_id
, block_size
), invoc_id
);
298 nir_intrinsic_instr
*offset
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
299 nir_intrinsic_set_base(offset
, 0);
300 nir_intrinsic_set_range(offset
, 16);
301 offset
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
302 offset
->num_components
= is_3d
? 3 : 2;
303 nir_ssa_dest_init(&offset
->instr
, &offset
->dest
, is_3d
? 3 : 2, 32, "offset");
304 nir_builder_instr_insert(&b
, &offset
->instr
);
306 nir_intrinsic_instr
*stride
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
307 nir_intrinsic_set_base(stride
, 0);
308 nir_intrinsic_set_range(stride
, 16);
309 stride
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 12));
310 stride
->num_components
= 1;
311 nir_ssa_dest_init(&stride
->instr
, &stride
->dest
, 1, 32, "stride");
312 nir_builder_instr_insert(&b
, &stride
->instr
);
314 nir_ssa_def
*pos_x
= nir_channel(&b
, global_id
, 0);
315 nir_ssa_def
*pos_y
= nir_channel(&b
, global_id
, 1);
317 nir_ssa_def
*tmp
= nir_imul(&b
, pos_y
, &stride
->dest
.ssa
);
318 tmp
= nir_iadd(&b
, tmp
, pos_x
);
320 nir_ssa_def
*buf_coord
= nir_vec4(&b
, tmp
, tmp
, tmp
, tmp
);
322 nir_ssa_def
*img_coord
= nir_iadd(&b
, global_id
, &offset
->dest
.ssa
);
324 nir_tex_instr
*tex
= nir_tex_instr_create(b
.shader
, 2);
325 tex
->sampler_dim
= GLSL_SAMPLER_DIM_BUF
;
326 tex
->op
= nir_texop_txf
;
327 tex
->src
[0].src_type
= nir_tex_src_coord
;
328 tex
->src
[0].src
= nir_src_for_ssa(nir_channels(&b
, buf_coord
, 1));
329 tex
->src
[1].src_type
= nir_tex_src_lod
;
330 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(&b
, 0));
331 tex
->dest_type
= nir_type_float
;
332 tex
->is_array
= false;
333 tex
->coord_components
= 1;
334 tex
->texture
= nir_deref_var_create(tex
, input_img
);
337 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
338 nir_builder_instr_insert(&b
, &tex
->instr
);
340 nir_ssa_def
*outval
= &tex
->dest
.ssa
;
341 nir_intrinsic_instr
*store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_image_var_store
);
342 store
->src
[0] = nir_src_for_ssa(img_coord
);
343 store
->src
[1] = nir_src_for_ssa(nir_ssa_undef(&b
, 1, 32));
344 store
->src
[2] = nir_src_for_ssa(outval
);
345 store
->variables
[0] = nir_deref_var_create(store
, output_img
);
347 nir_builder_instr_insert(&b
, &store
->instr
);
351 /* Buffer to image - don't write use image accessors */
353 radv_device_init_meta_btoi_state(struct radv_device
*device
)
356 struct radv_shader_module cs
= { .nir
= NULL
};
357 struct radv_shader_module cs_3d
= { .nir
= NULL
};
358 cs
.nir
= build_nir_btoi_compute_shader(device
, false);
359 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
360 cs_3d
.nir
= build_nir_btoi_compute_shader(device
, true);
362 * two descriptors one for the image being sampled
363 * one for the buffer being written.
365 VkDescriptorSetLayoutCreateInfo ds_create_info
= {
366 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
367 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
369 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
372 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
,
373 .descriptorCount
= 1,
374 .stageFlags
= VK_SHADER_STAGE_COMPUTE_BIT
,
375 .pImmutableSamplers
= NULL
379 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
,
380 .descriptorCount
= 1,
381 .stageFlags
= VK_SHADER_STAGE_COMPUTE_BIT
,
382 .pImmutableSamplers
= NULL
387 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
389 &device
->meta_state
.alloc
,
390 &device
->meta_state
.btoi
.img_ds_layout
);
391 if (result
!= VK_SUCCESS
)
395 VkPipelineLayoutCreateInfo pl_create_info
= {
396 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
398 .pSetLayouts
= &device
->meta_state
.btoi
.img_ds_layout
,
399 .pushConstantRangeCount
= 1,
400 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_COMPUTE_BIT
, 0, 16},
403 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
405 &device
->meta_state
.alloc
,
406 &device
->meta_state
.btoi
.img_p_layout
);
407 if (result
!= VK_SUCCESS
)
412 VkPipelineShaderStageCreateInfo pipeline_shader_stage
= {
413 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
414 .stage
= VK_SHADER_STAGE_COMPUTE_BIT
,
415 .module
= radv_shader_module_to_handle(&cs
),
417 .pSpecializationInfo
= NULL
,
420 VkComputePipelineCreateInfo vk_pipeline_info
= {
421 .sType
= VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
,
422 .stage
= pipeline_shader_stage
,
424 .layout
= device
->meta_state
.btoi
.img_p_layout
,
427 result
= radv_CreateComputePipelines(radv_device_to_handle(device
),
428 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
429 1, &vk_pipeline_info
, NULL
,
430 &device
->meta_state
.btoi
.pipeline
);
431 if (result
!= VK_SUCCESS
)
434 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
435 VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d
= {
436 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
437 .stage
= VK_SHADER_STAGE_COMPUTE_BIT
,
438 .module
= radv_shader_module_to_handle(&cs_3d
),
440 .pSpecializationInfo
= NULL
,
443 VkComputePipelineCreateInfo vk_pipeline_info_3d
= {
444 .sType
= VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
,
445 .stage
= pipeline_shader_stage_3d
,
447 .layout
= device
->meta_state
.btoi
.img_p_layout
,
450 result
= radv_CreateComputePipelines(radv_device_to_handle(device
),
451 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
452 1, &vk_pipeline_info_3d
, NULL
,
453 &device
->meta_state
.btoi
.pipeline_3d
);
454 ralloc_free(cs_3d
.nir
);
460 ralloc_free(cs_3d
.nir
);
466 radv_device_finish_meta_btoi_state(struct radv_device
*device
)
468 struct radv_meta_state
*state
= &device
->meta_state
;
470 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
471 state
->btoi
.img_p_layout
, &state
->alloc
);
472 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
473 state
->btoi
.img_ds_layout
,
475 radv_DestroyPipeline(radv_device_to_handle(device
),
476 state
->btoi
.pipeline
, &state
->alloc
);
477 radv_DestroyPipeline(radv_device_to_handle(device
),
478 state
->btoi
.pipeline_3d
, &state
->alloc
);
482 build_nir_itoi_compute_shader(struct radv_device
*dev
, bool is_3d
)
485 enum glsl_sampler_dim dim
= is_3d
? GLSL_SAMPLER_DIM_3D
: GLSL_SAMPLER_DIM_2D
;
486 const struct glsl_type
*buf_type
= glsl_sampler_type(dim
,
490 const struct glsl_type
*img_type
= glsl_sampler_type(dim
,
494 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_COMPUTE
, NULL
);
495 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, is_3d
? "meta_itoi_cs_3d" : "meta_itoi_cs");
496 b
.shader
->info
.cs
.local_size
[0] = 16;
497 b
.shader
->info
.cs
.local_size
[1] = 16;
498 b
.shader
->info
.cs
.local_size
[2] = 1;
499 nir_variable
*input_img
= nir_variable_create(b
.shader
, nir_var_uniform
,
501 input_img
->data
.descriptor_set
= 0;
502 input_img
->data
.binding
= 0;
504 nir_variable
*output_img
= nir_variable_create(b
.shader
, nir_var_uniform
,
505 img_type
, "out_img");
506 output_img
->data
.descriptor_set
= 0;
507 output_img
->data
.binding
= 1;
509 nir_ssa_def
*invoc_id
= nir_load_system_value(&b
, nir_intrinsic_load_local_invocation_id
, 0);
510 nir_ssa_def
*wg_id
= nir_load_system_value(&b
, nir_intrinsic_load_work_group_id
, 0);
511 nir_ssa_def
*block_size
= nir_imm_ivec4(&b
,
512 b
.shader
->info
.cs
.local_size
[0],
513 b
.shader
->info
.cs
.local_size
[1],
514 b
.shader
->info
.cs
.local_size
[2], 0);
516 nir_ssa_def
*global_id
= nir_iadd(&b
, nir_imul(&b
, wg_id
, block_size
), invoc_id
);
518 nir_intrinsic_instr
*src_offset
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
519 nir_intrinsic_set_base(src_offset
, 0);
520 nir_intrinsic_set_range(src_offset
, 24);
521 src_offset
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
522 src_offset
->num_components
= is_3d
? 3 : 2;
523 nir_ssa_dest_init(&src_offset
->instr
, &src_offset
->dest
, is_3d
? 3 : 2, 32, "src_offset");
524 nir_builder_instr_insert(&b
, &src_offset
->instr
);
526 nir_intrinsic_instr
*dst_offset
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
527 nir_intrinsic_set_base(dst_offset
, 0);
528 nir_intrinsic_set_range(dst_offset
, 24);
529 dst_offset
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 12));
530 dst_offset
->num_components
= is_3d
? 3 : 2;
531 nir_ssa_dest_init(&dst_offset
->instr
, &dst_offset
->dest
, is_3d
? 3 : 2, 32, "dst_offset");
532 nir_builder_instr_insert(&b
, &dst_offset
->instr
);
534 nir_ssa_def
*src_coord
= nir_iadd(&b
, global_id
, &src_offset
->dest
.ssa
);
536 nir_ssa_def
*dst_coord
= nir_iadd(&b
, global_id
, &dst_offset
->dest
.ssa
);
538 nir_tex_instr
*tex
= nir_tex_instr_create(b
.shader
, 2);
539 tex
->sampler_dim
= dim
;
540 tex
->op
= nir_texop_txf
;
541 tex
->src
[0].src_type
= nir_tex_src_coord
;
542 tex
->src
[0].src
= nir_src_for_ssa(nir_channels(&b
, src_coord
, is_3d
? 0x7 : 0x3));
543 tex
->src
[1].src_type
= nir_tex_src_lod
;
544 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(&b
, 0));
545 tex
->dest_type
= nir_type_float
;
546 tex
->is_array
= false;
547 tex
->coord_components
= is_3d
? 3 : 2;
548 tex
->texture
= nir_deref_var_create(tex
, input_img
);
551 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
552 nir_builder_instr_insert(&b
, &tex
->instr
);
554 nir_ssa_def
*outval
= &tex
->dest
.ssa
;
555 nir_intrinsic_instr
*store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_image_var_store
);
556 store
->src
[0] = nir_src_for_ssa(dst_coord
);
557 store
->src
[1] = nir_src_for_ssa(nir_ssa_undef(&b
, 1, 32));
558 store
->src
[2] = nir_src_for_ssa(outval
);
559 store
->variables
[0] = nir_deref_var_create(store
, output_img
);
561 nir_builder_instr_insert(&b
, &store
->instr
);
565 /* image to image - don't write use image accessors */
567 radv_device_init_meta_itoi_state(struct radv_device
*device
)
570 struct radv_shader_module cs
= { .nir
= NULL
};
571 struct radv_shader_module cs_3d
= { .nir
= NULL
};
572 cs
.nir
= build_nir_itoi_compute_shader(device
, false);
573 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
574 cs_3d
.nir
= build_nir_itoi_compute_shader(device
, true);
576 * two descriptors one for the image being sampled
577 * one for the buffer being written.
579 VkDescriptorSetLayoutCreateInfo ds_create_info
= {
580 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
581 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
583 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
586 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
587 .descriptorCount
= 1,
588 .stageFlags
= VK_SHADER_STAGE_COMPUTE_BIT
,
589 .pImmutableSamplers
= NULL
593 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
,
594 .descriptorCount
= 1,
595 .stageFlags
= VK_SHADER_STAGE_COMPUTE_BIT
,
596 .pImmutableSamplers
= NULL
601 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
603 &device
->meta_state
.alloc
,
604 &device
->meta_state
.itoi
.img_ds_layout
);
605 if (result
!= VK_SUCCESS
)
609 VkPipelineLayoutCreateInfo pl_create_info
= {
610 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
612 .pSetLayouts
= &device
->meta_state
.itoi
.img_ds_layout
,
613 .pushConstantRangeCount
= 1,
614 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_COMPUTE_BIT
, 0, 24},
617 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
619 &device
->meta_state
.alloc
,
620 &device
->meta_state
.itoi
.img_p_layout
);
621 if (result
!= VK_SUCCESS
)
626 VkPipelineShaderStageCreateInfo pipeline_shader_stage
= {
627 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
628 .stage
= VK_SHADER_STAGE_COMPUTE_BIT
,
629 .module
= radv_shader_module_to_handle(&cs
),
631 .pSpecializationInfo
= NULL
,
634 VkComputePipelineCreateInfo vk_pipeline_info
= {
635 .sType
= VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
,
636 .stage
= pipeline_shader_stage
,
638 .layout
= device
->meta_state
.itoi
.img_p_layout
,
641 result
= radv_CreateComputePipelines(radv_device_to_handle(device
),
642 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
643 1, &vk_pipeline_info
, NULL
,
644 &device
->meta_state
.itoi
.pipeline
);
645 if (result
!= VK_SUCCESS
)
648 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
649 VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d
= {
650 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
651 .stage
= VK_SHADER_STAGE_COMPUTE_BIT
,
652 .module
= radv_shader_module_to_handle(&cs_3d
),
654 .pSpecializationInfo
= NULL
,
657 VkComputePipelineCreateInfo vk_pipeline_info_3d
= {
658 .sType
= VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
,
659 .stage
= pipeline_shader_stage_3d
,
661 .layout
= device
->meta_state
.itoi
.img_p_layout
,
664 result
= radv_CreateComputePipelines(radv_device_to_handle(device
),
665 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
666 1, &vk_pipeline_info_3d
, NULL
,
667 &device
->meta_state
.itoi
.pipeline_3d
);
669 ralloc_free(cs_3d
.nir
);
676 ralloc_free(cs_3d
.nir
);
681 radv_device_finish_meta_itoi_state(struct radv_device
*device
)
683 struct radv_meta_state
*state
= &device
->meta_state
;
685 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
686 state
->itoi
.img_p_layout
, &state
->alloc
);
687 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
688 state
->itoi
.img_ds_layout
,
690 radv_DestroyPipeline(radv_device_to_handle(device
),
691 state
->itoi
.pipeline
, &state
->alloc
);
692 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
693 radv_DestroyPipeline(radv_device_to_handle(device
),
694 state
->itoi
.pipeline_3d
, &state
->alloc
);
698 build_nir_cleari_compute_shader(struct radv_device
*dev
, bool is_3d
)
701 enum glsl_sampler_dim dim
= is_3d
? GLSL_SAMPLER_DIM_3D
: GLSL_SAMPLER_DIM_2D
;
702 const struct glsl_type
*img_type
= glsl_sampler_type(dim
,
706 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_COMPUTE
, NULL
);
707 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, is_3d
? "meta_cleari_cs_3d" : "meta_cleari_cs");
708 b
.shader
->info
.cs
.local_size
[0] = 16;
709 b
.shader
->info
.cs
.local_size
[1] = 16;
710 b
.shader
->info
.cs
.local_size
[2] = 1;
712 nir_variable
*output_img
= nir_variable_create(b
.shader
, nir_var_uniform
,
713 img_type
, "out_img");
714 output_img
->data
.descriptor_set
= 0;
715 output_img
->data
.binding
= 0;
717 nir_ssa_def
*invoc_id
= nir_load_system_value(&b
, nir_intrinsic_load_local_invocation_id
, 0);
718 nir_ssa_def
*wg_id
= nir_load_system_value(&b
, nir_intrinsic_load_work_group_id
, 0);
719 nir_ssa_def
*block_size
= nir_imm_ivec4(&b
,
720 b
.shader
->info
.cs
.local_size
[0],
721 b
.shader
->info
.cs
.local_size
[1],
722 b
.shader
->info
.cs
.local_size
[2], 0);
724 nir_ssa_def
*global_id
= nir_iadd(&b
, nir_imul(&b
, wg_id
, block_size
), invoc_id
);
726 nir_intrinsic_instr
*clear_val
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
727 nir_intrinsic_set_base(clear_val
, 0);
728 nir_intrinsic_set_range(clear_val
, 20);
729 clear_val
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
730 clear_val
->num_components
= 4;
731 nir_ssa_dest_init(&clear_val
->instr
, &clear_val
->dest
, 4, 32, "clear_value");
732 nir_builder_instr_insert(&b
, &clear_val
->instr
);
734 nir_intrinsic_instr
*layer
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
735 nir_intrinsic_set_base(layer
, 0);
736 nir_intrinsic_set_range(layer
, 20);
737 layer
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 16));
738 layer
->num_components
= 1;
739 nir_ssa_dest_init(&layer
->instr
, &layer
->dest
, 1, 32, "layer");
740 nir_builder_instr_insert(&b
, &layer
->instr
);
742 nir_ssa_def
*global_z
= nir_iadd(&b
, nir_channel(&b
, global_id
, 2), &layer
->dest
.ssa
);
744 nir_ssa_def
*comps
[4];
745 comps
[0] = nir_channel(&b
, global_id
, 0);
746 comps
[1] = nir_channel(&b
, global_id
, 1);
748 comps
[3] = nir_imm_int(&b
, 0);
749 global_id
= nir_vec(&b
, comps
, 4);
751 nir_intrinsic_instr
*store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_image_var_store
);
752 store
->src
[0] = nir_src_for_ssa(global_id
);
753 store
->src
[1] = nir_src_for_ssa(nir_ssa_undef(&b
, 1, 32));
754 store
->src
[2] = nir_src_for_ssa(&clear_val
->dest
.ssa
);
755 store
->variables
[0] = nir_deref_var_create(store
, output_img
);
757 nir_builder_instr_insert(&b
, &store
->instr
);
762 radv_device_init_meta_cleari_state(struct radv_device
*device
)
765 struct radv_shader_module cs
= { .nir
= NULL
};
766 struct radv_shader_module cs_3d
= { .nir
= NULL
};
767 cs
.nir
= build_nir_cleari_compute_shader(device
, false);
768 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
769 cs_3d
.nir
= build_nir_cleari_compute_shader(device
, true);
772 * two descriptors one for the image being sampled
773 * one for the buffer being written.
775 VkDescriptorSetLayoutCreateInfo ds_create_info
= {
776 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
777 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
779 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
782 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
,
783 .descriptorCount
= 1,
784 .stageFlags
= VK_SHADER_STAGE_COMPUTE_BIT
,
785 .pImmutableSamplers
= NULL
790 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
792 &device
->meta_state
.alloc
,
793 &device
->meta_state
.cleari
.img_ds_layout
);
794 if (result
!= VK_SUCCESS
)
798 VkPipelineLayoutCreateInfo pl_create_info
= {
799 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
801 .pSetLayouts
= &device
->meta_state
.cleari
.img_ds_layout
,
802 .pushConstantRangeCount
= 1,
803 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_COMPUTE_BIT
, 0, 20},
806 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
808 &device
->meta_state
.alloc
,
809 &device
->meta_state
.cleari
.img_p_layout
);
810 if (result
!= VK_SUCCESS
)
815 VkPipelineShaderStageCreateInfo pipeline_shader_stage
= {
816 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
817 .stage
= VK_SHADER_STAGE_COMPUTE_BIT
,
818 .module
= radv_shader_module_to_handle(&cs
),
820 .pSpecializationInfo
= NULL
,
823 VkComputePipelineCreateInfo vk_pipeline_info
= {
824 .sType
= VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
,
825 .stage
= pipeline_shader_stage
,
827 .layout
= device
->meta_state
.cleari
.img_p_layout
,
830 result
= radv_CreateComputePipelines(radv_device_to_handle(device
),
831 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
832 1, &vk_pipeline_info
, NULL
,
833 &device
->meta_state
.cleari
.pipeline
);
834 if (result
!= VK_SUCCESS
)
838 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
840 VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d
= {
841 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
842 .stage
= VK_SHADER_STAGE_COMPUTE_BIT
,
843 .module
= radv_shader_module_to_handle(&cs_3d
),
845 .pSpecializationInfo
= NULL
,
848 VkComputePipelineCreateInfo vk_pipeline_info_3d
= {
849 .sType
= VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
,
850 .stage
= pipeline_shader_stage_3d
,
852 .layout
= device
->meta_state
.cleari
.img_p_layout
,
855 result
= radv_CreateComputePipelines(radv_device_to_handle(device
),
856 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
857 1, &vk_pipeline_info_3d
, NULL
,
858 &device
->meta_state
.cleari
.pipeline_3d
);
859 if (result
!= VK_SUCCESS
)
862 ralloc_free(cs_3d
.nir
);
868 ralloc_free(cs_3d
.nir
);
873 radv_device_finish_meta_cleari_state(struct radv_device
*device
)
875 struct radv_meta_state
*state
= &device
->meta_state
;
877 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
878 state
->cleari
.img_p_layout
, &state
->alloc
);
879 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
880 state
->cleari
.img_ds_layout
,
882 radv_DestroyPipeline(radv_device_to_handle(device
),
883 state
->cleari
.pipeline
, &state
->alloc
);
884 radv_DestroyPipeline(radv_device_to_handle(device
),
885 state
->cleari
.pipeline_3d
, &state
->alloc
);
889 radv_device_finish_meta_bufimage_state(struct radv_device
*device
)
891 radv_device_finish_meta_itob_state(device
);
892 radv_device_finish_meta_btoi_state(device
);
893 radv_device_finish_meta_itoi_state(device
);
894 radv_device_finish_meta_cleari_state(device
);
898 radv_device_init_meta_bufimage_state(struct radv_device
*device
)
902 result
= radv_device_init_meta_itob_state(device
);
903 if (result
!= VK_SUCCESS
)
906 result
= radv_device_init_meta_btoi_state(device
);
907 if (result
!= VK_SUCCESS
)
910 result
= radv_device_init_meta_itoi_state(device
);
911 if (result
!= VK_SUCCESS
)
914 result
= radv_device_init_meta_cleari_state(device
);
915 if (result
!= VK_SUCCESS
)
920 radv_device_finish_meta_cleari_state(device
);
922 radv_device_finish_meta_itoi_state(device
);
924 radv_device_finish_meta_btoi_state(device
);
926 radv_device_finish_meta_itob_state(device
);
931 create_iview(struct radv_cmd_buffer
*cmd_buffer
,
932 struct radv_meta_blit2d_surf
*surf
,
933 struct radv_image_view
*iview
)
935 VkImageViewType view_type
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
< GFX9
? VK_IMAGE_VIEW_TYPE_2D
:
936 radv_meta_get_view_type(surf
->image
);
937 radv_image_view_init(iview
, cmd_buffer
->device
,
938 &(VkImageViewCreateInfo
) {
939 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
940 .image
= radv_image_to_handle(surf
->image
),
941 .viewType
= view_type
,
942 .format
= surf
->format
,
943 .subresourceRange
= {
944 .aspectMask
= surf
->aspect_mask
,
945 .baseMipLevel
= surf
->level
,
947 .baseArrayLayer
= surf
->layer
,
954 create_bview(struct radv_cmd_buffer
*cmd_buffer
,
955 struct radv_buffer
*buffer
,
958 struct radv_buffer_view
*bview
)
960 radv_buffer_view_init(bview
, cmd_buffer
->device
,
961 &(VkBufferViewCreateInfo
) {
962 .sType
= VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO
,
964 .buffer
= radv_buffer_to_handle(buffer
),
967 .range
= VK_WHOLE_SIZE
,
973 itob_bind_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
974 struct radv_image_view
*src
,
975 struct radv_buffer_view
*dst
)
977 struct radv_device
*device
= cmd_buffer
->device
;
979 radv_meta_push_descriptor_set(cmd_buffer
,
980 VK_PIPELINE_BIND_POINT_COMPUTE
,
981 device
->meta_state
.itob
.img_p_layout
,
983 2, /* descriptorWriteCount */
984 (VkWriteDescriptorSet
[]) {
986 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
988 .dstArrayElement
= 0,
989 .descriptorCount
= 1,
990 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
991 .pImageInfo
= (VkDescriptorImageInfo
[]) {
993 .sampler
= VK_NULL_HANDLE
,
994 .imageView
= radv_image_view_to_handle(src
),
995 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
1000 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
1002 .dstArrayElement
= 0,
1003 .descriptorCount
= 1,
1004 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
,
1005 .pTexelBufferView
= (VkBufferView
[]) { radv_buffer_view_to_handle(dst
) },
1011 radv_meta_image_to_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1012 struct radv_meta_blit2d_surf
*src
,
1013 struct radv_meta_blit2d_buffer
*dst
,
1015 struct radv_meta_blit2d_rect
*rects
)
1017 VkPipeline pipeline
= cmd_buffer
->device
->meta_state
.itob
.pipeline
;
1018 struct radv_device
*device
= cmd_buffer
->device
;
1019 struct radv_image_view src_view
;
1020 struct radv_buffer_view dst_view
;
1022 create_iview(cmd_buffer
, src
, &src_view
);
1023 create_bview(cmd_buffer
, dst
->buffer
, dst
->offset
, dst
->format
, &dst_view
);
1024 itob_bind_descriptors(cmd_buffer
, &src_view
, &dst_view
);
1026 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1027 src
->image
->type
== VK_IMAGE_TYPE_3D
)
1028 pipeline
= cmd_buffer
->device
->meta_state
.itob
.pipeline_3d
;
1030 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
1031 VK_PIPELINE_BIND_POINT_COMPUTE
, pipeline
);
1033 for (unsigned r
= 0; r
< num_rects
; ++r
) {
1034 unsigned push_constants
[4] = {
1040 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
1041 device
->meta_state
.itob
.img_p_layout
,
1042 VK_SHADER_STAGE_COMPUTE_BIT
, 0, 16,
1045 radv_unaligned_dispatch(cmd_buffer
, rects
[r
].width
, rects
[r
].height
, 1);
1050 btoi_bind_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1051 struct radv_buffer_view
*src
,
1052 struct radv_image_view
*dst
)
1054 struct radv_device
*device
= cmd_buffer
->device
;
1056 radv_meta_push_descriptor_set(cmd_buffer
,
1057 VK_PIPELINE_BIND_POINT_COMPUTE
,
1058 device
->meta_state
.btoi
.img_p_layout
,
1060 2, /* descriptorWriteCount */
1061 (VkWriteDescriptorSet
[]) {
1063 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
1065 .dstArrayElement
= 0,
1066 .descriptorCount
= 1,
1067 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
,
1068 .pTexelBufferView
= (VkBufferView
[]) { radv_buffer_view_to_handle(src
) },
1071 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
1073 .dstArrayElement
= 0,
1074 .descriptorCount
= 1,
1075 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
,
1076 .pImageInfo
= (VkDescriptorImageInfo
[]) {
1078 .sampler
= VK_NULL_HANDLE
,
1079 .imageView
= radv_image_view_to_handle(dst
),
1080 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
1088 radv_meta_buffer_to_image_cs(struct radv_cmd_buffer
*cmd_buffer
,
1089 struct radv_meta_blit2d_buffer
*src
,
1090 struct radv_meta_blit2d_surf
*dst
,
1092 struct radv_meta_blit2d_rect
*rects
)
1094 VkPipeline pipeline
= cmd_buffer
->device
->meta_state
.btoi
.pipeline
;
1095 struct radv_device
*device
= cmd_buffer
->device
;
1096 struct radv_buffer_view src_view
;
1097 struct radv_image_view dst_view
;
1099 create_bview(cmd_buffer
, src
->buffer
, src
->offset
, src
->format
, &src_view
);
1100 create_iview(cmd_buffer
, dst
, &dst_view
);
1101 btoi_bind_descriptors(cmd_buffer
, &src_view
, &dst_view
);
1103 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1104 dst
->image
->type
== VK_IMAGE_TYPE_3D
)
1105 pipeline
= cmd_buffer
->device
->meta_state
.btoi
.pipeline_3d
;
1106 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
1107 VK_PIPELINE_BIND_POINT_COMPUTE
, pipeline
);
1109 for (unsigned r
= 0; r
< num_rects
; ++r
) {
1110 unsigned push_constants
[4] = {
1116 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
1117 device
->meta_state
.btoi
.img_p_layout
,
1118 VK_SHADER_STAGE_COMPUTE_BIT
, 0, 16,
1121 radv_unaligned_dispatch(cmd_buffer
, rects
[r
].width
, rects
[r
].height
, 1);
1126 itoi_bind_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1127 struct radv_image_view
*src
,
1128 struct radv_image_view
*dst
)
1130 struct radv_device
*device
= cmd_buffer
->device
;
1132 radv_meta_push_descriptor_set(cmd_buffer
,
1133 VK_PIPELINE_BIND_POINT_COMPUTE
,
1134 device
->meta_state
.itoi
.img_p_layout
,
1136 2, /* descriptorWriteCount */
1137 (VkWriteDescriptorSet
[]) {
1139 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
1141 .dstArrayElement
= 0,
1142 .descriptorCount
= 1,
1143 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
1144 .pImageInfo
= (VkDescriptorImageInfo
[]) {
1146 .sampler
= VK_NULL_HANDLE
,
1147 .imageView
= radv_image_view_to_handle(src
),
1148 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
1153 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
1155 .dstArrayElement
= 0,
1156 .descriptorCount
= 1,
1157 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
,
1158 .pImageInfo
= (VkDescriptorImageInfo
[]) {
1160 .sampler
= VK_NULL_HANDLE
,
1161 .imageView
= radv_image_view_to_handle(dst
),
1162 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
1170 radv_meta_image_to_image_cs(struct radv_cmd_buffer
*cmd_buffer
,
1171 struct radv_meta_blit2d_surf
*src
,
1172 struct radv_meta_blit2d_surf
*dst
,
1174 struct radv_meta_blit2d_rect
*rects
)
1176 VkPipeline pipeline
= cmd_buffer
->device
->meta_state
.itoi
.pipeline
;
1177 struct radv_device
*device
= cmd_buffer
->device
;
1178 struct radv_image_view src_view
, dst_view
;
1180 create_iview(cmd_buffer
, src
, &src_view
);
1181 create_iview(cmd_buffer
, dst
, &dst_view
);
1183 itoi_bind_descriptors(cmd_buffer
, &src_view
, &dst_view
);
1185 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1186 src
->image
->type
== VK_IMAGE_TYPE_3D
)
1187 pipeline
= cmd_buffer
->device
->meta_state
.itoi
.pipeline_3d
;
1188 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
1189 VK_PIPELINE_BIND_POINT_COMPUTE
, pipeline
);
1191 for (unsigned r
= 0; r
< num_rects
; ++r
) {
1192 unsigned push_constants
[6] = {
1200 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
1201 device
->meta_state
.itoi
.img_p_layout
,
1202 VK_SHADER_STAGE_COMPUTE_BIT
, 0, 24,
1205 radv_unaligned_dispatch(cmd_buffer
, rects
[r
].width
, rects
[r
].height
, 1);
1210 cleari_bind_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1211 struct radv_image_view
*dst_iview
)
1213 struct radv_device
*device
= cmd_buffer
->device
;
1215 radv_meta_push_descriptor_set(cmd_buffer
,
1216 VK_PIPELINE_BIND_POINT_COMPUTE
,
1217 device
->meta_state
.cleari
.img_p_layout
,
1219 1, /* descriptorWriteCount */
1220 (VkWriteDescriptorSet
[]) {
1222 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
1224 .dstArrayElement
= 0,
1225 .descriptorCount
= 1,
1226 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
,
1227 .pImageInfo
= (VkDescriptorImageInfo
[]) {
1229 .sampler
= VK_NULL_HANDLE
,
1230 .imageView
= radv_image_view_to_handle(dst_iview
),
1231 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
1239 radv_meta_clear_image_cs(struct radv_cmd_buffer
*cmd_buffer
,
1240 struct radv_meta_blit2d_surf
*dst
,
1241 const VkClearColorValue
*clear_color
)
1243 VkPipeline pipeline
= cmd_buffer
->device
->meta_state
.cleari
.pipeline
;
1244 struct radv_device
*device
= cmd_buffer
->device
;
1245 struct radv_image_view dst_iview
;
1247 create_iview(cmd_buffer
, dst
, &dst_iview
);
1248 cleari_bind_descriptors(cmd_buffer
, &dst_iview
);
1250 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1251 dst
->image
->type
== VK_IMAGE_TYPE_3D
)
1252 pipeline
= cmd_buffer
->device
->meta_state
.cleari
.pipeline_3d
;
1254 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
1255 VK_PIPELINE_BIND_POINT_COMPUTE
, pipeline
);
1257 unsigned push_constants
[5] = {
1258 clear_color
->uint32
[0],
1259 clear_color
->uint32
[1],
1260 clear_color
->uint32
[2],
1261 clear_color
->uint32
[3],
1265 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
1266 device
->meta_state
.cleari
.img_p_layout
,
1267 VK_SHADER_STAGE_COMPUTE_BIT
, 0, 20,
1270 radv_unaligned_dispatch(cmd_buffer
, dst
->image
->info
.width
, dst
->image
->info
.height
, 1);