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06485137fc7baa8b48a60ee29405b9826decb1c2
[mesa.git] / src / amd / vulkan / radv_meta_clear.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_meta.h"
25 #include "radv_private.h"
26 #include "nir/nir_builder.h"
27
28 #include "util/format_rgb9e5.h"
29 #include "vk_format.h"
30
31 enum {
32 DEPTH_CLEAR_SLOW,
33 DEPTH_CLEAR_FAST_EXPCLEAR,
34 DEPTH_CLEAR_FAST_NO_EXPCLEAR
35 };
36
37 static void
38 build_color_shaders(struct nir_shader **out_vs,
39 struct nir_shader **out_fs,
40 uint32_t frag_output)
41 {
42 nir_builder vs_b;
43 nir_builder fs_b;
44
45 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
46 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
47
48 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
49 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
50
51 const struct glsl_type *position_type = glsl_vec4_type();
52 const struct glsl_type *color_type = glsl_vec4_type();
53
54 nir_variable *vs_out_pos =
55 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
56 "gl_Position");
57 vs_out_pos->data.location = VARYING_SLOT_POS;
58
59 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
60 nir_intrinsic_set_base(in_color_load, 0);
61 nir_intrinsic_set_range(in_color_load, 16);
62 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
63 in_color_load->num_components = 4;
64 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
65 nir_builder_instr_insert(&fs_b, &in_color_load->instr);
66
67 nir_variable *fs_out_color =
68 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
69 "f_color");
70 fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
71
72 nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
73
74 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
75 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
76
77 const struct glsl_type *layer_type = glsl_int_type();
78 nir_variable *vs_out_layer =
79 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
80 "v_layer");
81 vs_out_layer->data.location = VARYING_SLOT_LAYER;
82 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
83 nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
84
85 nir_store_var(&vs_b, vs_out_layer, inst_id, 0x1);
86
87 *out_vs = vs_b.shader;
88 *out_fs = fs_b.shader;
89 }
90
91 static VkResult
92 create_pipeline(struct radv_device *device,
93 struct radv_render_pass *render_pass,
94 uint32_t samples,
95 struct nir_shader *vs_nir,
96 struct nir_shader *fs_nir,
97 const VkPipelineVertexInputStateCreateInfo *vi_state,
98 const VkPipelineDepthStencilStateCreateInfo *ds_state,
99 const VkPipelineColorBlendStateCreateInfo *cb_state,
100 const VkPipelineLayout layout,
101 const struct radv_graphics_pipeline_create_info *extra,
102 const VkAllocationCallbacks *alloc,
103 struct radv_pipeline **pipeline)
104 {
105 VkDevice device_h = radv_device_to_handle(device);
106 VkResult result;
107
108 struct radv_shader_module vs_m = { .nir = vs_nir };
109 struct radv_shader_module fs_m = { .nir = fs_nir };
110
111 VkPipeline pipeline_h = VK_NULL_HANDLE;
112 result = radv_graphics_pipeline_create(device_h,
113 radv_pipeline_cache_to_handle(&device->meta_state.cache),
114 &(VkGraphicsPipelineCreateInfo) {
115 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
116 .stageCount = fs_nir ? 2 : 1,
117 .pStages = (VkPipelineShaderStageCreateInfo[]) {
118 {
119 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
120 .stage = VK_SHADER_STAGE_VERTEX_BIT,
121 .module = radv_shader_module_to_handle(&vs_m),
122 .pName = "main",
123 },
124 {
125 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
126 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
127 .module = radv_shader_module_to_handle(&fs_m),
128 .pName = "main",
129 },
130 },
131 .pVertexInputState = vi_state,
132 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
133 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
134 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
135 .primitiveRestartEnable = false,
136 },
137 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
138 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
139 .viewportCount = 1,
140 .scissorCount = 1,
141 },
142 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
143 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
144 .rasterizerDiscardEnable = false,
145 .polygonMode = VK_POLYGON_MODE_FILL,
146 .cullMode = VK_CULL_MODE_NONE,
147 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
148 .depthBiasEnable = false,
149 },
150 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
151 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
152 .rasterizationSamples = samples,
153 .sampleShadingEnable = false,
154 .pSampleMask = NULL,
155 .alphaToCoverageEnable = false,
156 .alphaToOneEnable = false,
157 },
158 .pDepthStencilState = ds_state,
159 .pColorBlendState = cb_state,
160 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
161 /* The meta clear pipeline declares all state as dynamic.
162 * As a consequence, vkCmdBindPipeline writes no dynamic state
163 * to the cmd buffer. Therefore, at the end of the meta clear,
164 * we need only restore dynamic state was vkCmdSet.
165 */
166 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
167 .dynamicStateCount = 8,
168 .pDynamicStates = (VkDynamicState[]) {
169 /* Everything except stencil write mask */
170 VK_DYNAMIC_STATE_VIEWPORT,
171 VK_DYNAMIC_STATE_SCISSOR,
172 VK_DYNAMIC_STATE_LINE_WIDTH,
173 VK_DYNAMIC_STATE_DEPTH_BIAS,
174 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
175 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
176 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
177 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
178 },
179 },
180 .layout = layout,
181 .flags = 0,
182 .renderPass = radv_render_pass_to_handle(render_pass),
183 .subpass = 0,
184 },
185 extra,
186 alloc,
187 &pipeline_h);
188
189 ralloc_free(vs_nir);
190 ralloc_free(fs_nir);
191
192 *pipeline = radv_pipeline_from_handle(pipeline_h);
193
194 return result;
195 }
196
197 static VkResult
198 create_color_renderpass(struct radv_device *device,
199 VkFormat vk_format,
200 uint32_t samples,
201 VkRenderPass *pass)
202 {
203 return radv_CreateRenderPass(radv_device_to_handle(device),
204 &(VkRenderPassCreateInfo) {
205 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
206 .attachmentCount = 1,
207 .pAttachments = &(VkAttachmentDescription) {
208 .format = vk_format,
209 .samples = samples,
210 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
211 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
212 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
213 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
214 },
215 .subpassCount = 1,
216 .pSubpasses = &(VkSubpassDescription) {
217 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
218 .inputAttachmentCount = 0,
219 .colorAttachmentCount = 1,
220 .pColorAttachments = &(VkAttachmentReference) {
221 .attachment = 0,
222 .layout = VK_IMAGE_LAYOUT_GENERAL,
223 },
224 .pResolveAttachments = NULL,
225 .pDepthStencilAttachment = &(VkAttachmentReference) {
226 .attachment = VK_ATTACHMENT_UNUSED,
227 .layout = VK_IMAGE_LAYOUT_GENERAL,
228 },
229 .preserveAttachmentCount = 1,
230 .pPreserveAttachments = (uint32_t[]) { 0 },
231 },
232 .dependencyCount = 0,
233 }, &device->meta_state.alloc, pass);
234 }
235
236 static VkResult
237 create_color_pipeline(struct radv_device *device,
238 uint32_t samples,
239 uint32_t frag_output,
240 struct radv_pipeline **pipeline,
241 VkRenderPass pass)
242 {
243 struct nir_shader *vs_nir;
244 struct nir_shader *fs_nir;
245 VkResult result;
246 build_color_shaders(&vs_nir, &fs_nir, frag_output);
247
248 const VkPipelineVertexInputStateCreateInfo vi_state = {
249 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
250 .vertexBindingDescriptionCount = 0,
251 .vertexAttributeDescriptionCount = 0,
252 };
253
254 const VkPipelineDepthStencilStateCreateInfo ds_state = {
255 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
256 .depthTestEnable = false,
257 .depthWriteEnable = false,
258 .depthBoundsTestEnable = false,
259 .stencilTestEnable = false,
260 };
261
262 VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
263 blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
264 .blendEnable = false,
265 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
266 VK_COLOR_COMPONENT_R_BIT |
267 VK_COLOR_COMPONENT_G_BIT |
268 VK_COLOR_COMPONENT_B_BIT,
269 };
270
271 const VkPipelineColorBlendStateCreateInfo cb_state = {
272 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
273 .logicOpEnable = false,
274 .attachmentCount = MAX_RTS,
275 .pAttachments = blend_attachment_state
276 };
277
278
279 struct radv_graphics_pipeline_create_info extra = {
280 .use_rectlist = true,
281 };
282 result = create_pipeline(device, radv_render_pass_from_handle(pass),
283 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
284 device->meta_state.clear_color_p_layout,
285 &extra, &device->meta_state.alloc, pipeline);
286
287 return result;
288 }
289
290 static void
291 destroy_pipeline(struct radv_device *device, struct radv_pipeline *pipeline)
292 {
293 if (!pipeline)
294 return;
295
296 radv_DestroyPipeline(radv_device_to_handle(device),
297 radv_pipeline_to_handle(pipeline),
298 &device->meta_state.alloc);
299
300 }
301
302 static void
303 destroy_render_pass(struct radv_device *device, VkRenderPass renderpass)
304 {
305 radv_DestroyRenderPass(radv_device_to_handle(device), renderpass,
306 &device->meta_state.alloc);
307 }
308
309 void
310 radv_device_finish_meta_clear_state(struct radv_device *device)
311 {
312 struct radv_meta_state *state = &device->meta_state;
313
314 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
315 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
316 destroy_pipeline(device, state->clear[i].color_pipelines[j]);
317 destroy_render_pass(device, state->clear[i].render_pass[j]);
318 }
319
320 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
321 destroy_pipeline(device, state->clear[i].depth_only_pipeline[j]);
322 destroy_pipeline(device, state->clear[i].stencil_only_pipeline[j]);
323 destroy_pipeline(device, state->clear[i].depthstencil_pipeline[j]);
324 }
325 destroy_render_pass(device, state->clear[i].depthstencil_rp);
326 }
327 radv_DestroyPipelineLayout(radv_device_to_handle(device),
328 state->clear_color_p_layout,
329 &state->alloc);
330 radv_DestroyPipelineLayout(radv_device_to_handle(device),
331 state->clear_depth_p_layout,
332 &state->alloc);
333 }
334
335 static void
336 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
337 const VkClearAttachment *clear_att,
338 const VkClearRect *clear_rect)
339 {
340 struct radv_device *device = cmd_buffer->device;
341 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
342 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
343 const uint32_t subpass_att = clear_att->colorAttachment;
344 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
345 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
346 const uint32_t samples = iview->image->info.samples;
347 const uint32_t samples_log2 = ffs(samples) - 1;
348 unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
349 struct radv_pipeline *pipeline;
350 VkClearColorValue clear_value = clear_att->clearValue.color;
351 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
352 VkPipeline pipeline_h;
353
354 if (fs_key == -1) {
355 radv_finishme("color clears incomplete");
356 return;
357 }
358 pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
359 pipeline_h = radv_pipeline_to_handle(pipeline);
360
361 if (!pipeline) {
362 radv_finishme("color clears incomplete");
363 return;
364 }
365 assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
366 assert(pipeline);
367 assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
368 assert(clear_att->colorAttachment < subpass->color_count);
369
370 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
371 device->meta_state.clear_color_p_layout,
372 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
373 &clear_value);
374
375 struct radv_subpass clear_subpass = {
376 .color_count = 1,
377 .color_attachments = (VkAttachmentReference[]) {
378 subpass->color_attachments[clear_att->colorAttachment]
379 },
380 .depth_stencil_attachment = (VkAttachmentReference) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
381 };
382
383 radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
384
385 if (cmd_buffer->state.pipeline != pipeline) {
386 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
387 pipeline_h);
388 }
389
390 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
391 .x = clear_rect->rect.offset.x,
392 .y = clear_rect->rect.offset.y,
393 .width = clear_rect->rect.extent.width,
394 .height = clear_rect->rect.extent.height,
395 .minDepth = 0.0f,
396 .maxDepth = 1.0f
397 });
398
399 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
400
401 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, 0);
402
403 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
404 }
405
406
407 static void
408 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
409 {
410 nir_builder vs_b, fs_b;
411
412 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
413 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
414
415 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
416 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
417 const struct glsl_type *position_out_type = glsl_vec4_type();
418
419 nir_variable *vs_out_pos =
420 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
421 "gl_Position");
422 vs_out_pos->data.location = VARYING_SLOT_POS;
423
424 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
425 nir_intrinsic_set_base(in_color_load, 0);
426 nir_intrinsic_set_range(in_color_load, 4);
427 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
428 in_color_load->num_components = 1;
429 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
430 nir_builder_instr_insert(&vs_b, &in_color_load->instr);
431
432 nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
433 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
434
435 const struct glsl_type *layer_type = glsl_int_type();
436 nir_variable *vs_out_layer =
437 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
438 "v_layer");
439 vs_out_layer->data.location = VARYING_SLOT_LAYER;
440 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
441 nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
442 nir_store_var(&vs_b, vs_out_layer, inst_id, 0x1);
443
444 *out_vs = vs_b.shader;
445 *out_fs = fs_b.shader;
446 }
447
448 static VkResult
449 create_depthstencil_renderpass(struct radv_device *device,
450 uint32_t samples,
451 VkRenderPass *render_pass)
452 {
453 return radv_CreateRenderPass(radv_device_to_handle(device),
454 &(VkRenderPassCreateInfo) {
455 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
456 .attachmentCount = 1,
457 .pAttachments = &(VkAttachmentDescription) {
458 .format = VK_FORMAT_UNDEFINED,
459 .samples = samples,
460 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
461 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
462 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
463 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
464 },
465 .subpassCount = 1,
466 .pSubpasses = &(VkSubpassDescription) {
467 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
468 .inputAttachmentCount = 0,
469 .colorAttachmentCount = 0,
470 .pColorAttachments = NULL,
471 .pResolveAttachments = NULL,
472 .pDepthStencilAttachment = &(VkAttachmentReference) {
473 .attachment = 0,
474 .layout = VK_IMAGE_LAYOUT_GENERAL,
475 },
476 .preserveAttachmentCount = 1,
477 .pPreserveAttachments = (uint32_t[]) { 0 },
478 },
479 .dependencyCount = 0,
480 }, &device->meta_state.alloc, render_pass);
481 }
482
483 static VkResult
484 create_depthstencil_pipeline(struct radv_device *device,
485 VkImageAspectFlags aspects,
486 uint32_t samples,
487 int index,
488 struct radv_pipeline **pipeline,
489 VkRenderPass render_pass)
490 {
491 struct nir_shader *vs_nir, *fs_nir;
492 VkResult result;
493 build_depthstencil_shader(&vs_nir, &fs_nir);
494
495 const VkPipelineVertexInputStateCreateInfo vi_state = {
496 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
497 .vertexBindingDescriptionCount = 0,
498 .vertexAttributeDescriptionCount = 0,
499 };
500
501 const VkPipelineDepthStencilStateCreateInfo ds_state = {
502 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
503 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
504 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
505 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
506 .depthBoundsTestEnable = false,
507 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
508 .front = {
509 .passOp = VK_STENCIL_OP_REPLACE,
510 .compareOp = VK_COMPARE_OP_ALWAYS,
511 .writeMask = UINT32_MAX,
512 .reference = 0, /* dynamic */
513 },
514 .back = { 0 /* dont care */ },
515 };
516
517 const VkPipelineColorBlendStateCreateInfo cb_state = {
518 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
519 .logicOpEnable = false,
520 .attachmentCount = 0,
521 .pAttachments = NULL,
522 };
523
524 struct radv_graphics_pipeline_create_info extra = {
525 .use_rectlist = true,
526 };
527
528 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
529 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
530 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
531 }
532 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
533 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
534 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
535 }
536 result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
537 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
538 device->meta_state.clear_depth_p_layout,
539 &extra, &device->meta_state.alloc, pipeline);
540 return result;
541 }
542
543 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
544 const struct radv_image_view *iview,
545 VkImageLayout layout,
546 const VkClearRect *clear_rect)
547 {
548 uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
549 cmd_buffer->queue_family_index,
550 cmd_buffer->queue_family_index);
551 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
552 clear_rect->rect.extent.width != iview->extent.width ||
553 clear_rect->rect.extent.height != iview->extent.height)
554 return false;
555 if (iview->image->surface.htile_size &&
556 iview->base_mip == 0 &&
557 iview->base_layer == 0 &&
558 radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
559 !radv_image_extent_compare(iview->image, &iview->extent))
560 return true;
561 return false;
562 }
563
564 static struct radv_pipeline *
565 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
566 struct radv_meta_state *meta_state,
567 const struct radv_image_view *iview,
568 int samples_log2,
569 VkImageAspectFlags aspects,
570 VkImageLayout layout,
571 const VkClearRect *clear_rect,
572 VkClearDepthStencilValue clear_value)
573 {
574 bool fast = depth_view_can_fast_clear(cmd_buffer, iview, layout, clear_rect);
575 int index = DEPTH_CLEAR_SLOW;
576
577 if (fast) {
578 /* we don't know the previous clear values, so we always have
579 * the NO_EXPCLEAR path */
580 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
581 }
582
583 switch (aspects) {
584 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
585 return meta_state->clear[samples_log2].depthstencil_pipeline[index];
586 case VK_IMAGE_ASPECT_DEPTH_BIT:
587 return meta_state->clear[samples_log2].depth_only_pipeline[index];
588 case VK_IMAGE_ASPECT_STENCIL_BIT:
589 return meta_state->clear[samples_log2].stencil_only_pipeline[index];
590 }
591 unreachable("expected depth or stencil aspect");
592 }
593
594 static void
595 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
596 const VkClearAttachment *clear_att,
597 const VkClearRect *clear_rect)
598 {
599 struct radv_device *device = cmd_buffer->device;
600 struct radv_meta_state *meta_state = &device->meta_state;
601 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
602 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
603 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
604 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
605 VkImageAspectFlags aspects = clear_att->aspectMask;
606 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
607 const uint32_t samples = iview->image->info.samples;
608 const uint32_t samples_log2 = ffs(samples) - 1;
609 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
610
611 assert(aspects == VK_IMAGE_ASPECT_DEPTH_BIT ||
612 aspects == VK_IMAGE_ASPECT_STENCIL_BIT ||
613 aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
614 VK_IMAGE_ASPECT_STENCIL_BIT));
615 assert(pass_att != VK_ATTACHMENT_UNUSED);
616
617 if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
618 clear_value.depth = 1.0f;
619
620 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
621 device->meta_state.clear_depth_p_layout,
622 VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
623 &clear_value.depth);
624
625 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
626 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
627 clear_value.stencil);
628 }
629
630 struct radv_pipeline *pipeline = pick_depthstencil_pipeline(cmd_buffer,
631 meta_state,
632 iview,
633 samples_log2,
634 aspects,
635 subpass->depth_stencil_attachment.layout,
636 clear_rect,
637 clear_value);
638 if (cmd_buffer->state.pipeline != pipeline) {
639 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
640 radv_pipeline_to_handle(pipeline));
641 }
642
643 if (depth_view_can_fast_clear(cmd_buffer, iview, subpass->depth_stencil_attachment.layout, clear_rect))
644 radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
645
646 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
647 .x = clear_rect->rect.offset.x,
648 .y = clear_rect->rect.offset.y,
649 .width = clear_rect->rect.extent.width,
650 .height = clear_rect->rect.extent.height,
651 .minDepth = 0.0f,
652 .maxDepth = 1.0f
653 });
654
655 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
656
657 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, 0);
658 }
659
660 static bool
661 emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
662 const VkClearAttachment *clear_att,
663 const VkClearRect *clear_rect,
664 enum radv_cmd_flush_bits *pre_flush,
665 enum radv_cmd_flush_bits *post_flush)
666 {
667 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
668 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
669 VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
670 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
671 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
672 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
673 VkImageAspectFlags aspects = clear_att->aspectMask;
674 uint32_t clear_word;
675
676 if (!iview->image->surface.htile_size)
677 return false;
678
679 if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
680 return false;
681
682 if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
683 goto fail;
684
685 /* don't fast clear 3D */
686 if (iview->image->type == VK_IMAGE_TYPE_3D)
687 goto fail;
688
689 /* all layers are bound */
690 if (iview->base_layer > 0)
691 goto fail;
692 if (iview->image->info.array_size != iview->layer_count)
693 goto fail;
694
695 if (iview->image->info.levels > 1)
696 goto fail;
697
698 if (!radv_image_extent_compare(iview->image, &iview->extent))
699 goto fail;
700
701 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
702 clear_rect->rect.extent.width != iview->image->info.width ||
703 clear_rect->rect.extent.height != iview->image->info.height)
704 goto fail;
705
706 if (clear_rect->baseArrayLayer != 0)
707 goto fail;
708 if (clear_rect->layerCount != iview->image->info.array_size)
709 goto fail;
710
711 /* Don't do stencil clears till we have figured out if the clear words are
712 * correct. */
713 if (vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT)
714 goto fail;
715
716 if (clear_value.depth == 1.0)
717 clear_word = 0xfffffff0;
718 else if (clear_value.depth == 0.0)
719 clear_word = 0;
720 else
721 goto fail;
722
723 if (pre_flush) {
724 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
725 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
726 *pre_flush |= cmd_buffer->state.flush_bits;
727 } else
728 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
729 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
730
731 radv_fill_buffer(cmd_buffer, iview->image->bo,
732 iview->image->offset + iview->image->htile_offset,
733 iview->image->surface.htile_size, clear_word);
734
735
736 radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
737 if (post_flush)
738 *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
739 RADV_CMD_FLAG_INV_VMEM_L1 |
740 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
741 else
742 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
743 RADV_CMD_FLAG_INV_VMEM_L1 |
744 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
745 return true;
746 fail:
747 return false;
748 }
749
750 static VkFormat pipeline_formats[] = {
751 VK_FORMAT_R8G8B8A8_UNORM,
752 VK_FORMAT_R8G8B8A8_UINT,
753 VK_FORMAT_R8G8B8A8_SINT,
754 VK_FORMAT_R16G16B16A16_UNORM,
755 VK_FORMAT_R16G16B16A16_SNORM,
756 VK_FORMAT_R16G16B16A16_UINT,
757 VK_FORMAT_R16G16B16A16_SINT,
758 VK_FORMAT_R32_SFLOAT,
759 VK_FORMAT_R32G32_SFLOAT,
760 VK_FORMAT_R32G32B32A32_SFLOAT
761 };
762
763 VkResult
764 radv_device_init_meta_clear_state(struct radv_device *device)
765 {
766 VkResult res;
767 struct radv_meta_state *state = &device->meta_state;
768
769 memset(&device->meta_state.clear, 0, sizeof(device->meta_state.clear));
770
771 VkPipelineLayoutCreateInfo pl_color_create_info = {
772 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
773 .setLayoutCount = 0,
774 .pushConstantRangeCount = 1,
775 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
776 };
777
778 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
779 &pl_color_create_info,
780 &device->meta_state.alloc,
781 &device->meta_state.clear_color_p_layout);
782 if (res != VK_SUCCESS)
783 goto fail;
784
785 VkPipelineLayoutCreateInfo pl_depth_create_info = {
786 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
787 .setLayoutCount = 0,
788 .pushConstantRangeCount = 1,
789 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
790 };
791
792 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
793 &pl_depth_create_info,
794 &device->meta_state.alloc,
795 &device->meta_state.clear_depth_p_layout);
796 if (res != VK_SUCCESS)
797 goto fail;
798
799 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
800 uint32_t samples = 1 << i;
801 for (uint32_t j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
802 VkFormat format = pipeline_formats[j];
803 unsigned fs_key = radv_format_meta_fs_key(format);
804 assert(!state->clear[i].color_pipelines[fs_key]);
805
806 res = create_color_renderpass(device, format, samples,
807 &state->clear[i].render_pass[fs_key]);
808 if (res != VK_SUCCESS)
809 goto fail;
810
811 res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
812 state->clear[i].render_pass[fs_key]);
813 if (res != VK_SUCCESS)
814 goto fail;
815
816 }
817
818 res = create_depthstencil_renderpass(device,
819 samples,
820 &state->clear[i].depthstencil_rp);
821 if (res != VK_SUCCESS)
822 goto fail;
823
824 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
825 res = create_depthstencil_pipeline(device,
826 VK_IMAGE_ASPECT_DEPTH_BIT,
827 samples,
828 j,
829 &state->clear[i].depth_only_pipeline[j],
830 state->clear[i].depthstencil_rp);
831 if (res != VK_SUCCESS)
832 goto fail;
833
834 res = create_depthstencil_pipeline(device,
835 VK_IMAGE_ASPECT_STENCIL_BIT,
836 samples,
837 j,
838 &state->clear[i].stencil_only_pipeline[j],
839 state->clear[i].depthstencil_rp);
840 if (res != VK_SUCCESS)
841 goto fail;
842
843 res = create_depthstencil_pipeline(device,
844 VK_IMAGE_ASPECT_DEPTH_BIT |
845 VK_IMAGE_ASPECT_STENCIL_BIT,
846 samples,
847 j,
848 &state->clear[i].depthstencil_pipeline[j],
849 state->clear[i].depthstencil_rp);
850 if (res != VK_SUCCESS)
851 goto fail;
852 }
853 }
854 return VK_SUCCESS;
855
856 fail:
857 radv_device_finish_meta_clear_state(device);
858 return res;
859 }
860
861 static bool
862 emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
863 const VkClearAttachment *clear_att,
864 const VkClearRect *clear_rect,
865 enum radv_cmd_flush_bits *pre_flush,
866 enum radv_cmd_flush_bits *post_flush)
867 {
868 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
869 const uint32_t subpass_att = clear_att->colorAttachment;
870 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
871 VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
872 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
873 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
874 VkClearColorValue clear_value = clear_att->clearValue.color;
875 uint32_t clear_color[2];
876 bool ret;
877
878 if (!iview->image->cmask.size && !iview->image->surface.dcc_size)
879 return false;
880
881 if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
882 return false;
883
884 if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
885 goto fail;
886 if (vk_format_get_blocksizebits(iview->image->vk_format) > 64)
887 goto fail;
888
889 /* don't fast clear 3D */
890 if (iview->image->type == VK_IMAGE_TYPE_3D)
891 goto fail;
892
893 /* all layers are bound */
894 if (iview->base_layer > 0)
895 goto fail;
896 if (iview->image->info.array_size != iview->layer_count)
897 goto fail;
898
899 if (iview->image->info.levels > 1)
900 goto fail;
901
902 if (iview->image->surface.u.legacy.level[0].mode < RADEON_SURF_MODE_1D)
903 goto fail;
904 if (!radv_image_extent_compare(iview->image, &iview->extent))
905 goto fail;
906
907 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
908 clear_rect->rect.extent.width != iview->image->info.width ||
909 clear_rect->rect.extent.height != iview->image->info.height)
910 goto fail;
911
912 if (clear_rect->baseArrayLayer != 0)
913 goto fail;
914 if (clear_rect->layerCount != iview->image->info.array_size)
915 goto fail;
916
917 /* RB+ doesn't work with CMASK fast clear on Stoney. */
918 if (!iview->image->surface.dcc_size &&
919 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY)
920 goto fail;
921
922 /* DCC */
923 ret = radv_format_pack_clear_color(iview->image->vk_format,
924 clear_color, &clear_value);
925 if (ret == false)
926 goto fail;
927
928 if (pre_flush) {
929 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
930 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
931 *pre_flush |= cmd_buffer->state.flush_bits;
932 } else
933 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
934 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
935 /* clear cmask buffer */
936 if (iview->image->surface.dcc_size) {
937 radv_fill_buffer(cmd_buffer, iview->image->bo,
938 iview->image->offset + iview->image->dcc_offset,
939 iview->image->surface.dcc_size, 0x20202020);
940 } else {
941 radv_fill_buffer(cmd_buffer, iview->image->bo,
942 iview->image->offset + iview->image->cmask.offset,
943 iview->image->cmask.size, 0);
944 }
945
946 if (post_flush)
947 *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
948 RADV_CMD_FLAG_INV_VMEM_L1 |
949 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
950 else
951 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
952 RADV_CMD_FLAG_INV_VMEM_L1 |
953 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
954
955 radv_set_color_clear_regs(cmd_buffer, iview->image, subpass_att, clear_color);
956
957 return true;
958 fail:
959 return false;
960 }
961
962 /**
963 * The parameters mean that same as those in vkCmdClearAttachments.
964 */
965 static void
966 emit_clear(struct radv_cmd_buffer *cmd_buffer,
967 const VkClearAttachment *clear_att,
968 const VkClearRect *clear_rect,
969 enum radv_cmd_flush_bits *pre_flush,
970 enum radv_cmd_flush_bits *post_flush)
971 {
972 if (clear_att->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
973
974 if (!emit_fast_color_clear(cmd_buffer, clear_att, clear_rect,
975 pre_flush, post_flush))
976 emit_color_clear(cmd_buffer, clear_att, clear_rect);
977 } else {
978 assert(clear_att->aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT |
979 VK_IMAGE_ASPECT_STENCIL_BIT));
980 if (!emit_fast_htile_clear(cmd_buffer, clear_att, clear_rect,
981 pre_flush, post_flush))
982 emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
983 }
984 }
985
986 static bool
987 subpass_needs_clear(const struct radv_cmd_buffer *cmd_buffer)
988 {
989 const struct radv_cmd_state *cmd_state = &cmd_buffer->state;
990 uint32_t ds;
991
992 if (!cmd_state->subpass)
993 return false;
994 ds = cmd_state->subpass->depth_stencil_attachment.attachment;
995 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
996 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
997 if (cmd_state->attachments[a].pending_clear_aspects) {
998 return true;
999 }
1000 }
1001
1002 if (ds != VK_ATTACHMENT_UNUSED &&
1003 cmd_state->attachments[ds].pending_clear_aspects) {
1004 return true;
1005 }
1006
1007 return false;
1008 }
1009
1010 /**
1011 * Emit any pending attachment clears for the current subpass.
1012 *
1013 * @see radv_attachment_state::pending_clear_aspects
1014 */
1015 void
1016 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1017 {
1018 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1019 struct radv_meta_saved_state saved_state;
1020 enum radv_cmd_flush_bits pre_flush = 0;
1021 enum radv_cmd_flush_bits post_flush = 0;
1022
1023 if (!subpass_needs_clear(cmd_buffer))
1024 return;
1025
1026 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
1027
1028 VkClearRect clear_rect = {
1029 .rect = cmd_state->render_area,
1030 .baseArrayLayer = 0,
1031 .layerCount = cmd_state->framebuffer->layers,
1032 };
1033
1034 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1035 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1036
1037 if (!cmd_state->attachments[a].pending_clear_aspects)
1038 continue;
1039
1040 assert(cmd_state->attachments[a].pending_clear_aspects ==
1041 VK_IMAGE_ASPECT_COLOR_BIT);
1042
1043 VkClearAttachment clear_att = {
1044 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1045 .colorAttachment = i, /* Use attachment index relative to subpass */
1046 .clearValue = cmd_state->attachments[a].clear_value,
1047 };
1048
1049 emit_clear(cmd_buffer, &clear_att, &clear_rect, &pre_flush, &post_flush);
1050 cmd_state->attachments[a].pending_clear_aspects = 0;
1051 }
1052
1053 uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1054
1055 if (ds != VK_ATTACHMENT_UNUSED) {
1056
1057 if (cmd_state->attachments[ds].pending_clear_aspects) {
1058
1059 VkClearAttachment clear_att = {
1060 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1061 .clearValue = cmd_state->attachments[ds].clear_value,
1062 };
1063
1064 emit_clear(cmd_buffer, &clear_att, &clear_rect,
1065 &pre_flush, &post_flush);
1066 cmd_state->attachments[ds].pending_clear_aspects = 0;
1067 }
1068 }
1069
1070 radv_meta_restore(&saved_state, cmd_buffer);
1071 cmd_buffer->state.flush_bits |= post_flush;
1072 }
1073
1074 static void
1075 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1076 struct radv_image *image,
1077 VkImageLayout image_layout,
1078 const VkImageSubresourceRange *range,
1079 VkFormat format, int level, int layer,
1080 const VkClearValue *clear_val)
1081 {
1082 VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1083 struct radv_image_view iview;
1084 radv_image_view_init(&iview, cmd_buffer->device,
1085 &(VkImageViewCreateInfo) {
1086 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1087 .image = radv_image_to_handle(image),
1088 .viewType = radv_meta_get_view_type(image),
1089 .format = format,
1090 .subresourceRange = {
1091 .aspectMask = range->aspectMask,
1092 .baseMipLevel = range->baseMipLevel + level,
1093 .levelCount = 1,
1094 .baseArrayLayer = range->baseArrayLayer + layer,
1095 .layerCount = 1
1096 },
1097 });
1098
1099 VkFramebuffer fb;
1100 radv_CreateFramebuffer(device_h,
1101 &(VkFramebufferCreateInfo) {
1102 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1103 .attachmentCount = 1,
1104 .pAttachments = (VkImageView[]) {
1105 radv_image_view_to_handle(&iview),
1106 },
1107 .width = iview.extent.width,
1108 .height = iview.extent.height,
1109 .layers = 1
1110 },
1111 &cmd_buffer->pool->alloc,
1112 &fb);
1113
1114 VkAttachmentDescription att_desc = {
1115 .format = iview.vk_format,
1116 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1117 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1118 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1119 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1120 .initialLayout = image_layout,
1121 .finalLayout = image_layout,
1122 };
1123
1124 VkSubpassDescription subpass_desc = {
1125 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1126 .inputAttachmentCount = 0,
1127 .colorAttachmentCount = 0,
1128 .pColorAttachments = NULL,
1129 .pResolveAttachments = NULL,
1130 .pDepthStencilAttachment = NULL,
1131 .preserveAttachmentCount = 0,
1132 .pPreserveAttachments = NULL,
1133 };
1134
1135 const VkAttachmentReference att_ref = {
1136 .attachment = 0,
1137 .layout = image_layout,
1138 };
1139
1140 if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1141 subpass_desc.colorAttachmentCount = 1;
1142 subpass_desc.pColorAttachments = &att_ref;
1143 } else {
1144 subpass_desc.pDepthStencilAttachment = &att_ref;
1145 }
1146
1147 VkRenderPass pass;
1148 radv_CreateRenderPass(device_h,
1149 &(VkRenderPassCreateInfo) {
1150 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1151 .attachmentCount = 1,
1152 .pAttachments = &att_desc,
1153 .subpassCount = 1,
1154 .pSubpasses = &subpass_desc,
1155 },
1156 &cmd_buffer->pool->alloc,
1157 &pass);
1158
1159 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1160 &(VkRenderPassBeginInfo) {
1161 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1162 .renderArea = {
1163 .offset = { 0, 0, },
1164 .extent = {
1165 .width = iview.extent.width,
1166 .height = iview.extent.height,
1167 },
1168 },
1169 .renderPass = pass,
1170 .framebuffer = fb,
1171 .clearValueCount = 0,
1172 .pClearValues = NULL,
1173 },
1174 VK_SUBPASS_CONTENTS_INLINE);
1175
1176 VkClearAttachment clear_att = {
1177 .aspectMask = range->aspectMask,
1178 .colorAttachment = 0,
1179 .clearValue = *clear_val,
1180 };
1181
1182 VkClearRect clear_rect = {
1183 .rect = {
1184 .offset = { 0, 0 },
1185 .extent = { iview.extent.width, iview.extent.height },
1186 },
1187 .baseArrayLayer = range->baseArrayLayer,
1188 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1189 };
1190
1191 emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL);
1192
1193 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1194 radv_DestroyRenderPass(device_h, pass,
1195 &cmd_buffer->pool->alloc);
1196 radv_DestroyFramebuffer(device_h, fb,
1197 &cmd_buffer->pool->alloc);
1198 }
1199 static void
1200 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
1201 struct radv_image *image,
1202 VkImageLayout image_layout,
1203 const VkClearValue *clear_value,
1204 uint32_t range_count,
1205 const VkImageSubresourceRange *ranges,
1206 bool cs)
1207 {
1208 VkFormat format = image->vk_format;
1209 VkClearValue internal_clear_value = *clear_value;
1210
1211 if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
1212 uint32_t value;
1213 format = VK_FORMAT_R32_UINT;
1214 value = float3_to_rgb9e5(clear_value->color.float32);
1215 internal_clear_value.color.uint32[0] = value;
1216 }
1217
1218 if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
1219 uint8_t r, g;
1220 format = VK_FORMAT_R8_UINT;
1221 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
1222 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
1223 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
1224 }
1225
1226 for (uint32_t r = 0; r < range_count; r++) {
1227 const VkImageSubresourceRange *range = &ranges[r];
1228 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
1229 const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
1230 radv_minify(image->info.depth, range->baseMipLevel + l) :
1231 radv_get_layerCount(image, range);
1232 for (uint32_t s = 0; s < layer_count; ++s) {
1233
1234 if (cs) {
1235 struct radv_meta_blit2d_surf surf;
1236 surf.format = format;
1237 surf.image = image;
1238 surf.level = range->baseMipLevel + l;
1239 surf.layer = range->baseArrayLayer + s;
1240 surf.aspect_mask = range->aspectMask;
1241 radv_meta_clear_image_cs(cmd_buffer, &surf,
1242 &internal_clear_value.color);
1243 } else {
1244 radv_clear_image_layer(cmd_buffer, image, image_layout,
1245 range, format, l, s, &internal_clear_value);
1246 }
1247 }
1248 }
1249 }
1250 }
1251
1252 union meta_saved_state {
1253 struct radv_meta_saved_state gfx;
1254 struct radv_meta_saved_compute_state compute;
1255 };
1256
1257 void radv_CmdClearColorImage(
1258 VkCommandBuffer commandBuffer,
1259 VkImage image_h,
1260 VkImageLayout imageLayout,
1261 const VkClearColorValue* pColor,
1262 uint32_t rangeCount,
1263 const VkImageSubresourceRange* pRanges)
1264 {
1265 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1266 RADV_FROM_HANDLE(radv_image, image, image_h);
1267 union meta_saved_state saved_state;
1268 bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1269
1270 if (cs)
1271 radv_meta_begin_cleari(cmd_buffer, &saved_state.compute);
1272 else
1273 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state.gfx, cmd_buffer);
1274
1275 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1276 (const VkClearValue *) pColor,
1277 rangeCount, pRanges, cs);
1278
1279 if (cs)
1280 radv_meta_end_cleari(cmd_buffer, &saved_state.compute);
1281 else
1282 radv_meta_restore(&saved_state.gfx, cmd_buffer);
1283 }
1284
1285 void radv_CmdClearDepthStencilImage(
1286 VkCommandBuffer commandBuffer,
1287 VkImage image_h,
1288 VkImageLayout imageLayout,
1289 const VkClearDepthStencilValue* pDepthStencil,
1290 uint32_t rangeCount,
1291 const VkImageSubresourceRange* pRanges)
1292 {
1293 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1294 RADV_FROM_HANDLE(radv_image, image, image_h);
1295 struct radv_meta_saved_state saved_state;
1296
1297 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
1298
1299 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1300 (const VkClearValue *) pDepthStencil,
1301 rangeCount, pRanges, false);
1302
1303 radv_meta_restore(&saved_state, cmd_buffer);
1304 }
1305
1306 void radv_CmdClearAttachments(
1307 VkCommandBuffer commandBuffer,
1308 uint32_t attachmentCount,
1309 const VkClearAttachment* pAttachments,
1310 uint32_t rectCount,
1311 const VkClearRect* pRects)
1312 {
1313 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1314 struct radv_meta_saved_state saved_state;
1315 enum radv_cmd_flush_bits pre_flush = 0;
1316 enum radv_cmd_flush_bits post_flush = 0;
1317
1318 if (!cmd_buffer->state.subpass)
1319 return;
1320
1321 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
1322
1323 /* FINISHME: We can do better than this dumb loop. It thrashes too much
1324 * state.
1325 */
1326 for (uint32_t a = 0; a < attachmentCount; ++a) {
1327 for (uint32_t r = 0; r < rectCount; ++r) {
1328 emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush);
1329 }
1330 }
1331
1332 radv_meta_restore(&saved_state, cmd_buffer);
1333 cmd_buffer->state.flush_bits |= post_flush;
1334 }