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26bc5e75ef3bec3b9757253e37759360a553e5cc
[mesa.git] / src / amd / vulkan / radv_meta_clear.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_debug.h"
25 #include "radv_meta.h"
26 #include "radv_private.h"
27 #include "nir/nir_builder.h"
28
29 #include "util/format_rgb9e5.h"
30 #include "vk_format.h"
31
32 enum {
33 DEPTH_CLEAR_SLOW,
34 DEPTH_CLEAR_FAST_EXPCLEAR,
35 DEPTH_CLEAR_FAST_NO_EXPCLEAR
36 };
37
38 static void
39 build_color_shaders(struct nir_shader **out_vs,
40 struct nir_shader **out_fs,
41 uint32_t frag_output)
42 {
43 nir_builder vs_b;
44 nir_builder fs_b;
45
46 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
47 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
48
49 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
50 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
51
52 const struct glsl_type *position_type = glsl_vec4_type();
53 const struct glsl_type *color_type = glsl_vec4_type();
54
55 nir_variable *vs_out_pos =
56 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
57 "gl_Position");
58 vs_out_pos->data.location = VARYING_SLOT_POS;
59
60 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
61 nir_intrinsic_set_base(in_color_load, 0);
62 nir_intrinsic_set_range(in_color_load, 16);
63 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
64 in_color_load->num_components = 4;
65 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
66 nir_builder_instr_insert(&fs_b, &in_color_load->instr);
67
68 nir_variable *fs_out_color =
69 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
70 "f_color");
71 fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
72
73 nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
74
75 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
76 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
77
78 const struct glsl_type *layer_type = glsl_int_type();
79 nir_variable *vs_out_layer =
80 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
81 "v_layer");
82 vs_out_layer->data.location = VARYING_SLOT_LAYER;
83 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
84 nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
85 nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
86
87 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
88 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
89
90 *out_vs = vs_b.shader;
91 *out_fs = fs_b.shader;
92 }
93
94 static VkResult
95 create_pipeline(struct radv_device *device,
96 struct radv_render_pass *render_pass,
97 uint32_t samples,
98 struct nir_shader *vs_nir,
99 struct nir_shader *fs_nir,
100 const VkPipelineVertexInputStateCreateInfo *vi_state,
101 const VkPipelineDepthStencilStateCreateInfo *ds_state,
102 const VkPipelineColorBlendStateCreateInfo *cb_state,
103 const VkPipelineLayout layout,
104 const struct radv_graphics_pipeline_create_info *extra,
105 const VkAllocationCallbacks *alloc,
106 VkPipeline *pipeline)
107 {
108 VkDevice device_h = radv_device_to_handle(device);
109 VkResult result;
110
111 struct radv_shader_module vs_m = { .nir = vs_nir };
112 struct radv_shader_module fs_m = { .nir = fs_nir };
113
114 result = radv_graphics_pipeline_create(device_h,
115 radv_pipeline_cache_to_handle(&device->meta_state.cache),
116 &(VkGraphicsPipelineCreateInfo) {
117 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
118 .stageCount = fs_nir ? 2 : 1,
119 .pStages = (VkPipelineShaderStageCreateInfo[]) {
120 {
121 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
122 .stage = VK_SHADER_STAGE_VERTEX_BIT,
123 .module = radv_shader_module_to_handle(&vs_m),
124 .pName = "main",
125 },
126 {
127 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
128 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
129 .module = radv_shader_module_to_handle(&fs_m),
130 .pName = "main",
131 },
132 },
133 .pVertexInputState = vi_state,
134 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
135 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
136 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
137 .primitiveRestartEnable = false,
138 },
139 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
140 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
141 .viewportCount = 1,
142 .scissorCount = 1,
143 },
144 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
145 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
146 .rasterizerDiscardEnable = false,
147 .polygonMode = VK_POLYGON_MODE_FILL,
148 .cullMode = VK_CULL_MODE_NONE,
149 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
150 .depthBiasEnable = false,
151 },
152 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
153 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
154 .rasterizationSamples = samples,
155 .sampleShadingEnable = false,
156 .pSampleMask = NULL,
157 .alphaToCoverageEnable = false,
158 .alphaToOneEnable = false,
159 },
160 .pDepthStencilState = ds_state,
161 .pColorBlendState = cb_state,
162 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
163 /* The meta clear pipeline declares all state as dynamic.
164 * As a consequence, vkCmdBindPipeline writes no dynamic state
165 * to the cmd buffer. Therefore, at the end of the meta clear,
166 * we need only restore dynamic state was vkCmdSet.
167 */
168 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
169 .dynamicStateCount = 8,
170 .pDynamicStates = (VkDynamicState[]) {
171 /* Everything except stencil write mask */
172 VK_DYNAMIC_STATE_VIEWPORT,
173 VK_DYNAMIC_STATE_SCISSOR,
174 VK_DYNAMIC_STATE_LINE_WIDTH,
175 VK_DYNAMIC_STATE_DEPTH_BIAS,
176 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
177 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
178 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
179 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
180 },
181 },
182 .layout = layout,
183 .flags = 0,
184 .renderPass = radv_render_pass_to_handle(render_pass),
185 .subpass = 0,
186 },
187 extra,
188 alloc,
189 pipeline);
190
191 ralloc_free(vs_nir);
192 ralloc_free(fs_nir);
193
194 return result;
195 }
196
197 static VkResult
198 create_color_renderpass(struct radv_device *device,
199 VkFormat vk_format,
200 uint32_t samples,
201 VkRenderPass *pass)
202 {
203 mtx_lock(&device->meta_state.mtx);
204 if (*pass) {
205 mtx_unlock (&device->meta_state.mtx);
206 return VK_SUCCESS;
207 }
208
209 VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
210 &(VkRenderPassCreateInfo) {
211 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
212 .attachmentCount = 1,
213 .pAttachments = &(VkAttachmentDescription) {
214 .format = vk_format,
215 .samples = samples,
216 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
217 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
218 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
219 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
220 },
221 .subpassCount = 1,
222 .pSubpasses = &(VkSubpassDescription) {
223 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
224 .inputAttachmentCount = 0,
225 .colorAttachmentCount = 1,
226 .pColorAttachments = &(VkAttachmentReference) {
227 .attachment = 0,
228 .layout = VK_IMAGE_LAYOUT_GENERAL,
229 },
230 .pResolveAttachments = NULL,
231 .pDepthStencilAttachment = &(VkAttachmentReference) {
232 .attachment = VK_ATTACHMENT_UNUSED,
233 .layout = VK_IMAGE_LAYOUT_GENERAL,
234 },
235 .preserveAttachmentCount = 1,
236 .pPreserveAttachments = (uint32_t[]) { 0 },
237 },
238 .dependencyCount = 0,
239 }, &device->meta_state.alloc, pass);
240 mtx_unlock(&device->meta_state.mtx);
241 return result;
242 }
243
244 static VkResult
245 create_color_pipeline(struct radv_device *device,
246 uint32_t samples,
247 uint32_t frag_output,
248 VkPipeline *pipeline,
249 VkRenderPass pass)
250 {
251 struct nir_shader *vs_nir;
252 struct nir_shader *fs_nir;
253 VkResult result;
254
255 mtx_lock(&device->meta_state.mtx);
256 if (*pipeline) {
257 mtx_unlock(&device->meta_state.mtx);
258 return VK_SUCCESS;
259 }
260
261 build_color_shaders(&vs_nir, &fs_nir, frag_output);
262
263 const VkPipelineVertexInputStateCreateInfo vi_state = {
264 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
265 .vertexBindingDescriptionCount = 0,
266 .vertexAttributeDescriptionCount = 0,
267 };
268
269 const VkPipelineDepthStencilStateCreateInfo ds_state = {
270 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
271 .depthTestEnable = false,
272 .depthWriteEnable = false,
273 .depthBoundsTestEnable = false,
274 .stencilTestEnable = false,
275 };
276
277 VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
278 blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
279 .blendEnable = false,
280 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
281 VK_COLOR_COMPONENT_R_BIT |
282 VK_COLOR_COMPONENT_G_BIT |
283 VK_COLOR_COMPONENT_B_BIT,
284 };
285
286 const VkPipelineColorBlendStateCreateInfo cb_state = {
287 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
288 .logicOpEnable = false,
289 .attachmentCount = MAX_RTS,
290 .pAttachments = blend_attachment_state
291 };
292
293
294 struct radv_graphics_pipeline_create_info extra = {
295 .use_rectlist = true,
296 };
297 result = create_pipeline(device, radv_render_pass_from_handle(pass),
298 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
299 device->meta_state.clear_color_p_layout,
300 &extra, &device->meta_state.alloc, pipeline);
301
302 mtx_unlock(&device->meta_state.mtx);
303 return result;
304 }
305
306 static void
307 finish_meta_clear_htile_mask_state(struct radv_device *device)
308 {
309 struct radv_meta_state *state = &device->meta_state;
310
311 radv_DestroyPipeline(radv_device_to_handle(device),
312 state->clear_htile_mask_pipeline,
313 &state->alloc);
314 radv_DestroyPipelineLayout(radv_device_to_handle(device),
315 state->clear_htile_mask_p_layout,
316 &state->alloc);
317 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
318 state->clear_htile_mask_ds_layout,
319 &state->alloc);
320 }
321
322 void
323 radv_device_finish_meta_clear_state(struct radv_device *device)
324 {
325 struct radv_meta_state *state = &device->meta_state;
326
327 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
328 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
329 radv_DestroyPipeline(radv_device_to_handle(device),
330 state->clear[i].color_pipelines[j],
331 &state->alloc);
332 radv_DestroyRenderPass(radv_device_to_handle(device),
333 state->clear[i].render_pass[j],
334 &state->alloc);
335 }
336
337 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
338 radv_DestroyPipeline(radv_device_to_handle(device),
339 state->clear[i].depth_only_pipeline[j],
340 &state->alloc);
341 radv_DestroyPipeline(radv_device_to_handle(device),
342 state->clear[i].stencil_only_pipeline[j],
343 &state->alloc);
344 radv_DestroyPipeline(radv_device_to_handle(device),
345 state->clear[i].depthstencil_pipeline[j],
346 &state->alloc);
347 }
348 radv_DestroyRenderPass(radv_device_to_handle(device),
349 state->clear[i].depthstencil_rp,
350 &state->alloc);
351 }
352 radv_DestroyPipelineLayout(radv_device_to_handle(device),
353 state->clear_color_p_layout,
354 &state->alloc);
355 radv_DestroyPipelineLayout(radv_device_to_handle(device),
356 state->clear_depth_p_layout,
357 &state->alloc);
358
359 finish_meta_clear_htile_mask_state(device);
360 }
361
362 static void
363 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
364 const VkClearAttachment *clear_att,
365 const VkClearRect *clear_rect,
366 uint32_t view_mask)
367 {
368 struct radv_device *device = cmd_buffer->device;
369 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
370 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
371 const uint32_t subpass_att = clear_att->colorAttachment;
372 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
373 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
374 const uint32_t samples = iview->image->info.samples;
375 const uint32_t samples_log2 = ffs(samples) - 1;
376 unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
377 VkClearColorValue clear_value = clear_att->clearValue.color;
378 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
379 VkPipeline pipeline;
380
381 if (fs_key == -1) {
382 radv_finishme("color clears incomplete");
383 return;
384 }
385
386 if (device->meta_state.clear[samples_log2].render_pass[fs_key] == VK_NULL_HANDLE) {
387 VkResult ret = create_color_renderpass(device, radv_fs_key_format_exemplars[fs_key],
388 samples,
389 &device->meta_state.clear[samples_log2].render_pass[fs_key]);
390 if (ret != VK_SUCCESS) {
391 cmd_buffer->record_result = ret;
392 return;
393 }
394 }
395
396 if (device->meta_state.clear[samples_log2].color_pipelines[fs_key] == VK_NULL_HANDLE) {
397 VkResult ret = create_color_pipeline(device, samples, 0,
398 &device->meta_state.clear[samples_log2].color_pipelines[fs_key],
399 device->meta_state.clear[samples_log2].render_pass[fs_key]);
400 if (ret != VK_SUCCESS) {
401 cmd_buffer->record_result = ret;
402 return;
403 }
404 }
405
406 pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
407 if (!pipeline) {
408 radv_finishme("color clears incomplete");
409 return;
410 }
411 assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
412 assert(pipeline);
413 assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
414 assert(clear_att->colorAttachment < subpass->color_count);
415
416 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
417 device->meta_state.clear_color_p_layout,
418 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
419 &clear_value);
420
421 struct radv_subpass clear_subpass = {
422 .color_count = 1,
423 .color_attachments = (struct radv_subpass_attachment[]) {
424 subpass->color_attachments[clear_att->colorAttachment]
425 },
426 .depth_stencil_attachment = (struct radv_subpass_attachment) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
427 };
428
429 radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
430
431 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
432 pipeline);
433
434 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
435 .x = clear_rect->rect.offset.x,
436 .y = clear_rect->rect.offset.y,
437 .width = clear_rect->rect.extent.width,
438 .height = clear_rect->rect.extent.height,
439 .minDepth = 0.0f,
440 .maxDepth = 1.0f
441 });
442
443 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
444
445 if (view_mask) {
446 unsigned i;
447 for_each_bit(i, view_mask)
448 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
449 } else {
450 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
451 }
452
453 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
454 }
455
456
457 static void
458 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
459 {
460 nir_builder vs_b, fs_b;
461
462 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
463 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
464
465 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
466 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
467 const struct glsl_type *position_out_type = glsl_vec4_type();
468
469 nir_variable *vs_out_pos =
470 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
471 "gl_Position");
472 vs_out_pos->data.location = VARYING_SLOT_POS;
473
474 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
475 nir_intrinsic_set_base(in_color_load, 0);
476 nir_intrinsic_set_range(in_color_load, 4);
477 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
478 in_color_load->num_components = 1;
479 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
480 nir_builder_instr_insert(&vs_b, &in_color_load->instr);
481
482 nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
483 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
484
485 const struct glsl_type *layer_type = glsl_int_type();
486 nir_variable *vs_out_layer =
487 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
488 "v_layer");
489 vs_out_layer->data.location = VARYING_SLOT_LAYER;
490 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
491 nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
492 nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
493
494 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
495 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
496
497 *out_vs = vs_b.shader;
498 *out_fs = fs_b.shader;
499 }
500
501 static VkResult
502 create_depthstencil_renderpass(struct radv_device *device,
503 uint32_t samples,
504 VkRenderPass *render_pass)
505 {
506 mtx_lock(&device->meta_state.mtx);
507 if (*render_pass) {
508 mtx_unlock(&device->meta_state.mtx);
509 return VK_SUCCESS;
510 }
511
512 VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
513 &(VkRenderPassCreateInfo) {
514 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
515 .attachmentCount = 1,
516 .pAttachments = &(VkAttachmentDescription) {
517 .format = VK_FORMAT_D32_SFLOAT_S8_UINT,
518 .samples = samples,
519 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
520 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
521 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
522 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
523 },
524 .subpassCount = 1,
525 .pSubpasses = &(VkSubpassDescription) {
526 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
527 .inputAttachmentCount = 0,
528 .colorAttachmentCount = 0,
529 .pColorAttachments = NULL,
530 .pResolveAttachments = NULL,
531 .pDepthStencilAttachment = &(VkAttachmentReference) {
532 .attachment = 0,
533 .layout = VK_IMAGE_LAYOUT_GENERAL,
534 },
535 .preserveAttachmentCount = 1,
536 .pPreserveAttachments = (uint32_t[]) { 0 },
537 },
538 .dependencyCount = 0,
539 }, &device->meta_state.alloc, render_pass);
540 mtx_unlock(&device->meta_state.mtx);
541 return result;
542 }
543
544 static VkResult
545 create_depthstencil_pipeline(struct radv_device *device,
546 VkImageAspectFlags aspects,
547 uint32_t samples,
548 int index,
549 VkPipeline *pipeline,
550 VkRenderPass render_pass)
551 {
552 struct nir_shader *vs_nir, *fs_nir;
553 VkResult result;
554
555 mtx_lock(&device->meta_state.mtx);
556 if (*pipeline) {
557 mtx_unlock(&device->meta_state.mtx);
558 return VK_SUCCESS;
559 }
560
561 build_depthstencil_shader(&vs_nir, &fs_nir);
562
563 const VkPipelineVertexInputStateCreateInfo vi_state = {
564 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
565 .vertexBindingDescriptionCount = 0,
566 .vertexAttributeDescriptionCount = 0,
567 };
568
569 const VkPipelineDepthStencilStateCreateInfo ds_state = {
570 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
571 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
572 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
573 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
574 .depthBoundsTestEnable = false,
575 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
576 .front = {
577 .passOp = VK_STENCIL_OP_REPLACE,
578 .compareOp = VK_COMPARE_OP_ALWAYS,
579 .writeMask = UINT32_MAX,
580 .reference = 0, /* dynamic */
581 },
582 .back = { 0 /* dont care */ },
583 };
584
585 const VkPipelineColorBlendStateCreateInfo cb_state = {
586 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
587 .logicOpEnable = false,
588 .attachmentCount = 0,
589 .pAttachments = NULL,
590 };
591
592 struct radv_graphics_pipeline_create_info extra = {
593 .use_rectlist = true,
594 };
595
596 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
597 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
598 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
599 }
600 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
601 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
602 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
603 }
604 result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
605 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
606 device->meta_state.clear_depth_p_layout,
607 &extra, &device->meta_state.alloc, pipeline);
608
609 mtx_unlock(&device->meta_state.mtx);
610 return result;
611 }
612
613 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
614 const struct radv_image_view *iview,
615 VkImageAspectFlags aspects,
616 VkImageLayout layout,
617 const VkClearRect *clear_rect,
618 VkClearDepthStencilValue clear_value)
619 {
620 uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
621 cmd_buffer->queue_family_index,
622 cmd_buffer->queue_family_index);
623 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
624 clear_rect->rect.extent.width != iview->extent.width ||
625 clear_rect->rect.extent.height != iview->extent.height)
626 return false;
627 if (radv_image_is_tc_compat_htile(iview->image) &&
628 (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && clear_value.depth != 0.0 &&
629 clear_value.depth != 1.0) ||
630 ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0)))
631 return false;
632 if (radv_image_has_htile(iview->image) &&
633 iview->base_mip == 0 &&
634 iview->base_layer == 0 &&
635 radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
636 !radv_image_extent_compare(iview->image, &iview->extent))
637 return true;
638 return false;
639 }
640
641 static VkPipeline
642 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
643 struct radv_meta_state *meta_state,
644 const struct radv_image_view *iview,
645 int samples_log2,
646 VkImageAspectFlags aspects,
647 VkImageLayout layout,
648 const VkClearRect *clear_rect,
649 VkClearDepthStencilValue clear_value)
650 {
651 bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, clear_rect, clear_value);
652 int index = DEPTH_CLEAR_SLOW;
653 VkPipeline *pipeline;
654
655 if (fast) {
656 /* we don't know the previous clear values, so we always have
657 * the NO_EXPCLEAR path */
658 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
659 }
660
661 switch (aspects) {
662 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
663 pipeline = &meta_state->clear[samples_log2].depthstencil_pipeline[index];
664 break;
665 case VK_IMAGE_ASPECT_DEPTH_BIT:
666 pipeline = &meta_state->clear[samples_log2].depth_only_pipeline[index];
667 break;
668 case VK_IMAGE_ASPECT_STENCIL_BIT:
669 pipeline = &meta_state->clear[samples_log2].stencil_only_pipeline[index];
670 break;
671 default:
672 unreachable("expected depth or stencil aspect");
673 }
674
675 if (cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp == VK_NULL_HANDLE) {
676 VkResult ret = create_depthstencil_renderpass(cmd_buffer->device, 1u << samples_log2,
677 &cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
678 if (ret != VK_SUCCESS) {
679 cmd_buffer->record_result = ret;
680 return VK_NULL_HANDLE;
681 }
682 }
683
684 if (*pipeline == VK_NULL_HANDLE) {
685 VkResult ret = create_depthstencil_pipeline(cmd_buffer->device, aspects, 1u << samples_log2, index,
686 pipeline, cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
687 if (ret != VK_SUCCESS) {
688 cmd_buffer->record_result = ret;
689 return VK_NULL_HANDLE;
690 }
691 }
692 return *pipeline;
693 }
694
695 static void
696 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
697 const VkClearAttachment *clear_att,
698 const VkClearRect *clear_rect)
699 {
700 struct radv_device *device = cmd_buffer->device;
701 struct radv_meta_state *meta_state = &device->meta_state;
702 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
703 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
704 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
705 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
706 VkImageAspectFlags aspects = clear_att->aspectMask;
707 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
708 const uint32_t samples = iview->image->info.samples;
709 const uint32_t samples_log2 = ffs(samples) - 1;
710 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
711
712 assert(pass_att != VK_ATTACHMENT_UNUSED);
713
714 if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
715 clear_value.depth = 1.0f;
716
717 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
718 device->meta_state.clear_depth_p_layout,
719 VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
720 &clear_value.depth);
721
722 uint32_t prev_reference = cmd_buffer->state.dynamic.stencil_reference.front;
723 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
724 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
725 clear_value.stencil);
726 }
727
728 VkPipeline pipeline = pick_depthstencil_pipeline(cmd_buffer,
729 meta_state,
730 iview,
731 samples_log2,
732 aspects,
733 subpass->depth_stencil_attachment.layout,
734 clear_rect,
735 clear_value);
736 if (!pipeline)
737 return;
738
739 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
740 pipeline);
741
742 if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
743 subpass->depth_stencil_attachment.layout,
744 clear_rect, clear_value))
745 radv_update_ds_clear_metadata(cmd_buffer, iview->image,
746 clear_value, aspects);
747
748 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
749 .x = clear_rect->rect.offset.x,
750 .y = clear_rect->rect.offset.y,
751 .width = clear_rect->rect.extent.width,
752 .height = clear_rect->rect.extent.height,
753 .minDepth = 0.0f,
754 .maxDepth = 1.0f
755 });
756
757 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
758
759 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
760
761 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
762 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
763 prev_reference);
764 }
765 }
766
767 static uint32_t
768 clear_htile_mask(struct radv_cmd_buffer *cmd_buffer,
769 struct radeon_winsys_bo *bo, uint64_t offset, uint64_t size,
770 uint32_t htile_value, uint32_t htile_mask)
771 {
772 struct radv_device *device = cmd_buffer->device;
773 struct radv_meta_state *state = &device->meta_state;
774 uint64_t block_count = round_up_u64(size, 1024);
775 struct radv_meta_saved_state saved_state;
776
777 radv_meta_save(&saved_state, cmd_buffer,
778 RADV_META_SAVE_COMPUTE_PIPELINE |
779 RADV_META_SAVE_CONSTANTS |
780 RADV_META_SAVE_DESCRIPTORS);
781
782 struct radv_buffer dst_buffer = {
783 .bo = bo,
784 .offset = offset,
785 .size = size
786 };
787
788 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
789 VK_PIPELINE_BIND_POINT_COMPUTE,
790 state->clear_htile_mask_pipeline);
791
792 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
793 state->clear_htile_mask_p_layout,
794 0, /* set */
795 1, /* descriptorWriteCount */
796 (VkWriteDescriptorSet[]) {
797 {
798 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
799 .dstBinding = 0,
800 .dstArrayElement = 0,
801 .descriptorCount = 1,
802 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
803 .pBufferInfo = &(VkDescriptorBufferInfo) {
804 .buffer = radv_buffer_to_handle(&dst_buffer),
805 .offset = 0,
806 .range = size
807 }
808 }
809 });
810
811 const unsigned constants[2] = {
812 htile_value & htile_mask,
813 ~htile_mask,
814 };
815
816 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
817 state->clear_htile_mask_p_layout,
818 VK_SHADER_STAGE_COMPUTE_BIT, 0, 8,
819 constants);
820
821 radv_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer), block_count, 1, 1);
822
823 radv_meta_restore(&saved_state, cmd_buffer);
824
825 return RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
826 RADV_CMD_FLAG_INV_VMEM_L1 |
827 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
828 }
829
830 static uint32_t
831 radv_get_htile_fast_clear_value(const struct radv_image *image,
832 VkClearDepthStencilValue value)
833 {
834 uint32_t clear_value;
835
836 if (!image->surface.has_stencil) {
837 clear_value = value.depth ? 0xfffffff0 : 0;
838 } else {
839 clear_value = value.depth ? 0xfffc0000 : 0;
840 }
841
842 return clear_value;
843 }
844
845 static uint32_t
846 radv_get_htile_mask(const struct radv_image *image, VkImageAspectFlags aspects)
847 {
848 uint32_t mask = 0;
849
850 if (!image->surface.has_stencil) {
851 /* All the HTILE buffer is used when there is no stencil. */
852 mask = UINT32_MAX;
853 } else {
854 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
855 mask |= 0xfffffc0f;
856 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
857 mask |= 0x000003f0;
858 }
859
860 return mask;
861 }
862
863 static bool
864 radv_is_fast_clear_depth_allowed(VkClearDepthStencilValue value)
865 {
866 return value.depth == 1.0f || value.depth == 0.0f;
867 }
868
869 static bool
870 radv_is_fast_clear_stencil_allowed(VkClearDepthStencilValue value)
871 {
872 return value.stencil == 0;
873 }
874
875 static bool
876 emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
877 const VkClearAttachment *clear_att,
878 const VkClearRect *clear_rect,
879 enum radv_cmd_flush_bits *pre_flush,
880 enum radv_cmd_flush_bits *post_flush)
881 {
882 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
883 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
884 VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
885 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
886 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
887 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
888 VkImageAspectFlags aspects = clear_att->aspectMask;
889 uint32_t clear_word, flush_bits;
890 uint32_t htile_mask;
891
892 if (!radv_image_has_htile(iview->image))
893 return false;
894
895 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
896 return false;
897
898 if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
899 return false;
900
901 /* don't fast clear 3D */
902 if (iview->image->type == VK_IMAGE_TYPE_3D)
903 return false;
904
905 /* all layers are bound */
906 if (iview->base_layer > 0)
907 return false;
908 if (iview->image->info.array_size != iview->layer_count)
909 return false;
910
911 if (!radv_image_extent_compare(iview->image, &iview->extent))
912 return false;
913
914 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
915 clear_rect->rect.extent.width != iview->image->info.width ||
916 clear_rect->rect.extent.height != iview->image->info.height)
917 return false;
918
919 if (clear_rect->baseArrayLayer != 0)
920 return false;
921 if (clear_rect->layerCount != iview->image->info.array_size)
922 return false;
923
924 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 &&
925 (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT) ||
926 ((vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) &&
927 !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))))
928 return false;
929
930 if (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
931 !radv_is_fast_clear_depth_allowed(clear_value)) ||
932 ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
933 !radv_is_fast_clear_stencil_allowed(clear_value)))
934 return false;
935
936 /* GFX8 only supports 32-bit depth surfaces but we can enable TC-compat
937 * HTILE for 16-bit surfaces if no Z planes are compressed. Though,
938 * fast HTILE clears don't seem to work.
939 */
940 if (cmd_buffer->device->physical_device->rad_info.chip_class == VI &&
941 iview->image->vk_format == VK_FORMAT_D16_UNORM)
942 return false;
943
944 clear_word = radv_get_htile_fast_clear_value(iview->image, clear_value);
945 htile_mask = radv_get_htile_mask(iview->image, aspects);
946
947 if (pre_flush) {
948 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
949 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
950 *pre_flush |= cmd_buffer->state.flush_bits;
951 }
952
953 if (htile_mask == UINT_MAX) {
954 /* Clear the whole HTILE buffer. */
955 flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
956 iview->image->offset + iview->image->htile_offset,
957 iview->image->surface.htile_size, clear_word);
958 } else {
959 /* Only clear depth or stencil bytes in the HTILE buffer. */
960 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9);
961 flush_bits = clear_htile_mask(cmd_buffer, iview->image->bo,
962 iview->image->offset + iview->image->htile_offset,
963 iview->image->surface.htile_size, clear_word,
964 htile_mask);
965 }
966
967 radv_update_ds_clear_metadata(cmd_buffer, iview->image, clear_value, aspects);
968 if (post_flush) {
969 *post_flush |= flush_bits;
970 }
971
972 return true;
973 }
974
975 static nir_shader *
976 build_clear_htile_mask_shader()
977 {
978 nir_builder b;
979
980 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
981 b.shader->info.name = ralloc_strdup(b.shader, "meta_clear_htile_mask");
982 b.shader->info.cs.local_size[0] = 64;
983 b.shader->info.cs.local_size[1] = 1;
984 b.shader->info.cs.local_size[2] = 1;
985
986 nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
987 nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
988 nir_ssa_def *block_size = nir_imm_ivec4(&b,
989 b.shader->info.cs.local_size[0],
990 b.shader->info.cs.local_size[1],
991 b.shader->info.cs.local_size[2], 0);
992
993 nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
994
995 nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16));
996 offset = nir_channel(&b, offset, 0);
997
998 nir_intrinsic_instr *buf =
999 nir_intrinsic_instr_create(b.shader,
1000 nir_intrinsic_vulkan_resource_index);
1001
1002 buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
1003 nir_intrinsic_set_desc_set(buf, 0);
1004 nir_intrinsic_set_binding(buf, 0);
1005 nir_ssa_dest_init(&buf->instr, &buf->dest, 1, 32, NULL);
1006 nir_builder_instr_insert(&b, &buf->instr);
1007
1008 nir_intrinsic_instr *constants =
1009 nir_intrinsic_instr_create(b.shader,
1010 nir_intrinsic_load_push_constant);
1011 nir_intrinsic_set_base(constants, 0);
1012 nir_intrinsic_set_range(constants, 8);
1013 constants->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
1014 constants->num_components = 2;
1015 nir_ssa_dest_init(&constants->instr, &constants->dest, 2, 32, "constants");
1016 nir_builder_instr_insert(&b, &constants->instr);
1017
1018 nir_intrinsic_instr *load =
1019 nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
1020 load->src[0] = nir_src_for_ssa(&buf->dest.ssa);
1021 load->src[1] = nir_src_for_ssa(offset);
1022 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
1023 load->num_components = 4;
1024 nir_builder_instr_insert(&b, &load->instr);
1025
1026 /* data = (data & ~htile_mask) | (htile_value & htile_mask) */
1027 nir_ssa_def *data =
1028 nir_iand(&b, &load->dest.ssa,
1029 nir_channel(&b, &constants->dest.ssa, 1));
1030 data = nir_ior(&b, data, nir_channel(&b, &constants->dest.ssa, 0));
1031
1032 nir_intrinsic_instr *store =
1033 nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
1034 store->src[0] = nir_src_for_ssa(data);
1035 store->src[1] = nir_src_for_ssa(&buf->dest.ssa);
1036 store->src[2] = nir_src_for_ssa(offset);
1037 nir_intrinsic_set_write_mask(store, 0xf);
1038 store->num_components = 4;
1039 nir_builder_instr_insert(&b, &store->instr);
1040
1041 return b.shader;
1042 }
1043
1044 static VkResult
1045 init_meta_clear_htile_mask_state(struct radv_device *device)
1046 {
1047 struct radv_meta_state *state = &device->meta_state;
1048 struct radv_shader_module cs = { .nir = NULL };
1049 VkResult result;
1050
1051 cs.nir = build_clear_htile_mask_shader();
1052
1053 VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1054 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1055 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1056 .bindingCount = 1,
1057 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1058 {
1059 .binding = 0,
1060 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
1061 .descriptorCount = 1,
1062 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
1063 .pImmutableSamplers = NULL
1064 },
1065 }
1066 };
1067
1068 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1069 &ds_layout_info, &state->alloc,
1070 &state->clear_htile_mask_ds_layout);
1071 if (result != VK_SUCCESS)
1072 goto fail;
1073
1074 VkPipelineLayoutCreateInfo p_layout_info = {
1075 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1076 .setLayoutCount = 1,
1077 .pSetLayouts = &state->clear_htile_mask_ds_layout,
1078 .pushConstantRangeCount = 1,
1079 .pPushConstantRanges = &(VkPushConstantRange){
1080 VK_SHADER_STAGE_COMPUTE_BIT, 0, 8,
1081 },
1082 };
1083
1084 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1085 &p_layout_info, &state->alloc,
1086 &state->clear_htile_mask_p_layout);
1087 if (result != VK_SUCCESS)
1088 goto fail;
1089
1090 VkPipelineShaderStageCreateInfo shader_stage = {
1091 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1092 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
1093 .module = radv_shader_module_to_handle(&cs),
1094 .pName = "main",
1095 .pSpecializationInfo = NULL,
1096 };
1097
1098 VkComputePipelineCreateInfo pipeline_info = {
1099 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
1100 .stage = shader_stage,
1101 .flags = 0,
1102 .layout = state->clear_htile_mask_p_layout,
1103 };
1104
1105 result = radv_CreateComputePipelines(radv_device_to_handle(device),
1106 radv_pipeline_cache_to_handle(&state->cache),
1107 1, &pipeline_info, NULL,
1108 &state->clear_htile_mask_pipeline);
1109
1110 ralloc_free(cs.nir);
1111 return result;
1112 fail:
1113 ralloc_free(cs.nir);
1114 return result;
1115 }
1116
1117 VkResult
1118 radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand)
1119 {
1120 VkResult res;
1121 struct radv_meta_state *state = &device->meta_state;
1122
1123 VkPipelineLayoutCreateInfo pl_color_create_info = {
1124 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1125 .setLayoutCount = 0,
1126 .pushConstantRangeCount = 1,
1127 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
1128 };
1129
1130 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1131 &pl_color_create_info,
1132 &device->meta_state.alloc,
1133 &device->meta_state.clear_color_p_layout);
1134 if (res != VK_SUCCESS)
1135 goto fail;
1136
1137 VkPipelineLayoutCreateInfo pl_depth_create_info = {
1138 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1139 .setLayoutCount = 0,
1140 .pushConstantRangeCount = 1,
1141 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
1142 };
1143
1144 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1145 &pl_depth_create_info,
1146 &device->meta_state.alloc,
1147 &device->meta_state.clear_depth_p_layout);
1148 if (res != VK_SUCCESS)
1149 goto fail;
1150
1151 res = init_meta_clear_htile_mask_state(device);
1152 if (res != VK_SUCCESS)
1153 goto fail;
1154
1155 if (on_demand)
1156 return VK_SUCCESS;
1157
1158 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
1159 uint32_t samples = 1 << i;
1160 for (uint32_t j = 0; j < NUM_META_FS_KEYS; ++j) {
1161 VkFormat format = radv_fs_key_format_exemplars[j];
1162 unsigned fs_key = radv_format_meta_fs_key(format);
1163 assert(!state->clear[i].color_pipelines[fs_key]);
1164
1165 res = create_color_renderpass(device, format, samples,
1166 &state->clear[i].render_pass[fs_key]);
1167 if (res != VK_SUCCESS)
1168 goto fail;
1169
1170 res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
1171 state->clear[i].render_pass[fs_key]);
1172 if (res != VK_SUCCESS)
1173 goto fail;
1174
1175 }
1176
1177 res = create_depthstencil_renderpass(device,
1178 samples,
1179 &state->clear[i].depthstencil_rp);
1180 if (res != VK_SUCCESS)
1181 goto fail;
1182
1183 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
1184 res = create_depthstencil_pipeline(device,
1185 VK_IMAGE_ASPECT_DEPTH_BIT,
1186 samples,
1187 j,
1188 &state->clear[i].depth_only_pipeline[j],
1189 state->clear[i].depthstencil_rp);
1190 if (res != VK_SUCCESS)
1191 goto fail;
1192
1193 res = create_depthstencil_pipeline(device,
1194 VK_IMAGE_ASPECT_STENCIL_BIT,
1195 samples,
1196 j,
1197 &state->clear[i].stencil_only_pipeline[j],
1198 state->clear[i].depthstencil_rp);
1199 if (res != VK_SUCCESS)
1200 goto fail;
1201
1202 res = create_depthstencil_pipeline(device,
1203 VK_IMAGE_ASPECT_DEPTH_BIT |
1204 VK_IMAGE_ASPECT_STENCIL_BIT,
1205 samples,
1206 j,
1207 &state->clear[i].depthstencil_pipeline[j],
1208 state->clear[i].depthstencil_rp);
1209 if (res != VK_SUCCESS)
1210 goto fail;
1211 }
1212 }
1213 return VK_SUCCESS;
1214
1215 fail:
1216 radv_device_finish_meta_clear_state(device);
1217 return res;
1218 }
1219
1220 static uint32_t
1221 radv_get_cmask_fast_clear_value(const struct radv_image *image)
1222 {
1223 uint32_t value = 0; /* Default value when no DCC. */
1224
1225 /* The fast-clear value is different for images that have both DCC and
1226 * CMASK metadata.
1227 */
1228 if (radv_image_has_dcc(image)) {
1229 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
1230 return image->info.samples > 1 ? 0xcccccccc : 0xffffffff;
1231 }
1232
1233 return value;
1234 }
1235
1236 uint32_t
1237 radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
1238 struct radv_image *image, uint32_t value)
1239 {
1240 return radv_fill_buffer(cmd_buffer, image->bo,
1241 image->offset + image->cmask.offset,
1242 image->cmask.size, value);
1243 }
1244
1245 uint32_t
1246 radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
1247 struct radv_image *image, uint32_t value)
1248 {
1249 return radv_fill_buffer(cmd_buffer, image->bo,
1250 image->offset + image->dcc_offset,
1251 image->surface.dcc_size, value);
1252 }
1253
1254 static void vi_get_fast_clear_parameters(VkFormat format,
1255 const VkClearColorValue *clear_value,
1256 uint32_t* reset_value,
1257 bool *can_avoid_fast_clear_elim)
1258 {
1259 bool values[4] = {};
1260 int extra_channel;
1261 bool main_value = false;
1262 bool extra_value = false;
1263 int i;
1264 *can_avoid_fast_clear_elim = false;
1265
1266 *reset_value = 0x20202020U;
1267
1268 const struct vk_format_description *desc = vk_format_description(format);
1269 if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
1270 format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
1271 format == VK_FORMAT_B5G6R5_UNORM_PACK16)
1272 extra_channel = -1;
1273 else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
1274 if (radv_translate_colorswap(format, false) <= 1)
1275 extra_channel = desc->nr_channels - 1;
1276 else
1277 extra_channel = 0;
1278 } else
1279 return;
1280
1281 for (i = 0; i < 4; i++) {
1282 int index = desc->swizzle[i] - VK_SWIZZLE_X;
1283 if (desc->swizzle[i] < VK_SWIZZLE_X ||
1284 desc->swizzle[i] > VK_SWIZZLE_W)
1285 continue;
1286
1287 if (desc->channel[i].pure_integer &&
1288 desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
1289 /* Use the maximum value for clamping the clear color. */
1290 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
1291
1292 values[i] = clear_value->int32[i] != 0;
1293 if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
1294 return;
1295 } else if (desc->channel[i].pure_integer &&
1296 desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
1297 /* Use the maximum value for clamping the clear color. */
1298 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
1299
1300 values[i] = clear_value->uint32[i] != 0U;
1301 if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
1302 return;
1303 } else {
1304 values[i] = clear_value->float32[i] != 0.0F;
1305 if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
1306 return;
1307 }
1308
1309 if (index == extra_channel)
1310 extra_value = values[i];
1311 else
1312 main_value = values[i];
1313 }
1314
1315 for (int i = 0; i < 4; ++i)
1316 if (values[i] != main_value &&
1317 desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
1318 desc->swizzle[i] >= VK_SWIZZLE_X &&
1319 desc->swizzle[i] <= VK_SWIZZLE_W)
1320 return;
1321
1322 *can_avoid_fast_clear_elim = true;
1323 if (main_value)
1324 *reset_value |= 0x80808080U;
1325
1326 if (extra_value)
1327 *reset_value |= 0x40404040U;
1328 return;
1329 }
1330
1331 static bool
1332 emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
1333 const VkClearAttachment *clear_att,
1334 const VkClearRect *clear_rect,
1335 enum radv_cmd_flush_bits *pre_flush,
1336 enum radv_cmd_flush_bits *post_flush,
1337 uint32_t view_mask)
1338 {
1339 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1340 const uint32_t subpass_att = clear_att->colorAttachment;
1341 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
1342 VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
1343 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
1344 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
1345 VkClearColorValue clear_value = clear_att->clearValue.color;
1346 uint32_t clear_color[2], flush_bits = 0;
1347 uint32_t cmask_clear_value;
1348 bool ret;
1349
1350 if (!radv_image_has_cmask(iview->image) && !radv_image_has_dcc(iview->image))
1351 return false;
1352
1353 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
1354 return false;
1355
1356 if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
1357 return false;
1358
1359 /* don't fast clear 3D */
1360 if (iview->image->type == VK_IMAGE_TYPE_3D)
1361 return false;
1362
1363 /* all layers are bound */
1364 if (iview->base_layer > 0)
1365 return false;
1366 if (iview->image->info.array_size != iview->layer_count)
1367 return false;
1368
1369 if (!radv_image_extent_compare(iview->image, &iview->extent))
1370 return false;
1371
1372 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
1373 clear_rect->rect.extent.width != iview->image->info.width ||
1374 clear_rect->rect.extent.height != iview->image->info.height)
1375 return false;
1376
1377 if (view_mask && (iview->image->info.array_size >= 32 ||
1378 (1u << iview->image->info.array_size) - 1u != view_mask))
1379 return false;
1380 if (!view_mask && clear_rect->baseArrayLayer != 0)
1381 return false;
1382 if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
1383 return false;
1384
1385 /* RB+ doesn't work with CMASK fast clear on Stoney. */
1386 if (!radv_image_has_dcc(iview->image) &&
1387 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY)
1388 return false;
1389
1390 /* DCC */
1391 ret = radv_format_pack_clear_color(iview->vk_format,
1392 clear_color, &clear_value);
1393 if (ret == false)
1394 return false;
1395
1396 if (pre_flush) {
1397 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1398 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
1399 *pre_flush |= cmd_buffer->state.flush_bits;
1400 }
1401
1402 cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
1403
1404 /* clear cmask buffer */
1405 if (radv_image_has_dcc(iview->image)) {
1406 uint32_t reset_value;
1407 bool can_avoid_fast_clear_elim;
1408 bool need_decompress_pass = false;
1409
1410 vi_get_fast_clear_parameters(iview->vk_format,
1411 &clear_value, &reset_value,
1412 &can_avoid_fast_clear_elim);
1413
1414 if (iview->image->info.samples > 1) {
1415 /* DCC fast clear with MSAA should clear CMASK. */
1416 /* FIXME: This doesn't work for now. There is a
1417 * hardware bug with fast clears and DCC for MSAA
1418 * textures. AMDVLK has a workaround but it doesn't
1419 * seem to work here. Note that we might emit useless
1420 * CB flushes but that shouldn't matter.
1421 */
1422 if (!can_avoid_fast_clear_elim)
1423 return false;
1424
1425 assert(radv_image_has_cmask(iview->image));
1426
1427 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1428 cmask_clear_value);
1429
1430 need_decompress_pass = true;
1431 }
1432
1433 if (!can_avoid_fast_clear_elim)
1434 need_decompress_pass = true;
1435
1436 flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, reset_value);
1437
1438 radv_update_fce_metadata(cmd_buffer, iview->image,
1439 need_decompress_pass);
1440 } else {
1441 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1442 cmask_clear_value);
1443 }
1444
1445 if (post_flush) {
1446 *post_flush |= flush_bits;
1447 }
1448
1449 radv_update_color_clear_metadata(cmd_buffer, iview->image, subpass_att,
1450 clear_color);
1451
1452 return true;
1453 }
1454
1455 /**
1456 * The parameters mean that same as those in vkCmdClearAttachments.
1457 */
1458 static void
1459 emit_clear(struct radv_cmd_buffer *cmd_buffer,
1460 const VkClearAttachment *clear_att,
1461 const VkClearRect *clear_rect,
1462 enum radv_cmd_flush_bits *pre_flush,
1463 enum radv_cmd_flush_bits *post_flush,
1464 uint32_t view_mask)
1465 {
1466 if (clear_att->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1467 if (!emit_fast_color_clear(cmd_buffer, clear_att, clear_rect,
1468 pre_flush, post_flush, view_mask))
1469 emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask);
1470 } else {
1471 assert(clear_att->aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT |
1472 VK_IMAGE_ASPECT_STENCIL_BIT));
1473 if (!emit_fast_htile_clear(cmd_buffer, clear_att, clear_rect,
1474 pre_flush, post_flush))
1475 emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
1476 }
1477 }
1478
1479 static inline bool
1480 radv_attachment_needs_clear(struct radv_cmd_state *cmd_state, uint32_t a)
1481 {
1482 uint32_t view_mask = cmd_state->subpass->view_mask;
1483 return (a != VK_ATTACHMENT_UNUSED &&
1484 cmd_state->attachments[a].pending_clear_aspects &&
1485 (!view_mask || (view_mask & ~cmd_state->attachments[a].cleared_views)));
1486 }
1487
1488 static bool
1489 radv_subpass_needs_clear(struct radv_cmd_buffer *cmd_buffer)
1490 {
1491 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1492 uint32_t a;
1493
1494 if (!cmd_state->subpass)
1495 return false;
1496
1497 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1498 a = cmd_state->subpass->color_attachments[i].attachment;
1499 if (radv_attachment_needs_clear(cmd_state, a))
1500 return true;
1501 }
1502
1503 a = cmd_state->subpass->depth_stencil_attachment.attachment;
1504 return radv_attachment_needs_clear(cmd_state, a);
1505 }
1506
1507 static void
1508 radv_subpass_clear_attachment(struct radv_cmd_buffer *cmd_buffer,
1509 struct radv_attachment_state *attachment,
1510 const VkClearAttachment *clear_att,
1511 enum radv_cmd_flush_bits *pre_flush,
1512 enum radv_cmd_flush_bits *post_flush)
1513 {
1514 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1515 uint32_t view_mask = cmd_state->subpass->view_mask;
1516
1517 VkClearRect clear_rect = {
1518 .rect = cmd_state->render_area,
1519 .baseArrayLayer = 0,
1520 .layerCount = cmd_state->framebuffer->layers,
1521 };
1522
1523 emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush,
1524 view_mask & ~attachment->cleared_views);
1525 if (view_mask)
1526 attachment->cleared_views |= view_mask;
1527 else
1528 attachment->pending_clear_aspects = 0;
1529 }
1530
1531 /**
1532 * Emit any pending attachment clears for the current subpass.
1533 *
1534 * @see radv_attachment_state::pending_clear_aspects
1535 */
1536 void
1537 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1538 {
1539 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1540 struct radv_meta_saved_state saved_state;
1541 enum radv_cmd_flush_bits pre_flush = 0;
1542 enum radv_cmd_flush_bits post_flush = 0;
1543
1544 if (!radv_subpass_needs_clear(cmd_buffer))
1545 return;
1546
1547 radv_meta_save(&saved_state, cmd_buffer,
1548 RADV_META_SAVE_GRAPHICS_PIPELINE |
1549 RADV_META_SAVE_CONSTANTS);
1550
1551 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1552 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1553
1554 if (!radv_attachment_needs_clear(cmd_state, a))
1555 continue;
1556
1557 assert(cmd_state->attachments[a].pending_clear_aspects ==
1558 VK_IMAGE_ASPECT_COLOR_BIT);
1559
1560 VkClearAttachment clear_att = {
1561 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1562 .colorAttachment = i, /* Use attachment index relative to subpass */
1563 .clearValue = cmd_state->attachments[a].clear_value,
1564 };
1565
1566 radv_subpass_clear_attachment(cmd_buffer,
1567 &cmd_state->attachments[a],
1568 &clear_att, &pre_flush,
1569 &post_flush);
1570 }
1571
1572 uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1573 if (radv_attachment_needs_clear(cmd_state, ds)) {
1574 VkClearAttachment clear_att = {
1575 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1576 .clearValue = cmd_state->attachments[ds].clear_value,
1577 };
1578
1579 radv_subpass_clear_attachment(cmd_buffer,
1580 &cmd_state->attachments[ds],
1581 &clear_att, &pre_flush,
1582 &post_flush);
1583 }
1584
1585 radv_meta_restore(&saved_state, cmd_buffer);
1586 cmd_buffer->state.flush_bits |= post_flush;
1587 }
1588
1589 static void
1590 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1591 struct radv_image *image,
1592 VkImageLayout image_layout,
1593 const VkImageSubresourceRange *range,
1594 VkFormat format, int level, int layer,
1595 const VkClearValue *clear_val)
1596 {
1597 VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1598 struct radv_image_view iview;
1599 uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level);
1600 uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level);
1601
1602 radv_image_view_init(&iview, cmd_buffer->device,
1603 &(VkImageViewCreateInfo) {
1604 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1605 .image = radv_image_to_handle(image),
1606 .viewType = radv_meta_get_view_type(image),
1607 .format = format,
1608 .subresourceRange = {
1609 .aspectMask = range->aspectMask,
1610 .baseMipLevel = range->baseMipLevel + level,
1611 .levelCount = 1,
1612 .baseArrayLayer = range->baseArrayLayer + layer,
1613 .layerCount = 1
1614 },
1615 });
1616
1617 VkFramebuffer fb;
1618 radv_CreateFramebuffer(device_h,
1619 &(VkFramebufferCreateInfo) {
1620 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1621 .attachmentCount = 1,
1622 .pAttachments = (VkImageView[]) {
1623 radv_image_view_to_handle(&iview),
1624 },
1625 .width = width,
1626 .height = height,
1627 .layers = 1
1628 },
1629 &cmd_buffer->pool->alloc,
1630 &fb);
1631
1632 VkAttachmentDescription att_desc = {
1633 .format = iview.vk_format,
1634 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1635 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1636 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1637 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1638 .initialLayout = image_layout,
1639 .finalLayout = image_layout,
1640 };
1641
1642 VkSubpassDescription subpass_desc = {
1643 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1644 .inputAttachmentCount = 0,
1645 .colorAttachmentCount = 0,
1646 .pColorAttachments = NULL,
1647 .pResolveAttachments = NULL,
1648 .pDepthStencilAttachment = NULL,
1649 .preserveAttachmentCount = 0,
1650 .pPreserveAttachments = NULL,
1651 };
1652
1653 const VkAttachmentReference att_ref = {
1654 .attachment = 0,
1655 .layout = image_layout,
1656 };
1657
1658 if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1659 subpass_desc.colorAttachmentCount = 1;
1660 subpass_desc.pColorAttachments = &att_ref;
1661 } else {
1662 subpass_desc.pDepthStencilAttachment = &att_ref;
1663 }
1664
1665 VkRenderPass pass;
1666 radv_CreateRenderPass(device_h,
1667 &(VkRenderPassCreateInfo) {
1668 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1669 .attachmentCount = 1,
1670 .pAttachments = &att_desc,
1671 .subpassCount = 1,
1672 .pSubpasses = &subpass_desc,
1673 },
1674 &cmd_buffer->pool->alloc,
1675 &pass);
1676
1677 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1678 &(VkRenderPassBeginInfo) {
1679 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1680 .renderArea = {
1681 .offset = { 0, 0, },
1682 .extent = {
1683 .width = width,
1684 .height = height,
1685 },
1686 },
1687 .renderPass = pass,
1688 .framebuffer = fb,
1689 .clearValueCount = 0,
1690 .pClearValues = NULL,
1691 },
1692 VK_SUBPASS_CONTENTS_INLINE);
1693
1694 VkClearAttachment clear_att = {
1695 .aspectMask = range->aspectMask,
1696 .colorAttachment = 0,
1697 .clearValue = *clear_val,
1698 };
1699
1700 VkClearRect clear_rect = {
1701 .rect = {
1702 .offset = { 0, 0 },
1703 .extent = { width, height },
1704 },
1705 .baseArrayLayer = range->baseArrayLayer,
1706 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1707 };
1708
1709 emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0);
1710
1711 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1712 radv_DestroyRenderPass(device_h, pass,
1713 &cmd_buffer->pool->alloc);
1714 radv_DestroyFramebuffer(device_h, fb,
1715 &cmd_buffer->pool->alloc);
1716 }
1717 static void
1718 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
1719 struct radv_image *image,
1720 VkImageLayout image_layout,
1721 const VkClearValue *clear_value,
1722 uint32_t range_count,
1723 const VkImageSubresourceRange *ranges,
1724 bool cs)
1725 {
1726 VkFormat format = image->vk_format;
1727 VkClearValue internal_clear_value = *clear_value;
1728
1729 if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
1730 uint32_t value;
1731 format = VK_FORMAT_R32_UINT;
1732 value = float3_to_rgb9e5(clear_value->color.float32);
1733 internal_clear_value.color.uint32[0] = value;
1734 }
1735
1736 if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
1737 uint8_t r, g;
1738 format = VK_FORMAT_R8_UINT;
1739 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
1740 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
1741 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
1742 }
1743
1744 for (uint32_t r = 0; r < range_count; r++) {
1745 const VkImageSubresourceRange *range = &ranges[r];
1746 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
1747 const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
1748 radv_minify(image->info.depth, range->baseMipLevel + l) :
1749 radv_get_layerCount(image, range);
1750 for (uint32_t s = 0; s < layer_count; ++s) {
1751
1752 if (cs ||
1753 (format == VK_FORMAT_R32G32B32_UINT ||
1754 format == VK_FORMAT_R32G32B32_SINT ||
1755 format == VK_FORMAT_R32G32B32_SFLOAT)) {
1756 struct radv_meta_blit2d_surf surf;
1757 surf.format = format;
1758 surf.image = image;
1759 surf.level = range->baseMipLevel + l;
1760 surf.layer = range->baseArrayLayer + s;
1761 surf.aspect_mask = range->aspectMask;
1762 radv_meta_clear_image_cs(cmd_buffer, &surf,
1763 &internal_clear_value.color);
1764 } else {
1765 radv_clear_image_layer(cmd_buffer, image, image_layout,
1766 range, format, l, s, &internal_clear_value);
1767 }
1768 }
1769 }
1770 }
1771 }
1772
1773 void radv_CmdClearColorImage(
1774 VkCommandBuffer commandBuffer,
1775 VkImage image_h,
1776 VkImageLayout imageLayout,
1777 const VkClearColorValue* pColor,
1778 uint32_t rangeCount,
1779 const VkImageSubresourceRange* pRanges)
1780 {
1781 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1782 RADV_FROM_HANDLE(radv_image, image, image_h);
1783 struct radv_meta_saved_state saved_state;
1784 bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1785
1786 if (cs) {
1787 radv_meta_save(&saved_state, cmd_buffer,
1788 RADV_META_SAVE_COMPUTE_PIPELINE |
1789 RADV_META_SAVE_CONSTANTS |
1790 RADV_META_SAVE_DESCRIPTORS);
1791 } else {
1792 radv_meta_save(&saved_state, cmd_buffer,
1793 RADV_META_SAVE_GRAPHICS_PIPELINE |
1794 RADV_META_SAVE_CONSTANTS);
1795 }
1796
1797 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1798 (const VkClearValue *) pColor,
1799 rangeCount, pRanges, cs);
1800
1801 radv_meta_restore(&saved_state, cmd_buffer);
1802 }
1803
1804 void radv_CmdClearDepthStencilImage(
1805 VkCommandBuffer commandBuffer,
1806 VkImage image_h,
1807 VkImageLayout imageLayout,
1808 const VkClearDepthStencilValue* pDepthStencil,
1809 uint32_t rangeCount,
1810 const VkImageSubresourceRange* pRanges)
1811 {
1812 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1813 RADV_FROM_HANDLE(radv_image, image, image_h);
1814 struct radv_meta_saved_state saved_state;
1815
1816 radv_meta_save(&saved_state, cmd_buffer,
1817 RADV_META_SAVE_GRAPHICS_PIPELINE |
1818 RADV_META_SAVE_CONSTANTS);
1819
1820 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1821 (const VkClearValue *) pDepthStencil,
1822 rangeCount, pRanges, false);
1823
1824 radv_meta_restore(&saved_state, cmd_buffer);
1825 }
1826
1827 void radv_CmdClearAttachments(
1828 VkCommandBuffer commandBuffer,
1829 uint32_t attachmentCount,
1830 const VkClearAttachment* pAttachments,
1831 uint32_t rectCount,
1832 const VkClearRect* pRects)
1833 {
1834 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1835 struct radv_meta_saved_state saved_state;
1836 enum radv_cmd_flush_bits pre_flush = 0;
1837 enum radv_cmd_flush_bits post_flush = 0;
1838
1839 if (!cmd_buffer->state.subpass)
1840 return;
1841
1842 radv_meta_save(&saved_state, cmd_buffer,
1843 RADV_META_SAVE_GRAPHICS_PIPELINE |
1844 RADV_META_SAVE_CONSTANTS);
1845
1846 /* FINISHME: We can do better than this dumb loop. It thrashes too much
1847 * state.
1848 */
1849 for (uint32_t a = 0; a < attachmentCount; ++a) {
1850 for (uint32_t r = 0; r < rectCount; ++r) {
1851 emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush,
1852 cmd_buffer->state.subpass->view_mask);
1853 }
1854 }
1855
1856 radv_meta_restore(&saved_state, cmd_buffer);
1857 cmd_buffer->state.flush_bits |= post_flush;
1858 }