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radv: clean up radv_{set,load}_color_clear_regs() helpers
[mesa.git] / src / amd / vulkan / radv_meta_clear.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_debug.h"
25 #include "radv_meta.h"
26 #include "radv_private.h"
27 #include "nir/nir_builder.h"
28
29 #include "util/format_rgb9e5.h"
30 #include "vk_format.h"
31
32 enum {
33 DEPTH_CLEAR_SLOW,
34 DEPTH_CLEAR_FAST_EXPCLEAR,
35 DEPTH_CLEAR_FAST_NO_EXPCLEAR
36 };
37
38 static void
39 build_color_shaders(struct nir_shader **out_vs,
40 struct nir_shader **out_fs,
41 uint32_t frag_output)
42 {
43 nir_builder vs_b;
44 nir_builder fs_b;
45
46 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
47 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
48
49 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
50 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
51
52 const struct glsl_type *position_type = glsl_vec4_type();
53 const struct glsl_type *color_type = glsl_vec4_type();
54
55 nir_variable *vs_out_pos =
56 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
57 "gl_Position");
58 vs_out_pos->data.location = VARYING_SLOT_POS;
59
60 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
61 nir_intrinsic_set_base(in_color_load, 0);
62 nir_intrinsic_set_range(in_color_load, 16);
63 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
64 in_color_load->num_components = 4;
65 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
66 nir_builder_instr_insert(&fs_b, &in_color_load->instr);
67
68 nir_variable *fs_out_color =
69 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
70 "f_color");
71 fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
72
73 nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
74
75 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
76 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
77
78 const struct glsl_type *layer_type = glsl_int_type();
79 nir_variable *vs_out_layer =
80 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
81 "v_layer");
82 vs_out_layer->data.location = VARYING_SLOT_LAYER;
83 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
84 nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
85 nir_ssa_def *base_instance = nir_load_system_value(&vs_b, nir_intrinsic_load_base_instance, 0);
86
87 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
88 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
89
90 *out_vs = vs_b.shader;
91 *out_fs = fs_b.shader;
92 }
93
94 static VkResult
95 create_pipeline(struct radv_device *device,
96 struct radv_render_pass *render_pass,
97 uint32_t samples,
98 struct nir_shader *vs_nir,
99 struct nir_shader *fs_nir,
100 const VkPipelineVertexInputStateCreateInfo *vi_state,
101 const VkPipelineDepthStencilStateCreateInfo *ds_state,
102 const VkPipelineColorBlendStateCreateInfo *cb_state,
103 const VkPipelineLayout layout,
104 const struct radv_graphics_pipeline_create_info *extra,
105 const VkAllocationCallbacks *alloc,
106 VkPipeline *pipeline)
107 {
108 VkDevice device_h = radv_device_to_handle(device);
109 VkResult result;
110
111 struct radv_shader_module vs_m = { .nir = vs_nir };
112 struct radv_shader_module fs_m = { .nir = fs_nir };
113
114 result = radv_graphics_pipeline_create(device_h,
115 radv_pipeline_cache_to_handle(&device->meta_state.cache),
116 &(VkGraphicsPipelineCreateInfo) {
117 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
118 .stageCount = fs_nir ? 2 : 1,
119 .pStages = (VkPipelineShaderStageCreateInfo[]) {
120 {
121 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
122 .stage = VK_SHADER_STAGE_VERTEX_BIT,
123 .module = radv_shader_module_to_handle(&vs_m),
124 .pName = "main",
125 },
126 {
127 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
128 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
129 .module = radv_shader_module_to_handle(&fs_m),
130 .pName = "main",
131 },
132 },
133 .pVertexInputState = vi_state,
134 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
135 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
136 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
137 .primitiveRestartEnable = false,
138 },
139 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
140 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
141 .viewportCount = 1,
142 .scissorCount = 1,
143 },
144 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
145 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
146 .rasterizerDiscardEnable = false,
147 .polygonMode = VK_POLYGON_MODE_FILL,
148 .cullMode = VK_CULL_MODE_NONE,
149 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
150 .depthBiasEnable = false,
151 },
152 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
153 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
154 .rasterizationSamples = samples,
155 .sampleShadingEnable = false,
156 .pSampleMask = NULL,
157 .alphaToCoverageEnable = false,
158 .alphaToOneEnable = false,
159 },
160 .pDepthStencilState = ds_state,
161 .pColorBlendState = cb_state,
162 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
163 /* The meta clear pipeline declares all state as dynamic.
164 * As a consequence, vkCmdBindPipeline writes no dynamic state
165 * to the cmd buffer. Therefore, at the end of the meta clear,
166 * we need only restore dynamic state was vkCmdSet.
167 */
168 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
169 .dynamicStateCount = 8,
170 .pDynamicStates = (VkDynamicState[]) {
171 /* Everything except stencil write mask */
172 VK_DYNAMIC_STATE_VIEWPORT,
173 VK_DYNAMIC_STATE_SCISSOR,
174 VK_DYNAMIC_STATE_LINE_WIDTH,
175 VK_DYNAMIC_STATE_DEPTH_BIAS,
176 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
177 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
178 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
179 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
180 },
181 },
182 .layout = layout,
183 .flags = 0,
184 .renderPass = radv_render_pass_to_handle(render_pass),
185 .subpass = 0,
186 },
187 extra,
188 alloc,
189 pipeline);
190
191 ralloc_free(vs_nir);
192 ralloc_free(fs_nir);
193
194 return result;
195 }
196
197 static VkResult
198 create_color_renderpass(struct radv_device *device,
199 VkFormat vk_format,
200 uint32_t samples,
201 VkRenderPass *pass)
202 {
203 return radv_CreateRenderPass(radv_device_to_handle(device),
204 &(VkRenderPassCreateInfo) {
205 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
206 .attachmentCount = 1,
207 .pAttachments = &(VkAttachmentDescription) {
208 .format = vk_format,
209 .samples = samples,
210 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
211 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
212 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
213 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
214 },
215 .subpassCount = 1,
216 .pSubpasses = &(VkSubpassDescription) {
217 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
218 .inputAttachmentCount = 0,
219 .colorAttachmentCount = 1,
220 .pColorAttachments = &(VkAttachmentReference) {
221 .attachment = 0,
222 .layout = VK_IMAGE_LAYOUT_GENERAL,
223 },
224 .pResolveAttachments = NULL,
225 .pDepthStencilAttachment = &(VkAttachmentReference) {
226 .attachment = VK_ATTACHMENT_UNUSED,
227 .layout = VK_IMAGE_LAYOUT_GENERAL,
228 },
229 .preserveAttachmentCount = 1,
230 .pPreserveAttachments = (uint32_t[]) { 0 },
231 },
232 .dependencyCount = 0,
233 }, &device->meta_state.alloc, pass);
234 }
235
236 static VkResult
237 create_color_pipeline(struct radv_device *device,
238 uint32_t samples,
239 uint32_t frag_output,
240 VkPipeline *pipeline,
241 VkRenderPass pass)
242 {
243 struct nir_shader *vs_nir;
244 struct nir_shader *fs_nir;
245 VkResult result;
246 build_color_shaders(&vs_nir, &fs_nir, frag_output);
247
248 const VkPipelineVertexInputStateCreateInfo vi_state = {
249 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
250 .vertexBindingDescriptionCount = 0,
251 .vertexAttributeDescriptionCount = 0,
252 };
253
254 const VkPipelineDepthStencilStateCreateInfo ds_state = {
255 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
256 .depthTestEnable = false,
257 .depthWriteEnable = false,
258 .depthBoundsTestEnable = false,
259 .stencilTestEnable = false,
260 };
261
262 VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
263 blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
264 .blendEnable = false,
265 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
266 VK_COLOR_COMPONENT_R_BIT |
267 VK_COLOR_COMPONENT_G_BIT |
268 VK_COLOR_COMPONENT_B_BIT,
269 };
270
271 const VkPipelineColorBlendStateCreateInfo cb_state = {
272 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
273 .logicOpEnable = false,
274 .attachmentCount = MAX_RTS,
275 .pAttachments = blend_attachment_state
276 };
277
278
279 struct radv_graphics_pipeline_create_info extra = {
280 .use_rectlist = true,
281 };
282 result = create_pipeline(device, radv_render_pass_from_handle(pass),
283 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
284 device->meta_state.clear_color_p_layout,
285 &extra, &device->meta_state.alloc, pipeline);
286
287 return result;
288 }
289
290 void
291 radv_device_finish_meta_clear_state(struct radv_device *device)
292 {
293 struct radv_meta_state *state = &device->meta_state;
294
295 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
296 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
297 radv_DestroyPipeline(radv_device_to_handle(device),
298 state->clear[i].color_pipelines[j],
299 &state->alloc);
300 radv_DestroyRenderPass(radv_device_to_handle(device),
301 state->clear[i].render_pass[j],
302 &state->alloc);
303 }
304
305 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
306 radv_DestroyPipeline(radv_device_to_handle(device),
307 state->clear[i].depth_only_pipeline[j],
308 &state->alloc);
309 radv_DestroyPipeline(radv_device_to_handle(device),
310 state->clear[i].stencil_only_pipeline[j],
311 &state->alloc);
312 radv_DestroyPipeline(radv_device_to_handle(device),
313 state->clear[i].depthstencil_pipeline[j],
314 &state->alloc);
315 }
316 radv_DestroyRenderPass(radv_device_to_handle(device),
317 state->clear[i].depthstencil_rp,
318 &state->alloc);
319 }
320 radv_DestroyPipelineLayout(radv_device_to_handle(device),
321 state->clear_color_p_layout,
322 &state->alloc);
323 radv_DestroyPipelineLayout(radv_device_to_handle(device),
324 state->clear_depth_p_layout,
325 &state->alloc);
326 }
327
328 static void
329 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
330 const VkClearAttachment *clear_att,
331 const VkClearRect *clear_rect,
332 uint32_t view_mask)
333 {
334 struct radv_device *device = cmd_buffer->device;
335 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
336 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
337 const uint32_t subpass_att = clear_att->colorAttachment;
338 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
339 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
340 const uint32_t samples = iview->image->info.samples;
341 const uint32_t samples_log2 = ffs(samples) - 1;
342 unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
343 VkClearColorValue clear_value = clear_att->clearValue.color;
344 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
345 VkPipeline pipeline;
346
347 if (fs_key == -1) {
348 radv_finishme("color clears incomplete");
349 return;
350 }
351
352 pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
353 if (!pipeline) {
354 radv_finishme("color clears incomplete");
355 return;
356 }
357 assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
358 assert(pipeline);
359 assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
360 assert(clear_att->colorAttachment < subpass->color_count);
361
362 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
363 device->meta_state.clear_color_p_layout,
364 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
365 &clear_value);
366
367 struct radv_subpass clear_subpass = {
368 .color_count = 1,
369 .color_attachments = (VkAttachmentReference[]) {
370 subpass->color_attachments[clear_att->colorAttachment]
371 },
372 .depth_stencil_attachment = (VkAttachmentReference) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
373 };
374
375 radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
376
377 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
378 pipeline);
379
380 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
381 .x = clear_rect->rect.offset.x,
382 .y = clear_rect->rect.offset.y,
383 .width = clear_rect->rect.extent.width,
384 .height = clear_rect->rect.extent.height,
385 .minDepth = 0.0f,
386 .maxDepth = 1.0f
387 });
388
389 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
390
391 if (view_mask) {
392 unsigned i;
393 for_each_bit(i, view_mask)
394 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
395 } else {
396 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
397 }
398
399 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
400 }
401
402
403 static void
404 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
405 {
406 nir_builder vs_b, fs_b;
407
408 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
409 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
410
411 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
412 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
413 const struct glsl_type *position_out_type = glsl_vec4_type();
414
415 nir_variable *vs_out_pos =
416 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
417 "gl_Position");
418 vs_out_pos->data.location = VARYING_SLOT_POS;
419
420 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
421 nir_intrinsic_set_base(in_color_load, 0);
422 nir_intrinsic_set_range(in_color_load, 4);
423 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
424 in_color_load->num_components = 1;
425 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
426 nir_builder_instr_insert(&vs_b, &in_color_load->instr);
427
428 nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
429 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
430
431 const struct glsl_type *layer_type = glsl_int_type();
432 nir_variable *vs_out_layer =
433 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
434 "v_layer");
435 vs_out_layer->data.location = VARYING_SLOT_LAYER;
436 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
437 nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
438 nir_ssa_def *base_instance = nir_load_system_value(&vs_b, nir_intrinsic_load_base_instance, 0);
439
440 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
441 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
442
443 *out_vs = vs_b.shader;
444 *out_fs = fs_b.shader;
445 }
446
447 static VkResult
448 create_depthstencil_renderpass(struct radv_device *device,
449 uint32_t samples,
450 VkRenderPass *render_pass)
451 {
452 return radv_CreateRenderPass(radv_device_to_handle(device),
453 &(VkRenderPassCreateInfo) {
454 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
455 .attachmentCount = 1,
456 .pAttachments = &(VkAttachmentDescription) {
457 .format = VK_FORMAT_D32_SFLOAT_S8_UINT,
458 .samples = samples,
459 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
460 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
461 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
462 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
463 },
464 .subpassCount = 1,
465 .pSubpasses = &(VkSubpassDescription) {
466 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
467 .inputAttachmentCount = 0,
468 .colorAttachmentCount = 0,
469 .pColorAttachments = NULL,
470 .pResolveAttachments = NULL,
471 .pDepthStencilAttachment = &(VkAttachmentReference) {
472 .attachment = 0,
473 .layout = VK_IMAGE_LAYOUT_GENERAL,
474 },
475 .preserveAttachmentCount = 1,
476 .pPreserveAttachments = (uint32_t[]) { 0 },
477 },
478 .dependencyCount = 0,
479 }, &device->meta_state.alloc, render_pass);
480 }
481
482 static VkResult
483 create_depthstencil_pipeline(struct radv_device *device,
484 VkImageAspectFlags aspects,
485 uint32_t samples,
486 int index,
487 VkPipeline *pipeline,
488 VkRenderPass render_pass)
489 {
490 struct nir_shader *vs_nir, *fs_nir;
491 VkResult result;
492 build_depthstencil_shader(&vs_nir, &fs_nir);
493
494 const VkPipelineVertexInputStateCreateInfo vi_state = {
495 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
496 .vertexBindingDescriptionCount = 0,
497 .vertexAttributeDescriptionCount = 0,
498 };
499
500 const VkPipelineDepthStencilStateCreateInfo ds_state = {
501 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
502 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
503 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
504 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
505 .depthBoundsTestEnable = false,
506 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
507 .front = {
508 .passOp = VK_STENCIL_OP_REPLACE,
509 .compareOp = VK_COMPARE_OP_ALWAYS,
510 .writeMask = UINT32_MAX,
511 .reference = 0, /* dynamic */
512 },
513 .back = { 0 /* dont care */ },
514 };
515
516 const VkPipelineColorBlendStateCreateInfo cb_state = {
517 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
518 .logicOpEnable = false,
519 .attachmentCount = 0,
520 .pAttachments = NULL,
521 };
522
523 struct radv_graphics_pipeline_create_info extra = {
524 .use_rectlist = true,
525 };
526
527 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
528 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
529 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
530 }
531 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
532 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
533 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
534 }
535 result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
536 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
537 device->meta_state.clear_depth_p_layout,
538 &extra, &device->meta_state.alloc, pipeline);
539 return result;
540 }
541
542 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
543 const struct radv_image_view *iview,
544 VkImageAspectFlags aspects,
545 VkImageLayout layout,
546 const VkClearRect *clear_rect,
547 VkClearDepthStencilValue clear_value)
548 {
549 uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
550 cmd_buffer->queue_family_index,
551 cmd_buffer->queue_family_index);
552 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
553 clear_rect->rect.extent.width != iview->extent.width ||
554 clear_rect->rect.extent.height != iview->extent.height)
555 return false;
556 if (radv_image_is_tc_compat_htile(iview->image) &&
557 (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && clear_value.depth != 0.0 &&
558 clear_value.depth != 1.0) ||
559 ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0)))
560 return false;
561 if (radv_image_has_htile(iview->image) &&
562 iview->base_mip == 0 &&
563 iview->base_layer == 0 &&
564 radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
565 !radv_image_extent_compare(iview->image, &iview->extent))
566 return true;
567 return false;
568 }
569
570 static VkPipeline
571 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
572 struct radv_meta_state *meta_state,
573 const struct radv_image_view *iview,
574 int samples_log2,
575 VkImageAspectFlags aspects,
576 VkImageLayout layout,
577 const VkClearRect *clear_rect,
578 VkClearDepthStencilValue clear_value)
579 {
580 bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, clear_rect, clear_value);
581 int index = DEPTH_CLEAR_SLOW;
582
583 if (fast) {
584 /* we don't know the previous clear values, so we always have
585 * the NO_EXPCLEAR path */
586 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
587 }
588
589 switch (aspects) {
590 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
591 return meta_state->clear[samples_log2].depthstencil_pipeline[index];
592 case VK_IMAGE_ASPECT_DEPTH_BIT:
593 return meta_state->clear[samples_log2].depth_only_pipeline[index];
594 case VK_IMAGE_ASPECT_STENCIL_BIT:
595 return meta_state->clear[samples_log2].stencil_only_pipeline[index];
596 }
597 unreachable("expected depth or stencil aspect");
598 }
599
600 static void
601 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
602 const VkClearAttachment *clear_att,
603 const VkClearRect *clear_rect)
604 {
605 struct radv_device *device = cmd_buffer->device;
606 struct radv_meta_state *meta_state = &device->meta_state;
607 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
608 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
609 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
610 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
611 VkImageAspectFlags aspects = clear_att->aspectMask;
612 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
613 const uint32_t samples = iview->image->info.samples;
614 const uint32_t samples_log2 = ffs(samples) - 1;
615 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
616
617 assert(pass_att != VK_ATTACHMENT_UNUSED);
618
619 if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
620 clear_value.depth = 1.0f;
621
622 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
623 device->meta_state.clear_depth_p_layout,
624 VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
625 &clear_value.depth);
626
627 uint32_t prev_reference = cmd_buffer->state.dynamic.stencil_reference.front;
628 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
629 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
630 clear_value.stencil);
631 }
632
633 VkPipeline pipeline = pick_depthstencil_pipeline(cmd_buffer,
634 meta_state,
635 iview,
636 samples_log2,
637 aspects,
638 subpass->depth_stencil_attachment.layout,
639 clear_rect,
640 clear_value);
641
642 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
643 pipeline);
644
645 if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
646 subpass->depth_stencil_attachment.layout,
647 clear_rect, clear_value))
648 radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
649
650 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
651 .x = clear_rect->rect.offset.x,
652 .y = clear_rect->rect.offset.y,
653 .width = clear_rect->rect.extent.width,
654 .height = clear_rect->rect.extent.height,
655 .minDepth = 0.0f,
656 .maxDepth = 1.0f
657 });
658
659 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
660
661 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
662
663 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
664 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
665 prev_reference);
666 }
667 }
668
669 static bool
670 emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
671 const VkClearAttachment *clear_att,
672 const VkClearRect *clear_rect,
673 enum radv_cmd_flush_bits *pre_flush,
674 enum radv_cmd_flush_bits *post_flush)
675 {
676 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
677 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
678 VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
679 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
680 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
681 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
682 VkImageAspectFlags aspects = clear_att->aspectMask;
683 uint32_t clear_word, flush_bits;
684
685 if (!radv_image_has_htile(iview->image))
686 return false;
687
688 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
689 return false;
690
691 if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
692 goto fail;
693
694 /* don't fast clear 3D */
695 if (iview->image->type == VK_IMAGE_TYPE_3D)
696 goto fail;
697
698 /* all layers are bound */
699 if (iview->base_layer > 0)
700 goto fail;
701 if (iview->image->info.array_size != iview->layer_count)
702 goto fail;
703
704 if (!radv_image_extent_compare(iview->image, &iview->extent))
705 goto fail;
706
707 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
708 clear_rect->rect.extent.width != iview->image->info.width ||
709 clear_rect->rect.extent.height != iview->image->info.height)
710 goto fail;
711
712 if (clear_rect->baseArrayLayer != 0)
713 goto fail;
714 if (clear_rect->layerCount != iview->image->info.array_size)
715 goto fail;
716
717 if ((clear_value.depth != 0.0 && clear_value.depth != 1.0) || !(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
718 goto fail;
719
720 /* GFX8 only supports 32-bit depth surfaces but we can enable TC-compat
721 * HTILE for 16-bit surfaces if no Z planes are compressed. Though,
722 * fast HTILE clears don't seem to work.
723 */
724 if (cmd_buffer->device->physical_device->rad_info.chip_class == VI &&
725 iview->image->vk_format == VK_FORMAT_D16_UNORM)
726 goto fail;
727
728 if (vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) {
729 if (clear_value.stencil != 0 || !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))
730 goto fail;
731 clear_word = clear_value.depth ? 0xfffc0000 : 0;
732 } else
733 clear_word = clear_value.depth ? 0xfffffff0 : 0;
734
735 if (pre_flush) {
736 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
737 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
738 *pre_flush |= cmd_buffer->state.flush_bits;
739 } else
740 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
741 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
742
743 flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
744 iview->image->offset + iview->image->htile_offset,
745 iview->image->surface.htile_size, clear_word);
746
747 radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
748 if (post_flush) {
749 *post_flush |= flush_bits;
750 } else {
751 cmd_buffer->state.flush_bits |= flush_bits;
752 }
753
754 return true;
755 fail:
756 return false;
757 }
758
759 static VkFormat pipeline_formats[] = {
760 VK_FORMAT_R8G8B8A8_UNORM,
761 VK_FORMAT_R8G8B8A8_UINT,
762 VK_FORMAT_R8G8B8A8_SINT,
763 VK_FORMAT_A2R10G10B10_UINT_PACK32,
764 VK_FORMAT_A2R10G10B10_SINT_PACK32,
765 VK_FORMAT_R16G16B16A16_UNORM,
766 VK_FORMAT_R16G16B16A16_SNORM,
767 VK_FORMAT_R16G16B16A16_UINT,
768 VK_FORMAT_R16G16B16A16_SINT,
769 VK_FORMAT_R32_SFLOAT,
770 VK_FORMAT_R32G32_SFLOAT,
771 VK_FORMAT_R32G32B32A32_SFLOAT
772 };
773
774 VkResult
775 radv_device_init_meta_clear_state(struct radv_device *device)
776 {
777 VkResult res;
778 struct radv_meta_state *state = &device->meta_state;
779
780 VkPipelineLayoutCreateInfo pl_color_create_info = {
781 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
782 .setLayoutCount = 0,
783 .pushConstantRangeCount = 1,
784 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
785 };
786
787 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
788 &pl_color_create_info,
789 &device->meta_state.alloc,
790 &device->meta_state.clear_color_p_layout);
791 if (res != VK_SUCCESS)
792 goto fail;
793
794 VkPipelineLayoutCreateInfo pl_depth_create_info = {
795 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
796 .setLayoutCount = 0,
797 .pushConstantRangeCount = 1,
798 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
799 };
800
801 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
802 &pl_depth_create_info,
803 &device->meta_state.alloc,
804 &device->meta_state.clear_depth_p_layout);
805 if (res != VK_SUCCESS)
806 goto fail;
807
808 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
809 uint32_t samples = 1 << i;
810 for (uint32_t j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
811 VkFormat format = pipeline_formats[j];
812 unsigned fs_key = radv_format_meta_fs_key(format);
813 assert(!state->clear[i].color_pipelines[fs_key]);
814
815 res = create_color_renderpass(device, format, samples,
816 &state->clear[i].render_pass[fs_key]);
817 if (res != VK_SUCCESS)
818 goto fail;
819
820 res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
821 state->clear[i].render_pass[fs_key]);
822 if (res != VK_SUCCESS)
823 goto fail;
824
825 }
826
827 res = create_depthstencil_renderpass(device,
828 samples,
829 &state->clear[i].depthstencil_rp);
830 if (res != VK_SUCCESS)
831 goto fail;
832
833 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
834 res = create_depthstencil_pipeline(device,
835 VK_IMAGE_ASPECT_DEPTH_BIT,
836 samples,
837 j,
838 &state->clear[i].depth_only_pipeline[j],
839 state->clear[i].depthstencil_rp);
840 if (res != VK_SUCCESS)
841 goto fail;
842
843 res = create_depthstencil_pipeline(device,
844 VK_IMAGE_ASPECT_STENCIL_BIT,
845 samples,
846 j,
847 &state->clear[i].stencil_only_pipeline[j],
848 state->clear[i].depthstencil_rp);
849 if (res != VK_SUCCESS)
850 goto fail;
851
852 res = create_depthstencil_pipeline(device,
853 VK_IMAGE_ASPECT_DEPTH_BIT |
854 VK_IMAGE_ASPECT_STENCIL_BIT,
855 samples,
856 j,
857 &state->clear[i].depthstencil_pipeline[j],
858 state->clear[i].depthstencil_rp);
859 if (res != VK_SUCCESS)
860 goto fail;
861 }
862 }
863 return VK_SUCCESS;
864
865 fail:
866 radv_device_finish_meta_clear_state(device);
867 return res;
868 }
869
870 static uint32_t
871 radv_get_cmask_fast_clear_value(const struct radv_image *image)
872 {
873 uint32_t value = 0; /* Default value when no DCC. */
874
875 /* The fast-clear value is different for images that have both DCC and
876 * CMASK metadata.
877 */
878 if (radv_image_has_dcc(image)) {
879 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
880 return image->info.samples > 1 ? 0xcccccccc : 0xffffffff;
881 }
882
883 return value;
884 }
885
886 uint32_t
887 radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
888 struct radv_image *image, uint32_t value)
889 {
890 return radv_fill_buffer(cmd_buffer, image->bo,
891 image->offset + image->cmask.offset,
892 image->cmask.size, value);
893 }
894
895 uint32_t
896 radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
897 struct radv_image *image, uint32_t value)
898 {
899 return radv_fill_buffer(cmd_buffer, image->bo,
900 image->offset + image->dcc_offset,
901 image->surface.dcc_size, value);
902 }
903
904 static void vi_get_fast_clear_parameters(VkFormat format,
905 const VkClearColorValue *clear_value,
906 uint32_t* reset_value,
907 bool *can_avoid_fast_clear_elim)
908 {
909 bool values[4] = {};
910 int extra_channel;
911 bool main_value = false;
912 bool extra_value = false;
913 int i;
914 *can_avoid_fast_clear_elim = false;
915
916 *reset_value = 0x20202020U;
917
918 const struct vk_format_description *desc = vk_format_description(format);
919 if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
920 format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
921 format == VK_FORMAT_B5G6R5_UNORM_PACK16)
922 extra_channel = -1;
923 else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
924 if (radv_translate_colorswap(format, false) <= 1)
925 extra_channel = desc->nr_channels - 1;
926 else
927 extra_channel = 0;
928 } else
929 return;
930
931 for (i = 0; i < 4; i++) {
932 int index = desc->swizzle[i] - VK_SWIZZLE_X;
933 if (desc->swizzle[i] < VK_SWIZZLE_X ||
934 desc->swizzle[i] > VK_SWIZZLE_W)
935 continue;
936
937 if (desc->channel[i].pure_integer &&
938 desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
939 /* Use the maximum value for clamping the clear color. */
940 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
941
942 values[i] = clear_value->int32[i] != 0;
943 if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
944 return;
945 } else if (desc->channel[i].pure_integer &&
946 desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
947 /* Use the maximum value for clamping the clear color. */
948 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
949
950 values[i] = clear_value->uint32[i] != 0U;
951 if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
952 return;
953 } else {
954 values[i] = clear_value->float32[i] != 0.0F;
955 if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
956 return;
957 }
958
959 if (index == extra_channel)
960 extra_value = values[i];
961 else
962 main_value = values[i];
963 }
964
965 for (int i = 0; i < 4; ++i)
966 if (values[i] != main_value &&
967 desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
968 desc->swizzle[i] >= VK_SWIZZLE_X &&
969 desc->swizzle[i] <= VK_SWIZZLE_W)
970 return;
971
972 *can_avoid_fast_clear_elim = true;
973 if (main_value)
974 *reset_value |= 0x80808080U;
975
976 if (extra_value)
977 *reset_value |= 0x40404040U;
978 return;
979 }
980
981 static bool
982 emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
983 const VkClearAttachment *clear_att,
984 const VkClearRect *clear_rect,
985 enum radv_cmd_flush_bits *pre_flush,
986 enum radv_cmd_flush_bits *post_flush,
987 uint32_t view_mask)
988 {
989 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
990 const uint32_t subpass_att = clear_att->colorAttachment;
991 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
992 VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
993 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
994 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
995 VkClearColorValue clear_value = clear_att->clearValue.color;
996 uint32_t clear_color[2], flush_bits;
997 uint32_t cmask_clear_value;
998 bool ret;
999
1000 if (!radv_image_has_cmask(iview->image) && !radv_image_has_dcc(iview->image))
1001 return false;
1002
1003 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
1004 return false;
1005
1006 if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
1007 goto fail;
1008
1009 /* don't fast clear 3D */
1010 if (iview->image->type == VK_IMAGE_TYPE_3D)
1011 goto fail;
1012
1013 /* all layers are bound */
1014 if (iview->base_layer > 0)
1015 goto fail;
1016 if (iview->image->info.array_size != iview->layer_count)
1017 goto fail;
1018
1019 if (iview->image->info.levels > 1)
1020 goto fail;
1021
1022 if (iview->image->surface.is_linear)
1023 goto fail;
1024 if (!radv_image_extent_compare(iview->image, &iview->extent))
1025 goto fail;
1026
1027 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
1028 clear_rect->rect.extent.width != iview->image->info.width ||
1029 clear_rect->rect.extent.height != iview->image->info.height)
1030 goto fail;
1031
1032 if (view_mask && (iview->image->info.array_size >= 32 ||
1033 (1u << iview->image->info.array_size) - 1u != view_mask))
1034 goto fail;
1035 if (!view_mask && clear_rect->baseArrayLayer != 0)
1036 goto fail;
1037 if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
1038 goto fail;
1039
1040 /* RB+ doesn't work with CMASK fast clear on Stoney. */
1041 if (!radv_image_has_dcc(iview->image) &&
1042 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY)
1043 goto fail;
1044
1045 /* DCC */
1046 ret = radv_format_pack_clear_color(iview->vk_format,
1047 clear_color, &clear_value);
1048 if (ret == false)
1049 goto fail;
1050
1051 if (pre_flush) {
1052 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1053 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
1054 *pre_flush |= cmd_buffer->state.flush_bits;
1055 } else
1056 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1057 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1058
1059 cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
1060
1061 /* clear cmask buffer */
1062 if (radv_image_has_dcc(iview->image)) {
1063 uint32_t reset_value;
1064 bool can_avoid_fast_clear_elim;
1065 bool need_decompress_pass = false;
1066
1067 vi_get_fast_clear_parameters(iview->vk_format,
1068 &clear_value, &reset_value,
1069 &can_avoid_fast_clear_elim);
1070
1071 if (iview->image->info.samples > 1) {
1072 /* DCC fast clear with MSAA should clear CMASK. */
1073 /* FIXME: This doesn't work for now. There is a
1074 * hardware bug with fast clears and DCC for MSAA
1075 * textures. AMDVLK has a workaround but it doesn't
1076 * seem to work here. Note that we might emit useless
1077 * CB flushes but that shouldn't matter.
1078 */
1079 if (!can_avoid_fast_clear_elim)
1080 goto fail;
1081
1082 assert(radv_image_has_cmask(iview->image));
1083
1084 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1085 cmask_clear_value);
1086
1087 need_decompress_pass = true;
1088 }
1089
1090 if (!can_avoid_fast_clear_elim)
1091 need_decompress_pass = true;
1092
1093 flush_bits = radv_clear_dcc(cmd_buffer, iview->image, reset_value);
1094
1095 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
1096 need_decompress_pass);
1097 } else {
1098 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1099 cmask_clear_value);
1100 }
1101
1102 if (post_flush) {
1103 *post_flush |= flush_bits;
1104 } else {
1105 cmd_buffer->state.flush_bits |= flush_bits;
1106 }
1107
1108 radv_set_color_clear_metadata(cmd_buffer, iview->image, subpass_att,
1109 clear_color);
1110
1111 return true;
1112 fail:
1113 return false;
1114 }
1115
1116 /**
1117 * The parameters mean that same as those in vkCmdClearAttachments.
1118 */
1119 static void
1120 emit_clear(struct radv_cmd_buffer *cmd_buffer,
1121 const VkClearAttachment *clear_att,
1122 const VkClearRect *clear_rect,
1123 enum radv_cmd_flush_bits *pre_flush,
1124 enum radv_cmd_flush_bits *post_flush,
1125 uint32_t view_mask)
1126 {
1127 if (clear_att->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1128 if (!emit_fast_color_clear(cmd_buffer, clear_att, clear_rect,
1129 pre_flush, post_flush, view_mask))
1130 emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask);
1131 } else {
1132 assert(clear_att->aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT |
1133 VK_IMAGE_ASPECT_STENCIL_BIT));
1134 if (!emit_fast_htile_clear(cmd_buffer, clear_att, clear_rect,
1135 pre_flush, post_flush))
1136 emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
1137 }
1138 }
1139
1140 static inline bool
1141 radv_attachment_needs_clear(struct radv_cmd_state *cmd_state, uint32_t a)
1142 {
1143 uint32_t view_mask = cmd_state->subpass->view_mask;
1144 return (a != VK_ATTACHMENT_UNUSED &&
1145 cmd_state->attachments[a].pending_clear_aspects &&
1146 (!view_mask || (view_mask & ~cmd_state->attachments[a].cleared_views)));
1147 }
1148
1149 static bool
1150 radv_subpass_needs_clear(struct radv_cmd_buffer *cmd_buffer)
1151 {
1152 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1153 uint32_t a;
1154
1155 if (!cmd_state->subpass)
1156 return false;
1157
1158 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1159 a = cmd_state->subpass->color_attachments[i].attachment;
1160 if (radv_attachment_needs_clear(cmd_state, a))
1161 return true;
1162 }
1163
1164 a = cmd_state->subpass->depth_stencil_attachment.attachment;
1165 return radv_attachment_needs_clear(cmd_state, a);
1166 }
1167
1168 static void
1169 radv_subpass_clear_attachment(struct radv_cmd_buffer *cmd_buffer,
1170 struct radv_attachment_state *attachment,
1171 const VkClearAttachment *clear_att,
1172 enum radv_cmd_flush_bits *pre_flush,
1173 enum radv_cmd_flush_bits *post_flush)
1174 {
1175 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1176 uint32_t view_mask = cmd_state->subpass->view_mask;
1177
1178 VkClearRect clear_rect = {
1179 .rect = cmd_state->render_area,
1180 .baseArrayLayer = 0,
1181 .layerCount = cmd_state->framebuffer->layers,
1182 };
1183
1184 emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush,
1185 view_mask & ~attachment->cleared_views);
1186 if (view_mask)
1187 attachment->cleared_views |= view_mask;
1188 else
1189 attachment->pending_clear_aspects = 0;
1190 }
1191
1192 /**
1193 * Emit any pending attachment clears for the current subpass.
1194 *
1195 * @see radv_attachment_state::pending_clear_aspects
1196 */
1197 void
1198 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1199 {
1200 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1201 struct radv_meta_saved_state saved_state;
1202 enum radv_cmd_flush_bits pre_flush = 0;
1203 enum radv_cmd_flush_bits post_flush = 0;
1204
1205 if (!radv_subpass_needs_clear(cmd_buffer))
1206 return;
1207
1208 radv_meta_save(&saved_state, cmd_buffer,
1209 RADV_META_SAVE_GRAPHICS_PIPELINE |
1210 RADV_META_SAVE_CONSTANTS);
1211
1212 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1213 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1214
1215 if (!radv_attachment_needs_clear(cmd_state, a))
1216 continue;
1217
1218 assert(cmd_state->attachments[a].pending_clear_aspects ==
1219 VK_IMAGE_ASPECT_COLOR_BIT);
1220
1221 VkClearAttachment clear_att = {
1222 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1223 .colorAttachment = i, /* Use attachment index relative to subpass */
1224 .clearValue = cmd_state->attachments[a].clear_value,
1225 };
1226
1227 radv_subpass_clear_attachment(cmd_buffer,
1228 &cmd_state->attachments[a],
1229 &clear_att, &pre_flush,
1230 &post_flush);
1231 }
1232
1233 uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1234 if (radv_attachment_needs_clear(cmd_state, ds)) {
1235 VkClearAttachment clear_att = {
1236 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1237 .clearValue = cmd_state->attachments[ds].clear_value,
1238 };
1239
1240 radv_subpass_clear_attachment(cmd_buffer,
1241 &cmd_state->attachments[ds],
1242 &clear_att, &pre_flush,
1243 &post_flush);
1244 }
1245
1246 radv_meta_restore(&saved_state, cmd_buffer);
1247 cmd_buffer->state.flush_bits |= post_flush;
1248 }
1249
1250 static void
1251 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1252 struct radv_image *image,
1253 VkImageLayout image_layout,
1254 const VkImageSubresourceRange *range,
1255 VkFormat format, int level, int layer,
1256 const VkClearValue *clear_val)
1257 {
1258 VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1259 struct radv_image_view iview;
1260 uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level);
1261 uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level);
1262
1263 radv_image_view_init(&iview, cmd_buffer->device,
1264 &(VkImageViewCreateInfo) {
1265 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1266 .image = radv_image_to_handle(image),
1267 .viewType = radv_meta_get_view_type(image),
1268 .format = format,
1269 .subresourceRange = {
1270 .aspectMask = range->aspectMask,
1271 .baseMipLevel = range->baseMipLevel + level,
1272 .levelCount = 1,
1273 .baseArrayLayer = range->baseArrayLayer + layer,
1274 .layerCount = 1
1275 },
1276 });
1277
1278 VkFramebuffer fb;
1279 radv_CreateFramebuffer(device_h,
1280 &(VkFramebufferCreateInfo) {
1281 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1282 .attachmentCount = 1,
1283 .pAttachments = (VkImageView[]) {
1284 radv_image_view_to_handle(&iview),
1285 },
1286 .width = width,
1287 .height = height,
1288 .layers = 1
1289 },
1290 &cmd_buffer->pool->alloc,
1291 &fb);
1292
1293 VkAttachmentDescription att_desc = {
1294 .format = iview.vk_format,
1295 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1296 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1297 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1298 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1299 .initialLayout = image_layout,
1300 .finalLayout = image_layout,
1301 };
1302
1303 VkSubpassDescription subpass_desc = {
1304 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1305 .inputAttachmentCount = 0,
1306 .colorAttachmentCount = 0,
1307 .pColorAttachments = NULL,
1308 .pResolveAttachments = NULL,
1309 .pDepthStencilAttachment = NULL,
1310 .preserveAttachmentCount = 0,
1311 .pPreserveAttachments = NULL,
1312 };
1313
1314 const VkAttachmentReference att_ref = {
1315 .attachment = 0,
1316 .layout = image_layout,
1317 };
1318
1319 if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1320 subpass_desc.colorAttachmentCount = 1;
1321 subpass_desc.pColorAttachments = &att_ref;
1322 } else {
1323 subpass_desc.pDepthStencilAttachment = &att_ref;
1324 }
1325
1326 VkRenderPass pass;
1327 radv_CreateRenderPass(device_h,
1328 &(VkRenderPassCreateInfo) {
1329 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1330 .attachmentCount = 1,
1331 .pAttachments = &att_desc,
1332 .subpassCount = 1,
1333 .pSubpasses = &subpass_desc,
1334 },
1335 &cmd_buffer->pool->alloc,
1336 &pass);
1337
1338 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1339 &(VkRenderPassBeginInfo) {
1340 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1341 .renderArea = {
1342 .offset = { 0, 0, },
1343 .extent = {
1344 .width = width,
1345 .height = height,
1346 },
1347 },
1348 .renderPass = pass,
1349 .framebuffer = fb,
1350 .clearValueCount = 0,
1351 .pClearValues = NULL,
1352 },
1353 VK_SUBPASS_CONTENTS_INLINE);
1354
1355 VkClearAttachment clear_att = {
1356 .aspectMask = range->aspectMask,
1357 .colorAttachment = 0,
1358 .clearValue = *clear_val,
1359 };
1360
1361 VkClearRect clear_rect = {
1362 .rect = {
1363 .offset = { 0, 0 },
1364 .extent = { width, height },
1365 },
1366 .baseArrayLayer = range->baseArrayLayer,
1367 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1368 };
1369
1370 emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0);
1371
1372 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1373 radv_DestroyRenderPass(device_h, pass,
1374 &cmd_buffer->pool->alloc);
1375 radv_DestroyFramebuffer(device_h, fb,
1376 &cmd_buffer->pool->alloc);
1377 }
1378 static void
1379 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
1380 struct radv_image *image,
1381 VkImageLayout image_layout,
1382 const VkClearValue *clear_value,
1383 uint32_t range_count,
1384 const VkImageSubresourceRange *ranges,
1385 bool cs)
1386 {
1387 VkFormat format = image->vk_format;
1388 VkClearValue internal_clear_value = *clear_value;
1389
1390 if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
1391 uint32_t value;
1392 format = VK_FORMAT_R32_UINT;
1393 value = float3_to_rgb9e5(clear_value->color.float32);
1394 internal_clear_value.color.uint32[0] = value;
1395 }
1396
1397 if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
1398 uint8_t r, g;
1399 format = VK_FORMAT_R8_UINT;
1400 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
1401 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
1402 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
1403 }
1404
1405 for (uint32_t r = 0; r < range_count; r++) {
1406 const VkImageSubresourceRange *range = &ranges[r];
1407 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
1408 const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
1409 radv_minify(image->info.depth, range->baseMipLevel + l) :
1410 radv_get_layerCount(image, range);
1411 for (uint32_t s = 0; s < layer_count; ++s) {
1412
1413 if (cs) {
1414 struct radv_meta_blit2d_surf surf;
1415 surf.format = format;
1416 surf.image = image;
1417 surf.level = range->baseMipLevel + l;
1418 surf.layer = range->baseArrayLayer + s;
1419 surf.aspect_mask = range->aspectMask;
1420 radv_meta_clear_image_cs(cmd_buffer, &surf,
1421 &internal_clear_value.color);
1422 } else {
1423 radv_clear_image_layer(cmd_buffer, image, image_layout,
1424 range, format, l, s, &internal_clear_value);
1425 }
1426 }
1427 }
1428 }
1429 }
1430
1431 void radv_CmdClearColorImage(
1432 VkCommandBuffer commandBuffer,
1433 VkImage image_h,
1434 VkImageLayout imageLayout,
1435 const VkClearColorValue* pColor,
1436 uint32_t rangeCount,
1437 const VkImageSubresourceRange* pRanges)
1438 {
1439 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1440 RADV_FROM_HANDLE(radv_image, image, image_h);
1441 struct radv_meta_saved_state saved_state;
1442 bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1443
1444 if (cs) {
1445 radv_meta_save(&saved_state, cmd_buffer,
1446 RADV_META_SAVE_COMPUTE_PIPELINE |
1447 RADV_META_SAVE_CONSTANTS |
1448 RADV_META_SAVE_DESCRIPTORS);
1449 } else {
1450 radv_meta_save(&saved_state, cmd_buffer,
1451 RADV_META_SAVE_GRAPHICS_PIPELINE |
1452 RADV_META_SAVE_CONSTANTS);
1453 }
1454
1455 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1456 (const VkClearValue *) pColor,
1457 rangeCount, pRanges, cs);
1458
1459 radv_meta_restore(&saved_state, cmd_buffer);
1460 }
1461
1462 void radv_CmdClearDepthStencilImage(
1463 VkCommandBuffer commandBuffer,
1464 VkImage image_h,
1465 VkImageLayout imageLayout,
1466 const VkClearDepthStencilValue* pDepthStencil,
1467 uint32_t rangeCount,
1468 const VkImageSubresourceRange* pRanges)
1469 {
1470 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1471 RADV_FROM_HANDLE(radv_image, image, image_h);
1472 struct radv_meta_saved_state saved_state;
1473
1474 radv_meta_save(&saved_state, cmd_buffer,
1475 RADV_META_SAVE_GRAPHICS_PIPELINE |
1476 RADV_META_SAVE_CONSTANTS);
1477
1478 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1479 (const VkClearValue *) pDepthStencil,
1480 rangeCount, pRanges, false);
1481
1482 radv_meta_restore(&saved_state, cmd_buffer);
1483 }
1484
1485 void radv_CmdClearAttachments(
1486 VkCommandBuffer commandBuffer,
1487 uint32_t attachmentCount,
1488 const VkClearAttachment* pAttachments,
1489 uint32_t rectCount,
1490 const VkClearRect* pRects)
1491 {
1492 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1493 struct radv_meta_saved_state saved_state;
1494 enum radv_cmd_flush_bits pre_flush = 0;
1495 enum radv_cmd_flush_bits post_flush = 0;
1496
1497 if (!cmd_buffer->state.subpass)
1498 return;
1499
1500 radv_meta_save(&saved_state, cmd_buffer,
1501 RADV_META_SAVE_GRAPHICS_PIPELINE |
1502 RADV_META_SAVE_CONSTANTS);
1503
1504 /* FINISHME: We can do better than this dumb loop. It thrashes too much
1505 * state.
1506 */
1507 for (uint32_t a = 0; a < attachmentCount; ++a) {
1508 for (uint32_t r = 0; r < rectCount; ++r) {
1509 emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush,
1510 cmd_buffer->state.subpass->view_mask);
1511 }
1512 }
1513
1514 radv_meta_restore(&saved_state, cmd_buffer);
1515 cmd_buffer->state.flush_bits |= post_flush;
1516 }