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353e8382ca19892f5a5e554cfd2a4ea442810947
[mesa.git] / src / amd / vulkan / radv_meta_clear.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_meta.h"
25 #include "radv_private.h"
26 #include "nir/nir_builder.h"
27
28 #include "util/format_rgb9e5.h"
29 #include "vk_format.h"
30
31 enum {
32 DEPTH_CLEAR_SLOW,
33 DEPTH_CLEAR_FAST_EXPCLEAR,
34 DEPTH_CLEAR_FAST_NO_EXPCLEAR
35 };
36
37 static void
38 build_color_shaders(struct nir_shader **out_vs,
39 struct nir_shader **out_fs,
40 uint32_t frag_output)
41 {
42 nir_builder vs_b;
43 nir_builder fs_b;
44
45 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
46 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
47
48 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
49 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
50
51 const struct glsl_type *position_type = glsl_vec4_type();
52 const struct glsl_type *color_type = glsl_vec4_type();
53
54 nir_variable *vs_out_pos =
55 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
56 "gl_Position");
57 vs_out_pos->data.location = VARYING_SLOT_POS;
58
59 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
60 nir_intrinsic_set_base(in_color_load, 0);
61 nir_intrinsic_set_range(in_color_load, 16);
62 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
63 in_color_load->num_components = 4;
64 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
65 nir_builder_instr_insert(&fs_b, &in_color_load->instr);
66
67 nir_variable *fs_out_color =
68 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
69 "f_color");
70 fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
71
72 nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
73
74 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
75 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
76
77 const struct glsl_type *layer_type = glsl_int_type();
78 nir_variable *vs_out_layer =
79 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
80 "v_layer");
81 vs_out_layer->data.location = VARYING_SLOT_LAYER;
82 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
83 nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
84
85 nir_store_var(&vs_b, vs_out_layer, inst_id, 0x1);
86
87 *out_vs = vs_b.shader;
88 *out_fs = fs_b.shader;
89 }
90
91 static VkResult
92 create_pipeline(struct radv_device *device,
93 struct radv_render_pass *render_pass,
94 uint32_t samples,
95 struct nir_shader *vs_nir,
96 struct nir_shader *fs_nir,
97 const VkPipelineVertexInputStateCreateInfo *vi_state,
98 const VkPipelineDepthStencilStateCreateInfo *ds_state,
99 const VkPipelineColorBlendStateCreateInfo *cb_state,
100 const VkPipelineLayout layout,
101 const struct radv_graphics_pipeline_create_info *extra,
102 const VkAllocationCallbacks *alloc,
103 struct radv_pipeline **pipeline)
104 {
105 VkDevice device_h = radv_device_to_handle(device);
106 VkResult result;
107
108 struct radv_shader_module vs_m = { .nir = vs_nir };
109 struct radv_shader_module fs_m = { .nir = fs_nir };
110
111 VkPipeline pipeline_h = VK_NULL_HANDLE;
112 result = radv_graphics_pipeline_create(device_h,
113 radv_pipeline_cache_to_handle(&device->meta_state.cache),
114 &(VkGraphicsPipelineCreateInfo) {
115 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
116 .stageCount = fs_nir ? 2 : 1,
117 .pStages = (VkPipelineShaderStageCreateInfo[]) {
118 {
119 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
120 .stage = VK_SHADER_STAGE_VERTEX_BIT,
121 .module = radv_shader_module_to_handle(&vs_m),
122 .pName = "main",
123 },
124 {
125 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
126 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
127 .module = radv_shader_module_to_handle(&fs_m),
128 .pName = "main",
129 },
130 },
131 .pVertexInputState = vi_state,
132 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
133 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
134 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
135 .primitiveRestartEnable = false,
136 },
137 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
138 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
139 .viewportCount = 1,
140 .scissorCount = 1,
141 },
142 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
143 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
144 .rasterizerDiscardEnable = false,
145 .polygonMode = VK_POLYGON_MODE_FILL,
146 .cullMode = VK_CULL_MODE_NONE,
147 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
148 .depthBiasEnable = false,
149 },
150 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
151 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
152 .rasterizationSamples = samples,
153 .sampleShadingEnable = false,
154 .pSampleMask = NULL,
155 .alphaToCoverageEnable = false,
156 .alphaToOneEnable = false,
157 },
158 .pDepthStencilState = ds_state,
159 .pColorBlendState = cb_state,
160 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
161 /* The meta clear pipeline declares all state as dynamic.
162 * As a consequence, vkCmdBindPipeline writes no dynamic state
163 * to the cmd buffer. Therefore, at the end of the meta clear,
164 * we need only restore dynamic state was vkCmdSet.
165 */
166 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
167 .dynamicStateCount = 8,
168 .pDynamicStates = (VkDynamicState[]) {
169 /* Everything except stencil write mask */
170 VK_DYNAMIC_STATE_VIEWPORT,
171 VK_DYNAMIC_STATE_SCISSOR,
172 VK_DYNAMIC_STATE_LINE_WIDTH,
173 VK_DYNAMIC_STATE_DEPTH_BIAS,
174 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
175 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
176 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
177 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
178 },
179 },
180 .layout = layout,
181 .flags = 0,
182 .renderPass = radv_render_pass_to_handle(render_pass),
183 .subpass = 0,
184 },
185 extra,
186 alloc,
187 &pipeline_h);
188
189 ralloc_free(vs_nir);
190 ralloc_free(fs_nir);
191
192 *pipeline = radv_pipeline_from_handle(pipeline_h);
193
194 return result;
195 }
196
197 static VkResult
198 create_color_renderpass(struct radv_device *device,
199 VkFormat vk_format,
200 uint32_t samples,
201 VkRenderPass *pass)
202 {
203 return radv_CreateRenderPass(radv_device_to_handle(device),
204 &(VkRenderPassCreateInfo) {
205 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
206 .attachmentCount = 1,
207 .pAttachments = &(VkAttachmentDescription) {
208 .format = vk_format,
209 .samples = samples,
210 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
211 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
212 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
213 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
214 },
215 .subpassCount = 1,
216 .pSubpasses = &(VkSubpassDescription) {
217 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
218 .inputAttachmentCount = 0,
219 .colorAttachmentCount = 1,
220 .pColorAttachments = &(VkAttachmentReference) {
221 .attachment = 0,
222 .layout = VK_IMAGE_LAYOUT_GENERAL,
223 },
224 .pResolveAttachments = NULL,
225 .pDepthStencilAttachment = &(VkAttachmentReference) {
226 .attachment = VK_ATTACHMENT_UNUSED,
227 .layout = VK_IMAGE_LAYOUT_GENERAL,
228 },
229 .preserveAttachmentCount = 1,
230 .pPreserveAttachments = (uint32_t[]) { 0 },
231 },
232 .dependencyCount = 0,
233 }, &device->meta_state.alloc, pass);
234 }
235
236 static VkResult
237 create_color_pipeline(struct radv_device *device,
238 uint32_t samples,
239 uint32_t frag_output,
240 struct radv_pipeline **pipeline,
241 VkRenderPass pass)
242 {
243 struct nir_shader *vs_nir;
244 struct nir_shader *fs_nir;
245 VkResult result;
246 build_color_shaders(&vs_nir, &fs_nir, frag_output);
247
248 const VkPipelineVertexInputStateCreateInfo vi_state = {
249 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
250 .vertexBindingDescriptionCount = 0,
251 .vertexAttributeDescriptionCount = 0,
252 };
253
254 const VkPipelineDepthStencilStateCreateInfo ds_state = {
255 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
256 .depthTestEnable = false,
257 .depthWriteEnable = false,
258 .depthBoundsTestEnable = false,
259 .stencilTestEnable = false,
260 };
261
262 VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
263 blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
264 .blendEnable = false,
265 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
266 VK_COLOR_COMPONENT_R_BIT |
267 VK_COLOR_COMPONENT_G_BIT |
268 VK_COLOR_COMPONENT_B_BIT,
269 };
270
271 const VkPipelineColorBlendStateCreateInfo cb_state = {
272 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
273 .logicOpEnable = false,
274 .attachmentCount = MAX_RTS,
275 .pAttachments = blend_attachment_state
276 };
277
278
279 struct radv_graphics_pipeline_create_info extra = {
280 .use_rectlist = true,
281 };
282 result = create_pipeline(device, radv_render_pass_from_handle(pass),
283 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
284 device->meta_state.clear_color_p_layout,
285 &extra, &device->meta_state.alloc, pipeline);
286
287 return result;
288 }
289
290 static void
291 destroy_pipeline(struct radv_device *device, struct radv_pipeline *pipeline)
292 {
293 if (!pipeline)
294 return;
295
296 radv_DestroyPipeline(radv_device_to_handle(device),
297 radv_pipeline_to_handle(pipeline),
298 &device->meta_state.alloc);
299
300 }
301
302 static void
303 destroy_render_pass(struct radv_device *device, VkRenderPass renderpass)
304 {
305 radv_DestroyRenderPass(radv_device_to_handle(device), renderpass,
306 &device->meta_state.alloc);
307 }
308
309 void
310 radv_device_finish_meta_clear_state(struct radv_device *device)
311 {
312 struct radv_meta_state *state = &device->meta_state;
313
314 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
315 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
316 destroy_pipeline(device, state->clear[i].color_pipelines[j]);
317 destroy_render_pass(device, state->clear[i].render_pass[j]);
318 }
319
320 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
321 destroy_pipeline(device, state->clear[i].depth_only_pipeline[j]);
322 destroy_pipeline(device, state->clear[i].stencil_only_pipeline[j]);
323 destroy_pipeline(device, state->clear[i].depthstencil_pipeline[j]);
324 }
325 destroy_render_pass(device, state->clear[i].depthstencil_rp);
326 }
327 radv_DestroyPipelineLayout(radv_device_to_handle(device),
328 state->clear_color_p_layout,
329 &state->alloc);
330 radv_DestroyPipelineLayout(radv_device_to_handle(device),
331 state->clear_depth_p_layout,
332 &state->alloc);
333 }
334
335 static void
336 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
337 const VkClearAttachment *clear_att,
338 const VkClearRect *clear_rect)
339 {
340 struct radv_device *device = cmd_buffer->device;
341 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
342 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
343 const uint32_t subpass_att = clear_att->colorAttachment;
344 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
345 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
346 const uint32_t samples = iview->image->info.samples;
347 const uint32_t samples_log2 = ffs(samples) - 1;
348 unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
349 struct radv_pipeline *pipeline;
350 VkClearColorValue clear_value = clear_att->clearValue.color;
351 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
352 VkPipeline pipeline_h;
353
354 if (fs_key == -1) {
355 radv_finishme("color clears incomplete");
356 return;
357 }
358 pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
359 pipeline_h = radv_pipeline_to_handle(pipeline);
360
361 if (!pipeline) {
362 radv_finishme("color clears incomplete");
363 return;
364 }
365 assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
366 assert(pipeline);
367 assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
368 assert(clear_att->colorAttachment < subpass->color_count);
369
370 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
371 device->meta_state.clear_color_p_layout,
372 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
373 &clear_value);
374
375 struct radv_subpass clear_subpass = {
376 .color_count = 1,
377 .color_attachments = (VkAttachmentReference[]) {
378 subpass->color_attachments[clear_att->colorAttachment]
379 },
380 .depth_stencil_attachment = (VkAttachmentReference) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
381 };
382
383 radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
384
385 if (cmd_buffer->state.pipeline != pipeline) {
386 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
387 pipeline_h);
388 }
389
390 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
391 .x = clear_rect->rect.offset.x,
392 .y = clear_rect->rect.offset.y,
393 .width = clear_rect->rect.extent.width,
394 .height = clear_rect->rect.extent.height,
395 .minDepth = 0.0f,
396 .maxDepth = 1.0f
397 });
398
399 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
400
401 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, 0);
402
403 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
404 }
405
406
407 static void
408 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
409 {
410 nir_builder vs_b, fs_b;
411
412 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
413 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
414
415 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
416 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
417 const struct glsl_type *position_out_type = glsl_vec4_type();
418
419 nir_variable *vs_out_pos =
420 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
421 "gl_Position");
422 vs_out_pos->data.location = VARYING_SLOT_POS;
423
424 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
425 nir_intrinsic_set_base(in_color_load, 0);
426 nir_intrinsic_set_range(in_color_load, 4);
427 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
428 in_color_load->num_components = 1;
429 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
430 nir_builder_instr_insert(&vs_b, &in_color_load->instr);
431
432 nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
433 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
434
435 const struct glsl_type *layer_type = glsl_int_type();
436 nir_variable *vs_out_layer =
437 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
438 "v_layer");
439 vs_out_layer->data.location = VARYING_SLOT_LAYER;
440 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
441 nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
442 nir_store_var(&vs_b, vs_out_layer, inst_id, 0x1);
443
444 *out_vs = vs_b.shader;
445 *out_fs = fs_b.shader;
446 }
447
448 static VkResult
449 create_depthstencil_renderpass(struct radv_device *device,
450 uint32_t samples,
451 VkRenderPass *render_pass)
452 {
453 return radv_CreateRenderPass(radv_device_to_handle(device),
454 &(VkRenderPassCreateInfo) {
455 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
456 .attachmentCount = 1,
457 .pAttachments = &(VkAttachmentDescription) {
458 .format = VK_FORMAT_D32_SFLOAT_S8_UINT,
459 .samples = samples,
460 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
461 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
462 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
463 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
464 },
465 .subpassCount = 1,
466 .pSubpasses = &(VkSubpassDescription) {
467 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
468 .inputAttachmentCount = 0,
469 .colorAttachmentCount = 0,
470 .pColorAttachments = NULL,
471 .pResolveAttachments = NULL,
472 .pDepthStencilAttachment = &(VkAttachmentReference) {
473 .attachment = 0,
474 .layout = VK_IMAGE_LAYOUT_GENERAL,
475 },
476 .preserveAttachmentCount = 1,
477 .pPreserveAttachments = (uint32_t[]) { 0 },
478 },
479 .dependencyCount = 0,
480 }, &device->meta_state.alloc, render_pass);
481 }
482
483 static VkResult
484 create_depthstencil_pipeline(struct radv_device *device,
485 VkImageAspectFlags aspects,
486 uint32_t samples,
487 int index,
488 struct radv_pipeline **pipeline,
489 VkRenderPass render_pass)
490 {
491 struct nir_shader *vs_nir, *fs_nir;
492 VkResult result;
493 build_depthstencil_shader(&vs_nir, &fs_nir);
494
495 const VkPipelineVertexInputStateCreateInfo vi_state = {
496 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
497 .vertexBindingDescriptionCount = 0,
498 .vertexAttributeDescriptionCount = 0,
499 };
500
501 const VkPipelineDepthStencilStateCreateInfo ds_state = {
502 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
503 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
504 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
505 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
506 .depthBoundsTestEnable = false,
507 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
508 .front = {
509 .passOp = VK_STENCIL_OP_REPLACE,
510 .compareOp = VK_COMPARE_OP_ALWAYS,
511 .writeMask = UINT32_MAX,
512 .reference = 0, /* dynamic */
513 },
514 .back = { 0 /* dont care */ },
515 };
516
517 const VkPipelineColorBlendStateCreateInfo cb_state = {
518 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
519 .logicOpEnable = false,
520 .attachmentCount = 0,
521 .pAttachments = NULL,
522 };
523
524 struct radv_graphics_pipeline_create_info extra = {
525 .use_rectlist = true,
526 };
527
528 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
529 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
530 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
531 }
532 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
533 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
534 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
535 }
536 result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
537 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
538 device->meta_state.clear_depth_p_layout,
539 &extra, &device->meta_state.alloc, pipeline);
540 return result;
541 }
542
543 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
544 const struct radv_image_view *iview,
545 VkImageLayout layout,
546 const VkClearRect *clear_rect)
547 {
548 uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
549 cmd_buffer->queue_family_index,
550 cmd_buffer->queue_family_index);
551 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
552 clear_rect->rect.extent.width != iview->extent.width ||
553 clear_rect->rect.extent.height != iview->extent.height)
554 return false;
555 if (iview->image->surface.htile_size &&
556 iview->base_mip == 0 &&
557 iview->base_layer == 0 &&
558 radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
559 !radv_image_extent_compare(iview->image, &iview->extent))
560 return true;
561 return false;
562 }
563
564 static struct radv_pipeline *
565 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
566 struct radv_meta_state *meta_state,
567 const struct radv_image_view *iview,
568 int samples_log2,
569 VkImageAspectFlags aspects,
570 VkImageLayout layout,
571 const VkClearRect *clear_rect,
572 VkClearDepthStencilValue clear_value)
573 {
574 bool fast = depth_view_can_fast_clear(cmd_buffer, iview, layout, clear_rect);
575 int index = DEPTH_CLEAR_SLOW;
576
577 if (fast) {
578 /* we don't know the previous clear values, so we always have
579 * the NO_EXPCLEAR path */
580 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
581 }
582
583 switch (aspects) {
584 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
585 return meta_state->clear[samples_log2].depthstencil_pipeline[index];
586 case VK_IMAGE_ASPECT_DEPTH_BIT:
587 return meta_state->clear[samples_log2].depth_only_pipeline[index];
588 case VK_IMAGE_ASPECT_STENCIL_BIT:
589 return meta_state->clear[samples_log2].stencil_only_pipeline[index];
590 }
591 unreachable("expected depth or stencil aspect");
592 }
593
594 static void
595 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
596 const VkClearAttachment *clear_att,
597 const VkClearRect *clear_rect)
598 {
599 struct radv_device *device = cmd_buffer->device;
600 struct radv_meta_state *meta_state = &device->meta_state;
601 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
602 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
603 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
604 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
605 VkImageAspectFlags aspects = clear_att->aspectMask;
606 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
607 const uint32_t samples = iview->image->info.samples;
608 const uint32_t samples_log2 = ffs(samples) - 1;
609 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
610
611 assert(aspects == VK_IMAGE_ASPECT_DEPTH_BIT ||
612 aspects == VK_IMAGE_ASPECT_STENCIL_BIT ||
613 aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
614 VK_IMAGE_ASPECT_STENCIL_BIT));
615 assert(pass_att != VK_ATTACHMENT_UNUSED);
616
617 if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
618 clear_value.depth = 1.0f;
619
620 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
621 device->meta_state.clear_depth_p_layout,
622 VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
623 &clear_value.depth);
624
625 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
626 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
627 clear_value.stencil);
628 }
629
630 struct radv_pipeline *pipeline = pick_depthstencil_pipeline(cmd_buffer,
631 meta_state,
632 iview,
633 samples_log2,
634 aspects,
635 subpass->depth_stencil_attachment.layout,
636 clear_rect,
637 clear_value);
638 if (cmd_buffer->state.pipeline != pipeline) {
639 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
640 radv_pipeline_to_handle(pipeline));
641 }
642
643 if (depth_view_can_fast_clear(cmd_buffer, iview, subpass->depth_stencil_attachment.layout, clear_rect))
644 radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
645
646 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
647 .x = clear_rect->rect.offset.x,
648 .y = clear_rect->rect.offset.y,
649 .width = clear_rect->rect.extent.width,
650 .height = clear_rect->rect.extent.height,
651 .minDepth = 0.0f,
652 .maxDepth = 1.0f
653 });
654
655 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
656
657 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, 0);
658 }
659
660 static bool
661 emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
662 const VkClearAttachment *clear_att,
663 const VkClearRect *clear_rect,
664 enum radv_cmd_flush_bits *pre_flush,
665 enum radv_cmd_flush_bits *post_flush)
666 {
667 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
668 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
669 VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
670 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
671 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
672 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
673 VkImageAspectFlags aspects = clear_att->aspectMask;
674 uint32_t clear_word;
675
676 if (!iview->image->surface.htile_size)
677 return false;
678
679 if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
680 return false;
681
682 if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
683 goto fail;
684
685 /* don't fast clear 3D */
686 if (iview->image->type == VK_IMAGE_TYPE_3D)
687 goto fail;
688
689 /* all layers are bound */
690 if (iview->base_layer > 0)
691 goto fail;
692 if (iview->image->info.array_size != iview->layer_count)
693 goto fail;
694
695 if (iview->image->info.levels > 1)
696 goto fail;
697
698 if (!radv_image_extent_compare(iview->image, &iview->extent))
699 goto fail;
700
701 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
702 clear_rect->rect.extent.width != iview->image->info.width ||
703 clear_rect->rect.extent.height != iview->image->info.height)
704 goto fail;
705
706 if (clear_rect->baseArrayLayer != 0)
707 goto fail;
708 if (clear_rect->layerCount != iview->image->info.array_size)
709 goto fail;
710
711 if ((clear_value.depth != 0.0 && clear_value.depth != 1.0) || !(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
712 goto fail;
713
714 if (vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) {
715 if (clear_value.stencil != 0 || !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))
716 goto fail;
717 clear_word = clear_value.depth ? 0xfffc0000 : 0;
718 } else
719 clear_word = clear_value.depth ? 0xfffffff0 : 0;
720
721 if (pre_flush) {
722 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
723 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
724 *pre_flush |= cmd_buffer->state.flush_bits;
725 } else
726 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
727 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
728
729 radv_fill_buffer(cmd_buffer, iview->image->bo,
730 iview->image->offset + iview->image->htile_offset,
731 iview->image->surface.htile_size, clear_word);
732
733
734 radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
735 if (post_flush)
736 *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
737 RADV_CMD_FLAG_INV_VMEM_L1 |
738 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
739 else
740 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
741 RADV_CMD_FLAG_INV_VMEM_L1 |
742 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
743 return true;
744 fail:
745 return false;
746 }
747
748 static VkFormat pipeline_formats[] = {
749 VK_FORMAT_R8G8B8A8_UNORM,
750 VK_FORMAT_R8G8B8A8_UINT,
751 VK_FORMAT_R8G8B8A8_SINT,
752 VK_FORMAT_R16G16B16A16_UNORM,
753 VK_FORMAT_R16G16B16A16_SNORM,
754 VK_FORMAT_R16G16B16A16_UINT,
755 VK_FORMAT_R16G16B16A16_SINT,
756 VK_FORMAT_R32_SFLOAT,
757 VK_FORMAT_R32G32_SFLOAT,
758 VK_FORMAT_R32G32B32A32_SFLOAT
759 };
760
761 VkResult
762 radv_device_init_meta_clear_state(struct radv_device *device)
763 {
764 VkResult res;
765 struct radv_meta_state *state = &device->meta_state;
766
767 memset(&device->meta_state.clear, 0, sizeof(device->meta_state.clear));
768
769 VkPipelineLayoutCreateInfo pl_color_create_info = {
770 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
771 .setLayoutCount = 0,
772 .pushConstantRangeCount = 1,
773 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
774 };
775
776 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
777 &pl_color_create_info,
778 &device->meta_state.alloc,
779 &device->meta_state.clear_color_p_layout);
780 if (res != VK_SUCCESS)
781 goto fail;
782
783 VkPipelineLayoutCreateInfo pl_depth_create_info = {
784 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
785 .setLayoutCount = 0,
786 .pushConstantRangeCount = 1,
787 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
788 };
789
790 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
791 &pl_depth_create_info,
792 &device->meta_state.alloc,
793 &device->meta_state.clear_depth_p_layout);
794 if (res != VK_SUCCESS)
795 goto fail;
796
797 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
798 uint32_t samples = 1 << i;
799 for (uint32_t j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
800 VkFormat format = pipeline_formats[j];
801 unsigned fs_key = radv_format_meta_fs_key(format);
802 assert(!state->clear[i].color_pipelines[fs_key]);
803
804 res = create_color_renderpass(device, format, samples,
805 &state->clear[i].render_pass[fs_key]);
806 if (res != VK_SUCCESS)
807 goto fail;
808
809 res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
810 state->clear[i].render_pass[fs_key]);
811 if (res != VK_SUCCESS)
812 goto fail;
813
814 }
815
816 res = create_depthstencil_renderpass(device,
817 samples,
818 &state->clear[i].depthstencil_rp);
819 if (res != VK_SUCCESS)
820 goto fail;
821
822 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
823 res = create_depthstencil_pipeline(device,
824 VK_IMAGE_ASPECT_DEPTH_BIT,
825 samples,
826 j,
827 &state->clear[i].depth_only_pipeline[j],
828 state->clear[i].depthstencil_rp);
829 if (res != VK_SUCCESS)
830 goto fail;
831
832 res = create_depthstencil_pipeline(device,
833 VK_IMAGE_ASPECT_STENCIL_BIT,
834 samples,
835 j,
836 &state->clear[i].stencil_only_pipeline[j],
837 state->clear[i].depthstencil_rp);
838 if (res != VK_SUCCESS)
839 goto fail;
840
841 res = create_depthstencil_pipeline(device,
842 VK_IMAGE_ASPECT_DEPTH_BIT |
843 VK_IMAGE_ASPECT_STENCIL_BIT,
844 samples,
845 j,
846 &state->clear[i].depthstencil_pipeline[j],
847 state->clear[i].depthstencil_rp);
848 if (res != VK_SUCCESS)
849 goto fail;
850 }
851 }
852 return VK_SUCCESS;
853
854 fail:
855 radv_device_finish_meta_clear_state(device);
856 return res;
857 }
858
859 static void vi_get_fast_clear_parameters(VkFormat format,
860 const VkClearColorValue *clear_value,
861 uint32_t* reset_value,
862 bool *can_avoid_fast_clear_elim)
863 {
864 bool values[4] = {};
865 int extra_channel;
866 bool main_value = false;
867 bool extra_value = false;
868 int i;
869 *can_avoid_fast_clear_elim = false;
870
871 *reset_value = 0x20202020U;
872
873 const struct vk_format_description *desc = vk_format_description(format);
874 if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
875 format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
876 format == VK_FORMAT_B5G6R5_UNORM_PACK16)
877 extra_channel = -1;
878 else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
879 if (radv_translate_colorswap(format, false) <= 1)
880 extra_channel = desc->nr_channels - 1;
881 else
882 extra_channel = 0;
883 } else
884 return;
885
886 for (i = 0; i < 4; i++) {
887 int index = desc->swizzle[i] - VK_SWIZZLE_X;
888 if (desc->swizzle[i] < VK_SWIZZLE_X ||
889 desc->swizzle[i] > VK_SWIZZLE_W)
890 continue;
891
892 if (desc->channel[i].pure_integer &&
893 desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
894 /* Use the maximum value for clamping the clear color. */
895 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
896
897 values[i] = clear_value->int32[i] != 0;
898 if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
899 return;
900 } else if (desc->channel[i].pure_integer &&
901 desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
902 /* Use the maximum value for clamping the clear color. */
903 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
904
905 values[i] = clear_value->uint32[i] != 0U;
906 if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
907 return;
908 } else {
909 values[i] = clear_value->float32[i] != 0.0F;
910 if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
911 return;
912 }
913
914 if (index == extra_channel)
915 extra_value = values[i];
916 else
917 main_value = values[i];
918 }
919
920 for (int i = 0; i < 4; ++i)
921 if (values[i] != main_value &&
922 desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
923 desc->swizzle[i] >= VK_SWIZZLE_X &&
924 desc->swizzle[i] <= VK_SWIZZLE_W)
925 return;
926
927 *can_avoid_fast_clear_elim = true;
928 if (main_value)
929 *reset_value |= 0x80808080U;
930
931 if (extra_value)
932 *reset_value |= 0x40404040U;
933 return;
934 }
935
936 static bool
937 emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
938 const VkClearAttachment *clear_att,
939 const VkClearRect *clear_rect,
940 enum radv_cmd_flush_bits *pre_flush,
941 enum radv_cmd_flush_bits *post_flush)
942 {
943 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
944 const uint32_t subpass_att = clear_att->colorAttachment;
945 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
946 VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
947 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
948 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
949 VkClearColorValue clear_value = clear_att->clearValue.color;
950 uint32_t clear_color[2];
951 bool ret;
952
953 if (!iview->image->cmask.size && !iview->image->surface.dcc_size)
954 return false;
955
956 if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
957 return false;
958
959 if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
960 goto fail;
961
962 /* don't fast clear 3D */
963 if (iview->image->type == VK_IMAGE_TYPE_3D)
964 goto fail;
965
966 /* all layers are bound */
967 if (iview->base_layer > 0)
968 goto fail;
969 if (iview->image->info.array_size != iview->layer_count)
970 goto fail;
971
972 if (iview->image->info.levels > 1)
973 goto fail;
974
975 if (iview->image->surface.u.legacy.level[0].mode < RADEON_SURF_MODE_1D)
976 goto fail;
977 if (!radv_image_extent_compare(iview->image, &iview->extent))
978 goto fail;
979
980 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
981 clear_rect->rect.extent.width != iview->image->info.width ||
982 clear_rect->rect.extent.height != iview->image->info.height)
983 goto fail;
984
985 if (clear_rect->baseArrayLayer != 0)
986 goto fail;
987 if (clear_rect->layerCount != iview->image->info.array_size)
988 goto fail;
989
990 /* RB+ doesn't work with CMASK fast clear on Stoney. */
991 if (!iview->image->surface.dcc_size &&
992 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY)
993 goto fail;
994
995 /* DCC */
996 ret = radv_format_pack_clear_color(iview->image->vk_format,
997 clear_color, &clear_value);
998 if (ret == false)
999 goto fail;
1000
1001 if (pre_flush) {
1002 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1003 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
1004 *pre_flush |= cmd_buffer->state.flush_bits;
1005 } else
1006 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1007 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1008 /* clear cmask buffer */
1009 if (iview->image->surface.dcc_size) {
1010 uint32_t reset_value;
1011 bool can_avoid_fast_clear_elim;
1012 vi_get_fast_clear_parameters(iview->image->vk_format,
1013 &clear_value, &reset_value,
1014 &can_avoid_fast_clear_elim);
1015
1016 radv_fill_buffer(cmd_buffer, iview->image->bo,
1017 iview->image->offset + iview->image->dcc_offset,
1018 iview->image->surface.dcc_size, reset_value);
1019 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
1020 !can_avoid_fast_clear_elim);
1021 } else {
1022
1023 if (iview->image->surface.bpe > 8) {
1024 /* 128 bit formats not supported */
1025 return false;
1026 }
1027 radv_fill_buffer(cmd_buffer, iview->image->bo,
1028 iview->image->offset + iview->image->cmask.offset,
1029 iview->image->cmask.size, 0);
1030 }
1031
1032 if (post_flush)
1033 *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1034 RADV_CMD_FLAG_INV_VMEM_L1 |
1035 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1036 else
1037 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1038 RADV_CMD_FLAG_INV_VMEM_L1 |
1039 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1040
1041 radv_set_color_clear_regs(cmd_buffer, iview->image, subpass_att, clear_color);
1042
1043 return true;
1044 fail:
1045 return false;
1046 }
1047
1048 /**
1049 * The parameters mean that same as those in vkCmdClearAttachments.
1050 */
1051 static void
1052 emit_clear(struct radv_cmd_buffer *cmd_buffer,
1053 const VkClearAttachment *clear_att,
1054 const VkClearRect *clear_rect,
1055 enum radv_cmd_flush_bits *pre_flush,
1056 enum radv_cmd_flush_bits *post_flush)
1057 {
1058 if (clear_att->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1059
1060 if (!emit_fast_color_clear(cmd_buffer, clear_att, clear_rect,
1061 pre_flush, post_flush))
1062 emit_color_clear(cmd_buffer, clear_att, clear_rect);
1063 } else {
1064 assert(clear_att->aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT |
1065 VK_IMAGE_ASPECT_STENCIL_BIT));
1066 if (!emit_fast_htile_clear(cmd_buffer, clear_att, clear_rect,
1067 pre_flush, post_flush))
1068 emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
1069 }
1070 }
1071
1072 static bool
1073 subpass_needs_clear(const struct radv_cmd_buffer *cmd_buffer)
1074 {
1075 const struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1076 uint32_t ds;
1077
1078 if (!cmd_state->subpass)
1079 return false;
1080 ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1081 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1082 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1083 if (cmd_state->attachments[a].pending_clear_aspects) {
1084 return true;
1085 }
1086 }
1087
1088 if (ds != VK_ATTACHMENT_UNUSED &&
1089 cmd_state->attachments[ds].pending_clear_aspects) {
1090 return true;
1091 }
1092
1093 return false;
1094 }
1095
1096 /**
1097 * Emit any pending attachment clears for the current subpass.
1098 *
1099 * @see radv_attachment_state::pending_clear_aspects
1100 */
1101 void
1102 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1103 {
1104 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1105 struct radv_meta_saved_state saved_state;
1106 enum radv_cmd_flush_bits pre_flush = 0;
1107 enum radv_cmd_flush_bits post_flush = 0;
1108
1109 if (!subpass_needs_clear(cmd_buffer))
1110 return;
1111
1112 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
1113
1114 VkClearRect clear_rect = {
1115 .rect = cmd_state->render_area,
1116 .baseArrayLayer = 0,
1117 .layerCount = cmd_state->framebuffer->layers,
1118 };
1119
1120 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1121 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1122
1123 if (!cmd_state->attachments[a].pending_clear_aspects)
1124 continue;
1125
1126 assert(cmd_state->attachments[a].pending_clear_aspects ==
1127 VK_IMAGE_ASPECT_COLOR_BIT);
1128
1129 VkClearAttachment clear_att = {
1130 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1131 .colorAttachment = i, /* Use attachment index relative to subpass */
1132 .clearValue = cmd_state->attachments[a].clear_value,
1133 };
1134
1135 emit_clear(cmd_buffer, &clear_att, &clear_rect, &pre_flush, &post_flush);
1136 cmd_state->attachments[a].pending_clear_aspects = 0;
1137 }
1138
1139 uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1140
1141 if (ds != VK_ATTACHMENT_UNUSED) {
1142
1143 if (cmd_state->attachments[ds].pending_clear_aspects) {
1144
1145 VkClearAttachment clear_att = {
1146 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1147 .clearValue = cmd_state->attachments[ds].clear_value,
1148 };
1149
1150 emit_clear(cmd_buffer, &clear_att, &clear_rect,
1151 &pre_flush, &post_flush);
1152 cmd_state->attachments[ds].pending_clear_aspects = 0;
1153 }
1154 }
1155
1156 radv_meta_restore(&saved_state, cmd_buffer);
1157 cmd_buffer->state.flush_bits |= post_flush;
1158 }
1159
1160 static void
1161 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1162 struct radv_image *image,
1163 VkImageLayout image_layout,
1164 const VkImageSubresourceRange *range,
1165 VkFormat format, int level, int layer,
1166 const VkClearValue *clear_val)
1167 {
1168 VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1169 struct radv_image_view iview;
1170 radv_image_view_init(&iview, cmd_buffer->device,
1171 &(VkImageViewCreateInfo) {
1172 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1173 .image = radv_image_to_handle(image),
1174 .viewType = radv_meta_get_view_type(image),
1175 .format = format,
1176 .subresourceRange = {
1177 .aspectMask = range->aspectMask,
1178 .baseMipLevel = range->baseMipLevel + level,
1179 .levelCount = 1,
1180 .baseArrayLayer = range->baseArrayLayer + layer,
1181 .layerCount = 1
1182 },
1183 });
1184
1185 VkFramebuffer fb;
1186 radv_CreateFramebuffer(device_h,
1187 &(VkFramebufferCreateInfo) {
1188 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1189 .attachmentCount = 1,
1190 .pAttachments = (VkImageView[]) {
1191 radv_image_view_to_handle(&iview),
1192 },
1193 .width = iview.extent.width,
1194 .height = iview.extent.height,
1195 .layers = 1
1196 },
1197 &cmd_buffer->pool->alloc,
1198 &fb);
1199
1200 VkAttachmentDescription att_desc = {
1201 .format = iview.vk_format,
1202 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1203 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1204 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1205 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1206 .initialLayout = image_layout,
1207 .finalLayout = image_layout,
1208 };
1209
1210 VkSubpassDescription subpass_desc = {
1211 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1212 .inputAttachmentCount = 0,
1213 .colorAttachmentCount = 0,
1214 .pColorAttachments = NULL,
1215 .pResolveAttachments = NULL,
1216 .pDepthStencilAttachment = NULL,
1217 .preserveAttachmentCount = 0,
1218 .pPreserveAttachments = NULL,
1219 };
1220
1221 const VkAttachmentReference att_ref = {
1222 .attachment = 0,
1223 .layout = image_layout,
1224 };
1225
1226 if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1227 subpass_desc.colorAttachmentCount = 1;
1228 subpass_desc.pColorAttachments = &att_ref;
1229 } else {
1230 subpass_desc.pDepthStencilAttachment = &att_ref;
1231 }
1232
1233 VkRenderPass pass;
1234 radv_CreateRenderPass(device_h,
1235 &(VkRenderPassCreateInfo) {
1236 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1237 .attachmentCount = 1,
1238 .pAttachments = &att_desc,
1239 .subpassCount = 1,
1240 .pSubpasses = &subpass_desc,
1241 },
1242 &cmd_buffer->pool->alloc,
1243 &pass);
1244
1245 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1246 &(VkRenderPassBeginInfo) {
1247 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1248 .renderArea = {
1249 .offset = { 0, 0, },
1250 .extent = {
1251 .width = iview.extent.width,
1252 .height = iview.extent.height,
1253 },
1254 },
1255 .renderPass = pass,
1256 .framebuffer = fb,
1257 .clearValueCount = 0,
1258 .pClearValues = NULL,
1259 },
1260 VK_SUBPASS_CONTENTS_INLINE);
1261
1262 VkClearAttachment clear_att = {
1263 .aspectMask = range->aspectMask,
1264 .colorAttachment = 0,
1265 .clearValue = *clear_val,
1266 };
1267
1268 VkClearRect clear_rect = {
1269 .rect = {
1270 .offset = { 0, 0 },
1271 .extent = { iview.extent.width, iview.extent.height },
1272 },
1273 .baseArrayLayer = range->baseArrayLayer,
1274 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1275 };
1276
1277 emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL);
1278
1279 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1280 radv_DestroyRenderPass(device_h, pass,
1281 &cmd_buffer->pool->alloc);
1282 radv_DestroyFramebuffer(device_h, fb,
1283 &cmd_buffer->pool->alloc);
1284 }
1285 static void
1286 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
1287 struct radv_image *image,
1288 VkImageLayout image_layout,
1289 const VkClearValue *clear_value,
1290 uint32_t range_count,
1291 const VkImageSubresourceRange *ranges,
1292 bool cs)
1293 {
1294 VkFormat format = image->vk_format;
1295 VkClearValue internal_clear_value = *clear_value;
1296
1297 if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
1298 uint32_t value;
1299 format = VK_FORMAT_R32_UINT;
1300 value = float3_to_rgb9e5(clear_value->color.float32);
1301 internal_clear_value.color.uint32[0] = value;
1302 }
1303
1304 if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
1305 uint8_t r, g;
1306 format = VK_FORMAT_R8_UINT;
1307 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
1308 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
1309 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
1310 }
1311
1312 for (uint32_t r = 0; r < range_count; r++) {
1313 const VkImageSubresourceRange *range = &ranges[r];
1314 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
1315 const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
1316 radv_minify(image->info.depth, range->baseMipLevel + l) :
1317 radv_get_layerCount(image, range);
1318 for (uint32_t s = 0; s < layer_count; ++s) {
1319
1320 if (cs) {
1321 struct radv_meta_blit2d_surf surf;
1322 surf.format = format;
1323 surf.image = image;
1324 surf.level = range->baseMipLevel + l;
1325 surf.layer = range->baseArrayLayer + s;
1326 surf.aspect_mask = range->aspectMask;
1327 radv_meta_clear_image_cs(cmd_buffer, &surf,
1328 &internal_clear_value.color);
1329 } else {
1330 radv_clear_image_layer(cmd_buffer, image, image_layout,
1331 range, format, l, s, &internal_clear_value);
1332 }
1333 }
1334 }
1335 }
1336 }
1337
1338 union meta_saved_state {
1339 struct radv_meta_saved_state gfx;
1340 struct radv_meta_saved_compute_state compute;
1341 };
1342
1343 void radv_CmdClearColorImage(
1344 VkCommandBuffer commandBuffer,
1345 VkImage image_h,
1346 VkImageLayout imageLayout,
1347 const VkClearColorValue* pColor,
1348 uint32_t rangeCount,
1349 const VkImageSubresourceRange* pRanges)
1350 {
1351 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1352 RADV_FROM_HANDLE(radv_image, image, image_h);
1353 union meta_saved_state saved_state;
1354 bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1355
1356 if (cs)
1357 radv_meta_begin_cleari(cmd_buffer, &saved_state.compute);
1358 else
1359 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state.gfx, cmd_buffer);
1360
1361 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1362 (const VkClearValue *) pColor,
1363 rangeCount, pRanges, cs);
1364
1365 if (cs)
1366 radv_meta_end_cleari(cmd_buffer, &saved_state.compute);
1367 else
1368 radv_meta_restore(&saved_state.gfx, cmd_buffer);
1369 }
1370
1371 void radv_CmdClearDepthStencilImage(
1372 VkCommandBuffer commandBuffer,
1373 VkImage image_h,
1374 VkImageLayout imageLayout,
1375 const VkClearDepthStencilValue* pDepthStencil,
1376 uint32_t rangeCount,
1377 const VkImageSubresourceRange* pRanges)
1378 {
1379 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1380 RADV_FROM_HANDLE(radv_image, image, image_h);
1381 struct radv_meta_saved_state saved_state;
1382
1383 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
1384
1385 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1386 (const VkClearValue *) pDepthStencil,
1387 rangeCount, pRanges, false);
1388
1389 radv_meta_restore(&saved_state, cmd_buffer);
1390 }
1391
1392 void radv_CmdClearAttachments(
1393 VkCommandBuffer commandBuffer,
1394 uint32_t attachmentCount,
1395 const VkClearAttachment* pAttachments,
1396 uint32_t rectCount,
1397 const VkClearRect* pRects)
1398 {
1399 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1400 struct radv_meta_saved_state saved_state;
1401 enum radv_cmd_flush_bits pre_flush = 0;
1402 enum radv_cmd_flush_bits post_flush = 0;
1403
1404 if (!cmd_buffer->state.subpass)
1405 return;
1406
1407 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
1408
1409 /* FINISHME: We can do better than this dumb loop. It thrashes too much
1410 * state.
1411 */
1412 for (uint32_t a = 0; a < attachmentCount; ++a) {
1413 for (uint32_t r = 0; r < rectCount; ++r) {
1414 emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush);
1415 }
1416 }
1417
1418 radv_meta_restore(&saved_state, cmd_buffer);
1419 cmd_buffer->state.flush_bits |= post_flush;
1420 }