src/amd/vulkan/radv_meta_clear.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "radv_debug.h"
  25 #include "radv_meta.h"
  26 #include "radv_private.h"
  27 #include "nir/nir_builder.h"
  28
  29 #include "util/format_rgb9e5.h"
  30 #include "vk_format.h"
  31
  32 enum {
  33         DEPTH_CLEAR_SLOW,
  34         DEPTH_CLEAR_FAST_EXPCLEAR,
  35         DEPTH_CLEAR_FAST_NO_EXPCLEAR
  36 };
  37
  38 static void
  39 build_color_shaders(struct nir_shader **out_vs,
  40                     struct nir_shader **out_fs,
  41                     uint32_t frag_output)
  42 {
  43         nir_builder vs_b;
  44         nir_builder fs_b;
  45
  46         nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
  47         nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
  48
  49         vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
  50         fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
  51
  52         const struct glsl_type *position_type = glsl_vec4_type();
  53         const struct glsl_type *color_type = glsl_vec4_type();
  54
  55         nir_variable *vs_out_pos =
  56                 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
  57                                     "gl_Position");
  58         vs_out_pos->data.location = VARYING_SLOT_POS;
  59
  60         nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
  61         nir_intrinsic_set_base(in_color_load, 0);
  62         nir_intrinsic_set_range(in_color_load, 16);
  63         in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
  64         in_color_load->num_components = 4;
  65         nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
  66         nir_builder_instr_insert(&fs_b, &in_color_load->instr);
  67
  68         nir_variable *fs_out_color =
  69                 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
  70                                     "f_color");
  71         fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
  72
  73         nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
  74
  75         nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
  76         nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
  77
  78         const struct glsl_type *layer_type = glsl_int_type();
  79         nir_variable *vs_out_layer =
  80                 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
  81                                     "v_layer");
  82         vs_out_layer->data.location = VARYING_SLOT_LAYER;
  83         vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
  84         nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
  85         nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
  86
  87         nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
  88         nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
  89
  90         *out_vs = vs_b.shader;
  91         *out_fs = fs_b.shader;
  92 }
  93
  94 static VkResult
  95 create_pipeline(struct radv_device *device,
  96                 struct radv_render_pass *render_pass,
  97                 uint32_t samples,
  98                 struct nir_shader *vs_nir,
  99                 struct nir_shader *fs_nir,
 100                 const VkPipelineVertexInputStateCreateInfo *vi_state,
 101                 const VkPipelineDepthStencilStateCreateInfo *ds_state,
 102                 const VkPipelineColorBlendStateCreateInfo *cb_state,
 103                 const VkPipelineLayout layout,
 104                 const struct radv_graphics_pipeline_create_info *extra,
 105                 const VkAllocationCallbacks *alloc,
 106                 VkPipeline *pipeline)
 107 {
 108         VkDevice device_h = radv_device_to_handle(device);
 109         VkResult result;
 110
 111         struct radv_shader_module vs_m = { .nir = vs_nir };
 112         struct radv_shader_module fs_m = { .nir = fs_nir };
 113
 114         result = radv_graphics_pipeline_create(device_h,
 115                                                radv_pipeline_cache_to_handle(&device->meta_state.cache),
 116                                                &(VkGraphicsPipelineCreateInfo) {
 117                                                        .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
 118                                                                .stageCount = fs_nir ? 2 : 1,
 119                                                                .pStages = (VkPipelineShaderStageCreateInfo[]) {
 120                                                                {
 121                                                                        .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
 122                                                                        .stage = VK_SHADER_STAGE_VERTEX_BIT,
 123                                                                        .module = radv_shader_module_to_handle(&vs_m),
 124                                                                        .pName = "main",
 125                                                                },
 126                                                                {
 127                                                                        .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
 128                                                                        .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
 129                                                                        .module = radv_shader_module_to_handle(&fs_m),
 130                                                                        .pName = "main",
 131                                                                },
 132                                                        },
 133                                                                .pVertexInputState = vi_state,
 134                                                                         .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
 135                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
 136                                                                .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
 137                                                                .primitiveRestartEnable = false,
 138                                                        },
 139                                                                         .pViewportState = &(VkPipelineViewportStateCreateInfo) {
 140                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
 141                                                                .viewportCount = 1,
 142                                                                .scissorCount = 1,
 143                                                        },
 144                                                                                  .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
 145                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
 146                                                                .rasterizerDiscardEnable = false,
 147                                                                .polygonMode = VK_POLYGON_MODE_FILL,
 148                                                                .cullMode = VK_CULL_MODE_NONE,
 149                                                                .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
 150                                                                .depthBiasEnable = false,
 151                                                        },
 152                                                                                           .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
 153                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
 154                                                                .rasterizationSamples = samples,
 155                                                                .sampleShadingEnable = false,
 156                                                                .pSampleMask = NULL,
 157                                                                .alphaToCoverageEnable = false,
 158                                                                .alphaToOneEnable = false,
 159                                                        },
 160                                                                                                    .pDepthStencilState = ds_state,
 161                                                                                                             .pColorBlendState = cb_state,
 162                                                                                                             .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
 163                                                                /* The meta clear pipeline declares all state as dynamic.
 164                                                                 * As a consequence, vkCmdBindPipeline writes no dynamic state
 165                                                                 * to the cmd buffer. Therefore, at the end of the meta clear,
 166                                                                 * we need only restore dynamic state was vkCmdSet.
 167                                                                 */
 168                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
 169                                                                .dynamicStateCount = 8,
 170                                                                .pDynamicStates = (VkDynamicState[]) {
 171                                                                        /* Everything except stencil write mask */
 172                                                                        VK_DYNAMIC_STATE_VIEWPORT,
 173                                                                        VK_DYNAMIC_STATE_SCISSOR,
 174                                                                        VK_DYNAMIC_STATE_LINE_WIDTH,
 175                                                                        VK_DYNAMIC_STATE_DEPTH_BIAS,
 176                                                                        VK_DYNAMIC_STATE_BLEND_CONSTANTS,
 177                                                                        VK_DYNAMIC_STATE_DEPTH_BOUNDS,
 178                                                                        VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
 179                                                                        VK_DYNAMIC_STATE_STENCIL_REFERENCE,
 180                                                                },
 181                                                        },
 182                                                     .layout = layout,
 183                                                     .flags = 0,
 184                                                     .renderPass = radv_render_pass_to_handle(render_pass),
 185                                                     .subpass = 0,
 186                                                 },
 187                                                extra,
 188                                                alloc,
 189                                                pipeline);
 190
 191         ralloc_free(vs_nir);
 192         ralloc_free(fs_nir);
 193
 194         return result;
 195 }
 196
 197 static VkResult
 198 create_color_renderpass(struct radv_device *device,
 199                         VkFormat vk_format,
 200                         uint32_t samples,
 201                         VkRenderPass *pass)
 202 {
 203         mtx_lock(&device->meta_state.mtx);
 204         if (*pass) {
 205                 mtx_unlock (&device->meta_state.mtx);
 206                 return VK_SUCCESS;
 207         }
 208
 209         VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
 210                                        &(VkRenderPassCreateInfo) {
 211                                                .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
 212                                                        .attachmentCount = 1,
 213                                                        .pAttachments = &(VkAttachmentDescription) {
 214                                                        .format = vk_format,
 215                                                        .samples = samples,
 216                                                        .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
 217                                                        .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
 218                                                        .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
 219                                                        .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
 220                                                },
 221                                                        .subpassCount = 1,
 222                                                                 .pSubpasses = &(VkSubpassDescription) {
 223                                                        .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
 224                                                        .inputAttachmentCount = 0,
 225                                                        .colorAttachmentCount = 1,
 226                                                        .pColorAttachments = &(VkAttachmentReference) {
 227                                                                .attachment = 0,
 228                                                                .layout = VK_IMAGE_LAYOUT_GENERAL,
 229                                                        },
 230                                                        .pResolveAttachments = NULL,
 231                                                        .pDepthStencilAttachment = &(VkAttachmentReference) {
 232                                                                .attachment = VK_ATTACHMENT_UNUSED,
 233                                                                .layout = VK_IMAGE_LAYOUT_GENERAL,
 234                                                        },
 235                                                        .preserveAttachmentCount = 0,
 236                                                        .pPreserveAttachments = NULL,
 237                                                },
 238                                                                 .dependencyCount = 0,
 239                                                                          }, &device->meta_state.alloc, pass);
 240         mtx_unlock(&device->meta_state.mtx);
 241         return result;
 242 }
 243
 244 static VkResult
 245 create_color_pipeline(struct radv_device *device,
 246                       uint32_t samples,
 247                       uint32_t frag_output,
 248                       VkPipeline *pipeline,
 249                       VkRenderPass pass)
 250 {
 251         struct nir_shader *vs_nir;
 252         struct nir_shader *fs_nir;
 253         VkResult result;
 254
 255         mtx_lock(&device->meta_state.mtx);
 256         if (*pipeline) {
 257                 mtx_unlock(&device->meta_state.mtx);
 258                 return VK_SUCCESS;
 259         }
 260
 261         build_color_shaders(&vs_nir, &fs_nir, frag_output);
 262
 263         const VkPipelineVertexInputStateCreateInfo vi_state = {
 264                 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
 265                 .vertexBindingDescriptionCount = 0,
 266                 .vertexAttributeDescriptionCount = 0,
 267         };
 268
 269         const VkPipelineDepthStencilStateCreateInfo ds_state = {
 270                 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
 271                 .depthTestEnable = false,
 272                 .depthWriteEnable = false,
 273                 .depthBoundsTestEnable = false,
 274                 .stencilTestEnable = false,
 275         };
 276
 277         VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
 278         blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
 279                 .blendEnable = false,
 280                 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
 281                 VK_COLOR_COMPONENT_R_BIT |
 282                 VK_COLOR_COMPONENT_G_BIT |
 283                 VK_COLOR_COMPONENT_B_BIT,
 284         };
 285
 286         const VkPipelineColorBlendStateCreateInfo cb_state = {
 287                 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
 288                 .logicOpEnable = false,
 289                 .attachmentCount = MAX_RTS,
 290                 .pAttachments = blend_attachment_state
 291         };
 292
 293
 294         struct radv_graphics_pipeline_create_info extra = {
 295                 .use_rectlist = true,
 296         };
 297         result = create_pipeline(device, radv_render_pass_from_handle(pass),
 298                                  samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
 299                                  device->meta_state.clear_color_p_layout,
 300                                  &extra, &device->meta_state.alloc, pipeline);
 301
 302         mtx_unlock(&device->meta_state.mtx);
 303         return result;
 304 }
 305
 306 static void
 307 finish_meta_clear_htile_mask_state(struct radv_device *device)
 308 {
 309         struct radv_meta_state *state = &device->meta_state;
 310
 311         radv_DestroyPipeline(radv_device_to_handle(device),
 312                              state->clear_htile_mask_pipeline,
 313                              &state->alloc);
 314         radv_DestroyPipelineLayout(radv_device_to_handle(device),
 315                                    state->clear_htile_mask_p_layout,
 316                                    &state->alloc);
 317         radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
 318                                         state->clear_htile_mask_ds_layout,
 319                                         &state->alloc);
 320 }
 321
 322 void
 323 radv_device_finish_meta_clear_state(struct radv_device *device)
 324 {
 325         struct radv_meta_state *state = &device->meta_state;
 326
 327         for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
 328                 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
 329                         radv_DestroyPipeline(radv_device_to_handle(device),
 330                                              state->clear[i].color_pipelines[j],
 331                                              &state->alloc);
 332                         radv_DestroyRenderPass(radv_device_to_handle(device),
 333                                                state->clear[i].render_pass[j],
 334                                                &state->alloc);
 335                 }
 336
 337                 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
 338                         radv_DestroyPipeline(radv_device_to_handle(device),
 339                                              state->clear[i].depth_only_pipeline[j],
 340                                              &state->alloc);
 341                         radv_DestroyPipeline(radv_device_to_handle(device),
 342                                              state->clear[i].stencil_only_pipeline[j],
 343                                              &state->alloc);
 344                         radv_DestroyPipeline(radv_device_to_handle(device),
 345                                              state->clear[i].depthstencil_pipeline[j],
 346                                              &state->alloc);
 347                 }
 348                 radv_DestroyRenderPass(radv_device_to_handle(device),
 349                                       state->clear[i].depthstencil_rp,
 350                                       &state->alloc);
 351         }
 352         radv_DestroyPipelineLayout(radv_device_to_handle(device),
 353                                    state->clear_color_p_layout,
 354                                    &state->alloc);
 355         radv_DestroyPipelineLayout(radv_device_to_handle(device),
 356                                    state->clear_depth_p_layout,
 357                                    &state->alloc);
 358
 359         finish_meta_clear_htile_mask_state(device);
 360 }
 361
 362 static void
 363 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
 364                  const VkClearAttachment *clear_att,
 365                  const VkClearRect *clear_rect,
 366                  uint32_t view_mask)
 367 {
 368         struct radv_device *device = cmd_buffer->device;
 369         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 370         const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
 371         const uint32_t subpass_att = clear_att->colorAttachment;
 372         const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
 373         const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
 374         const uint32_t samples = iview->image->info.samples;
 375         const uint32_t samples_log2 = ffs(samples) - 1;
 376         unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
 377         VkClearColorValue clear_value = clear_att->clearValue.color;
 378         VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
 379         VkPipeline pipeline;
 380
 381         if (fs_key == -1) {
 382                 radv_finishme("color clears incomplete");
 383                 return;
 384         }
 385
 386         if (device->meta_state.clear[samples_log2].render_pass[fs_key] == VK_NULL_HANDLE) {
 387                 VkResult ret = create_color_renderpass(device, radv_fs_key_format_exemplars[fs_key],
 388                                                        samples,
 389                                                        &device->meta_state.clear[samples_log2].render_pass[fs_key]);
 390                 if (ret != VK_SUCCESS) {
 391                         cmd_buffer->record_result = ret;
 392                         return;
 393                 }
 394         }
 395
 396         if (device->meta_state.clear[samples_log2].color_pipelines[fs_key] == VK_NULL_HANDLE) {
 397                 VkResult ret = create_color_pipeline(device, samples, 0,
 398                                                      &device->meta_state.clear[samples_log2].color_pipelines[fs_key],
 399                                                      device->meta_state.clear[samples_log2].render_pass[fs_key]);
 400                 if (ret != VK_SUCCESS) {
 401                         cmd_buffer->record_result = ret;
 402                         return;
 403                 }
 404         }
 405
 406         pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
 407         if (!pipeline) {
 408                 radv_finishme("color clears incomplete");
 409                 return;
 410         }
 411         assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
 412         assert(pipeline);
 413         assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
 414         assert(clear_att->colorAttachment < subpass->color_count);
 415
 416         radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
 417                               device->meta_state.clear_color_p_layout,
 418                               VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
 419                               &clear_value);
 420
 421         struct radv_subpass clear_subpass = {
 422                 .color_count = 1,
 423                 .color_attachments = (struct radv_subpass_attachment[]) {
 424                         subpass->color_attachments[clear_att->colorAttachment]
 425                 },
 426                 .depth_stencil_attachment = NULL,
 427         };
 428
 429         radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass);
 430
 431         radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
 432                              pipeline);
 433
 434         radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
 435                         .x = clear_rect->rect.offset.x,
 436                         .y = clear_rect->rect.offset.y,
 437                         .width = clear_rect->rect.extent.width,
 438                         .height = clear_rect->rect.extent.height,
 439                         .minDepth = 0.0f,
 440                         .maxDepth = 1.0f
 441                 });
 442
 443         radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
 444
 445         if (view_mask) {
 446                 unsigned i;
 447                 for_each_bit(i, view_mask)
 448                         radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
 449         } else {
 450                 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
 451         }
 452
 453         radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
 454 }
 455
 456
 457 static void
 458 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
 459 {
 460         nir_builder vs_b, fs_b;
 461
 462         nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
 463         nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
 464
 465         vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
 466         fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
 467         const struct glsl_type *position_out_type = glsl_vec4_type();
 468
 469         nir_variable *vs_out_pos =
 470                 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
 471                                     "gl_Position");
 472         vs_out_pos->data.location = VARYING_SLOT_POS;
 473
 474         nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
 475         nir_intrinsic_set_base(in_color_load, 0);
 476         nir_intrinsic_set_range(in_color_load, 4);
 477         in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
 478         in_color_load->num_components = 1;
 479         nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
 480         nir_builder_instr_insert(&vs_b, &in_color_load->instr);
 481
 482         nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
 483         nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
 484
 485         const struct glsl_type *layer_type = glsl_int_type();
 486         nir_variable *vs_out_layer =
 487                 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
 488                                     "v_layer");
 489         vs_out_layer->data.location = VARYING_SLOT_LAYER;
 490         vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
 491         nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
 492         nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
 493
 494         nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
 495         nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
 496
 497         *out_vs = vs_b.shader;
 498         *out_fs = fs_b.shader;
 499 }
 500
 501 static VkResult
 502 create_depthstencil_renderpass(struct radv_device *device,
 503                                uint32_t samples,
 504                                VkRenderPass *render_pass)
 505 {
 506         mtx_lock(&device->meta_state.mtx);
 507         if (*render_pass) {
 508                 mtx_unlock(&device->meta_state.mtx);
 509                 return VK_SUCCESS;
 510         }
 511
 512         VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
 513                                        &(VkRenderPassCreateInfo) {
 514                                                .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
 515                                                        .attachmentCount = 1,
 516                                                        .pAttachments = &(VkAttachmentDescription) {
 517                                                        .format = VK_FORMAT_D32_SFLOAT_S8_UINT,
 518                                                        .samples = samples,
 519                                                        .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
 520                                                        .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
 521                                                        .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
 522                                                        .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
 523                                                },
 524                                                        .subpassCount = 1,
 525                                                                 .pSubpasses = &(VkSubpassDescription) {
 526                                                        .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
 527                                                        .inputAttachmentCount = 0,
 528                                                        .colorAttachmentCount = 0,
 529                                                        .pColorAttachments = NULL,
 530                                                        .pResolveAttachments = NULL,
 531                                                        .pDepthStencilAttachment = &(VkAttachmentReference) {
 532                                                                .attachment = 0,
 533                                                                .layout = VK_IMAGE_LAYOUT_GENERAL,
 534                                                        },
 535                                                        .preserveAttachmentCount = 0,
 536                                                        .pPreserveAttachments = NULL,
 537                                                },
 538                                                                 .dependencyCount = 0,
 539                                                                          }, &device->meta_state.alloc, render_pass);
 540         mtx_unlock(&device->meta_state.mtx);
 541         return result;
 542 }
 543
 544 static VkResult
 545 create_depthstencil_pipeline(struct radv_device *device,
 546                              VkImageAspectFlags aspects,
 547                              uint32_t samples,
 548                              int index,
 549                              VkPipeline *pipeline,
 550                              VkRenderPass render_pass)
 551 {
 552         struct nir_shader *vs_nir, *fs_nir;
 553         VkResult result;
 554
 555         mtx_lock(&device->meta_state.mtx);
 556         if (*pipeline) {
 557                 mtx_unlock(&device->meta_state.mtx);
 558                 return VK_SUCCESS;
 559         }
 560
 561         build_depthstencil_shader(&vs_nir, &fs_nir);
 562
 563         const VkPipelineVertexInputStateCreateInfo vi_state = {
 564                 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
 565                 .vertexBindingDescriptionCount = 0,
 566                 .vertexAttributeDescriptionCount = 0,
 567         };
 568
 569         const VkPipelineDepthStencilStateCreateInfo ds_state = {
 570                 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
 571                 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
 572                 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
 573                 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
 574                 .depthBoundsTestEnable = false,
 575                 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
 576                 .front = {
 577                         .passOp = VK_STENCIL_OP_REPLACE,
 578                         .compareOp = VK_COMPARE_OP_ALWAYS,
 579                         .writeMask = UINT32_MAX,
 580                         .reference = 0, /* dynamic */
 581                 },
 582                 .back = { 0 /* dont care */ },
 583         };
 584
 585         const VkPipelineColorBlendStateCreateInfo cb_state = {
 586                 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
 587                 .logicOpEnable = false,
 588                 .attachmentCount = 0,
 589                 .pAttachments = NULL,
 590         };
 591
 592         struct radv_graphics_pipeline_create_info extra = {
 593                 .use_rectlist = true,
 594         };
 595
 596         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
 597                 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
 598                 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
 599         }
 600         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
 601                 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
 602                 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
 603         }
 604         result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
 605                                  samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
 606                                  device->meta_state.clear_depth_p_layout,
 607                                  &extra, &device->meta_state.alloc, pipeline);
 608
 609         mtx_unlock(&device->meta_state.mtx);
 610         return result;
 611 }
 612
 613 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
 614                                       const struct radv_image_view *iview,
 615                                       VkImageAspectFlags aspects,
 616                                       VkImageLayout layout,
 617                                       const VkClearRect *clear_rect,
 618                                       VkClearDepthStencilValue clear_value)
 619 {
 620         uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
 621                                                            cmd_buffer->queue_family_index,
 622                                                            cmd_buffer->queue_family_index);
 623         if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
 624             clear_rect->rect.extent.width != iview->extent.width ||
 625             clear_rect->rect.extent.height != iview->extent.height)
 626                 return false;
 627         if (radv_image_is_tc_compat_htile(iview->image) &&
 628             (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && clear_value.depth != 0.0 &&
 629               clear_value.depth != 1.0) ||
 630              ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0)))
 631                 return false;
 632         if (radv_image_has_htile(iview->image) &&
 633             iview->base_mip == 0 &&
 634             iview->base_layer == 0 &&
 635             radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
 636             !radv_image_extent_compare(iview->image, &iview->extent))
 637                 return true;
 638         return false;
 639 }
 640
 641 static VkPipeline
 642 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
 643                            struct radv_meta_state *meta_state,
 644                            const struct radv_image_view *iview,
 645                            int samples_log2,
 646                            VkImageAspectFlags aspects,
 647                            VkImageLayout layout,
 648                            const VkClearRect *clear_rect,
 649                            VkClearDepthStencilValue clear_value)
 650 {
 651         bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, clear_rect, clear_value);
 652         int index = DEPTH_CLEAR_SLOW;
 653         VkPipeline *pipeline;
 654
 655         if (fast) {
 656                 /* we don't know the previous clear values, so we always have
 657                  * the NO_EXPCLEAR path */
 658                 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
 659         }
 660
 661         switch (aspects) {
 662         case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
 663                 pipeline = &meta_state->clear[samples_log2].depthstencil_pipeline[index];
 664                 break;
 665         case VK_IMAGE_ASPECT_DEPTH_BIT:
 666                 pipeline = &meta_state->clear[samples_log2].depth_only_pipeline[index];
 667                 break;
 668         case VK_IMAGE_ASPECT_STENCIL_BIT:
 669                 pipeline = &meta_state->clear[samples_log2].stencil_only_pipeline[index];
 670                 break;
 671         default:
 672                 unreachable("expected depth or stencil aspect");
 673         }
 674
 675         if (cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp == VK_NULL_HANDLE) {
 676                 VkResult ret = create_depthstencil_renderpass(cmd_buffer->device, 1u << samples_log2,
 677                                                               &cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
 678                 if (ret != VK_SUCCESS) {
 679                         cmd_buffer->record_result = ret;
 680                         return VK_NULL_HANDLE;
 681                 }
 682         }
 683
 684         if (*pipeline == VK_NULL_HANDLE) {
 685                 VkResult ret = create_depthstencil_pipeline(cmd_buffer->device, aspects, 1u << samples_log2, index,
 686                                                             pipeline, cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
 687                 if (ret != VK_SUCCESS) {
 688                         cmd_buffer->record_result = ret;
 689                         return VK_NULL_HANDLE;
 690                 }
 691         }
 692         return *pipeline;
 693 }
 694
 695 static void
 696 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
 697                         const VkClearAttachment *clear_att,
 698                         const VkClearRect *clear_rect,
 699                         uint32_t view_mask)
 700 {
 701         struct radv_device *device = cmd_buffer->device;
 702         struct radv_meta_state *meta_state = &device->meta_state;
 703         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 704         const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
 705         const uint32_t pass_att = subpass->depth_stencil_attachment->attachment;
 706         VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
 707         VkImageAspectFlags aspects = clear_att->aspectMask;
 708         const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
 709         const uint32_t samples = iview->image->info.samples;
 710         const uint32_t samples_log2 = ffs(samples) - 1;
 711         VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
 712
 713         assert(pass_att != VK_ATTACHMENT_UNUSED);
 714
 715         if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
 716                 clear_value.depth = 1.0f;
 717
 718         radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
 719                               device->meta_state.clear_depth_p_layout,
 720                               VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
 721                               &clear_value.depth);
 722
 723         uint32_t prev_reference = cmd_buffer->state.dynamic.stencil_reference.front;
 724         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
 725                 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
 726                                                   clear_value.stencil);
 727         }
 728
 729         VkPipeline pipeline = pick_depthstencil_pipeline(cmd_buffer,
 730                                                          meta_state,
 731                                                          iview,
 732                                                          samples_log2,
 733                                                          aspects,
 734                                                          subpass->depth_stencil_attachment->layout,
 735                                                          clear_rect,
 736                                                          clear_value);
 737         if (!pipeline)
 738                 return;
 739
 740         radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
 741                              pipeline);
 742
 743         if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
 744                                       subpass->depth_stencil_attachment->layout,
 745                                       clear_rect, clear_value))
 746                 radv_update_ds_clear_metadata(cmd_buffer, iview->image,
 747                                               clear_value, aspects);
 748
 749         radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
 750                         .x = clear_rect->rect.offset.x,
 751                         .y = clear_rect->rect.offset.y,
 752                         .width = clear_rect->rect.extent.width,
 753                         .height = clear_rect->rect.extent.height,
 754                         .minDepth = 0.0f,
 755                         .maxDepth = 1.0f
 756                 });
 757
 758         radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
 759
 760         if (view_mask) {
 761                 unsigned i;
 762                 for_each_bit(i, view_mask)
 763                         radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
 764         } else {
 765                 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
 766         }
 767
 768         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
 769                 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
 770                                                   prev_reference);
 771         }
 772 }
 773
 774 static uint32_t
 775 clear_htile_mask(struct radv_cmd_buffer *cmd_buffer,
 776                  struct radeon_winsys_bo *bo, uint64_t offset, uint64_t size,
 777                  uint32_t htile_value, uint32_t htile_mask)
 778 {
 779         struct radv_device *device = cmd_buffer->device;
 780         struct radv_meta_state *state = &device->meta_state;
 781         uint64_t block_count = round_up_u64(size, 1024);
 782         struct radv_meta_saved_state saved_state;
 783
 784         radv_meta_save(&saved_state, cmd_buffer,
 785                        RADV_META_SAVE_COMPUTE_PIPELINE |
 786                        RADV_META_SAVE_CONSTANTS |
 787                        RADV_META_SAVE_DESCRIPTORS);
 788
 789         struct radv_buffer dst_buffer = {
 790                 .bo = bo,
 791                 .offset = offset,
 792                 .size = size
 793         };
 794
 795         radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
 796                              VK_PIPELINE_BIND_POINT_COMPUTE,
 797                              state->clear_htile_mask_pipeline);
 798
 799         radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
 800                                       state->clear_htile_mask_p_layout,
 801                                       0, /* set */
 802                                       1, /* descriptorWriteCount */
 803                                       (VkWriteDescriptorSet[]) {
 804                                               {
 805                                                       .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
 806                                                       .dstBinding = 0,
 807                                                       .dstArrayElement = 0,
 808                                                       .descriptorCount = 1,
 809                                                       .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
 810                                                       .pBufferInfo = &(VkDescriptorBufferInfo) {
 811                                                               .buffer = radv_buffer_to_handle(&dst_buffer),
 812                                                               .offset = 0,
 813                                                               .range = size
 814                                                       }
 815                                               }
 816                                       });
 817
 818         const unsigned constants[2] = {
 819                 htile_value & htile_mask,
 820                 ~htile_mask,
 821         };
 822
 823         radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
 824                               state->clear_htile_mask_p_layout,
 825                               VK_SHADER_STAGE_COMPUTE_BIT, 0, 8,
 826                               constants);
 827
 828         radv_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer), block_count, 1, 1);
 829
 830         radv_meta_restore(&saved_state, cmd_buffer);
 831
 832         return RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
 833                RADV_CMD_FLAG_INV_VMEM_L1 |
 834                RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
 835 }
 836
 837 static uint32_t
 838 radv_get_htile_fast_clear_value(const struct radv_image *image,
 839                                 VkClearDepthStencilValue value)
 840 {
 841         uint32_t clear_value;
 842
 843         if (!image->surface.has_stencil) {
 844                 clear_value = value.depth ? 0xfffffff0 : 0;
 845         } else {
 846                 clear_value = value.depth ? 0xfffc0000 : 0;
 847         }
 848
 849         return clear_value;
 850 }
 851
 852 static uint32_t
 853 radv_get_htile_mask(const struct radv_image *image, VkImageAspectFlags aspects)
 854 {
 855         uint32_t mask = 0;
 856
 857         if (!image->surface.has_stencil) {
 858                 /* All the HTILE buffer is used when there is no stencil. */
 859                 mask = UINT32_MAX;
 860         } else {
 861                 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
 862                         mask |= 0xfffffc0f;
 863                 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
 864                         mask |= 0x000003f0;
 865         }
 866
 867         return mask;
 868 }
 869
 870 static bool
 871 radv_is_fast_clear_depth_allowed(VkClearDepthStencilValue value)
 872 {
 873         return value.depth == 1.0f || value.depth == 0.0f;
 874 }
 875
 876 static bool
 877 radv_is_fast_clear_stencil_allowed(VkClearDepthStencilValue value)
 878 {
 879         return value.stencil == 0;
 880 }
 881
 882 /**
 883  * Determine if the given image can be fast cleared.
 884  */
 885 static bool
 886 radv_image_can_fast_clear(struct radv_device *device,  struct radv_image *image)
 887 {
 888         if (device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
 889                 return false;
 890
 891         if (vk_format_is_color(image->vk_format)) {
 892                 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
 893                         return false;
 894
 895                 /* RB+ doesn't work with CMASK fast clear on Stoney. */
 896                 if (!radv_image_has_dcc(image) &&
 897                     device->physical_device->rad_info.family == CHIP_STONEY)
 898                         return false;
 899         } else {
 900                 if (!radv_image_has_htile(image))
 901                         return false;
 902         }
 903
 904         /* Do not fast clears 3D images. */
 905         if (image->type == VK_IMAGE_TYPE_3D)
 906                 return false;
 907
 908         return true;
 909 }
 910
 911 /**
 912  * Determine if the given image view can be fast cleared.
 913  */
 914 static bool
 915 radv_image_view_can_fast_clear(struct radv_device *device,
 916                                const struct radv_image_view *iview)
 917 {
 918         struct radv_image *image = iview->image;
 919
 920         /* Only fast clear if the image itself can be fast cleared. */
 921         if (!radv_image_can_fast_clear(device, image))
 922                 return false;
 923
 924         /* Only fast clear if all layers are bound. */
 925         if (iview->base_layer > 0 ||
 926             iview->layer_count != image->info.array_size)
 927                 return false;
 928
 929         /* Only fast clear if the view covers the whole image. */
 930         if (!radv_image_extent_compare(image, &iview->extent))
 931                 return false;
 932
 933         return true;
 934 }
 935
 936 static bool
 937 radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer,
 938                           const struct radv_image_view *iview,
 939                           VkImageLayout image_layout,
 940                           VkImageAspectFlags aspects,
 941                           const VkClearRect *clear_rect,
 942                           const VkClearDepthStencilValue clear_value,
 943                           uint32_t view_mask)
 944 {
 945         if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview))
 946                 return false;
 947
 948         if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
 949                 return false;
 950
 951         if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
 952             clear_rect->rect.extent.width != iview->image->info.width ||
 953             clear_rect->rect.extent.height != iview->image->info.height)
 954                 return false;
 955
 956         if (view_mask && (iview->image->info.array_size >= 32 ||
 957                          (1u << iview->image->info.array_size) - 1u != view_mask))
 958                 return false;
 959         if (!view_mask && clear_rect->baseArrayLayer != 0)
 960                 return false;
 961         if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
 962                 return false;
 963
 964         if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 &&
 965             (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT) ||
 966             ((vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) &&
 967              !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))))
 968                 return false;
 969
 970         if (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
 971             !radv_is_fast_clear_depth_allowed(clear_value)) ||
 972             ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
 973              !radv_is_fast_clear_stencil_allowed(clear_value)))
 974                 return false;
 975
 976         return true;
 977 }
 978
 979 static void
 980 radv_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer,
 981                       const struct radv_image_view *iview,
 982                       const VkClearAttachment *clear_att,
 983                       enum radv_cmd_flush_bits *pre_flush,
 984                       enum radv_cmd_flush_bits *post_flush)
 985 {
 986         VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
 987         VkImageAspectFlags aspects = clear_att->aspectMask;
 988         uint32_t clear_word, flush_bits;
 989         uint32_t htile_mask;
 990
 991         clear_word = radv_get_htile_fast_clear_value(iview->image, clear_value);
 992         htile_mask = radv_get_htile_mask(iview->image, aspects);
 993
 994         if (pre_flush) {
 995                 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
 996                                                  RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
 997                 *pre_flush |= cmd_buffer->state.flush_bits;
 998         }
 999
1000         if (htile_mask == UINT_MAX) {
1001                 /* Clear the whole HTILE buffer. */
1002                 flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
1003                                               iview->image->offset + iview->image->htile_offset,
1004                                               iview->image->surface.htile_size, clear_word);
1005         } else {
1006                 /* Only clear depth or stencil bytes in the HTILE buffer. */
1007                 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9);
1008                 flush_bits = clear_htile_mask(cmd_buffer, iview->image->bo,
1009                                               iview->image->offset + iview->image->htile_offset,
1010                                               iview->image->surface.htile_size, clear_word,
1011                                               htile_mask);
1012         }
1013
1014         radv_update_ds_clear_metadata(cmd_buffer, iview->image, clear_value, aspects);
1015         if (post_flush) {
1016                 *post_flush |= flush_bits;
1017         }
1018 }
1019
1020 static nir_shader *
1021 build_clear_htile_mask_shader()
1022 {
1023         nir_builder b;
1024
1025         nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
1026         b.shader->info.name = ralloc_strdup(b.shader, "meta_clear_htile_mask");
1027         b.shader->info.cs.local_size[0] = 64;
1028         b.shader->info.cs.local_size[1] = 1;
1029         b.shader->info.cs.local_size[2] = 1;
1030
1031         nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
1032         nir_ssa_def *wg_id = nir_load_work_group_id(&b);
1033         nir_ssa_def *block_size = nir_imm_ivec4(&b,
1034                                                 b.shader->info.cs.local_size[0],
1035                                                 b.shader->info.cs.local_size[1],
1036                                                 b.shader->info.cs.local_size[2], 0);
1037
1038         nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
1039
1040         nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16));
1041         offset = nir_channel(&b, offset, 0);
1042
1043         nir_intrinsic_instr *buf =
1044                 nir_intrinsic_instr_create(b.shader,
1045                                            nir_intrinsic_vulkan_resource_index);
1046
1047         buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
1048         nir_intrinsic_set_desc_set(buf, 0);
1049         nir_intrinsic_set_binding(buf, 0);
1050         nir_ssa_dest_init(&buf->instr, &buf->dest, 1, 32, NULL);
1051         nir_builder_instr_insert(&b, &buf->instr);
1052
1053         nir_intrinsic_instr *constants =
1054                 nir_intrinsic_instr_create(b.shader,
1055                                            nir_intrinsic_load_push_constant);
1056         nir_intrinsic_set_base(constants, 0);
1057         nir_intrinsic_set_range(constants, 8);
1058         constants->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
1059         constants->num_components = 2;
1060         nir_ssa_dest_init(&constants->instr, &constants->dest, 2, 32, "constants");
1061         nir_builder_instr_insert(&b, &constants->instr);
1062
1063         nir_intrinsic_instr *load =
1064                 nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
1065         load->src[0] = nir_src_for_ssa(&buf->dest.ssa);
1066         load->src[1] = nir_src_for_ssa(offset);
1067         nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
1068         load->num_components = 4;
1069         nir_builder_instr_insert(&b, &load->instr);
1070
1071         /* data = (data & ~htile_mask) | (htile_value & htile_mask) */
1072         nir_ssa_def *data =
1073                 nir_iand(&b, &load->dest.ssa,
1074                          nir_channel(&b, &constants->dest.ssa, 1));
1075         data = nir_ior(&b, data, nir_channel(&b, &constants->dest.ssa, 0));
1076
1077         nir_intrinsic_instr *store =
1078                 nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
1079         store->src[0] = nir_src_for_ssa(data);
1080         store->src[1] = nir_src_for_ssa(&buf->dest.ssa);
1081         store->src[2] = nir_src_for_ssa(offset);
1082         nir_intrinsic_set_write_mask(store, 0xf);
1083         store->num_components = 4;
1084         nir_builder_instr_insert(&b, &store->instr);
1085
1086         return b.shader;
1087 }
1088
1089 static VkResult
1090 init_meta_clear_htile_mask_state(struct radv_device *device)
1091 {
1092         struct radv_meta_state *state = &device->meta_state;
1093         struct radv_shader_module cs = { .nir = NULL };
1094         VkResult result;
1095
1096         cs.nir = build_clear_htile_mask_shader();
1097
1098         VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1099                 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1100                 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1101                 .bindingCount = 1,
1102                 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1103                         {
1104                                 .binding = 0,
1105                                 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
1106                                 .descriptorCount = 1,
1107                                 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
1108                                 .pImmutableSamplers = NULL
1109                         },
1110                 }
1111         };
1112
1113         result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1114                                                 &ds_layout_info, &state->alloc,
1115                                                 &state->clear_htile_mask_ds_layout);
1116         if (result != VK_SUCCESS)
1117                 goto fail;
1118
1119         VkPipelineLayoutCreateInfo p_layout_info = {
1120                 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1121                 .setLayoutCount = 1,
1122                 .pSetLayouts = &state->clear_htile_mask_ds_layout,
1123                 .pushConstantRangeCount = 1,
1124                 .pPushConstantRanges = &(VkPushConstantRange){
1125                         VK_SHADER_STAGE_COMPUTE_BIT, 0, 8,
1126                 },
1127         };
1128
1129         result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1130                                           &p_layout_info, &state->alloc,
1131                                           &state->clear_htile_mask_p_layout);
1132         if (result != VK_SUCCESS)
1133                 goto fail;
1134
1135         VkPipelineShaderStageCreateInfo shader_stage = {
1136                 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1137                 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
1138                 .module = radv_shader_module_to_handle(&cs),
1139                 .pName = "main",
1140                 .pSpecializationInfo = NULL,
1141         };
1142
1143         VkComputePipelineCreateInfo pipeline_info = {
1144                 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
1145                 .stage = shader_stage,
1146                 .flags = 0,
1147                 .layout = state->clear_htile_mask_p_layout,
1148         };
1149
1150         result = radv_CreateComputePipelines(radv_device_to_handle(device),
1151                                              radv_pipeline_cache_to_handle(&state->cache),
1152                                              1, &pipeline_info, NULL,
1153                                              &state->clear_htile_mask_pipeline);
1154
1155         ralloc_free(cs.nir);
1156         return result;
1157 fail:
1158         ralloc_free(cs.nir);
1159         return result;
1160 }
1161
1162 VkResult
1163 radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand)
1164 {
1165         VkResult res;
1166         struct radv_meta_state *state = &device->meta_state;
1167
1168         VkPipelineLayoutCreateInfo pl_color_create_info = {
1169                 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1170                 .setLayoutCount = 0,
1171                 .pushConstantRangeCount = 1,
1172                 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
1173         };
1174
1175         res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1176                                         &pl_color_create_info,
1177                                         &device->meta_state.alloc,
1178                                         &device->meta_state.clear_color_p_layout);
1179         if (res != VK_SUCCESS)
1180                 goto fail;
1181
1182         VkPipelineLayoutCreateInfo pl_depth_create_info = {
1183                 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1184                 .setLayoutCount = 0,
1185                 .pushConstantRangeCount = 1,
1186                 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
1187         };
1188
1189         res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1190                                         &pl_depth_create_info,
1191                                         &device->meta_state.alloc,
1192                                         &device->meta_state.clear_depth_p_layout);
1193         if (res != VK_SUCCESS)
1194                 goto fail;
1195
1196         res = init_meta_clear_htile_mask_state(device);
1197         if (res != VK_SUCCESS)
1198                 goto fail;
1199
1200         if (on_demand)
1201                 return VK_SUCCESS;
1202
1203         for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
1204                 uint32_t samples = 1 << i;
1205                 for (uint32_t j = 0; j < NUM_META_FS_KEYS; ++j) {
1206                         VkFormat format = radv_fs_key_format_exemplars[j];
1207                         unsigned fs_key = radv_format_meta_fs_key(format);
1208                         assert(!state->clear[i].color_pipelines[fs_key]);
1209
1210                         res = create_color_renderpass(device, format, samples,
1211                                                       &state->clear[i].render_pass[fs_key]);
1212                         if (res != VK_SUCCESS)
1213                                 goto fail;
1214
1215                         res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
1216                                                     state->clear[i].render_pass[fs_key]);
1217                         if (res != VK_SUCCESS)
1218                                 goto fail;
1219
1220                 }
1221
1222                 res = create_depthstencil_renderpass(device,
1223                                                      samples,
1224                                                      &state->clear[i].depthstencil_rp);
1225                 if (res != VK_SUCCESS)
1226                         goto fail;
1227
1228                 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
1229                         res = create_depthstencil_pipeline(device,
1230                                                            VK_IMAGE_ASPECT_DEPTH_BIT,
1231                                                            samples,
1232                                                            j,
1233                                                            &state->clear[i].depth_only_pipeline[j],
1234                                                            state->clear[i].depthstencil_rp);
1235                         if (res != VK_SUCCESS)
1236                                 goto fail;
1237
1238                         res = create_depthstencil_pipeline(device,
1239                                                            VK_IMAGE_ASPECT_STENCIL_BIT,
1240                                                            samples,
1241                                                            j,
1242                                                            &state->clear[i].stencil_only_pipeline[j],
1243                                                            state->clear[i].depthstencil_rp);
1244                         if (res != VK_SUCCESS)
1245                                 goto fail;
1246
1247                         res = create_depthstencil_pipeline(device,
1248                                                            VK_IMAGE_ASPECT_DEPTH_BIT |
1249                                                            VK_IMAGE_ASPECT_STENCIL_BIT,
1250                                                            samples,
1251                                                            j,
1252                                                            &state->clear[i].depthstencil_pipeline[j],
1253                                                            state->clear[i].depthstencil_rp);
1254                         if (res != VK_SUCCESS)
1255                                 goto fail;
1256                 }
1257         }
1258         return VK_SUCCESS;
1259
1260 fail:
1261         radv_device_finish_meta_clear_state(device);
1262         return res;
1263 }
1264
1265 static uint32_t
1266 radv_get_cmask_fast_clear_value(const struct radv_image *image)
1267 {
1268         uint32_t value = 0; /* Default value when no DCC. */
1269
1270         /* The fast-clear value is different for images that have both DCC and
1271          * CMASK metadata.
1272          */
1273         if (radv_image_has_dcc(image)) {
1274                 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
1275                 return image->info.samples > 1 ? 0xcccccccc : 0xffffffff;
1276         }
1277
1278         return value;
1279 }
1280
1281 uint32_t
1282 radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
1283                  struct radv_image *image, uint32_t value)
1284 {
1285         return radv_fill_buffer(cmd_buffer, image->bo,
1286                                 image->offset + image->cmask.offset,
1287                                 image->cmask.size, value);
1288 }
1289
1290
1291 uint32_t
1292 radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
1293                  struct radv_image *image, uint32_t value)
1294 {
1295         return radv_fill_buffer(cmd_buffer, image->bo,
1296                                 image->offset + image->fmask.offset,
1297                                 image->fmask.size, value);
1298 }
1299
1300 uint32_t
1301 radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
1302                struct radv_image *image, uint32_t value)
1303 {
1304         /* Mark the image as being compressed. */
1305         radv_update_dcc_metadata(cmd_buffer, image, true);
1306
1307         return radv_fill_buffer(cmd_buffer, image->bo,
1308                                 image->offset + image->dcc_offset,
1309                                 image->surface.dcc_size, value);
1310 }
1311
1312 static void vi_get_fast_clear_parameters(VkFormat format,
1313                                          const VkClearColorValue *clear_value,
1314                                          uint32_t* reset_value,
1315                                          bool *can_avoid_fast_clear_elim)
1316 {
1317         bool values[4] = {};
1318         int extra_channel;
1319         bool main_value = false;
1320         bool extra_value = false;
1321         int i;
1322         *can_avoid_fast_clear_elim = false;
1323
1324         *reset_value = 0x20202020U;
1325
1326         const struct vk_format_description *desc = vk_format_description(format);
1327         if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
1328             format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
1329             format == VK_FORMAT_B5G6R5_UNORM_PACK16)
1330                 extra_channel = -1;
1331         else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
1332                 if (radv_translate_colorswap(format, false) <= 1)
1333                         extra_channel = desc->nr_channels - 1;
1334                 else
1335                         extra_channel = 0;
1336         } else
1337                 return;
1338
1339         for (i = 0; i < 4; i++) {
1340                 int index = desc->swizzle[i] - VK_SWIZZLE_X;
1341                 if (desc->swizzle[i] < VK_SWIZZLE_X ||
1342                     desc->swizzle[i] > VK_SWIZZLE_W)
1343                         continue;
1344
1345                 if (desc->channel[i].pure_integer &&
1346                     desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
1347                         /* Use the maximum value for clamping the clear color. */
1348                         int max = u_bit_consecutive(0, desc->channel[i].size - 1);
1349
1350                         values[i] = clear_value->int32[i] != 0;
1351                         if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
1352                                 return;
1353                 } else if (desc->channel[i].pure_integer &&
1354                            desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
1355                         /* Use the maximum value for clamping the clear color. */
1356                         unsigned max = u_bit_consecutive(0, desc->channel[i].size);
1357
1358                         values[i] = clear_value->uint32[i] != 0U;
1359                         if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
1360                                 return;
1361                 } else {
1362                         values[i] = clear_value->float32[i] != 0.0F;
1363                         if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
1364                                 return;
1365                 }
1366
1367                 if (index == extra_channel)
1368                         extra_value = values[i];
1369                 else
1370                         main_value = values[i];
1371         }
1372
1373         for (int i = 0; i < 4; ++i)
1374                 if (values[i] != main_value &&
1375                     desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
1376                     desc->swizzle[i] >= VK_SWIZZLE_X &&
1377                     desc->swizzle[i] <= VK_SWIZZLE_W)
1378                         return;
1379
1380         *can_avoid_fast_clear_elim = true;
1381         if (main_value)
1382                 *reset_value |= 0x80808080U;
1383
1384         if (extra_value)
1385                 *reset_value |= 0x40404040U;
1386         return;
1387 }
1388
1389 static bool
1390 radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1391                           const struct radv_image_view *iview,
1392                           VkImageLayout image_layout,
1393                           const VkClearRect *clear_rect,
1394                           VkClearColorValue clear_value,
1395                           uint32_t view_mask)
1396 {
1397         uint32_t clear_color[2];
1398
1399         if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview))
1400                 return false;
1401
1402         if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
1403                 return false;
1404
1405         if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
1406             clear_rect->rect.extent.width != iview->image->info.width ||
1407             clear_rect->rect.extent.height != iview->image->info.height)
1408                 return false;
1409
1410         if (view_mask && (iview->image->info.array_size >= 32 ||
1411                          (1u << iview->image->info.array_size) - 1u != view_mask))
1412                 return false;
1413         if (!view_mask && clear_rect->baseArrayLayer != 0)
1414                 return false;
1415         if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
1416                 return false;
1417
1418         /* DCC */
1419         if (!radv_format_pack_clear_color(iview->vk_format,
1420                                           clear_color, &clear_value))
1421                 return false;
1422
1423         if (radv_image_has_dcc(iview->image)) {
1424                 bool can_avoid_fast_clear_elim;
1425                 uint32_t reset_value;
1426
1427                 vi_get_fast_clear_parameters(iview->vk_format,
1428                                              &clear_value, &reset_value,
1429                                              &can_avoid_fast_clear_elim);
1430
1431                 if (iview->image->info.samples > 1) {
1432                         /* DCC fast clear with MSAA should clear CMASK. */
1433                         /* FIXME: This doesn't work for now. There is a
1434                          * hardware bug with fast clears and DCC for MSAA
1435                          * textures. AMDVLK has a workaround but it doesn't
1436                          * seem to work here. Note that we might emit useless
1437                          * CB flushes but that shouldn't matter.
1438                          */
1439                         if (!can_avoid_fast_clear_elim)
1440                                 return false;
1441                 }
1442         }
1443
1444         return true;
1445 }
1446
1447
1448 static void
1449 radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1450                       const struct radv_image_view *iview,
1451                       const VkClearAttachment *clear_att,
1452                       uint32_t subpass_att,
1453                       enum radv_cmd_flush_bits *pre_flush,
1454                       enum radv_cmd_flush_bits *post_flush)
1455 {
1456         VkClearColorValue clear_value = clear_att->clearValue.color;
1457         uint32_t clear_color[2], flush_bits = 0;
1458         uint32_t cmask_clear_value;
1459
1460         if (pre_flush) {
1461                 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1462                                                  RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
1463                 *pre_flush |= cmd_buffer->state.flush_bits;
1464         }
1465
1466         /* DCC */
1467         radv_format_pack_clear_color(iview->vk_format, clear_color, &clear_value);
1468
1469         cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
1470
1471         /* clear cmask buffer */
1472         if (radv_image_has_dcc(iview->image)) {
1473                 uint32_t reset_value;
1474                 bool can_avoid_fast_clear_elim;
1475                 bool need_decompress_pass = false;
1476
1477                 vi_get_fast_clear_parameters(iview->vk_format,
1478                                              &clear_value, &reset_value,
1479                                              &can_avoid_fast_clear_elim);
1480
1481                 if (radv_image_has_cmask(iview->image)) {
1482                         flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1483                                                       cmask_clear_value);
1484
1485                         need_decompress_pass = true;
1486                 }
1487
1488                 if (!can_avoid_fast_clear_elim)
1489                         need_decompress_pass = true;
1490
1491                 flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, reset_value);
1492
1493                 radv_update_fce_metadata(cmd_buffer, iview->image,
1494                                          need_decompress_pass);
1495         } else {
1496                 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1497                                               cmask_clear_value);
1498         }
1499
1500         if (post_flush) {
1501                 *post_flush |= flush_bits;
1502         }
1503
1504         radv_update_color_clear_metadata(cmd_buffer, iview->image, subpass_att,
1505                                          clear_color);
1506 }
1507
1508 /**
1509  * The parameters mean that same as those in vkCmdClearAttachments.
1510  */
1511 static void
1512 emit_clear(struct radv_cmd_buffer *cmd_buffer,
1513            const VkClearAttachment *clear_att,
1514            const VkClearRect *clear_rect,
1515            enum radv_cmd_flush_bits *pre_flush,
1516            enum radv_cmd_flush_bits *post_flush,
1517            uint32_t view_mask)
1518 {
1519         const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
1520         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1521         VkImageAspectFlags aspects = clear_att->aspectMask;
1522
1523         if (aspects & VK_IMAGE_ASPECT_COLOR_BIT) {
1524                 const uint32_t subpass_att = clear_att->colorAttachment;
1525                 if (subpass_att == VK_ATTACHMENT_UNUSED)
1526                         return;
1527
1528                 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
1529                 if (pass_att == VK_ATTACHMENT_UNUSED)
1530                         return;
1531
1532                 VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
1533                 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
1534                 VkClearColorValue clear_value = clear_att->clearValue.color;
1535
1536                 if (radv_can_fast_clear_color(cmd_buffer, iview, image_layout,
1537                                               clear_rect, clear_value, view_mask)) {
1538                         radv_fast_clear_color(cmd_buffer, iview, clear_att,
1539                                               subpass_att, pre_flush,
1540                                               post_flush);
1541                 } else {
1542                         emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask);
1543                 }
1544         } else {
1545                 const uint32_t pass_att = subpass->depth_stencil_attachment->attachment;
1546                 if (pass_att == VK_ATTACHMENT_UNUSED)
1547                         return;
1548
1549                 VkImageLayout image_layout = subpass->depth_stencil_attachment->layout;
1550                 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
1551                 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
1552
1553                 assert(aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
1554                                   VK_IMAGE_ASPECT_STENCIL_BIT));
1555
1556                 if (radv_can_fast_clear_depth(cmd_buffer, iview, image_layout,
1557                                               aspects, clear_rect, clear_value,
1558                                               view_mask)) {
1559                         radv_fast_clear_depth(cmd_buffer, iview, clear_att,
1560                                               pre_flush, post_flush);
1561                 } else {
1562                         emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect,
1563                                                 view_mask);
1564                 }
1565         }
1566 }
1567
1568 static inline bool
1569 radv_attachment_needs_clear(struct radv_cmd_state *cmd_state, uint32_t a)
1570 {
1571         uint32_t view_mask = cmd_state->subpass->view_mask;
1572         return (a != VK_ATTACHMENT_UNUSED &&
1573                 cmd_state->attachments[a].pending_clear_aspects &&
1574                 (!view_mask || (view_mask & ~cmd_state->attachments[a].cleared_views)));
1575 }
1576
1577 static bool
1578 radv_subpass_needs_clear(struct radv_cmd_buffer *cmd_buffer)
1579 {
1580         struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1581         uint32_t a;
1582
1583         if (!cmd_state->subpass)
1584                 return false;
1585
1586         for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1587                 a = cmd_state->subpass->color_attachments[i].attachment;
1588                 if (radv_attachment_needs_clear(cmd_state, a))
1589                         return true;
1590         }
1591
1592         if (!cmd_state->subpass->depth_stencil_attachment)
1593                 return false;
1594
1595         a = cmd_state->subpass->depth_stencil_attachment->attachment;
1596         return radv_attachment_needs_clear(cmd_state, a);
1597 }
1598
1599 static void
1600 radv_subpass_clear_attachment(struct radv_cmd_buffer *cmd_buffer,
1601                               struct radv_attachment_state *attachment,
1602                               const VkClearAttachment *clear_att,
1603                               enum radv_cmd_flush_bits *pre_flush,
1604                               enum radv_cmd_flush_bits *post_flush)
1605 {
1606         struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1607         uint32_t view_mask = cmd_state->subpass->view_mask;
1608
1609         VkClearRect clear_rect = {
1610                 .rect = cmd_state->render_area,
1611                 .baseArrayLayer = 0,
1612                 .layerCount = cmd_state->framebuffer->layers,
1613         };
1614
1615         emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush,
1616                    view_mask & ~attachment->cleared_views);
1617         if (view_mask)
1618                 attachment->cleared_views |= view_mask;
1619         else
1620                 attachment->pending_clear_aspects = 0;
1621 }
1622
1623 /**
1624  * Emit any pending attachment clears for the current subpass.
1625  *
1626  * @see radv_attachment_state::pending_clear_aspects
1627  */
1628 void
1629 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1630 {
1631         struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1632         struct radv_meta_saved_state saved_state;
1633         enum radv_cmd_flush_bits pre_flush = 0;
1634         enum radv_cmd_flush_bits post_flush = 0;
1635
1636         if (!radv_subpass_needs_clear(cmd_buffer))
1637                 return;
1638
1639         radv_meta_save(&saved_state, cmd_buffer,
1640                        RADV_META_SAVE_GRAPHICS_PIPELINE |
1641                        RADV_META_SAVE_CONSTANTS);
1642
1643         for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1644                 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1645
1646                 if (!radv_attachment_needs_clear(cmd_state, a))
1647                         continue;
1648
1649                 assert(cmd_state->attachments[a].pending_clear_aspects ==
1650                        VK_IMAGE_ASPECT_COLOR_BIT);
1651
1652                 VkClearAttachment clear_att = {
1653                         .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1654                         .colorAttachment = i, /* Use attachment index relative to subpass */
1655                         .clearValue = cmd_state->attachments[a].clear_value,
1656                 };
1657
1658                 radv_subpass_clear_attachment(cmd_buffer,
1659                                               &cmd_state->attachments[a],
1660                                               &clear_att, &pre_flush,
1661                                               &post_flush);
1662         }
1663
1664         if (cmd_state->subpass->depth_stencil_attachment) {
1665                 uint32_t ds = cmd_state->subpass->depth_stencil_attachment->attachment;
1666                 if (radv_attachment_needs_clear(cmd_state, ds)) {
1667                         VkClearAttachment clear_att = {
1668                                 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1669                                 .clearValue = cmd_state->attachments[ds].clear_value,
1670                         };
1671
1672                         radv_subpass_clear_attachment(cmd_buffer,
1673                                                       &cmd_state->attachments[ds],
1674                                                       &clear_att, &pre_flush,
1675                                                       &post_flush);
1676                 }
1677         }
1678
1679         radv_meta_restore(&saved_state, cmd_buffer);
1680         cmd_buffer->state.flush_bits |= post_flush;
1681 }
1682
1683 static void
1684 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1685                        struct radv_image *image,
1686                        VkImageLayout image_layout,
1687                        const VkImageSubresourceRange *range,
1688                        VkFormat format, int level, int layer,
1689                        const VkClearValue *clear_val)
1690 {
1691         VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1692         struct radv_image_view iview;
1693         uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level);
1694         uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level);
1695
1696         radv_image_view_init(&iview, cmd_buffer->device,
1697                              &(VkImageViewCreateInfo) {
1698                                      .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1699                                              .image = radv_image_to_handle(image),
1700                                              .viewType = radv_meta_get_view_type(image),
1701                                              .format = format,
1702                                              .subresourceRange = {
1703                                              .aspectMask = range->aspectMask,
1704                                              .baseMipLevel = range->baseMipLevel + level,
1705                                              .levelCount = 1,
1706                                              .baseArrayLayer = range->baseArrayLayer + layer,
1707                                              .layerCount = 1
1708                                      },
1709                              });
1710
1711         VkFramebuffer fb;
1712         radv_CreateFramebuffer(device_h,
1713                                &(VkFramebufferCreateInfo) {
1714                                        .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1715                                                .attachmentCount = 1,
1716                                                .pAttachments = (VkImageView[]) {
1717                                                radv_image_view_to_handle(&iview),
1718                                        },
1719                                                .width = width,
1720                                                .height = height,
1721                                                .layers = 1
1722                                },
1723                                &cmd_buffer->pool->alloc,
1724                                &fb);
1725
1726         VkAttachmentDescription att_desc = {
1727                 .format = iview.vk_format,
1728                 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1729                 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1730                 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1731                 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1732                 .initialLayout = image_layout,
1733                 .finalLayout = image_layout,
1734         };
1735
1736         VkSubpassDescription subpass_desc = {
1737                 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1738                 .inputAttachmentCount = 0,
1739                 .colorAttachmentCount = 0,
1740                 .pColorAttachments = NULL,
1741                 .pResolveAttachments = NULL,
1742                 .pDepthStencilAttachment = NULL,
1743                 .preserveAttachmentCount = 0,
1744                 .pPreserveAttachments = NULL,
1745         };
1746
1747         const VkAttachmentReference att_ref = {
1748                 .attachment = 0,
1749                 .layout = image_layout,
1750         };
1751
1752         if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1753                 subpass_desc.colorAttachmentCount = 1;
1754                 subpass_desc.pColorAttachments = &att_ref;
1755         } else {
1756                 subpass_desc.pDepthStencilAttachment = &att_ref;
1757         }
1758
1759         VkRenderPass pass;
1760         radv_CreateRenderPass(device_h,
1761                               &(VkRenderPassCreateInfo) {
1762                                       .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1763                                               .attachmentCount = 1,
1764                                               .pAttachments = &att_desc,
1765                                               .subpassCount = 1,
1766                                               .pSubpasses = &subpass_desc,
1767                                               },
1768                               &cmd_buffer->pool->alloc,
1769                               &pass);
1770
1771         radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1772                                 &(VkRenderPassBeginInfo) {
1773                                         .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1774                                                 .renderArea = {
1775                                                 .offset = { 0, 0, },
1776                                                 .extent = {
1777                                                         .width = width,
1778                                                         .height = height,
1779                                                 },
1780                                         },
1781                                                 .renderPass = pass,
1782                                                 .framebuffer = fb,
1783                                                 .clearValueCount = 0,
1784                                                 .pClearValues = NULL,
1785                                                 },
1786                                 VK_SUBPASS_CONTENTS_INLINE);
1787
1788         VkClearAttachment clear_att = {
1789                 .aspectMask = range->aspectMask,
1790                 .colorAttachment = 0,
1791                 .clearValue = *clear_val,
1792         };
1793
1794         VkClearRect clear_rect = {
1795                 .rect = {
1796                         .offset = { 0, 0 },
1797                         .extent = { width, height },
1798                 },
1799                 .baseArrayLayer = range->baseArrayLayer,
1800                 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1801         };
1802
1803         emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0);
1804
1805         radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1806         radv_DestroyRenderPass(device_h, pass,
1807                                &cmd_buffer->pool->alloc);
1808         radv_DestroyFramebuffer(device_h, fb,
1809                                 &cmd_buffer->pool->alloc);
1810 }
1811
1812 /**
1813  * Return TRUE if a fast color or depth clear has been performed.
1814  */
1815 static bool
1816 radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer,
1817                       struct radv_image *image,
1818                       VkFormat format,
1819                       VkImageLayout image_layout,
1820                       const VkImageSubresourceRange *range,
1821                       const VkClearValue *clear_val)
1822 {
1823         struct radv_image_view iview;
1824
1825         radv_image_view_init(&iview, cmd_buffer->device,
1826                              &(VkImageViewCreateInfo) {
1827                                         .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1828                                         .image = radv_image_to_handle(image),
1829                                         .viewType = radv_meta_get_view_type(image),
1830                                         .format = image->vk_format,
1831                                         .subresourceRange = {
1832                                         .aspectMask = range->aspectMask,
1833                                         .baseMipLevel = range->baseMipLevel,
1834                                         .levelCount = range->levelCount,
1835                                         .baseArrayLayer = range->baseArrayLayer,
1836                                         .layerCount = range->layerCount,
1837                                    },
1838                              });
1839
1840         VkClearRect clear_rect = {
1841                 .rect = {
1842                         .offset = { 0, 0 },
1843                         .extent = {
1844                                 radv_minify(image->info.width, range->baseMipLevel),
1845                                 radv_minify(image->info.height, range->baseMipLevel),
1846                         },
1847                 },
1848                 .baseArrayLayer = range->baseArrayLayer,
1849                 .layerCount = range->layerCount,
1850         };
1851
1852         VkClearAttachment clear_att = {
1853                 .aspectMask = range->aspectMask,
1854                 .colorAttachment = 0,
1855                 .clearValue = *clear_val,
1856         };
1857
1858         if (vk_format_is_color(format)) {
1859                 if (radv_can_fast_clear_color(cmd_buffer, &iview,
1860                                               image_layout, &clear_rect,
1861                                               clear_att.clearValue.color, 0)) {
1862                         radv_fast_clear_color(cmd_buffer, &iview, &clear_att,
1863                                               clear_att.colorAttachment,
1864                                               NULL, NULL);
1865                         return true;
1866                 }
1867         } else {
1868                 if (radv_can_fast_clear_depth(cmd_buffer, &iview, image_layout,
1869                                               range->aspectMask, &clear_rect,
1870                                               clear_att.clearValue.depthStencil, 0)) {
1871                         radv_fast_clear_depth(cmd_buffer, &iview, &clear_att,
1872                                               NULL, NULL);
1873                         return true;
1874                 }
1875         }
1876
1877         return false;
1878 }
1879
1880 static void
1881 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
1882                      struct radv_image *image,
1883                      VkImageLayout image_layout,
1884                      const VkClearValue *clear_value,
1885                      uint32_t range_count,
1886                      const VkImageSubresourceRange *ranges,
1887                      bool cs)
1888 {
1889         VkFormat format = image->vk_format;
1890         VkClearValue internal_clear_value = *clear_value;
1891
1892         if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
1893                 uint32_t value;
1894                 format = VK_FORMAT_R32_UINT;
1895                 value = float3_to_rgb9e5(clear_value->color.float32);
1896                 internal_clear_value.color.uint32[0] = value;
1897         }
1898
1899         if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
1900                 uint8_t r, g;
1901                 format = VK_FORMAT_R8_UINT;
1902                 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
1903                 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
1904                 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
1905         }
1906
1907         if (format == VK_FORMAT_R32G32B32_UINT ||
1908             format == VK_FORMAT_R32G32B32_SINT ||
1909             format == VK_FORMAT_R32G32B32_SFLOAT)
1910                 cs = true;
1911
1912         for (uint32_t r = 0; r < range_count; r++) {
1913                 const VkImageSubresourceRange *range = &ranges[r];
1914
1915                 /* Try to perform a fast clear first, otherwise fallback to
1916                  * the legacy path.
1917                  */
1918                 if (!cs &&
1919                     radv_fast_clear_range(cmd_buffer, image, format,
1920                                           image_layout, range,
1921                                           &internal_clear_value)) {
1922                         continue;
1923                 }
1924
1925                 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
1926                         const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
1927                                 radv_minify(image->info.depth, range->baseMipLevel + l) :
1928                                 radv_get_layerCount(image, range);
1929                         for (uint32_t s = 0; s < layer_count; ++s) {
1930
1931                                 if (cs) {
1932                                         struct radv_meta_blit2d_surf surf;
1933                                         surf.format = format;
1934                                         surf.image = image;
1935                                         surf.level = range->baseMipLevel + l;
1936                                         surf.layer = range->baseArrayLayer + s;
1937                                         surf.aspect_mask = range->aspectMask;
1938                                         radv_meta_clear_image_cs(cmd_buffer, &surf,
1939                                                                  &internal_clear_value.color);
1940                                 } else {
1941                                         radv_clear_image_layer(cmd_buffer, image, image_layout,
1942                                                                range, format, l, s, &internal_clear_value);
1943                                 }
1944                         }
1945                 }
1946         }
1947 }
1948
1949 void radv_CmdClearColorImage(
1950         VkCommandBuffer                             commandBuffer,
1951         VkImage                                     image_h,
1952         VkImageLayout                               imageLayout,
1953         const VkClearColorValue*                    pColor,
1954         uint32_t                                    rangeCount,
1955         const VkImageSubresourceRange*              pRanges)
1956 {
1957         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1958         RADV_FROM_HANDLE(radv_image, image, image_h);
1959         struct radv_meta_saved_state saved_state;
1960         bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1961
1962         if (cs) {
1963                 radv_meta_save(&saved_state, cmd_buffer,
1964                                RADV_META_SAVE_COMPUTE_PIPELINE |
1965                                RADV_META_SAVE_CONSTANTS |
1966                                RADV_META_SAVE_DESCRIPTORS);
1967         } else {
1968                 radv_meta_save(&saved_state, cmd_buffer,
1969                                RADV_META_SAVE_GRAPHICS_PIPELINE |
1970                                RADV_META_SAVE_CONSTANTS);
1971         }
1972
1973         radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1974                              (const VkClearValue *) pColor,
1975                              rangeCount, pRanges, cs);
1976
1977         radv_meta_restore(&saved_state, cmd_buffer);
1978 }
1979
1980 void radv_CmdClearDepthStencilImage(
1981         VkCommandBuffer                             commandBuffer,
1982         VkImage                                     image_h,
1983         VkImageLayout                               imageLayout,
1984         const VkClearDepthStencilValue*             pDepthStencil,
1985         uint32_t                                    rangeCount,
1986         const VkImageSubresourceRange*              pRanges)
1987 {
1988         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1989         RADV_FROM_HANDLE(radv_image, image, image_h);
1990         struct radv_meta_saved_state saved_state;
1991
1992         radv_meta_save(&saved_state, cmd_buffer,
1993                        RADV_META_SAVE_GRAPHICS_PIPELINE |
1994                        RADV_META_SAVE_CONSTANTS);
1995
1996         radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1997                              (const VkClearValue *) pDepthStencil,
1998                              rangeCount, pRanges, false);
1999
2000         radv_meta_restore(&saved_state, cmd_buffer);
2001 }
2002
2003 void radv_CmdClearAttachments(
2004         VkCommandBuffer                             commandBuffer,
2005         uint32_t                                    attachmentCount,
2006         const VkClearAttachment*                    pAttachments,
2007         uint32_t                                    rectCount,
2008         const VkClearRect*                          pRects)
2009 {
2010         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2011         struct radv_meta_saved_state saved_state;
2012         enum radv_cmd_flush_bits pre_flush = 0;
2013         enum radv_cmd_flush_bits post_flush = 0;
2014
2015         if (!cmd_buffer->state.subpass)
2016                 return;
2017
2018         radv_meta_save(&saved_state, cmd_buffer,
2019                        RADV_META_SAVE_GRAPHICS_PIPELINE |
2020                        RADV_META_SAVE_CONSTANTS);
2021
2022         /* FINISHME: We can do better than this dumb loop. It thrashes too much
2023          * state.
2024          */
2025         for (uint32_t a = 0; a < attachmentCount; ++a) {
2026                 for (uint32_t r = 0; r < rectCount; ++r) {
2027                         emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush,
2028                                    cmd_buffer->state.subpass->view_mask);
2029                 }
2030         }
2031
2032         radv_meta_restore(&saved_state, cmd_buffer);
2033         cmd_buffer->state.flush_bits |= post_flush;
2034 }