2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "radv_debug.h"
25 #include "radv_meta.h"
26 #include "radv_private.h"
27 #include "nir/nir_builder.h"
29 #include "util/format_rgb9e5.h"
30 #include "vk_format.h"
34 DEPTH_CLEAR_FAST_EXPCLEAR
,
35 DEPTH_CLEAR_FAST_NO_EXPCLEAR
39 build_color_shaders(struct nir_shader
**out_vs
,
40 struct nir_shader
**out_fs
,
46 nir_builder_init_simple_shader(&vs_b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
47 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
49 vs_b
.shader
->info
.name
= ralloc_strdup(vs_b
.shader
, "meta_clear_color_vs");
50 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "meta_clear_color_fs");
52 const struct glsl_type
*position_type
= glsl_vec4_type();
53 const struct glsl_type
*color_type
= glsl_vec4_type();
55 nir_variable
*vs_out_pos
=
56 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, position_type
,
58 vs_out_pos
->data
.location
= VARYING_SLOT_POS
;
60 nir_intrinsic_instr
*in_color_load
= nir_intrinsic_instr_create(fs_b
.shader
, nir_intrinsic_load_push_constant
);
61 nir_intrinsic_set_base(in_color_load
, 0);
62 nir_intrinsic_set_range(in_color_load
, 16);
63 in_color_load
->src
[0] = nir_src_for_ssa(nir_imm_int(&fs_b
, 0));
64 in_color_load
->num_components
= 4;
65 nir_ssa_dest_init(&in_color_load
->instr
, &in_color_load
->dest
, 4, 32, "clear color");
66 nir_builder_instr_insert(&fs_b
, &in_color_load
->instr
);
68 nir_variable
*fs_out_color
=
69 nir_variable_create(fs_b
.shader
, nir_var_shader_out
, color_type
,
71 fs_out_color
->data
.location
= FRAG_RESULT_DATA0
+ frag_output
;
73 nir_store_var(&fs_b
, fs_out_color
, &in_color_load
->dest
.ssa
, 0xf);
75 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices(&vs_b
);
76 nir_store_var(&vs_b
, vs_out_pos
, outvec
, 0xf);
78 const struct glsl_type
*layer_type
= glsl_int_type();
79 nir_variable
*vs_out_layer
=
80 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, layer_type
,
82 vs_out_layer
->data
.location
= VARYING_SLOT_LAYER
;
83 vs_out_layer
->data
.interpolation
= INTERP_MODE_FLAT
;
84 nir_ssa_def
*inst_id
= nir_load_instance_id(&vs_b
);
85 nir_ssa_def
*base_instance
= nir_load_base_instance(&vs_b
);
87 nir_ssa_def
*layer_id
= nir_iadd(&vs_b
, inst_id
, base_instance
);
88 nir_store_var(&vs_b
, vs_out_layer
, layer_id
, 0x1);
90 *out_vs
= vs_b
.shader
;
91 *out_fs
= fs_b
.shader
;
95 create_pipeline(struct radv_device
*device
,
96 struct radv_render_pass
*render_pass
,
98 struct nir_shader
*vs_nir
,
99 struct nir_shader
*fs_nir
,
100 const VkPipelineVertexInputStateCreateInfo
*vi_state
,
101 const VkPipelineDepthStencilStateCreateInfo
*ds_state
,
102 const VkPipelineColorBlendStateCreateInfo
*cb_state
,
103 const VkPipelineLayout layout
,
104 const struct radv_graphics_pipeline_create_info
*extra
,
105 const VkAllocationCallbacks
*alloc
,
106 VkPipeline
*pipeline
)
108 VkDevice device_h
= radv_device_to_handle(device
);
111 struct radv_shader_module vs_m
= { .nir
= vs_nir
};
112 struct radv_shader_module fs_m
= { .nir
= fs_nir
};
114 result
= radv_graphics_pipeline_create(device_h
,
115 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
116 &(VkGraphicsPipelineCreateInfo
) {
117 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
118 .stageCount
= fs_nir
? 2 : 1,
119 .pStages
= (VkPipelineShaderStageCreateInfo
[]) {
121 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
122 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
123 .module
= radv_shader_module_to_handle(&vs_m
),
127 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
128 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
129 .module
= radv_shader_module_to_handle(&fs_m
),
133 .pVertexInputState
= vi_state
,
134 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
135 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
136 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
137 .primitiveRestartEnable
= false,
139 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
140 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
144 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
145 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
146 .rasterizerDiscardEnable
= false,
147 .polygonMode
= VK_POLYGON_MODE_FILL
,
148 .cullMode
= VK_CULL_MODE_NONE
,
149 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
,
150 .depthBiasEnable
= false,
152 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
153 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
154 .rasterizationSamples
= samples
,
155 .sampleShadingEnable
= false,
157 .alphaToCoverageEnable
= false,
158 .alphaToOneEnable
= false,
160 .pDepthStencilState
= ds_state
,
161 .pColorBlendState
= cb_state
,
162 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
163 /* The meta clear pipeline declares all state as dynamic.
164 * As a consequence, vkCmdBindPipeline writes no dynamic state
165 * to the cmd buffer. Therefore, at the end of the meta clear,
166 * we need only restore dynamic state was vkCmdSet.
168 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
169 .dynamicStateCount
= 8,
170 .pDynamicStates
= (VkDynamicState
[]) {
171 /* Everything except stencil write mask */
172 VK_DYNAMIC_STATE_VIEWPORT
,
173 VK_DYNAMIC_STATE_SCISSOR
,
174 VK_DYNAMIC_STATE_LINE_WIDTH
,
175 VK_DYNAMIC_STATE_DEPTH_BIAS
,
176 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
177 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
178 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
179 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
184 .renderPass
= radv_render_pass_to_handle(render_pass
),
198 create_color_renderpass(struct radv_device
*device
,
203 mtx_lock(&device
->meta_state
.mtx
);
205 mtx_unlock (&device
->meta_state
.mtx
);
209 VkResult result
= radv_CreateRenderPass(radv_device_to_handle(device
),
210 &(VkRenderPassCreateInfo
) {
211 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
212 .attachmentCount
= 1,
213 .pAttachments
= &(VkAttachmentDescription
) {
216 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
217 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
218 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
219 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
222 .pSubpasses
= &(VkSubpassDescription
) {
223 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
224 .inputAttachmentCount
= 0,
225 .colorAttachmentCount
= 1,
226 .pColorAttachments
= &(VkAttachmentReference
) {
228 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
230 .pResolveAttachments
= NULL
,
231 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
232 .attachment
= VK_ATTACHMENT_UNUSED
,
233 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
235 .preserveAttachmentCount
= 1,
236 .pPreserveAttachments
= (uint32_t[]) { 0 },
238 .dependencyCount
= 0,
239 }, &device
->meta_state
.alloc
, pass
);
240 mtx_unlock(&device
->meta_state
.mtx
);
245 create_color_pipeline(struct radv_device
*device
,
247 uint32_t frag_output
,
248 VkPipeline
*pipeline
,
251 struct nir_shader
*vs_nir
;
252 struct nir_shader
*fs_nir
;
255 mtx_lock(&device
->meta_state
.mtx
);
257 mtx_unlock(&device
->meta_state
.mtx
);
261 build_color_shaders(&vs_nir
, &fs_nir
, frag_output
);
263 const VkPipelineVertexInputStateCreateInfo vi_state
= {
264 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
265 .vertexBindingDescriptionCount
= 0,
266 .vertexAttributeDescriptionCount
= 0,
269 const VkPipelineDepthStencilStateCreateInfo ds_state
= {
270 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
271 .depthTestEnable
= false,
272 .depthWriteEnable
= false,
273 .depthBoundsTestEnable
= false,
274 .stencilTestEnable
= false,
277 VkPipelineColorBlendAttachmentState blend_attachment_state
[MAX_RTS
] = { 0 };
278 blend_attachment_state
[frag_output
] = (VkPipelineColorBlendAttachmentState
) {
279 .blendEnable
= false,
280 .colorWriteMask
= VK_COLOR_COMPONENT_A_BIT
|
281 VK_COLOR_COMPONENT_R_BIT
|
282 VK_COLOR_COMPONENT_G_BIT
|
283 VK_COLOR_COMPONENT_B_BIT
,
286 const VkPipelineColorBlendStateCreateInfo cb_state
= {
287 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
288 .logicOpEnable
= false,
289 .attachmentCount
= MAX_RTS
,
290 .pAttachments
= blend_attachment_state
294 struct radv_graphics_pipeline_create_info extra
= {
295 .use_rectlist
= true,
297 result
= create_pipeline(device
, radv_render_pass_from_handle(pass
),
298 samples
, vs_nir
, fs_nir
, &vi_state
, &ds_state
, &cb_state
,
299 device
->meta_state
.clear_color_p_layout
,
300 &extra
, &device
->meta_state
.alloc
, pipeline
);
302 mtx_unlock(&device
->meta_state
.mtx
);
307 radv_device_finish_meta_clear_state(struct radv_device
*device
)
309 struct radv_meta_state
*state
= &device
->meta_state
;
311 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->clear
); ++i
) {
312 for (uint32_t j
= 0; j
< ARRAY_SIZE(state
->clear
[i
].color_pipelines
); ++j
) {
313 radv_DestroyPipeline(radv_device_to_handle(device
),
314 state
->clear
[i
].color_pipelines
[j
],
316 radv_DestroyRenderPass(radv_device_to_handle(device
),
317 state
->clear
[i
].render_pass
[j
],
321 for (uint32_t j
= 0; j
< NUM_DEPTH_CLEAR_PIPELINES
; j
++) {
322 radv_DestroyPipeline(radv_device_to_handle(device
),
323 state
->clear
[i
].depth_only_pipeline
[j
],
325 radv_DestroyPipeline(radv_device_to_handle(device
),
326 state
->clear
[i
].stencil_only_pipeline
[j
],
328 radv_DestroyPipeline(radv_device_to_handle(device
),
329 state
->clear
[i
].depthstencil_pipeline
[j
],
332 radv_DestroyRenderPass(radv_device_to_handle(device
),
333 state
->clear
[i
].depthstencil_rp
,
336 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
337 state
->clear_color_p_layout
,
339 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
340 state
->clear_depth_p_layout
,
345 emit_color_clear(struct radv_cmd_buffer
*cmd_buffer
,
346 const VkClearAttachment
*clear_att
,
347 const VkClearRect
*clear_rect
,
350 struct radv_device
*device
= cmd_buffer
->device
;
351 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
352 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
353 const uint32_t subpass_att
= clear_att
->colorAttachment
;
354 const uint32_t pass_att
= subpass
->color_attachments
[subpass_att
].attachment
;
355 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
356 const uint32_t samples
= iview
->image
->info
.samples
;
357 const uint32_t samples_log2
= ffs(samples
) - 1;
358 unsigned fs_key
= radv_format_meta_fs_key(iview
->vk_format
);
359 VkClearColorValue clear_value
= clear_att
->clearValue
.color
;
360 VkCommandBuffer cmd_buffer_h
= radv_cmd_buffer_to_handle(cmd_buffer
);
364 radv_finishme("color clears incomplete");
368 if (device
->meta_state
.clear
[samples_log2
].render_pass
[fs_key
] == VK_NULL_HANDLE
) {
369 VkResult ret
= create_color_renderpass(device
, radv_fs_key_format_exemplars
[fs_key
],
371 &device
->meta_state
.clear
[samples_log2
].render_pass
[fs_key
]);
372 if (ret
!= VK_SUCCESS
) {
373 cmd_buffer
->record_result
= ret
;
378 if (device
->meta_state
.clear
[samples_log2
].color_pipelines
[fs_key
] == VK_NULL_HANDLE
) {
379 VkResult ret
= create_color_pipeline(device
, samples
, 0,
380 &device
->meta_state
.clear
[samples_log2
].color_pipelines
[fs_key
],
381 device
->meta_state
.clear
[samples_log2
].render_pass
[fs_key
]);
382 if (ret
!= VK_SUCCESS
) {
383 cmd_buffer
->record_result
= ret
;
388 pipeline
= device
->meta_state
.clear
[samples_log2
].color_pipelines
[fs_key
];
390 radv_finishme("color clears incomplete");
393 assert(samples_log2
< ARRAY_SIZE(device
->meta_state
.clear
));
395 assert(clear_att
->aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
);
396 assert(clear_att
->colorAttachment
< subpass
->color_count
);
398 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
399 device
->meta_state
.clear_color_p_layout
,
400 VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 16,
403 struct radv_subpass clear_subpass
= {
405 .color_attachments
= (struct radv_subpass_attachment
[]) {
406 subpass
->color_attachments
[clear_att
->colorAttachment
]
408 .depth_stencil_attachment
= (struct radv_subpass_attachment
) { VK_ATTACHMENT_UNUSED
, VK_IMAGE_LAYOUT_UNDEFINED
}
411 radv_cmd_buffer_set_subpass(cmd_buffer
, &clear_subpass
, false);
413 radv_CmdBindPipeline(cmd_buffer_h
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
416 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
417 .x
= clear_rect
->rect
.offset
.x
,
418 .y
= clear_rect
->rect
.offset
.y
,
419 .width
= clear_rect
->rect
.extent
.width
,
420 .height
= clear_rect
->rect
.extent
.height
,
425 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &clear_rect
->rect
);
429 for_each_bit(i
, view_mask
)
430 radv_CmdDraw(cmd_buffer_h
, 3, 1, 0, i
);
432 radv_CmdDraw(cmd_buffer_h
, 3, clear_rect
->layerCount
, 0, clear_rect
->baseArrayLayer
);
435 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
440 build_depthstencil_shader(struct nir_shader
**out_vs
, struct nir_shader
**out_fs
)
442 nir_builder vs_b
, fs_b
;
444 nir_builder_init_simple_shader(&vs_b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
445 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
447 vs_b
.shader
->info
.name
= ralloc_strdup(vs_b
.shader
, "meta_clear_depthstencil_vs");
448 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "meta_clear_depthstencil_fs");
449 const struct glsl_type
*position_out_type
= glsl_vec4_type();
451 nir_variable
*vs_out_pos
=
452 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, position_out_type
,
454 vs_out_pos
->data
.location
= VARYING_SLOT_POS
;
456 nir_intrinsic_instr
*in_color_load
= nir_intrinsic_instr_create(vs_b
.shader
, nir_intrinsic_load_push_constant
);
457 nir_intrinsic_set_base(in_color_load
, 0);
458 nir_intrinsic_set_range(in_color_load
, 4);
459 in_color_load
->src
[0] = nir_src_for_ssa(nir_imm_int(&vs_b
, 0));
460 in_color_load
->num_components
= 1;
461 nir_ssa_dest_init(&in_color_load
->instr
, &in_color_load
->dest
, 1, 32, "depth value");
462 nir_builder_instr_insert(&vs_b
, &in_color_load
->instr
);
464 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices_comp2(&vs_b
, &in_color_load
->dest
.ssa
);
465 nir_store_var(&vs_b
, vs_out_pos
, outvec
, 0xf);
467 const struct glsl_type
*layer_type
= glsl_int_type();
468 nir_variable
*vs_out_layer
=
469 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, layer_type
,
471 vs_out_layer
->data
.location
= VARYING_SLOT_LAYER
;
472 vs_out_layer
->data
.interpolation
= INTERP_MODE_FLAT
;
473 nir_ssa_def
*inst_id
= nir_load_instance_id(&vs_b
);
474 nir_ssa_def
*base_instance
= nir_load_base_instance(&vs_b
);
476 nir_ssa_def
*layer_id
= nir_iadd(&vs_b
, inst_id
, base_instance
);
477 nir_store_var(&vs_b
, vs_out_layer
, layer_id
, 0x1);
479 *out_vs
= vs_b
.shader
;
480 *out_fs
= fs_b
.shader
;
484 create_depthstencil_renderpass(struct radv_device
*device
,
486 VkRenderPass
*render_pass
)
488 mtx_lock(&device
->meta_state
.mtx
);
490 mtx_unlock(&device
->meta_state
.mtx
);
494 VkResult result
= radv_CreateRenderPass(radv_device_to_handle(device
),
495 &(VkRenderPassCreateInfo
) {
496 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
497 .attachmentCount
= 1,
498 .pAttachments
= &(VkAttachmentDescription
) {
499 .format
= VK_FORMAT_D32_SFLOAT_S8_UINT
,
501 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
502 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
503 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
504 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
507 .pSubpasses
= &(VkSubpassDescription
) {
508 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
509 .inputAttachmentCount
= 0,
510 .colorAttachmentCount
= 0,
511 .pColorAttachments
= NULL
,
512 .pResolveAttachments
= NULL
,
513 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
515 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
517 .preserveAttachmentCount
= 1,
518 .pPreserveAttachments
= (uint32_t[]) { 0 },
520 .dependencyCount
= 0,
521 }, &device
->meta_state
.alloc
, render_pass
);
522 mtx_unlock(&device
->meta_state
.mtx
);
527 create_depthstencil_pipeline(struct radv_device
*device
,
528 VkImageAspectFlags aspects
,
531 VkPipeline
*pipeline
,
532 VkRenderPass render_pass
)
534 struct nir_shader
*vs_nir
, *fs_nir
;
537 mtx_lock(&device
->meta_state
.mtx
);
539 mtx_unlock(&device
->meta_state
.mtx
);
543 build_depthstencil_shader(&vs_nir
, &fs_nir
);
545 const VkPipelineVertexInputStateCreateInfo vi_state
= {
546 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
547 .vertexBindingDescriptionCount
= 0,
548 .vertexAttributeDescriptionCount
= 0,
551 const VkPipelineDepthStencilStateCreateInfo ds_state
= {
552 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
553 .depthTestEnable
= (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
),
554 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
555 .depthWriteEnable
= (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
),
556 .depthBoundsTestEnable
= false,
557 .stencilTestEnable
= (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
),
559 .passOp
= VK_STENCIL_OP_REPLACE
,
560 .compareOp
= VK_COMPARE_OP_ALWAYS
,
561 .writeMask
= UINT32_MAX
,
562 .reference
= 0, /* dynamic */
564 .back
= { 0 /* dont care */ },
567 const VkPipelineColorBlendStateCreateInfo cb_state
= {
568 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
569 .logicOpEnable
= false,
570 .attachmentCount
= 0,
571 .pAttachments
= NULL
,
574 struct radv_graphics_pipeline_create_info extra
= {
575 .use_rectlist
= true,
578 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
579 extra
.db_depth_clear
= index
== DEPTH_CLEAR_SLOW
? false : true;
580 extra
.db_depth_disable_expclear
= index
== DEPTH_CLEAR_FAST_NO_EXPCLEAR
? true : false;
582 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
583 extra
.db_stencil_clear
= index
== DEPTH_CLEAR_SLOW
? false : true;
584 extra
.db_stencil_disable_expclear
= index
== DEPTH_CLEAR_FAST_NO_EXPCLEAR
? true : false;
586 result
= create_pipeline(device
, radv_render_pass_from_handle(render_pass
),
587 samples
, vs_nir
, fs_nir
, &vi_state
, &ds_state
, &cb_state
,
588 device
->meta_state
.clear_depth_p_layout
,
589 &extra
, &device
->meta_state
.alloc
, pipeline
);
591 mtx_unlock(&device
->meta_state
.mtx
);
595 static bool depth_view_can_fast_clear(struct radv_cmd_buffer
*cmd_buffer
,
596 const struct radv_image_view
*iview
,
597 VkImageAspectFlags aspects
,
598 VkImageLayout layout
,
599 const VkClearRect
*clear_rect
,
600 VkClearDepthStencilValue clear_value
)
602 uint32_t queue_mask
= radv_image_queue_family_mask(iview
->image
,
603 cmd_buffer
->queue_family_index
,
604 cmd_buffer
->queue_family_index
);
605 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
606 clear_rect
->rect
.extent
.width
!= iview
->extent
.width
||
607 clear_rect
->rect
.extent
.height
!= iview
->extent
.height
)
609 if (radv_image_is_tc_compat_htile(iview
->image
) &&
610 (((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) && clear_value
.depth
!= 0.0 &&
611 clear_value
.depth
!= 1.0) ||
612 ((aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) && clear_value
.stencil
!= 0)))
614 if (radv_image_has_htile(iview
->image
) &&
615 iview
->base_mip
== 0 &&
616 iview
->base_layer
== 0 &&
617 radv_layout_is_htile_compressed(iview
->image
, layout
, queue_mask
) &&
618 !radv_image_extent_compare(iview
->image
, &iview
->extent
))
624 pick_depthstencil_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
625 struct radv_meta_state
*meta_state
,
626 const struct radv_image_view
*iview
,
628 VkImageAspectFlags aspects
,
629 VkImageLayout layout
,
630 const VkClearRect
*clear_rect
,
631 VkClearDepthStencilValue clear_value
)
633 bool fast
= depth_view_can_fast_clear(cmd_buffer
, iview
, aspects
, layout
, clear_rect
, clear_value
);
634 int index
= DEPTH_CLEAR_SLOW
;
635 VkPipeline
*pipeline
;
638 /* we don't know the previous clear values, so we always have
639 * the NO_EXPCLEAR path */
640 index
= DEPTH_CLEAR_FAST_NO_EXPCLEAR
;
644 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
645 pipeline
= &meta_state
->clear
[samples_log2
].depthstencil_pipeline
[index
];
647 case VK_IMAGE_ASPECT_DEPTH_BIT
:
648 pipeline
= &meta_state
->clear
[samples_log2
].depth_only_pipeline
[index
];
650 case VK_IMAGE_ASPECT_STENCIL_BIT
:
651 pipeline
= &meta_state
->clear
[samples_log2
].stencil_only_pipeline
[index
];
654 unreachable("expected depth or stencil aspect");
657 if (cmd_buffer
->device
->meta_state
.clear
[samples_log2
].depthstencil_rp
== VK_NULL_HANDLE
) {
658 VkResult ret
= create_depthstencil_renderpass(cmd_buffer
->device
, 1u << samples_log2
,
659 &cmd_buffer
->device
->meta_state
.clear
[samples_log2
].depthstencil_rp
);
660 if (ret
!= VK_SUCCESS
) {
661 cmd_buffer
->record_result
= ret
;
662 return VK_NULL_HANDLE
;
666 if (*pipeline
== VK_NULL_HANDLE
) {
667 VkResult ret
= create_depthstencil_pipeline(cmd_buffer
->device
, aspects
, 1u << samples_log2
, index
,
668 pipeline
, cmd_buffer
->device
->meta_state
.clear
[samples_log2
].depthstencil_rp
);
669 if (ret
!= VK_SUCCESS
) {
670 cmd_buffer
->record_result
= ret
;
671 return VK_NULL_HANDLE
;
678 emit_depthstencil_clear(struct radv_cmd_buffer
*cmd_buffer
,
679 const VkClearAttachment
*clear_att
,
680 const VkClearRect
*clear_rect
)
682 struct radv_device
*device
= cmd_buffer
->device
;
683 struct radv_meta_state
*meta_state
= &device
->meta_state
;
684 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
685 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
686 const uint32_t pass_att
= subpass
->depth_stencil_attachment
.attachment
;
687 VkClearDepthStencilValue clear_value
= clear_att
->clearValue
.depthStencil
;
688 VkImageAspectFlags aspects
= clear_att
->aspectMask
;
689 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
690 const uint32_t samples
= iview
->image
->info
.samples
;
691 const uint32_t samples_log2
= ffs(samples
) - 1;
692 VkCommandBuffer cmd_buffer_h
= radv_cmd_buffer_to_handle(cmd_buffer
);
694 assert(pass_att
!= VK_ATTACHMENT_UNUSED
);
696 if (!(aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
697 clear_value
.depth
= 1.0f
;
699 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
700 device
->meta_state
.clear_depth_p_layout
,
701 VK_SHADER_STAGE_VERTEX_BIT
, 0, 4,
704 uint32_t prev_reference
= cmd_buffer
->state
.dynamic
.stencil_reference
.front
;
705 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
706 radv_CmdSetStencilReference(cmd_buffer_h
, VK_STENCIL_FACE_FRONT_BIT
,
707 clear_value
.stencil
);
710 VkPipeline pipeline
= pick_depthstencil_pipeline(cmd_buffer
,
715 subpass
->depth_stencil_attachment
.layout
,
721 radv_CmdBindPipeline(cmd_buffer_h
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
724 if (depth_view_can_fast_clear(cmd_buffer
, iview
, aspects
,
725 subpass
->depth_stencil_attachment
.layout
,
726 clear_rect
, clear_value
))
727 radv_update_ds_clear_metadata(cmd_buffer
, iview
->image
,
728 clear_value
, aspects
);
730 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
731 .x
= clear_rect
->rect
.offset
.x
,
732 .y
= clear_rect
->rect
.offset
.y
,
733 .width
= clear_rect
->rect
.extent
.width
,
734 .height
= clear_rect
->rect
.extent
.height
,
739 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &clear_rect
->rect
);
741 radv_CmdDraw(cmd_buffer_h
, 3, clear_rect
->layerCount
, 0, clear_rect
->baseArrayLayer
);
743 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
744 radv_CmdSetStencilReference(cmd_buffer_h
, VK_STENCIL_FACE_FRONT_BIT
,
750 emit_fast_htile_clear(struct radv_cmd_buffer
*cmd_buffer
,
751 const VkClearAttachment
*clear_att
,
752 const VkClearRect
*clear_rect
,
753 enum radv_cmd_flush_bits
*pre_flush
,
754 enum radv_cmd_flush_bits
*post_flush
)
756 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
757 const uint32_t pass_att
= subpass
->depth_stencil_attachment
.attachment
;
758 VkImageLayout image_layout
= subpass
->depth_stencil_attachment
.layout
;
759 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
760 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
761 VkClearDepthStencilValue clear_value
= clear_att
->clearValue
.depthStencil
;
762 VkImageAspectFlags aspects
= clear_att
->aspectMask
;
763 uint32_t clear_word
, flush_bits
;
765 if (!radv_image_has_htile(iview
->image
))
768 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
)
771 if (!radv_layout_is_htile_compressed(iview
->image
, image_layout
, radv_image_queue_family_mask(iview
->image
, cmd_buffer
->queue_family_index
, cmd_buffer
->queue_family_index
)))
774 /* don't fast clear 3D */
775 if (iview
->image
->type
== VK_IMAGE_TYPE_3D
)
778 /* all layers are bound */
779 if (iview
->base_layer
> 0)
781 if (iview
->image
->info
.array_size
!= iview
->layer_count
)
784 if (!radv_image_extent_compare(iview
->image
, &iview
->extent
))
787 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
788 clear_rect
->rect
.extent
.width
!= iview
->image
->info
.width
||
789 clear_rect
->rect
.extent
.height
!= iview
->image
->info
.height
)
792 if (clear_rect
->baseArrayLayer
!= 0)
794 if (clear_rect
->layerCount
!= iview
->image
->info
.array_size
)
797 if ((clear_value
.depth
!= 0.0 && clear_value
.depth
!= 1.0) || !(aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
800 /* GFX8 only supports 32-bit depth surfaces but we can enable TC-compat
801 * HTILE for 16-bit surfaces if no Z planes are compressed. Though,
802 * fast HTILE clears don't seem to work.
804 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== VI
&&
805 iview
->image
->vk_format
== VK_FORMAT_D16_UNORM
)
808 if (vk_format_aspects(iview
->image
->vk_format
) & VK_IMAGE_ASPECT_STENCIL_BIT
) {
809 if (clear_value
.stencil
!= 0 || !(aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
))
811 clear_word
= clear_value
.depth
? 0xfffc0000 : 0;
813 clear_word
= clear_value
.depth
? 0xfffffff0 : 0;
816 cmd_buffer
->state
.flush_bits
|= (RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
817 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
) & ~ *pre_flush
;
818 *pre_flush
|= cmd_buffer
->state
.flush_bits
;
820 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
821 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
823 flush_bits
= radv_fill_buffer(cmd_buffer
, iview
->image
->bo
,
824 iview
->image
->offset
+ iview
->image
->htile_offset
,
825 iview
->image
->surface
.htile_size
, clear_word
);
827 radv_update_ds_clear_metadata(cmd_buffer
, iview
->image
, clear_value
, aspects
);
829 *post_flush
|= flush_bits
;
831 cmd_buffer
->state
.flush_bits
|= flush_bits
;
840 radv_device_init_meta_clear_state(struct radv_device
*device
, bool on_demand
)
843 struct radv_meta_state
*state
= &device
->meta_state
;
845 VkPipelineLayoutCreateInfo pl_color_create_info
= {
846 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
848 .pushConstantRangeCount
= 1,
849 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 16},
852 res
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
853 &pl_color_create_info
,
854 &device
->meta_state
.alloc
,
855 &device
->meta_state
.clear_color_p_layout
);
856 if (res
!= VK_SUCCESS
)
859 VkPipelineLayoutCreateInfo pl_depth_create_info
= {
860 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
862 .pushConstantRangeCount
= 1,
863 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_VERTEX_BIT
, 0, 4},
866 res
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
867 &pl_depth_create_info
,
868 &device
->meta_state
.alloc
,
869 &device
->meta_state
.clear_depth_p_layout
);
870 if (res
!= VK_SUCCESS
)
876 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->clear
); ++i
) {
877 uint32_t samples
= 1 << i
;
878 for (uint32_t j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
879 VkFormat format
= radv_fs_key_format_exemplars
[j
];
880 unsigned fs_key
= radv_format_meta_fs_key(format
);
881 assert(!state
->clear
[i
].color_pipelines
[fs_key
]);
883 res
= create_color_renderpass(device
, format
, samples
,
884 &state
->clear
[i
].render_pass
[fs_key
]);
885 if (res
!= VK_SUCCESS
)
888 res
= create_color_pipeline(device
, samples
, 0, &state
->clear
[i
].color_pipelines
[fs_key
],
889 state
->clear
[i
].render_pass
[fs_key
]);
890 if (res
!= VK_SUCCESS
)
895 res
= create_depthstencil_renderpass(device
,
897 &state
->clear
[i
].depthstencil_rp
);
898 if (res
!= VK_SUCCESS
)
901 for (uint32_t j
= 0; j
< NUM_DEPTH_CLEAR_PIPELINES
; j
++) {
902 res
= create_depthstencil_pipeline(device
,
903 VK_IMAGE_ASPECT_DEPTH_BIT
,
906 &state
->clear
[i
].depth_only_pipeline
[j
],
907 state
->clear
[i
].depthstencil_rp
);
908 if (res
!= VK_SUCCESS
)
911 res
= create_depthstencil_pipeline(device
,
912 VK_IMAGE_ASPECT_STENCIL_BIT
,
915 &state
->clear
[i
].stencil_only_pipeline
[j
],
916 state
->clear
[i
].depthstencil_rp
);
917 if (res
!= VK_SUCCESS
)
920 res
= create_depthstencil_pipeline(device
,
921 VK_IMAGE_ASPECT_DEPTH_BIT
|
922 VK_IMAGE_ASPECT_STENCIL_BIT
,
925 &state
->clear
[i
].depthstencil_pipeline
[j
],
926 state
->clear
[i
].depthstencil_rp
);
927 if (res
!= VK_SUCCESS
)
934 radv_device_finish_meta_clear_state(device
);
939 radv_get_cmask_fast_clear_value(const struct radv_image
*image
)
941 uint32_t value
= 0; /* Default value when no DCC. */
943 /* The fast-clear value is different for images that have both DCC and
946 if (radv_image_has_dcc(image
)) {
947 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
948 return image
->info
.samples
> 1 ? 0xcccccccc : 0xffffffff;
955 radv_clear_cmask(struct radv_cmd_buffer
*cmd_buffer
,
956 struct radv_image
*image
, uint32_t value
)
958 return radv_fill_buffer(cmd_buffer
, image
->bo
,
959 image
->offset
+ image
->cmask
.offset
,
960 image
->cmask
.size
, value
);
964 radv_clear_dcc(struct radv_cmd_buffer
*cmd_buffer
,
965 struct radv_image
*image
, uint32_t value
)
967 return radv_fill_buffer(cmd_buffer
, image
->bo
,
968 image
->offset
+ image
->dcc_offset
,
969 image
->surface
.dcc_size
, value
);
972 static void vi_get_fast_clear_parameters(VkFormat format
,
973 const VkClearColorValue
*clear_value
,
974 uint32_t* reset_value
,
975 bool *can_avoid_fast_clear_elim
)
979 bool main_value
= false;
980 bool extra_value
= false;
982 *can_avoid_fast_clear_elim
= false;
984 *reset_value
= 0x20202020U
;
986 const struct vk_format_description
*desc
= vk_format_description(format
);
987 if (format
== VK_FORMAT_B10G11R11_UFLOAT_PACK32
||
988 format
== VK_FORMAT_R5G6B5_UNORM_PACK16
||
989 format
== VK_FORMAT_B5G6R5_UNORM_PACK16
)
991 else if (desc
->layout
== VK_FORMAT_LAYOUT_PLAIN
) {
992 if (radv_translate_colorswap(format
, false) <= 1)
993 extra_channel
= desc
->nr_channels
- 1;
999 for (i
= 0; i
< 4; i
++) {
1000 int index
= desc
->swizzle
[i
] - VK_SWIZZLE_X
;
1001 if (desc
->swizzle
[i
] < VK_SWIZZLE_X
||
1002 desc
->swizzle
[i
] > VK_SWIZZLE_W
)
1005 if (desc
->channel
[i
].pure_integer
&&
1006 desc
->channel
[i
].type
== VK_FORMAT_TYPE_SIGNED
) {
1007 /* Use the maximum value for clamping the clear color. */
1008 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
1010 values
[i
] = clear_value
->int32
[i
] != 0;
1011 if (clear_value
->int32
[i
] != 0 && MIN2(clear_value
->int32
[i
], max
) != max
)
1013 } else if (desc
->channel
[i
].pure_integer
&&
1014 desc
->channel
[i
].type
== VK_FORMAT_TYPE_UNSIGNED
) {
1015 /* Use the maximum value for clamping the clear color. */
1016 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
1018 values
[i
] = clear_value
->uint32
[i
] != 0U;
1019 if (clear_value
->uint32
[i
] != 0U && MIN2(clear_value
->uint32
[i
], max
) != max
)
1022 values
[i
] = clear_value
->float32
[i
] != 0.0F
;
1023 if (clear_value
->float32
[i
] != 0.0F
&& clear_value
->float32
[i
] != 1.0F
)
1027 if (index
== extra_channel
)
1028 extra_value
= values
[i
];
1030 main_value
= values
[i
];
1033 for (int i
= 0; i
< 4; ++i
)
1034 if (values
[i
] != main_value
&&
1035 desc
->swizzle
[i
] - VK_SWIZZLE_X
!= extra_channel
&&
1036 desc
->swizzle
[i
] >= VK_SWIZZLE_X
&&
1037 desc
->swizzle
[i
] <= VK_SWIZZLE_W
)
1040 *can_avoid_fast_clear_elim
= true;
1042 *reset_value
|= 0x80808080U
;
1045 *reset_value
|= 0x40404040U
;
1050 emit_fast_color_clear(struct radv_cmd_buffer
*cmd_buffer
,
1051 const VkClearAttachment
*clear_att
,
1052 const VkClearRect
*clear_rect
,
1053 enum radv_cmd_flush_bits
*pre_flush
,
1054 enum radv_cmd_flush_bits
*post_flush
,
1057 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1058 const uint32_t subpass_att
= clear_att
->colorAttachment
;
1059 const uint32_t pass_att
= subpass
->color_attachments
[subpass_att
].attachment
;
1060 VkImageLayout image_layout
= subpass
->color_attachments
[subpass_att
].layout
;
1061 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1062 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
1063 VkClearColorValue clear_value
= clear_att
->clearValue
.color
;
1064 uint32_t clear_color
[2], flush_bits
= 0;
1065 uint32_t cmask_clear_value
;
1068 if (!radv_image_has_cmask(iview
->image
) && !radv_image_has_dcc(iview
->image
))
1071 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
)
1074 if (!radv_layout_can_fast_clear(iview
->image
, image_layout
, radv_image_queue_family_mask(iview
->image
, cmd_buffer
->queue_family_index
, cmd_buffer
->queue_family_index
)))
1077 /* don't fast clear 3D */
1078 if (iview
->image
->type
== VK_IMAGE_TYPE_3D
)
1081 /* all layers are bound */
1082 if (iview
->base_layer
> 0)
1084 if (iview
->image
->info
.array_size
!= iview
->layer_count
)
1087 if (iview
->image
->info
.levels
> 1)
1090 if (!radv_image_extent_compare(iview
->image
, &iview
->extent
))
1093 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
1094 clear_rect
->rect
.extent
.width
!= iview
->image
->info
.width
||
1095 clear_rect
->rect
.extent
.height
!= iview
->image
->info
.height
)
1098 if (view_mask
&& (iview
->image
->info
.array_size
>= 32 ||
1099 (1u << iview
->image
->info
.array_size
) - 1u != view_mask
))
1101 if (!view_mask
&& clear_rect
->baseArrayLayer
!= 0)
1103 if (!view_mask
&& clear_rect
->layerCount
!= iview
->image
->info
.array_size
)
1106 /* RB+ doesn't work with CMASK fast clear on Stoney. */
1107 if (!radv_image_has_dcc(iview
->image
) &&
1108 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_STONEY
)
1112 ret
= radv_format_pack_clear_color(iview
->vk_format
,
1113 clear_color
, &clear_value
);
1118 cmd_buffer
->state
.flush_bits
|= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1119 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
) & ~ *pre_flush
;
1120 *pre_flush
|= cmd_buffer
->state
.flush_bits
;
1122 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1123 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1125 cmask_clear_value
= radv_get_cmask_fast_clear_value(iview
->image
);
1127 /* clear cmask buffer */
1128 if (radv_image_has_dcc(iview
->image
)) {
1129 uint32_t reset_value
;
1130 bool can_avoid_fast_clear_elim
;
1131 bool need_decompress_pass
= false;
1133 vi_get_fast_clear_parameters(iview
->vk_format
,
1134 &clear_value
, &reset_value
,
1135 &can_avoid_fast_clear_elim
);
1137 if (iview
->image
->info
.samples
> 1) {
1138 /* DCC fast clear with MSAA should clear CMASK. */
1139 /* FIXME: This doesn't work for now. There is a
1140 * hardware bug with fast clears and DCC for MSAA
1141 * textures. AMDVLK has a workaround but it doesn't
1142 * seem to work here. Note that we might emit useless
1143 * CB flushes but that shouldn't matter.
1145 if (!can_avoid_fast_clear_elim
)
1148 assert(radv_image_has_cmask(iview
->image
));
1150 flush_bits
= radv_clear_cmask(cmd_buffer
, iview
->image
,
1153 need_decompress_pass
= true;
1156 if (!can_avoid_fast_clear_elim
)
1157 need_decompress_pass
= true;
1159 flush_bits
|= radv_clear_dcc(cmd_buffer
, iview
->image
, reset_value
);
1161 radv_set_dcc_need_cmask_elim_pred(cmd_buffer
, iview
->image
,
1162 need_decompress_pass
);
1164 flush_bits
= radv_clear_cmask(cmd_buffer
, iview
->image
,
1169 *post_flush
|= flush_bits
;
1171 cmd_buffer
->state
.flush_bits
|= flush_bits
;
1174 radv_update_color_clear_metadata(cmd_buffer
, iview
->image
, subpass_att
,
1183 * The parameters mean that same as those in vkCmdClearAttachments.
1186 emit_clear(struct radv_cmd_buffer
*cmd_buffer
,
1187 const VkClearAttachment
*clear_att
,
1188 const VkClearRect
*clear_rect
,
1189 enum radv_cmd_flush_bits
*pre_flush
,
1190 enum radv_cmd_flush_bits
*post_flush
,
1193 if (clear_att
->aspectMask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
1194 if (!emit_fast_color_clear(cmd_buffer
, clear_att
, clear_rect
,
1195 pre_flush
, post_flush
, view_mask
))
1196 emit_color_clear(cmd_buffer
, clear_att
, clear_rect
, view_mask
);
1198 assert(clear_att
->aspectMask
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
1199 VK_IMAGE_ASPECT_STENCIL_BIT
));
1200 if (!emit_fast_htile_clear(cmd_buffer
, clear_att
, clear_rect
,
1201 pre_flush
, post_flush
))
1202 emit_depthstencil_clear(cmd_buffer
, clear_att
, clear_rect
);
1207 radv_attachment_needs_clear(struct radv_cmd_state
*cmd_state
, uint32_t a
)
1209 uint32_t view_mask
= cmd_state
->subpass
->view_mask
;
1210 return (a
!= VK_ATTACHMENT_UNUSED
&&
1211 cmd_state
->attachments
[a
].pending_clear_aspects
&&
1212 (!view_mask
|| (view_mask
& ~cmd_state
->attachments
[a
].cleared_views
)));
1216 radv_subpass_needs_clear(struct radv_cmd_buffer
*cmd_buffer
)
1218 struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1221 if (!cmd_state
->subpass
)
1224 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
1225 a
= cmd_state
->subpass
->color_attachments
[i
].attachment
;
1226 if (radv_attachment_needs_clear(cmd_state
, a
))
1230 a
= cmd_state
->subpass
->depth_stencil_attachment
.attachment
;
1231 return radv_attachment_needs_clear(cmd_state
, a
);
1235 radv_subpass_clear_attachment(struct radv_cmd_buffer
*cmd_buffer
,
1236 struct radv_attachment_state
*attachment
,
1237 const VkClearAttachment
*clear_att
,
1238 enum radv_cmd_flush_bits
*pre_flush
,
1239 enum radv_cmd_flush_bits
*post_flush
)
1241 struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1242 uint32_t view_mask
= cmd_state
->subpass
->view_mask
;
1244 VkClearRect clear_rect
= {
1245 .rect
= cmd_state
->render_area
,
1246 .baseArrayLayer
= 0,
1247 .layerCount
= cmd_state
->framebuffer
->layers
,
1250 emit_clear(cmd_buffer
, clear_att
, &clear_rect
, pre_flush
, post_flush
,
1251 view_mask
& ~attachment
->cleared_views
);
1253 attachment
->cleared_views
|= view_mask
;
1255 attachment
->pending_clear_aspects
= 0;
1259 * Emit any pending attachment clears for the current subpass.
1261 * @see radv_attachment_state::pending_clear_aspects
1264 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
)
1266 struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1267 struct radv_meta_saved_state saved_state
;
1268 enum radv_cmd_flush_bits pre_flush
= 0;
1269 enum radv_cmd_flush_bits post_flush
= 0;
1271 if (!radv_subpass_needs_clear(cmd_buffer
))
1274 radv_meta_save(&saved_state
, cmd_buffer
,
1275 RADV_META_SAVE_GRAPHICS_PIPELINE
|
1276 RADV_META_SAVE_CONSTANTS
);
1278 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
1279 uint32_t a
= cmd_state
->subpass
->color_attachments
[i
].attachment
;
1281 if (!radv_attachment_needs_clear(cmd_state
, a
))
1284 assert(cmd_state
->attachments
[a
].pending_clear_aspects
==
1285 VK_IMAGE_ASPECT_COLOR_BIT
);
1287 VkClearAttachment clear_att
= {
1288 .aspectMask
= VK_IMAGE_ASPECT_COLOR_BIT
,
1289 .colorAttachment
= i
, /* Use attachment index relative to subpass */
1290 .clearValue
= cmd_state
->attachments
[a
].clear_value
,
1293 radv_subpass_clear_attachment(cmd_buffer
,
1294 &cmd_state
->attachments
[a
],
1295 &clear_att
, &pre_flush
,
1299 uint32_t ds
= cmd_state
->subpass
->depth_stencil_attachment
.attachment
;
1300 if (radv_attachment_needs_clear(cmd_state
, ds
)) {
1301 VkClearAttachment clear_att
= {
1302 .aspectMask
= cmd_state
->attachments
[ds
].pending_clear_aspects
,
1303 .clearValue
= cmd_state
->attachments
[ds
].clear_value
,
1306 radv_subpass_clear_attachment(cmd_buffer
,
1307 &cmd_state
->attachments
[ds
],
1308 &clear_att
, &pre_flush
,
1312 radv_meta_restore(&saved_state
, cmd_buffer
);
1313 cmd_buffer
->state
.flush_bits
|= post_flush
;
1317 radv_clear_image_layer(struct radv_cmd_buffer
*cmd_buffer
,
1318 struct radv_image
*image
,
1319 VkImageLayout image_layout
,
1320 const VkImageSubresourceRange
*range
,
1321 VkFormat format
, int level
, int layer
,
1322 const VkClearValue
*clear_val
)
1324 VkDevice device_h
= radv_device_to_handle(cmd_buffer
->device
);
1325 struct radv_image_view iview
;
1326 uint32_t width
= radv_minify(image
->info
.width
, range
->baseMipLevel
+ level
);
1327 uint32_t height
= radv_minify(image
->info
.height
, range
->baseMipLevel
+ level
);
1329 radv_image_view_init(&iview
, cmd_buffer
->device
,
1330 &(VkImageViewCreateInfo
) {
1331 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
1332 .image
= radv_image_to_handle(image
),
1333 .viewType
= radv_meta_get_view_type(image
),
1335 .subresourceRange
= {
1336 .aspectMask
= range
->aspectMask
,
1337 .baseMipLevel
= range
->baseMipLevel
+ level
,
1339 .baseArrayLayer
= range
->baseArrayLayer
+ layer
,
1345 radv_CreateFramebuffer(device_h
,
1346 &(VkFramebufferCreateInfo
) {
1347 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
1348 .attachmentCount
= 1,
1349 .pAttachments
= (VkImageView
[]) {
1350 radv_image_view_to_handle(&iview
),
1356 &cmd_buffer
->pool
->alloc
,
1359 VkAttachmentDescription att_desc
= {
1360 .format
= iview
.vk_format
,
1361 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1362 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1363 .stencilLoadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1364 .stencilStoreOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1365 .initialLayout
= image_layout
,
1366 .finalLayout
= image_layout
,
1369 VkSubpassDescription subpass_desc
= {
1370 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
1371 .inputAttachmentCount
= 0,
1372 .colorAttachmentCount
= 0,
1373 .pColorAttachments
= NULL
,
1374 .pResolveAttachments
= NULL
,
1375 .pDepthStencilAttachment
= NULL
,
1376 .preserveAttachmentCount
= 0,
1377 .pPreserveAttachments
= NULL
,
1380 const VkAttachmentReference att_ref
= {
1382 .layout
= image_layout
,
1385 if (range
->aspectMask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
1386 subpass_desc
.colorAttachmentCount
= 1;
1387 subpass_desc
.pColorAttachments
= &att_ref
;
1389 subpass_desc
.pDepthStencilAttachment
= &att_ref
;
1393 radv_CreateRenderPass(device_h
,
1394 &(VkRenderPassCreateInfo
) {
1395 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
1396 .attachmentCount
= 1,
1397 .pAttachments
= &att_desc
,
1399 .pSubpasses
= &subpass_desc
,
1401 &cmd_buffer
->pool
->alloc
,
1404 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
1405 &(VkRenderPassBeginInfo
) {
1406 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
1408 .offset
= { 0, 0, },
1416 .clearValueCount
= 0,
1417 .pClearValues
= NULL
,
1419 VK_SUBPASS_CONTENTS_INLINE
);
1421 VkClearAttachment clear_att
= {
1422 .aspectMask
= range
->aspectMask
,
1423 .colorAttachment
= 0,
1424 .clearValue
= *clear_val
,
1427 VkClearRect clear_rect
= {
1430 .extent
= { width
, height
},
1432 .baseArrayLayer
= range
->baseArrayLayer
,
1433 .layerCount
= 1, /* FINISHME: clear multi-layer framebuffer */
1436 emit_clear(cmd_buffer
, &clear_att
, &clear_rect
, NULL
, NULL
, 0);
1438 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
));
1439 radv_DestroyRenderPass(device_h
, pass
,
1440 &cmd_buffer
->pool
->alloc
);
1441 radv_DestroyFramebuffer(device_h
, fb
,
1442 &cmd_buffer
->pool
->alloc
);
1445 radv_cmd_clear_image(struct radv_cmd_buffer
*cmd_buffer
,
1446 struct radv_image
*image
,
1447 VkImageLayout image_layout
,
1448 const VkClearValue
*clear_value
,
1449 uint32_t range_count
,
1450 const VkImageSubresourceRange
*ranges
,
1453 VkFormat format
= image
->vk_format
;
1454 VkClearValue internal_clear_value
= *clear_value
;
1456 if (format
== VK_FORMAT_E5B9G9R9_UFLOAT_PACK32
) {
1458 format
= VK_FORMAT_R32_UINT
;
1459 value
= float3_to_rgb9e5(clear_value
->color
.float32
);
1460 internal_clear_value
.color
.uint32
[0] = value
;
1463 if (format
== VK_FORMAT_R4G4_UNORM_PACK8
) {
1465 format
= VK_FORMAT_R8_UINT
;
1466 r
= float_to_ubyte(clear_value
->color
.float32
[0]) >> 4;
1467 g
= float_to_ubyte(clear_value
->color
.float32
[1]) >> 4;
1468 internal_clear_value
.color
.uint32
[0] = (r
<< 4) | (g
& 0xf);
1471 for (uint32_t r
= 0; r
< range_count
; r
++) {
1472 const VkImageSubresourceRange
*range
= &ranges
[r
];
1473 for (uint32_t l
= 0; l
< radv_get_levelCount(image
, range
); ++l
) {
1474 const uint32_t layer_count
= image
->type
== VK_IMAGE_TYPE_3D
?
1475 radv_minify(image
->info
.depth
, range
->baseMipLevel
+ l
) :
1476 radv_get_layerCount(image
, range
);
1477 for (uint32_t s
= 0; s
< layer_count
; ++s
) {
1480 (format
== VK_FORMAT_R32G32B32_UINT
||
1481 format
== VK_FORMAT_R32G32B32_SINT
||
1482 format
== VK_FORMAT_R32G32B32_SFLOAT
)) {
1483 struct radv_meta_blit2d_surf surf
;
1484 surf
.format
= format
;
1486 surf
.level
= range
->baseMipLevel
+ l
;
1487 surf
.layer
= range
->baseArrayLayer
+ s
;
1488 surf
.aspect_mask
= range
->aspectMask
;
1489 radv_meta_clear_image_cs(cmd_buffer
, &surf
,
1490 &internal_clear_value
.color
);
1492 radv_clear_image_layer(cmd_buffer
, image
, image_layout
,
1493 range
, format
, l
, s
, &internal_clear_value
);
1500 void radv_CmdClearColorImage(
1501 VkCommandBuffer commandBuffer
,
1503 VkImageLayout imageLayout
,
1504 const VkClearColorValue
* pColor
,
1505 uint32_t rangeCount
,
1506 const VkImageSubresourceRange
* pRanges
)
1508 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1509 RADV_FROM_HANDLE(radv_image
, image
, image_h
);
1510 struct radv_meta_saved_state saved_state
;
1511 bool cs
= cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
;
1514 radv_meta_save(&saved_state
, cmd_buffer
,
1515 RADV_META_SAVE_COMPUTE_PIPELINE
|
1516 RADV_META_SAVE_CONSTANTS
|
1517 RADV_META_SAVE_DESCRIPTORS
);
1519 radv_meta_save(&saved_state
, cmd_buffer
,
1520 RADV_META_SAVE_GRAPHICS_PIPELINE
|
1521 RADV_META_SAVE_CONSTANTS
);
1524 radv_cmd_clear_image(cmd_buffer
, image
, imageLayout
,
1525 (const VkClearValue
*) pColor
,
1526 rangeCount
, pRanges
, cs
);
1528 radv_meta_restore(&saved_state
, cmd_buffer
);
1531 void radv_CmdClearDepthStencilImage(
1532 VkCommandBuffer commandBuffer
,
1534 VkImageLayout imageLayout
,
1535 const VkClearDepthStencilValue
* pDepthStencil
,
1536 uint32_t rangeCount
,
1537 const VkImageSubresourceRange
* pRanges
)
1539 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1540 RADV_FROM_HANDLE(radv_image
, image
, image_h
);
1541 struct radv_meta_saved_state saved_state
;
1543 radv_meta_save(&saved_state
, cmd_buffer
,
1544 RADV_META_SAVE_GRAPHICS_PIPELINE
|
1545 RADV_META_SAVE_CONSTANTS
);
1547 radv_cmd_clear_image(cmd_buffer
, image
, imageLayout
,
1548 (const VkClearValue
*) pDepthStencil
,
1549 rangeCount
, pRanges
, false);
1551 radv_meta_restore(&saved_state
, cmd_buffer
);
1554 void radv_CmdClearAttachments(
1555 VkCommandBuffer commandBuffer
,
1556 uint32_t attachmentCount
,
1557 const VkClearAttachment
* pAttachments
,
1559 const VkClearRect
* pRects
)
1561 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1562 struct radv_meta_saved_state saved_state
;
1563 enum radv_cmd_flush_bits pre_flush
= 0;
1564 enum radv_cmd_flush_bits post_flush
= 0;
1566 if (!cmd_buffer
->state
.subpass
)
1569 radv_meta_save(&saved_state
, cmd_buffer
,
1570 RADV_META_SAVE_GRAPHICS_PIPELINE
|
1571 RADV_META_SAVE_CONSTANTS
);
1573 /* FINISHME: We can do better than this dumb loop. It thrashes too much
1576 for (uint32_t a
= 0; a
< attachmentCount
; ++a
) {
1577 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
1578 emit_clear(cmd_buffer
, &pAttachments
[a
], &pRects
[r
], &pre_flush
, &post_flush
,
1579 cmd_buffer
->state
.subpass
->view_mask
);
1583 radv_meta_restore(&saved_state
, cmd_buffer
);
1584 cmd_buffer
->state
.flush_bits
|= post_flush
;