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[mesa.git] / src / amd / vulkan / radv_meta_clear.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_debug.h"
25 #include "radv_meta.h"
26 #include "radv_private.h"
27 #include "nir/nir_builder.h"
28
29 #include "util/format_rgb9e5.h"
30 #include "vk_format.h"
31
32 enum {
33 DEPTH_CLEAR_SLOW,
34 DEPTH_CLEAR_FAST_EXPCLEAR,
35 DEPTH_CLEAR_FAST_NO_EXPCLEAR
36 };
37
38 static void
39 build_color_shaders(struct nir_shader **out_vs,
40 struct nir_shader **out_fs,
41 uint32_t frag_output)
42 {
43 nir_builder vs_b;
44 nir_builder fs_b;
45
46 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
47 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
48
49 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
50 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
51
52 const struct glsl_type *position_type = glsl_vec4_type();
53 const struct glsl_type *color_type = glsl_vec4_type();
54
55 nir_variable *vs_out_pos =
56 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
57 "gl_Position");
58 vs_out_pos->data.location = VARYING_SLOT_POS;
59
60 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
61 nir_intrinsic_set_base(in_color_load, 0);
62 nir_intrinsic_set_range(in_color_load, 16);
63 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
64 in_color_load->num_components = 4;
65 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
66 nir_builder_instr_insert(&fs_b, &in_color_load->instr);
67
68 nir_variable *fs_out_color =
69 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
70 "f_color");
71 fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
72
73 nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
74
75 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
76 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
77
78 const struct glsl_type *layer_type = glsl_int_type();
79 nir_variable *vs_out_layer =
80 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
81 "v_layer");
82 vs_out_layer->data.location = VARYING_SLOT_LAYER;
83 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
84 nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
85 nir_ssa_def *base_instance = nir_load_system_value(&vs_b, nir_intrinsic_load_base_instance, 0);
86
87 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
88 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
89
90 *out_vs = vs_b.shader;
91 *out_fs = fs_b.shader;
92 }
93
94 static VkResult
95 create_pipeline(struct radv_device *device,
96 struct radv_render_pass *render_pass,
97 uint32_t samples,
98 struct nir_shader *vs_nir,
99 struct nir_shader *fs_nir,
100 const VkPipelineVertexInputStateCreateInfo *vi_state,
101 const VkPipelineDepthStencilStateCreateInfo *ds_state,
102 const VkPipelineColorBlendStateCreateInfo *cb_state,
103 const VkPipelineLayout layout,
104 const struct radv_graphics_pipeline_create_info *extra,
105 const VkAllocationCallbacks *alloc,
106 VkPipeline *pipeline)
107 {
108 VkDevice device_h = radv_device_to_handle(device);
109 VkResult result;
110
111 struct radv_shader_module vs_m = { .nir = vs_nir };
112 struct radv_shader_module fs_m = { .nir = fs_nir };
113
114 result = radv_graphics_pipeline_create(device_h,
115 radv_pipeline_cache_to_handle(&device->meta_state.cache),
116 &(VkGraphicsPipelineCreateInfo) {
117 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
118 .stageCount = fs_nir ? 2 : 1,
119 .pStages = (VkPipelineShaderStageCreateInfo[]) {
120 {
121 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
122 .stage = VK_SHADER_STAGE_VERTEX_BIT,
123 .module = radv_shader_module_to_handle(&vs_m),
124 .pName = "main",
125 },
126 {
127 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
128 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
129 .module = radv_shader_module_to_handle(&fs_m),
130 .pName = "main",
131 },
132 },
133 .pVertexInputState = vi_state,
134 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
135 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
136 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
137 .primitiveRestartEnable = false,
138 },
139 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
140 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
141 .viewportCount = 1,
142 .scissorCount = 1,
143 },
144 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
145 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
146 .rasterizerDiscardEnable = false,
147 .polygonMode = VK_POLYGON_MODE_FILL,
148 .cullMode = VK_CULL_MODE_NONE,
149 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
150 .depthBiasEnable = false,
151 },
152 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
153 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
154 .rasterizationSamples = samples,
155 .sampleShadingEnable = false,
156 .pSampleMask = NULL,
157 .alphaToCoverageEnable = false,
158 .alphaToOneEnable = false,
159 },
160 .pDepthStencilState = ds_state,
161 .pColorBlendState = cb_state,
162 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
163 /* The meta clear pipeline declares all state as dynamic.
164 * As a consequence, vkCmdBindPipeline writes no dynamic state
165 * to the cmd buffer. Therefore, at the end of the meta clear,
166 * we need only restore dynamic state was vkCmdSet.
167 */
168 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
169 .dynamicStateCount = 8,
170 .pDynamicStates = (VkDynamicState[]) {
171 /* Everything except stencil write mask */
172 VK_DYNAMIC_STATE_VIEWPORT,
173 VK_DYNAMIC_STATE_SCISSOR,
174 VK_DYNAMIC_STATE_LINE_WIDTH,
175 VK_DYNAMIC_STATE_DEPTH_BIAS,
176 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
177 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
178 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
179 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
180 },
181 },
182 .layout = layout,
183 .flags = 0,
184 .renderPass = radv_render_pass_to_handle(render_pass),
185 .subpass = 0,
186 },
187 extra,
188 alloc,
189 pipeline);
190
191 ralloc_free(vs_nir);
192 ralloc_free(fs_nir);
193
194 return result;
195 }
196
197 static VkResult
198 create_color_renderpass(struct radv_device *device,
199 VkFormat vk_format,
200 uint32_t samples,
201 VkRenderPass *pass)
202 {
203 return radv_CreateRenderPass(radv_device_to_handle(device),
204 &(VkRenderPassCreateInfo) {
205 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
206 .attachmentCount = 1,
207 .pAttachments = &(VkAttachmentDescription) {
208 .format = vk_format,
209 .samples = samples,
210 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
211 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
212 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
213 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
214 },
215 .subpassCount = 1,
216 .pSubpasses = &(VkSubpassDescription) {
217 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
218 .inputAttachmentCount = 0,
219 .colorAttachmentCount = 1,
220 .pColorAttachments = &(VkAttachmentReference) {
221 .attachment = 0,
222 .layout = VK_IMAGE_LAYOUT_GENERAL,
223 },
224 .pResolveAttachments = NULL,
225 .pDepthStencilAttachment = &(VkAttachmentReference) {
226 .attachment = VK_ATTACHMENT_UNUSED,
227 .layout = VK_IMAGE_LAYOUT_GENERAL,
228 },
229 .preserveAttachmentCount = 1,
230 .pPreserveAttachments = (uint32_t[]) { 0 },
231 },
232 .dependencyCount = 0,
233 }, &device->meta_state.alloc, pass);
234 }
235
236 static VkResult
237 create_color_pipeline(struct radv_device *device,
238 uint32_t samples,
239 uint32_t frag_output,
240 VkPipeline *pipeline,
241 VkRenderPass pass)
242 {
243 struct nir_shader *vs_nir;
244 struct nir_shader *fs_nir;
245 VkResult result;
246 build_color_shaders(&vs_nir, &fs_nir, frag_output);
247
248 const VkPipelineVertexInputStateCreateInfo vi_state = {
249 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
250 .vertexBindingDescriptionCount = 0,
251 .vertexAttributeDescriptionCount = 0,
252 };
253
254 const VkPipelineDepthStencilStateCreateInfo ds_state = {
255 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
256 .depthTestEnable = false,
257 .depthWriteEnable = false,
258 .depthBoundsTestEnable = false,
259 .stencilTestEnable = false,
260 };
261
262 VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
263 blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
264 .blendEnable = false,
265 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
266 VK_COLOR_COMPONENT_R_BIT |
267 VK_COLOR_COMPONENT_G_BIT |
268 VK_COLOR_COMPONENT_B_BIT,
269 };
270
271 const VkPipelineColorBlendStateCreateInfo cb_state = {
272 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
273 .logicOpEnable = false,
274 .attachmentCount = MAX_RTS,
275 .pAttachments = blend_attachment_state
276 };
277
278
279 struct radv_graphics_pipeline_create_info extra = {
280 .use_rectlist = true,
281 };
282 result = create_pipeline(device, radv_render_pass_from_handle(pass),
283 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
284 device->meta_state.clear_color_p_layout,
285 &extra, &device->meta_state.alloc, pipeline);
286
287 return result;
288 }
289
290 void
291 radv_device_finish_meta_clear_state(struct radv_device *device)
292 {
293 struct radv_meta_state *state = &device->meta_state;
294
295 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
296 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
297 radv_DestroyPipeline(radv_device_to_handle(device),
298 state->clear[i].color_pipelines[j],
299 &device->meta_state.alloc);
300 radv_DestroyRenderPass(radv_device_to_handle(device),
301 state->clear[i].render_pass[j],
302 &device->meta_state.alloc);
303 }
304
305 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
306 radv_DestroyPipeline(radv_device_to_handle(device),
307 state->clear[i].depth_only_pipeline[j],
308 &device->meta_state.alloc);
309 radv_DestroyPipeline(radv_device_to_handle(device),
310 state->clear[i].stencil_only_pipeline[j],
311 &device->meta_state.alloc);
312 radv_DestroyPipeline(radv_device_to_handle(device),
313 state->clear[i].depthstencil_pipeline[j],
314 &device->meta_state.alloc);
315 }
316 radv_DestroyRenderPass(radv_device_to_handle(device),
317 state->clear[i].depthstencil_rp,
318 &device->meta_state.alloc);
319 }
320 radv_DestroyPipelineLayout(radv_device_to_handle(device),
321 state->clear_color_p_layout,
322 &state->alloc);
323 radv_DestroyPipelineLayout(radv_device_to_handle(device),
324 state->clear_depth_p_layout,
325 &state->alloc);
326 }
327
328 static void
329 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
330 const VkClearAttachment *clear_att,
331 const VkClearRect *clear_rect,
332 uint32_t view_mask)
333 {
334 struct radv_device *device = cmd_buffer->device;
335 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
336 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
337 const uint32_t subpass_att = clear_att->colorAttachment;
338 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
339 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
340 const uint32_t samples = iview->image->info.samples;
341 const uint32_t samples_log2 = ffs(samples) - 1;
342 unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
343 VkClearColorValue clear_value = clear_att->clearValue.color;
344 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
345 VkPipeline pipeline;
346
347 if (fs_key == -1) {
348 radv_finishme("color clears incomplete");
349 return;
350 }
351
352 pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
353 if (!pipeline) {
354 radv_finishme("color clears incomplete");
355 return;
356 }
357 assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
358 assert(pipeline);
359 assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
360 assert(clear_att->colorAttachment < subpass->color_count);
361
362 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
363 device->meta_state.clear_color_p_layout,
364 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
365 &clear_value);
366
367 struct radv_subpass clear_subpass = {
368 .color_count = 1,
369 .color_attachments = (VkAttachmentReference[]) {
370 subpass->color_attachments[clear_att->colorAttachment]
371 },
372 .depth_stencil_attachment = (VkAttachmentReference) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
373 };
374
375 radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
376
377 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
378 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
379 pipeline);
380 }
381
382 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
383 .x = clear_rect->rect.offset.x,
384 .y = clear_rect->rect.offset.y,
385 .width = clear_rect->rect.extent.width,
386 .height = clear_rect->rect.extent.height,
387 .minDepth = 0.0f,
388 .maxDepth = 1.0f
389 });
390
391 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
392
393 if (view_mask) {
394 unsigned i;
395 for_each_bit(i, view_mask)
396 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
397 } else {
398 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
399 }
400
401 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
402 }
403
404
405 static void
406 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
407 {
408 nir_builder vs_b, fs_b;
409
410 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
411 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
412
413 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
414 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
415 const struct glsl_type *position_out_type = glsl_vec4_type();
416
417 nir_variable *vs_out_pos =
418 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
419 "gl_Position");
420 vs_out_pos->data.location = VARYING_SLOT_POS;
421
422 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
423 nir_intrinsic_set_base(in_color_load, 0);
424 nir_intrinsic_set_range(in_color_load, 4);
425 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
426 in_color_load->num_components = 1;
427 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
428 nir_builder_instr_insert(&vs_b, &in_color_load->instr);
429
430 nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
431 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
432
433 const struct glsl_type *layer_type = glsl_int_type();
434 nir_variable *vs_out_layer =
435 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
436 "v_layer");
437 vs_out_layer->data.location = VARYING_SLOT_LAYER;
438 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
439 nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
440 nir_ssa_def *base_instance = nir_load_system_value(&vs_b, nir_intrinsic_load_base_instance, 0);
441
442 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
443 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
444
445 *out_vs = vs_b.shader;
446 *out_fs = fs_b.shader;
447 }
448
449 static VkResult
450 create_depthstencil_renderpass(struct radv_device *device,
451 uint32_t samples,
452 VkRenderPass *render_pass)
453 {
454 return radv_CreateRenderPass(radv_device_to_handle(device),
455 &(VkRenderPassCreateInfo) {
456 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
457 .attachmentCount = 1,
458 .pAttachments = &(VkAttachmentDescription) {
459 .format = VK_FORMAT_D32_SFLOAT_S8_UINT,
460 .samples = samples,
461 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
462 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
463 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
464 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
465 },
466 .subpassCount = 1,
467 .pSubpasses = &(VkSubpassDescription) {
468 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
469 .inputAttachmentCount = 0,
470 .colorAttachmentCount = 0,
471 .pColorAttachments = NULL,
472 .pResolveAttachments = NULL,
473 .pDepthStencilAttachment = &(VkAttachmentReference) {
474 .attachment = 0,
475 .layout = VK_IMAGE_LAYOUT_GENERAL,
476 },
477 .preserveAttachmentCount = 1,
478 .pPreserveAttachments = (uint32_t[]) { 0 },
479 },
480 .dependencyCount = 0,
481 }, &device->meta_state.alloc, render_pass);
482 }
483
484 static VkResult
485 create_depthstencil_pipeline(struct radv_device *device,
486 VkImageAspectFlags aspects,
487 uint32_t samples,
488 int index,
489 VkPipeline *pipeline,
490 VkRenderPass render_pass)
491 {
492 struct nir_shader *vs_nir, *fs_nir;
493 VkResult result;
494 build_depthstencil_shader(&vs_nir, &fs_nir);
495
496 const VkPipelineVertexInputStateCreateInfo vi_state = {
497 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
498 .vertexBindingDescriptionCount = 0,
499 .vertexAttributeDescriptionCount = 0,
500 };
501
502 const VkPipelineDepthStencilStateCreateInfo ds_state = {
503 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
504 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
505 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
506 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
507 .depthBoundsTestEnable = false,
508 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
509 .front = {
510 .passOp = VK_STENCIL_OP_REPLACE,
511 .compareOp = VK_COMPARE_OP_ALWAYS,
512 .writeMask = UINT32_MAX,
513 .reference = 0, /* dynamic */
514 },
515 .back = { 0 /* dont care */ },
516 };
517
518 const VkPipelineColorBlendStateCreateInfo cb_state = {
519 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
520 .logicOpEnable = false,
521 .attachmentCount = 0,
522 .pAttachments = NULL,
523 };
524
525 struct radv_graphics_pipeline_create_info extra = {
526 .use_rectlist = true,
527 };
528
529 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
530 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
531 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
532 }
533 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
534 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
535 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
536 }
537 result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
538 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
539 device->meta_state.clear_depth_p_layout,
540 &extra, &device->meta_state.alloc, pipeline);
541 return result;
542 }
543
544 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
545 const struct radv_image_view *iview,
546 VkImageLayout layout,
547 const VkClearRect *clear_rect)
548 {
549 uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
550 cmd_buffer->queue_family_index,
551 cmd_buffer->queue_family_index);
552 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
553 clear_rect->rect.extent.width != iview->extent.width ||
554 clear_rect->rect.extent.height != iview->extent.height)
555 return false;
556 if (iview->image->surface.htile_size &&
557 iview->base_mip == 0 &&
558 iview->base_layer == 0 &&
559 radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
560 !radv_image_extent_compare(iview->image, &iview->extent))
561 return true;
562 return false;
563 }
564
565 static VkPipeline
566 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
567 struct radv_meta_state *meta_state,
568 const struct radv_image_view *iview,
569 int samples_log2,
570 VkImageAspectFlags aspects,
571 VkImageLayout layout,
572 const VkClearRect *clear_rect,
573 VkClearDepthStencilValue clear_value)
574 {
575 bool fast = depth_view_can_fast_clear(cmd_buffer, iview, layout, clear_rect);
576 int index = DEPTH_CLEAR_SLOW;
577
578 if (fast) {
579 /* we don't know the previous clear values, so we always have
580 * the NO_EXPCLEAR path */
581 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
582 }
583
584 switch (aspects) {
585 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
586 return meta_state->clear[samples_log2].depthstencil_pipeline[index];
587 case VK_IMAGE_ASPECT_DEPTH_BIT:
588 return meta_state->clear[samples_log2].depth_only_pipeline[index];
589 case VK_IMAGE_ASPECT_STENCIL_BIT:
590 return meta_state->clear[samples_log2].stencil_only_pipeline[index];
591 }
592 unreachable("expected depth or stencil aspect");
593 }
594
595 static void
596 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
597 const VkClearAttachment *clear_att,
598 const VkClearRect *clear_rect)
599 {
600 struct radv_device *device = cmd_buffer->device;
601 struct radv_meta_state *meta_state = &device->meta_state;
602 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
603 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
604 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
605 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
606 VkImageAspectFlags aspects = clear_att->aspectMask;
607 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
608 const uint32_t samples = iview->image->info.samples;
609 const uint32_t samples_log2 = ffs(samples) - 1;
610 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
611
612 assert(aspects == VK_IMAGE_ASPECT_DEPTH_BIT ||
613 aspects == VK_IMAGE_ASPECT_STENCIL_BIT ||
614 aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
615 VK_IMAGE_ASPECT_STENCIL_BIT));
616 assert(pass_att != VK_ATTACHMENT_UNUSED);
617
618 if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
619 clear_value.depth = 1.0f;
620
621 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
622 device->meta_state.clear_depth_p_layout,
623 VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
624 &clear_value.depth);
625
626 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
627 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
628 clear_value.stencil);
629 }
630
631 VkPipeline pipeline = pick_depthstencil_pipeline(cmd_buffer,
632 meta_state,
633 iview,
634 samples_log2,
635 aspects,
636 subpass->depth_stencil_attachment.layout,
637 clear_rect,
638 clear_value);
639
640 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
641 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
642 pipeline);
643 }
644
645 if (depth_view_can_fast_clear(cmd_buffer, iview, subpass->depth_stencil_attachment.layout, clear_rect))
646 radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
647
648 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
649 .x = clear_rect->rect.offset.x,
650 .y = clear_rect->rect.offset.y,
651 .width = clear_rect->rect.extent.width,
652 .height = clear_rect->rect.extent.height,
653 .minDepth = 0.0f,
654 .maxDepth = 1.0f
655 });
656
657 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
658
659 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
660 }
661
662 static bool
663 emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
664 const VkClearAttachment *clear_att,
665 const VkClearRect *clear_rect,
666 enum radv_cmd_flush_bits *pre_flush,
667 enum radv_cmd_flush_bits *post_flush)
668 {
669 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
670 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
671 VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
672 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
673 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
674 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
675 VkImageAspectFlags aspects = clear_att->aspectMask;
676 uint32_t clear_word;
677
678 if (!iview->image->surface.htile_size)
679 return false;
680
681 if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
682 return false;
683
684 if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
685 goto fail;
686
687 /* don't fast clear 3D */
688 if (iview->image->type == VK_IMAGE_TYPE_3D)
689 goto fail;
690
691 /* all layers are bound */
692 if (iview->base_layer > 0)
693 goto fail;
694 if (iview->image->info.array_size != iview->layer_count)
695 goto fail;
696
697 if (iview->image->info.levels > 1)
698 goto fail;
699
700 if (!radv_image_extent_compare(iview->image, &iview->extent))
701 goto fail;
702
703 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
704 clear_rect->rect.extent.width != iview->image->info.width ||
705 clear_rect->rect.extent.height != iview->image->info.height)
706 goto fail;
707
708 if (clear_rect->baseArrayLayer != 0)
709 goto fail;
710 if (clear_rect->layerCount != iview->image->info.array_size)
711 goto fail;
712
713 if ((clear_value.depth != 0.0 && clear_value.depth != 1.0) || !(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
714 goto fail;
715
716 if (vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) {
717 if (clear_value.stencil != 0 || !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))
718 goto fail;
719 clear_word = clear_value.depth ? 0xfffc0000 : 0;
720 } else
721 clear_word = clear_value.depth ? 0xfffffff0 : 0;
722
723 if (pre_flush) {
724 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
725 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
726 *pre_flush |= cmd_buffer->state.flush_bits;
727 } else
728 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
729 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
730
731 radv_fill_buffer(cmd_buffer, iview->image->bo,
732 iview->image->offset + iview->image->htile_offset,
733 iview->image->surface.htile_size, clear_word);
734
735
736 radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
737 if (post_flush)
738 *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
739 RADV_CMD_FLAG_INV_VMEM_L1 |
740 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
741 else
742 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
743 RADV_CMD_FLAG_INV_VMEM_L1 |
744 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
745 return true;
746 fail:
747 return false;
748 }
749
750 static VkFormat pipeline_formats[] = {
751 VK_FORMAT_R8G8B8A8_UNORM,
752 VK_FORMAT_R8G8B8A8_UINT,
753 VK_FORMAT_R8G8B8A8_SINT,
754 VK_FORMAT_A2R10G10B10_UINT_PACK32,
755 VK_FORMAT_A2R10G10B10_SINT_PACK32,
756 VK_FORMAT_R16G16B16A16_UNORM,
757 VK_FORMAT_R16G16B16A16_SNORM,
758 VK_FORMAT_R16G16B16A16_UINT,
759 VK_FORMAT_R16G16B16A16_SINT,
760 VK_FORMAT_R32_SFLOAT,
761 VK_FORMAT_R32G32_SFLOAT,
762 VK_FORMAT_R32G32B32A32_SFLOAT
763 };
764
765 VkResult
766 radv_device_init_meta_clear_state(struct radv_device *device)
767 {
768 VkResult res;
769 struct radv_meta_state *state = &device->meta_state;
770
771 VkPipelineLayoutCreateInfo pl_color_create_info = {
772 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
773 .setLayoutCount = 0,
774 .pushConstantRangeCount = 1,
775 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
776 };
777
778 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
779 &pl_color_create_info,
780 &device->meta_state.alloc,
781 &device->meta_state.clear_color_p_layout);
782 if (res != VK_SUCCESS)
783 goto fail;
784
785 VkPipelineLayoutCreateInfo pl_depth_create_info = {
786 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
787 .setLayoutCount = 0,
788 .pushConstantRangeCount = 1,
789 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
790 };
791
792 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
793 &pl_depth_create_info,
794 &device->meta_state.alloc,
795 &device->meta_state.clear_depth_p_layout);
796 if (res != VK_SUCCESS)
797 goto fail;
798
799 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
800 uint32_t samples = 1 << i;
801 for (uint32_t j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
802 VkFormat format = pipeline_formats[j];
803 unsigned fs_key = radv_format_meta_fs_key(format);
804 assert(!state->clear[i].color_pipelines[fs_key]);
805
806 res = create_color_renderpass(device, format, samples,
807 &state->clear[i].render_pass[fs_key]);
808 if (res != VK_SUCCESS)
809 goto fail;
810
811 res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
812 state->clear[i].render_pass[fs_key]);
813 if (res != VK_SUCCESS)
814 goto fail;
815
816 }
817
818 res = create_depthstencil_renderpass(device,
819 samples,
820 &state->clear[i].depthstencil_rp);
821 if (res != VK_SUCCESS)
822 goto fail;
823
824 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
825 res = create_depthstencil_pipeline(device,
826 VK_IMAGE_ASPECT_DEPTH_BIT,
827 samples,
828 j,
829 &state->clear[i].depth_only_pipeline[j],
830 state->clear[i].depthstencil_rp);
831 if (res != VK_SUCCESS)
832 goto fail;
833
834 res = create_depthstencil_pipeline(device,
835 VK_IMAGE_ASPECT_STENCIL_BIT,
836 samples,
837 j,
838 &state->clear[i].stencil_only_pipeline[j],
839 state->clear[i].depthstencil_rp);
840 if (res != VK_SUCCESS)
841 goto fail;
842
843 res = create_depthstencil_pipeline(device,
844 VK_IMAGE_ASPECT_DEPTH_BIT |
845 VK_IMAGE_ASPECT_STENCIL_BIT,
846 samples,
847 j,
848 &state->clear[i].depthstencil_pipeline[j],
849 state->clear[i].depthstencil_rp);
850 if (res != VK_SUCCESS)
851 goto fail;
852 }
853 }
854 return VK_SUCCESS;
855
856 fail:
857 radv_device_finish_meta_clear_state(device);
858 return res;
859 }
860
861 static void vi_get_fast_clear_parameters(VkFormat format,
862 const VkClearColorValue *clear_value,
863 uint32_t* reset_value,
864 bool *can_avoid_fast_clear_elim)
865 {
866 bool values[4] = {};
867 int extra_channel;
868 bool main_value = false;
869 bool extra_value = false;
870 int i;
871 *can_avoid_fast_clear_elim = false;
872
873 *reset_value = 0x20202020U;
874
875 const struct vk_format_description *desc = vk_format_description(format);
876 if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
877 format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
878 format == VK_FORMAT_B5G6R5_UNORM_PACK16)
879 extra_channel = -1;
880 else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
881 if (radv_translate_colorswap(format, false) <= 1)
882 extra_channel = desc->nr_channels - 1;
883 else
884 extra_channel = 0;
885 } else
886 return;
887
888 for (i = 0; i < 4; i++) {
889 int index = desc->swizzle[i] - VK_SWIZZLE_X;
890 if (desc->swizzle[i] < VK_SWIZZLE_X ||
891 desc->swizzle[i] > VK_SWIZZLE_W)
892 continue;
893
894 if (desc->channel[i].pure_integer &&
895 desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
896 /* Use the maximum value for clamping the clear color. */
897 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
898
899 values[i] = clear_value->int32[i] != 0;
900 if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
901 return;
902 } else if (desc->channel[i].pure_integer &&
903 desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
904 /* Use the maximum value for clamping the clear color. */
905 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
906
907 values[i] = clear_value->uint32[i] != 0U;
908 if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
909 return;
910 } else {
911 values[i] = clear_value->float32[i] != 0.0F;
912 if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
913 return;
914 }
915
916 if (index == extra_channel)
917 extra_value = values[i];
918 else
919 main_value = values[i];
920 }
921
922 for (int i = 0; i < 4; ++i)
923 if (values[i] != main_value &&
924 desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
925 desc->swizzle[i] >= VK_SWIZZLE_X &&
926 desc->swizzle[i] <= VK_SWIZZLE_W)
927 return;
928
929 *can_avoid_fast_clear_elim = true;
930 if (main_value)
931 *reset_value |= 0x80808080U;
932
933 if (extra_value)
934 *reset_value |= 0x40404040U;
935 return;
936 }
937
938 static bool
939 emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
940 const VkClearAttachment *clear_att,
941 const VkClearRect *clear_rect,
942 enum radv_cmd_flush_bits *pre_flush,
943 enum radv_cmd_flush_bits *post_flush,
944 uint32_t view_mask)
945 {
946 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
947 const uint32_t subpass_att = clear_att->colorAttachment;
948 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
949 VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
950 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
951 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
952 VkClearColorValue clear_value = clear_att->clearValue.color;
953 uint32_t clear_color[2];
954 bool ret;
955
956 if (!iview->image->cmask.size && !iview->image->surface.dcc_size)
957 return false;
958
959 if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
960 return false;
961
962 if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
963 goto fail;
964
965 /* don't fast clear 3D */
966 if (iview->image->type == VK_IMAGE_TYPE_3D)
967 goto fail;
968
969 /* all layers are bound */
970 if (iview->base_layer > 0)
971 goto fail;
972 if (iview->image->info.array_size != iview->layer_count)
973 goto fail;
974
975 if (iview->image->info.levels > 1)
976 goto fail;
977
978 if (iview->image->surface.is_linear)
979 goto fail;
980 if (!radv_image_extent_compare(iview->image, &iview->extent))
981 goto fail;
982
983 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
984 clear_rect->rect.extent.width != iview->image->info.width ||
985 clear_rect->rect.extent.height != iview->image->info.height)
986 goto fail;
987
988 if (view_mask && (iview->image->info.array_size >= 32 ||
989 (1u << iview->image->info.array_size) - 1u != view_mask))
990 goto fail;
991 if (!view_mask && clear_rect->baseArrayLayer != 0)
992 goto fail;
993 if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
994 goto fail;
995
996 /* RB+ doesn't work with CMASK fast clear on Stoney. */
997 if (!iview->image->surface.dcc_size &&
998 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY)
999 goto fail;
1000
1001 /* DCC */
1002 ret = radv_format_pack_clear_color(iview->image->vk_format,
1003 clear_color, &clear_value);
1004 if (ret == false)
1005 goto fail;
1006
1007 if (pre_flush) {
1008 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1009 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
1010 *pre_flush |= cmd_buffer->state.flush_bits;
1011 } else
1012 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1013 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1014 /* clear cmask buffer */
1015 if (iview->image->surface.dcc_size) {
1016 uint32_t reset_value;
1017 bool can_avoid_fast_clear_elim;
1018 vi_get_fast_clear_parameters(iview->image->vk_format,
1019 &clear_value, &reset_value,
1020 &can_avoid_fast_clear_elim);
1021
1022 radv_fill_buffer(cmd_buffer, iview->image->bo,
1023 iview->image->offset + iview->image->dcc_offset,
1024 iview->image->surface.dcc_size, reset_value);
1025 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
1026 !can_avoid_fast_clear_elim);
1027 } else {
1028
1029 if (iview->image->surface.bpe > 8) {
1030 /* 128 bit formats not supported */
1031 return false;
1032 }
1033 radv_fill_buffer(cmd_buffer, iview->image->bo,
1034 iview->image->offset + iview->image->cmask.offset,
1035 iview->image->cmask.size, 0);
1036 }
1037
1038 if (post_flush)
1039 *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1040 RADV_CMD_FLAG_INV_VMEM_L1 |
1041 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1042 else
1043 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1044 RADV_CMD_FLAG_INV_VMEM_L1 |
1045 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1046
1047 radv_set_color_clear_regs(cmd_buffer, iview->image, subpass_att, clear_color);
1048
1049 return true;
1050 fail:
1051 return false;
1052 }
1053
1054 /**
1055 * The parameters mean that same as those in vkCmdClearAttachments.
1056 */
1057 static void
1058 emit_clear(struct radv_cmd_buffer *cmd_buffer,
1059 const VkClearAttachment *clear_att,
1060 const VkClearRect *clear_rect,
1061 enum radv_cmd_flush_bits *pre_flush,
1062 enum radv_cmd_flush_bits *post_flush,
1063 uint32_t view_mask)
1064 {
1065 if (clear_att->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1066 if (!emit_fast_color_clear(cmd_buffer, clear_att, clear_rect,
1067 pre_flush, post_flush, view_mask))
1068 emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask);
1069 } else {
1070 assert(clear_att->aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT |
1071 VK_IMAGE_ASPECT_STENCIL_BIT));
1072 if (!emit_fast_htile_clear(cmd_buffer, clear_att, clear_rect,
1073 pre_flush, post_flush))
1074 emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
1075 }
1076 }
1077
1078 static inline bool
1079 radv_attachment_needs_clear(struct radv_cmd_state *cmd_state, uint32_t a)
1080 {
1081 uint32_t view_mask = cmd_state->subpass->view_mask;
1082 return (a != VK_ATTACHMENT_UNUSED &&
1083 cmd_state->attachments[a].pending_clear_aspects &&
1084 (!view_mask || (view_mask & ~cmd_state->attachments[a].cleared_views)));
1085 }
1086
1087 static bool
1088 radv_subpass_needs_clear(struct radv_cmd_buffer *cmd_buffer)
1089 {
1090 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1091 uint32_t a;
1092
1093 if (!cmd_state->subpass)
1094 return false;
1095
1096 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1097 a = cmd_state->subpass->color_attachments[i].attachment;
1098 if (radv_attachment_needs_clear(cmd_state, a))
1099 return true;
1100 }
1101
1102 a = cmd_state->subpass->depth_stencil_attachment.attachment;
1103 return radv_attachment_needs_clear(cmd_state, a);
1104 }
1105
1106 static void
1107 radv_subpass_clear_attachment(struct radv_cmd_buffer *cmd_buffer,
1108 struct radv_attachment_state *attachment,
1109 const VkClearAttachment *clear_att,
1110 enum radv_cmd_flush_bits *pre_flush,
1111 enum radv_cmd_flush_bits *post_flush)
1112 {
1113 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1114 uint32_t view_mask = cmd_state->subpass->view_mask;
1115
1116 VkClearRect clear_rect = {
1117 .rect = cmd_state->render_area,
1118 .baseArrayLayer = 0,
1119 .layerCount = cmd_state->framebuffer->layers,
1120 };
1121
1122 emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush,
1123 view_mask & ~attachment->cleared_views);
1124 if (view_mask)
1125 attachment->cleared_views |= view_mask;
1126 else
1127 attachment->pending_clear_aspects = 0;
1128 }
1129
1130 /**
1131 * Emit any pending attachment clears for the current subpass.
1132 *
1133 * @see radv_attachment_state::pending_clear_aspects
1134 */
1135 void
1136 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1137 {
1138 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1139 struct radv_meta_saved_state saved_state;
1140 enum radv_cmd_flush_bits pre_flush = 0;
1141 enum radv_cmd_flush_bits post_flush = 0;
1142
1143 if (!radv_subpass_needs_clear(cmd_buffer))
1144 return;
1145
1146 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
1147
1148 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1149 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1150
1151 if (!radv_attachment_needs_clear(cmd_state, a))
1152 continue;
1153
1154 assert(cmd_state->attachments[a].pending_clear_aspects ==
1155 VK_IMAGE_ASPECT_COLOR_BIT);
1156
1157 VkClearAttachment clear_att = {
1158 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1159 .colorAttachment = i, /* Use attachment index relative to subpass */
1160 .clearValue = cmd_state->attachments[a].clear_value,
1161 };
1162
1163 radv_subpass_clear_attachment(cmd_buffer,
1164 &cmd_state->attachments[a],
1165 &clear_att, &pre_flush,
1166 &post_flush);
1167 }
1168
1169 uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1170 if (radv_attachment_needs_clear(cmd_state, ds)) {
1171 VkClearAttachment clear_att = {
1172 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1173 .clearValue = cmd_state->attachments[ds].clear_value,
1174 };
1175
1176 radv_subpass_clear_attachment(cmd_buffer,
1177 &cmd_state->attachments[ds],
1178 &clear_att, &pre_flush,
1179 &post_flush);
1180 }
1181
1182 radv_meta_restore(&saved_state, cmd_buffer);
1183 cmd_buffer->state.flush_bits |= post_flush;
1184 }
1185
1186 static void
1187 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1188 struct radv_image *image,
1189 VkImageLayout image_layout,
1190 const VkImageSubresourceRange *range,
1191 VkFormat format, int level, int layer,
1192 const VkClearValue *clear_val)
1193 {
1194 VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1195 struct radv_image_view iview;
1196 uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level);
1197 uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level);
1198
1199 radv_image_view_init(&iview, cmd_buffer->device,
1200 &(VkImageViewCreateInfo) {
1201 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1202 .image = radv_image_to_handle(image),
1203 .viewType = radv_meta_get_view_type(image),
1204 .format = format,
1205 .subresourceRange = {
1206 .aspectMask = range->aspectMask,
1207 .baseMipLevel = range->baseMipLevel + level,
1208 .levelCount = 1,
1209 .baseArrayLayer = range->baseArrayLayer + layer,
1210 .layerCount = 1
1211 },
1212 });
1213
1214 VkFramebuffer fb;
1215 radv_CreateFramebuffer(device_h,
1216 &(VkFramebufferCreateInfo) {
1217 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1218 .attachmentCount = 1,
1219 .pAttachments = (VkImageView[]) {
1220 radv_image_view_to_handle(&iview),
1221 },
1222 .width = width,
1223 .height = height,
1224 .layers = 1
1225 },
1226 &cmd_buffer->pool->alloc,
1227 &fb);
1228
1229 VkAttachmentDescription att_desc = {
1230 .format = iview.vk_format,
1231 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1232 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1233 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1234 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1235 .initialLayout = image_layout,
1236 .finalLayout = image_layout,
1237 };
1238
1239 VkSubpassDescription subpass_desc = {
1240 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1241 .inputAttachmentCount = 0,
1242 .colorAttachmentCount = 0,
1243 .pColorAttachments = NULL,
1244 .pResolveAttachments = NULL,
1245 .pDepthStencilAttachment = NULL,
1246 .preserveAttachmentCount = 0,
1247 .pPreserveAttachments = NULL,
1248 };
1249
1250 const VkAttachmentReference att_ref = {
1251 .attachment = 0,
1252 .layout = image_layout,
1253 };
1254
1255 if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1256 subpass_desc.colorAttachmentCount = 1;
1257 subpass_desc.pColorAttachments = &att_ref;
1258 } else {
1259 subpass_desc.pDepthStencilAttachment = &att_ref;
1260 }
1261
1262 VkRenderPass pass;
1263 radv_CreateRenderPass(device_h,
1264 &(VkRenderPassCreateInfo) {
1265 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1266 .attachmentCount = 1,
1267 .pAttachments = &att_desc,
1268 .subpassCount = 1,
1269 .pSubpasses = &subpass_desc,
1270 },
1271 &cmd_buffer->pool->alloc,
1272 &pass);
1273
1274 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1275 &(VkRenderPassBeginInfo) {
1276 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1277 .renderArea = {
1278 .offset = { 0, 0, },
1279 .extent = {
1280 .width = width,
1281 .height = height,
1282 },
1283 },
1284 .renderPass = pass,
1285 .framebuffer = fb,
1286 .clearValueCount = 0,
1287 .pClearValues = NULL,
1288 },
1289 VK_SUBPASS_CONTENTS_INLINE);
1290
1291 VkClearAttachment clear_att = {
1292 .aspectMask = range->aspectMask,
1293 .colorAttachment = 0,
1294 .clearValue = *clear_val,
1295 };
1296
1297 VkClearRect clear_rect = {
1298 .rect = {
1299 .offset = { 0, 0 },
1300 .extent = { width, height },
1301 },
1302 .baseArrayLayer = range->baseArrayLayer,
1303 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1304 };
1305
1306 emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0);
1307
1308 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1309 radv_DestroyRenderPass(device_h, pass,
1310 &cmd_buffer->pool->alloc);
1311 radv_DestroyFramebuffer(device_h, fb,
1312 &cmd_buffer->pool->alloc);
1313 }
1314 static void
1315 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
1316 struct radv_image *image,
1317 VkImageLayout image_layout,
1318 const VkClearValue *clear_value,
1319 uint32_t range_count,
1320 const VkImageSubresourceRange *ranges,
1321 bool cs)
1322 {
1323 VkFormat format = image->vk_format;
1324 VkClearValue internal_clear_value = *clear_value;
1325
1326 if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
1327 uint32_t value;
1328 format = VK_FORMAT_R32_UINT;
1329 value = float3_to_rgb9e5(clear_value->color.float32);
1330 internal_clear_value.color.uint32[0] = value;
1331 }
1332
1333 if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
1334 uint8_t r, g;
1335 format = VK_FORMAT_R8_UINT;
1336 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
1337 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
1338 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
1339 }
1340
1341 for (uint32_t r = 0; r < range_count; r++) {
1342 const VkImageSubresourceRange *range = &ranges[r];
1343 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
1344 const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
1345 radv_minify(image->info.depth, range->baseMipLevel + l) :
1346 radv_get_layerCount(image, range);
1347 for (uint32_t s = 0; s < layer_count; ++s) {
1348
1349 if (cs) {
1350 struct radv_meta_blit2d_surf surf;
1351 surf.format = format;
1352 surf.image = image;
1353 surf.level = range->baseMipLevel + l;
1354 surf.layer = range->baseArrayLayer + s;
1355 surf.aspect_mask = range->aspectMask;
1356 radv_meta_clear_image_cs(cmd_buffer, &surf,
1357 &internal_clear_value.color);
1358 } else {
1359 radv_clear_image_layer(cmd_buffer, image, image_layout,
1360 range, format, l, s, &internal_clear_value);
1361 }
1362 }
1363 }
1364 }
1365 }
1366
1367 union meta_saved_state {
1368 struct radv_meta_saved_state gfx;
1369 struct radv_meta_saved_compute_state compute;
1370 };
1371
1372 void radv_CmdClearColorImage(
1373 VkCommandBuffer commandBuffer,
1374 VkImage image_h,
1375 VkImageLayout imageLayout,
1376 const VkClearColorValue* pColor,
1377 uint32_t rangeCount,
1378 const VkImageSubresourceRange* pRanges)
1379 {
1380 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1381 RADV_FROM_HANDLE(radv_image, image, image_h);
1382 union meta_saved_state saved_state;
1383 bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1384
1385 if (cs)
1386 radv_meta_save_compute(&saved_state.compute, cmd_buffer, 16);
1387 else
1388 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state.gfx, cmd_buffer);
1389
1390 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1391 (const VkClearValue *) pColor,
1392 rangeCount, pRanges, cs);
1393
1394 if (cs)
1395 radv_meta_restore_compute(&saved_state.compute, cmd_buffer);
1396 else
1397 radv_meta_restore(&saved_state.gfx, cmd_buffer);
1398 }
1399
1400 void radv_CmdClearDepthStencilImage(
1401 VkCommandBuffer commandBuffer,
1402 VkImage image_h,
1403 VkImageLayout imageLayout,
1404 const VkClearDepthStencilValue* pDepthStencil,
1405 uint32_t rangeCount,
1406 const VkImageSubresourceRange* pRanges)
1407 {
1408 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1409 RADV_FROM_HANDLE(radv_image, image, image_h);
1410 struct radv_meta_saved_state saved_state;
1411
1412 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
1413
1414 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1415 (const VkClearValue *) pDepthStencil,
1416 rangeCount, pRanges, false);
1417
1418 radv_meta_restore(&saved_state, cmd_buffer);
1419 }
1420
1421 void radv_CmdClearAttachments(
1422 VkCommandBuffer commandBuffer,
1423 uint32_t attachmentCount,
1424 const VkClearAttachment* pAttachments,
1425 uint32_t rectCount,
1426 const VkClearRect* pRects)
1427 {
1428 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1429 struct radv_meta_saved_state saved_state;
1430 enum radv_cmd_flush_bits pre_flush = 0;
1431 enum radv_cmd_flush_bits post_flush = 0;
1432
1433 if (!cmd_buffer->state.subpass)
1434 return;
1435
1436 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
1437
1438 /* FINISHME: We can do better than this dumb loop. It thrashes too much
1439 * state.
1440 */
1441 for (uint32_t a = 0; a < attachmentCount; ++a) {
1442 for (uint32_t r = 0; r < rectCount; ++r) {
1443 emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush,
1444 cmd_buffer->state.subpass->view_mask);
1445 }
1446 }
1447
1448 radv_meta_restore(&saved_state, cmd_buffer);
1449 cmd_buffer->state.flush_bits |= post_flush;
1450 }