2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "radv_meta.h"
25 #include "radv_private.h"
26 #include "nir/nir_builder.h"
28 #include "util/format_rgb9e5.h"
29 #include "vk_format.h"
30 /** Vertex attributes for color clears. */
31 struct color_clear_vattrs
{
33 VkClearColorValue color
;
36 /** Vertex attributes for depthstencil clears. */
37 struct depthstencil_clear_vattrs
{
44 DEPTH_CLEAR_FAST_EXPCLEAR
,
45 DEPTH_CLEAR_FAST_NO_EXPCLEAR
49 build_color_shaders(struct nir_shader
**out_vs
,
50 struct nir_shader
**out_fs
,
56 nir_builder_init_simple_shader(&vs_b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
57 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
59 vs_b
.shader
->info
->name
= ralloc_strdup(vs_b
.shader
, "meta_clear_color_vs");
60 fs_b
.shader
->info
->name
= ralloc_strdup(fs_b
.shader
, "meta_clear_color_fs");
62 const struct glsl_type
*position_type
= glsl_vec4_type();
63 const struct glsl_type
*color_type
= glsl_vec4_type();
65 nir_variable
*vs_in_pos
=
66 nir_variable_create(vs_b
.shader
, nir_var_shader_in
, position_type
,
68 vs_in_pos
->data
.location
= VERT_ATTRIB_GENERIC0
;
70 nir_variable
*vs_out_pos
=
71 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, position_type
,
73 vs_out_pos
->data
.location
= VARYING_SLOT_POS
;
75 nir_variable
*vs_in_color
=
76 nir_variable_create(vs_b
.shader
, nir_var_shader_in
, color_type
,
78 vs_in_color
->data
.location
= VERT_ATTRIB_GENERIC1
;
80 nir_variable
*vs_out_color
=
81 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, color_type
,
83 vs_out_color
->data
.location
= VARYING_SLOT_VAR0
;
84 vs_out_color
->data
.interpolation
= INTERP_MODE_FLAT
;
86 nir_variable
*fs_in_color
=
87 nir_variable_create(fs_b
.shader
, nir_var_shader_in
, color_type
,
89 fs_in_color
->data
.location
= vs_out_color
->data
.location
;
90 fs_in_color
->data
.interpolation
= vs_out_color
->data
.interpolation
;
92 nir_variable
*fs_out_color
=
93 nir_variable_create(fs_b
.shader
, nir_var_shader_out
, color_type
,
95 fs_out_color
->data
.location
= FRAG_RESULT_DATA0
+ frag_output
;
97 nir_copy_var(&vs_b
, vs_out_pos
, vs_in_pos
);
98 nir_copy_var(&vs_b
, vs_out_color
, vs_in_color
);
99 nir_copy_var(&fs_b
, fs_out_color
, fs_in_color
);
101 *out_vs
= vs_b
.shader
;
102 *out_fs
= fs_b
.shader
;
106 create_pipeline(struct radv_device
*device
,
107 struct radv_render_pass
*render_pass
,
109 struct nir_shader
*vs_nir
,
110 struct nir_shader
*fs_nir
,
111 const VkPipelineVertexInputStateCreateInfo
*vi_state
,
112 const VkPipelineDepthStencilStateCreateInfo
*ds_state
,
113 const VkPipelineColorBlendStateCreateInfo
*cb_state
,
114 const struct radv_graphics_pipeline_create_info
*extra
,
115 const VkAllocationCallbacks
*alloc
,
116 struct radv_pipeline
**pipeline
)
118 VkDevice device_h
= radv_device_to_handle(device
);
121 struct radv_shader_module vs_m
= { .nir
= vs_nir
};
122 struct radv_shader_module fs_m
= { .nir
= fs_nir
};
124 VkPipeline pipeline_h
= VK_NULL_HANDLE
;
125 result
= radv_graphics_pipeline_create(device_h
,
126 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
127 &(VkGraphicsPipelineCreateInfo
) {
128 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
129 .stageCount
= fs_nir
? 2 : 1,
130 .pStages
= (VkPipelineShaderStageCreateInfo
[]) {
132 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
133 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
134 .module
= radv_shader_module_to_handle(&vs_m
),
138 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
139 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
140 .module
= radv_shader_module_to_handle(&fs_m
),
144 .pVertexInputState
= vi_state
,
145 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
146 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
147 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
148 .primitiveRestartEnable
= false,
150 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
151 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
155 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
156 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
157 .rasterizerDiscardEnable
= false,
158 .polygonMode
= VK_POLYGON_MODE_FILL
,
159 .cullMode
= VK_CULL_MODE_NONE
,
160 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
,
161 .depthBiasEnable
= false,
163 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
164 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
165 .rasterizationSamples
= samples
,
166 .sampleShadingEnable
= false,
168 .alphaToCoverageEnable
= false,
169 .alphaToOneEnable
= false,
171 .pDepthStencilState
= ds_state
,
172 .pColorBlendState
= cb_state
,
173 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
174 /* The meta clear pipeline declares all state as dynamic.
175 * As a consequence, vkCmdBindPipeline writes no dynamic state
176 * to the cmd buffer. Therefore, at the end of the meta clear,
177 * we need only restore dynamic state was vkCmdSet.
179 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
180 .dynamicStateCount
= 6,
181 .pDynamicStates
= (VkDynamicState
[]) {
182 /* Everything except stencil write mask */
183 VK_DYNAMIC_STATE_LINE_WIDTH
,
184 VK_DYNAMIC_STATE_DEPTH_BIAS
,
185 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
186 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
187 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
188 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
192 .renderPass
= radv_render_pass_to_handle(render_pass
),
202 *pipeline
= radv_pipeline_from_handle(pipeline_h
);
208 create_color_pipeline(struct radv_device
*device
,
211 uint32_t frag_output
,
212 struct radv_pipeline
**pipeline
,
215 struct nir_shader
*vs_nir
;
216 struct nir_shader
*fs_nir
;
218 build_color_shaders(&vs_nir
, &fs_nir
, frag_output
);
220 const VkPipelineVertexInputStateCreateInfo vi_state
= {
221 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
222 .vertexBindingDescriptionCount
= 1,
223 .pVertexBindingDescriptions
= (VkVertexInputBindingDescription
[]) {
226 .stride
= sizeof(struct color_clear_vattrs
),
227 .inputRate
= VK_VERTEX_INPUT_RATE_VERTEX
230 .vertexAttributeDescriptionCount
= 2,
231 .pVertexAttributeDescriptions
= (VkVertexInputAttributeDescription
[]) {
236 .format
= VK_FORMAT_R32G32_SFLOAT
,
237 .offset
= offsetof(struct color_clear_vattrs
, position
),
243 .format
= VK_FORMAT_R32G32B32A32_SFLOAT
,
244 .offset
= offsetof(struct color_clear_vattrs
, color
),
249 const VkPipelineDepthStencilStateCreateInfo ds_state
= {
250 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
251 .depthTestEnable
= false,
252 .depthWriteEnable
= false,
253 .depthBoundsTestEnable
= false,
254 .stencilTestEnable
= false,
257 VkPipelineColorBlendAttachmentState blend_attachment_state
[MAX_RTS
] = { 0 };
258 blend_attachment_state
[frag_output
] = (VkPipelineColorBlendAttachmentState
) {
259 .blendEnable
= false,
260 .colorWriteMask
= VK_COLOR_COMPONENT_A_BIT
|
261 VK_COLOR_COMPONENT_R_BIT
|
262 VK_COLOR_COMPONENT_G_BIT
|
263 VK_COLOR_COMPONENT_B_BIT
,
266 const VkPipelineColorBlendStateCreateInfo cb_state
= {
267 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
268 .logicOpEnable
= false,
269 .attachmentCount
= MAX_RTS
,
270 .pAttachments
= blend_attachment_state
273 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
274 &(VkRenderPassCreateInfo
) {
275 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
276 .attachmentCount
= 1,
277 .pAttachments
= &(VkAttachmentDescription
) {
280 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
281 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
282 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
283 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
286 .pSubpasses
= &(VkSubpassDescription
) {
287 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
288 .inputAttachmentCount
= 0,
289 .colorAttachmentCount
= 1,
290 .pColorAttachments
= &(VkAttachmentReference
) {
292 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
294 .pResolveAttachments
= NULL
,
295 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
296 .attachment
= VK_ATTACHMENT_UNUSED
,
297 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
299 .preserveAttachmentCount
= 1,
300 .pPreserveAttachments
= (uint32_t[]) { 0 },
302 .dependencyCount
= 0,
303 }, &device
->meta_state
.alloc
, pass
);
305 if (result
!= VK_SUCCESS
)
307 struct radv_graphics_pipeline_create_info extra
= {
308 .use_rectlist
= true,
310 result
= create_pipeline(device
, radv_render_pass_from_handle(*pass
),
311 samples
, vs_nir
, fs_nir
, &vi_state
, &ds_state
, &cb_state
,
312 &extra
, &device
->meta_state
.alloc
, pipeline
);
318 destroy_pipeline(struct radv_device
*device
, struct radv_pipeline
*pipeline
)
323 radv_DestroyPipeline(radv_device_to_handle(device
),
324 radv_pipeline_to_handle(pipeline
),
325 &device
->meta_state
.alloc
);
330 destroy_render_pass(struct radv_device
*device
, VkRenderPass renderpass
)
332 radv_DestroyRenderPass(radv_device_to_handle(device
), renderpass
,
333 &device
->meta_state
.alloc
);
337 radv_device_finish_meta_clear_state(struct radv_device
*device
)
339 struct radv_meta_state
*state
= &device
->meta_state
;
341 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->clear
); ++i
) {
342 for (uint32_t j
= 0; j
< ARRAY_SIZE(state
->clear
[i
].color_pipelines
); ++j
) {
343 destroy_pipeline(device
, state
->clear
[i
].color_pipelines
[j
]);
344 destroy_render_pass(device
, state
->clear
[i
].render_pass
[j
]);
347 for (uint32_t j
= 0; j
< NUM_DEPTH_CLEAR_PIPELINES
; j
++) {
348 destroy_pipeline(device
, state
->clear
[i
].depth_only_pipeline
[j
]);
349 destroy_render_pass(device
, state
->clear
[i
].depth_only_rp
[j
]);
350 destroy_pipeline(device
, state
->clear
[i
].stencil_only_pipeline
[j
]);
351 destroy_render_pass(device
, state
->clear
[i
].stencil_only_rp
[j
]);
352 destroy_pipeline(device
, state
->clear
[i
].depthstencil_pipeline
[j
]);
353 destroy_render_pass(device
, state
->clear
[i
].depthstencil_rp
[j
]);
360 emit_color_clear(struct radv_cmd_buffer
*cmd_buffer
,
361 const VkClearAttachment
*clear_att
,
362 const VkClearRect
*clear_rect
)
364 struct radv_device
*device
= cmd_buffer
->device
;
365 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
366 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
367 const uint32_t subpass_att
= clear_att
->colorAttachment
;
368 const uint32_t pass_att
= subpass
->color_attachments
[subpass_att
].attachment
;
369 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
370 const uint32_t samples
= iview
->image
->samples
;
371 const uint32_t samples_log2
= ffs(samples
) - 1;
372 unsigned fs_key
= radv_format_meta_fs_key(iview
->vk_format
);
373 struct radv_pipeline
*pipeline
;
374 VkClearColorValue clear_value
= clear_att
->clearValue
.color
;
375 VkCommandBuffer cmd_buffer_h
= radv_cmd_buffer_to_handle(cmd_buffer
);
376 VkPipeline pipeline_h
;
380 radv_finishme("color clears incomplete");
383 pipeline
= device
->meta_state
.clear
[samples_log2
].color_pipelines
[fs_key
];
384 pipeline_h
= radv_pipeline_to_handle(pipeline
);
387 radv_finishme("color clears incomplete");
390 assert(samples_log2
< ARRAY_SIZE(device
->meta_state
.clear
));
392 assert(clear_att
->aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
);
393 assert(clear_att
->colorAttachment
< subpass
->color_count
);
395 const struct color_clear_vattrs vertex_data
[3] = {
398 clear_rect
->rect
.offset
.x
,
399 clear_rect
->rect
.offset
.y
,
401 .color
= clear_value
,
405 clear_rect
->rect
.offset
.x
,
406 clear_rect
->rect
.offset
.y
+ clear_rect
->rect
.extent
.height
,
408 .color
= clear_value
,
412 clear_rect
->rect
.offset
.x
+ clear_rect
->rect
.extent
.width
,
413 clear_rect
->rect
.offset
.y
,
415 .color
= clear_value
,
419 struct radv_subpass clear_subpass
= {
421 .color_attachments
= (VkAttachmentReference
[]) {
422 subpass
->color_attachments
[clear_att
->colorAttachment
]
424 .depth_stencil_attachment
= (VkAttachmentReference
) { VK_ATTACHMENT_UNUSED
, VK_IMAGE_LAYOUT_UNDEFINED
}
427 radv_cmd_buffer_set_subpass(cmd_buffer
, &clear_subpass
, false);
429 radv_cmd_buffer_upload_data(cmd_buffer
, sizeof(vertex_data
), 16, vertex_data
, &offset
);
430 struct radv_buffer vertex_buffer
= {
432 .size
= sizeof(vertex_data
),
433 .bo
= cmd_buffer
->upload
.upload_bo
,
438 radv_CmdBindVertexBuffers(cmd_buffer_h
, 0, 1,
439 (VkBuffer
[]) { radv_buffer_to_handle(&vertex_buffer
) },
440 (VkDeviceSize
[]) { 0 });
442 if (cmd_buffer
->state
.pipeline
!= pipeline
) {
443 radv_CmdBindPipeline(cmd_buffer_h
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
447 radv_CmdDraw(cmd_buffer_h
, 3, 1, 0, 0);
449 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
454 build_depthstencil_shader(struct nir_shader
**out_vs
, struct nir_shader
**out_fs
)
456 nir_builder vs_b
, fs_b
;
458 nir_builder_init_simple_shader(&vs_b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
459 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
461 vs_b
.shader
->info
->name
= ralloc_strdup(vs_b
.shader
, "meta_clear_depthstencil_vs");
462 fs_b
.shader
->info
->name
= ralloc_strdup(fs_b
.shader
, "meta_clear_depthstencil_fs");
463 const struct glsl_type
*position_type
= glsl_vec4_type();
465 nir_variable
*vs_in_pos
=
466 nir_variable_create(vs_b
.shader
, nir_var_shader_in
, position_type
,
468 vs_in_pos
->data
.location
= VERT_ATTRIB_GENERIC0
;
470 nir_variable
*vs_out_pos
=
471 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, position_type
,
473 vs_out_pos
->data
.location
= VARYING_SLOT_POS
;
475 nir_copy_var(&vs_b
, vs_out_pos
, vs_in_pos
);
477 *out_vs
= vs_b
.shader
;
478 *out_fs
= fs_b
.shader
;
482 create_depthstencil_pipeline(struct radv_device
*device
,
483 VkImageAspectFlags aspects
,
486 struct radv_pipeline
**pipeline
,
487 VkRenderPass
*render_pass
)
489 struct nir_shader
*vs_nir
, *fs_nir
;
491 build_depthstencil_shader(&vs_nir
, &fs_nir
);
493 const VkPipelineVertexInputStateCreateInfo vi_state
= {
494 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
495 .vertexBindingDescriptionCount
= 1,
496 .pVertexBindingDescriptions
= (VkVertexInputBindingDescription
[]) {
499 .stride
= sizeof(struct depthstencil_clear_vattrs
),
500 .inputRate
= VK_VERTEX_INPUT_RATE_VERTEX
503 .vertexAttributeDescriptionCount
= 1,
504 .pVertexAttributeDescriptions
= (VkVertexInputAttributeDescription
[]) {
509 .format
= VK_FORMAT_R32G32B32_SFLOAT
,
510 .offset
= offsetof(struct depthstencil_clear_vattrs
, position
),
515 const VkPipelineDepthStencilStateCreateInfo ds_state
= {
516 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
517 .depthTestEnable
= (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
),
518 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
519 .depthWriteEnable
= (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
),
520 .depthBoundsTestEnable
= false,
521 .stencilTestEnable
= (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
),
523 .passOp
= VK_STENCIL_OP_REPLACE
,
524 .compareOp
= VK_COMPARE_OP_ALWAYS
,
525 .writeMask
= UINT32_MAX
,
526 .reference
= 0, /* dynamic */
528 .back
= { 0 /* dont care */ },
531 const VkPipelineColorBlendStateCreateInfo cb_state
= {
532 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
533 .logicOpEnable
= false,
534 .attachmentCount
= 0,
535 .pAttachments
= NULL
,
538 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
539 &(VkRenderPassCreateInfo
) {
540 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
541 .attachmentCount
= 1,
542 .pAttachments
= &(VkAttachmentDescription
) {
543 .format
= VK_FORMAT_UNDEFINED
,
544 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
545 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
546 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
547 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
550 .pSubpasses
= &(VkSubpassDescription
) {
551 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
552 .inputAttachmentCount
= 0,
553 .colorAttachmentCount
= 0,
554 .pColorAttachments
= NULL
,
555 .pResolveAttachments
= NULL
,
556 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
558 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
560 .preserveAttachmentCount
= 1,
561 .pPreserveAttachments
= (uint32_t[]) { 0 },
563 .dependencyCount
= 0,
564 }, &device
->meta_state
.alloc
, render_pass
);
565 if (result
!= VK_SUCCESS
)
568 struct radv_graphics_pipeline_create_info extra
= {
569 .use_rectlist
= true,
572 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
573 extra
.db_depth_clear
= index
== DEPTH_CLEAR_SLOW
? false : true;
574 extra
.db_depth_disable_expclear
= index
== DEPTH_CLEAR_FAST_NO_EXPCLEAR
? true : false;
576 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
577 extra
.db_stencil_clear
= index
== DEPTH_CLEAR_SLOW
? false : true;
578 extra
.db_stencil_disable_expclear
= index
== DEPTH_CLEAR_FAST_NO_EXPCLEAR
? true : false;
580 result
= create_pipeline(device
, radv_render_pass_from_handle(*render_pass
),
581 samples
, vs_nir
, fs_nir
, &vi_state
, &ds_state
, &cb_state
,
582 &extra
, &device
->meta_state
.alloc
, pipeline
);
586 static bool depth_view_can_fast_clear(const struct radv_image_view
*iview
,
587 VkImageLayout layout
,
588 const VkClearRect
*clear_rect
)
590 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
591 clear_rect
->rect
.extent
.width
!= iview
->extent
.width
||
592 clear_rect
->rect
.extent
.height
!= iview
->extent
.height
)
594 if (iview
->image
->htile
.size
&&
595 iview
->base_mip
== 0 &&
596 iview
->base_layer
== 0 &&
597 radv_layout_can_expclear(iview
->image
, layout
) &&
598 memcmp(&iview
->extent
, &iview
->image
->extent
, sizeof(iview
->extent
)) == 0)
603 static struct radv_pipeline
*
604 pick_depthstencil_pipeline(struct radv_meta_state
*meta_state
,
605 const struct radv_image_view
*iview
,
607 VkImageAspectFlags aspects
,
608 VkImageLayout layout
,
609 const VkClearRect
*clear_rect
,
610 VkClearDepthStencilValue clear_value
)
612 bool fast
= depth_view_can_fast_clear(iview
, layout
, clear_rect
);
613 int index
= DEPTH_CLEAR_SLOW
;
616 /* we don't know the previous clear values, so we always have
617 * the NO_EXPCLEAR path */
618 index
= DEPTH_CLEAR_FAST_NO_EXPCLEAR
;
622 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
623 return meta_state
->clear
[samples_log2
].depthstencil_pipeline
[index
];
624 case VK_IMAGE_ASPECT_DEPTH_BIT
:
625 return meta_state
->clear
[samples_log2
].depth_only_pipeline
[index
];
626 case VK_IMAGE_ASPECT_STENCIL_BIT
:
627 return meta_state
->clear
[samples_log2
].stencil_only_pipeline
[index
];
629 unreachable("expected depth or stencil aspect");
633 emit_depthstencil_clear(struct radv_cmd_buffer
*cmd_buffer
,
634 const VkClearAttachment
*clear_att
,
635 const VkClearRect
*clear_rect
)
637 struct radv_device
*device
= cmd_buffer
->device
;
638 struct radv_meta_state
*meta_state
= &device
->meta_state
;
639 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
640 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
641 const uint32_t pass_att
= subpass
->depth_stencil_attachment
.attachment
;
642 VkClearDepthStencilValue clear_value
= clear_att
->clearValue
.depthStencil
;
643 VkImageAspectFlags aspects
= clear_att
->aspectMask
;
644 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
645 const uint32_t samples
= iview
->image
->samples
;
646 const uint32_t samples_log2
= ffs(samples
) - 1;
647 VkCommandBuffer cmd_buffer_h
= radv_cmd_buffer_to_handle(cmd_buffer
);
650 assert(aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
||
651 aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
||
652 aspects
== (VK_IMAGE_ASPECT_DEPTH_BIT
|
653 VK_IMAGE_ASPECT_STENCIL_BIT
));
654 assert(pass_att
!= VK_ATTACHMENT_UNUSED
);
656 const struct depthstencil_clear_vattrs vertex_data
[3] = {
659 clear_rect
->rect
.offset
.x
,
660 clear_rect
->rect
.offset
.y
,
662 .depth_clear
= clear_value
.depth
,
666 clear_rect
->rect
.offset
.x
,
667 clear_rect
->rect
.offset
.y
+ clear_rect
->rect
.extent
.height
,
669 .depth_clear
= clear_value
.depth
,
673 clear_rect
->rect
.offset
.x
+ clear_rect
->rect
.extent
.width
,
674 clear_rect
->rect
.offset
.y
,
676 .depth_clear
= clear_value
.depth
,
680 radv_cmd_buffer_upload_data(cmd_buffer
, sizeof(vertex_data
), 16, vertex_data
, &offset
);
681 struct radv_buffer vertex_buffer
= {
683 .size
= sizeof(vertex_data
),
684 .bo
= cmd_buffer
->upload
.upload_bo
,
688 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
689 radv_CmdSetStencilReference(cmd_buffer_h
, VK_STENCIL_FACE_FRONT_BIT
,
690 clear_value
.stencil
);
693 radv_CmdBindVertexBuffers(cmd_buffer_h
, 0, 1,
694 (VkBuffer
[]) { radv_buffer_to_handle(&vertex_buffer
) },
695 (VkDeviceSize
[]) { 0 });
697 struct radv_pipeline
*pipeline
= pick_depthstencil_pipeline(meta_state
,
701 subpass
->depth_stencil_attachment
.layout
,
704 if (cmd_buffer
->state
.pipeline
!= pipeline
) {
705 radv_CmdBindPipeline(cmd_buffer_h
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
706 radv_pipeline_to_handle(pipeline
));
709 if (depth_view_can_fast_clear(iview
, subpass
->depth_stencil_attachment
.layout
, clear_rect
))
710 radv_set_depth_clear_regs(cmd_buffer
, iview
->image
, clear_value
, aspects
);
712 radv_CmdDraw(cmd_buffer_h
, 3, 1, 0, 0);
716 static VkFormat pipeline_formats
[] = {
717 VK_FORMAT_R8G8B8A8_UNORM
,
718 VK_FORMAT_R8G8B8A8_UINT
,
719 VK_FORMAT_R8G8B8A8_SINT
,
720 VK_FORMAT_R16G16B16A16_UNORM
,
721 VK_FORMAT_R16G16B16A16_SNORM
,
722 VK_FORMAT_R16G16B16A16_UINT
,
723 VK_FORMAT_R16G16B16A16_SINT
,
724 VK_FORMAT_R32_SFLOAT
,
725 VK_FORMAT_R32G32_SFLOAT
,
726 VK_FORMAT_R32G32B32A32_SFLOAT
730 radv_device_init_meta_clear_state(struct radv_device
*device
)
733 struct radv_meta_state
*state
= &device
->meta_state
;
735 memset(&device
->meta_state
.clear
, 0, sizeof(device
->meta_state
.clear
));
737 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->clear
); ++i
) {
738 uint32_t samples
= 1 << i
;
739 for (uint32_t j
= 0; j
< ARRAY_SIZE(pipeline_formats
); ++j
) {
740 VkFormat format
= pipeline_formats
[j
];
741 unsigned fs_key
= radv_format_meta_fs_key(format
);
742 assert(!state
->clear
[i
].color_pipelines
[fs_key
]);
743 res
= create_color_pipeline(device
, format
, samples
, 0, &state
->clear
[i
].color_pipelines
[fs_key
],
744 &state
->clear
[i
].render_pass
[fs_key
]);
745 if (res
!= VK_SUCCESS
)
750 for (uint32_t j
= 0; j
< NUM_DEPTH_CLEAR_PIPELINES
; j
++) {
751 res
= create_depthstencil_pipeline(device
,
752 VK_IMAGE_ASPECT_DEPTH_BIT
,
755 &state
->clear
[i
].depth_only_pipeline
[j
],
756 &state
->clear
[i
].depth_only_rp
[j
]);
757 if (res
!= VK_SUCCESS
)
760 res
= create_depthstencil_pipeline(device
,
761 VK_IMAGE_ASPECT_STENCIL_BIT
,
764 &state
->clear
[i
].stencil_only_pipeline
[j
],
765 &state
->clear
[i
].stencil_only_rp
[j
]);
766 if (res
!= VK_SUCCESS
)
769 res
= create_depthstencil_pipeline(device
,
770 VK_IMAGE_ASPECT_DEPTH_BIT
|
771 VK_IMAGE_ASPECT_STENCIL_BIT
,
774 &state
->clear
[i
].depthstencil_pipeline
[j
],
775 &state
->clear
[i
].depthstencil_rp
[j
]);
776 if (res
!= VK_SUCCESS
)
783 radv_device_finish_meta_clear_state(device
);
788 emit_fast_color_clear(struct radv_cmd_buffer
*cmd_buffer
,
789 const VkClearAttachment
*clear_att
,
790 const VkClearRect
*clear_rect
)
792 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
793 const uint32_t subpass_att
= clear_att
->colorAttachment
;
794 const uint32_t pass_att
= subpass
->color_attachments
[subpass_att
].attachment
;
795 VkImageLayout image_layout
= subpass
->color_attachments
[subpass_att
].layout
;
796 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
797 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
798 VkClearColorValue clear_value
= clear_att
->clearValue
.color
;
799 uint32_t clear_color
[2];
802 if (!iview
->image
->cmask
.size
&& !iview
->image
->surface
.dcc_size
)
805 if (!cmd_buffer
->device
->allow_fast_clears
)
808 if (!radv_layout_has_cmask(iview
->image
, image_layout
))
810 if (vk_format_get_blocksizebits(iview
->image
->vk_format
) > 64)
813 /* don't fast clear 3D */
814 if (iview
->image
->type
== VK_IMAGE_TYPE_3D
)
817 /* all layers are bound */
818 if (iview
->base_layer
> 0)
820 if (iview
->image
->array_size
!= iview
->layer_count
)
823 if (iview
->image
->levels
> 1)
826 if (iview
->image
->surface
.level
[0].mode
< RADEON_SURF_MODE_1D
)
829 if (memcmp(&iview
->extent
, &iview
->image
->extent
, sizeof(iview
->extent
)))
832 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
833 clear_rect
->rect
.extent
.width
!= iview
->image
->extent
.width
||
834 clear_rect
->rect
.extent
.height
!= iview
->image
->extent
.height
)
837 if (clear_rect
->baseArrayLayer
!= 0)
839 if (clear_rect
->layerCount
!= iview
->image
->array_size
)
843 ret
= radv_format_pack_clear_color(iview
->image
->vk_format
,
844 clear_color
, &clear_value
);
848 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
849 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
850 si_emit_cache_flush(cmd_buffer
);
851 /* clear cmask buffer */
852 if (iview
->image
->surface
.dcc_size
) {
853 radv_fill_buffer(cmd_buffer
, iview
->image
->bo
,
854 iview
->image
->offset
+ iview
->image
->dcc_offset
,
855 iview
->image
->surface
.dcc_size
, 0x20202020);
857 radv_fill_buffer(cmd_buffer
, iview
->image
->bo
,
858 iview
->image
->offset
+ iview
->image
->cmask
.offset
,
859 iview
->image
->cmask
.size
, 0);
861 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
862 RADV_CMD_FLAG_INV_VMEM_L1
|
863 RADV_CMD_FLAG_INV_GLOBAL_L2
;
865 radv_set_color_clear_regs(cmd_buffer
, iview
->image
, subpass_att
, clear_color
);
873 * The parameters mean that same as those in vkCmdClearAttachments.
876 emit_clear(struct radv_cmd_buffer
*cmd_buffer
,
877 const VkClearAttachment
*clear_att
,
878 const VkClearRect
*clear_rect
)
880 if (clear_att
->aspectMask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
882 if (!emit_fast_color_clear(cmd_buffer
, clear_att
, clear_rect
))
883 emit_color_clear(cmd_buffer
, clear_att
, clear_rect
);
885 assert(clear_att
->aspectMask
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
886 VK_IMAGE_ASPECT_STENCIL_BIT
));
887 emit_depthstencil_clear(cmd_buffer
, clear_att
, clear_rect
);
892 subpass_needs_clear(const struct radv_cmd_buffer
*cmd_buffer
)
894 const struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
897 if (!cmd_state
->subpass
)
899 ds
= cmd_state
->subpass
->depth_stencil_attachment
.attachment
;
900 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
901 uint32_t a
= cmd_state
->subpass
->color_attachments
[i
].attachment
;
902 if (cmd_state
->attachments
[a
].pending_clear_aspects
) {
907 if (ds
!= VK_ATTACHMENT_UNUSED
&&
908 cmd_state
->attachments
[ds
].pending_clear_aspects
) {
916 * Emit any pending attachment clears for the current subpass.
918 * @see radv_attachment_state::pending_clear_aspects
921 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
)
923 struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
924 struct radv_meta_saved_state saved_state
;
926 if (!subpass_needs_clear(cmd_buffer
))
929 radv_meta_save_graphics_reset_vport_scissor(&saved_state
, cmd_buffer
);
931 if (cmd_state
->framebuffer
->layers
> 1)
932 radv_finishme("clearing multi-layer framebuffer");
934 VkClearRect clear_rect
= {
935 .rect
= cmd_state
->render_area
,
937 .layerCount
= 1, /* FINISHME: clear multi-layer framebuffer */
940 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
941 uint32_t a
= cmd_state
->subpass
->color_attachments
[i
].attachment
;
943 if (!cmd_state
->attachments
[a
].pending_clear_aspects
)
946 assert(cmd_state
->attachments
[a
].pending_clear_aspects
==
947 VK_IMAGE_ASPECT_COLOR_BIT
);
949 VkClearAttachment clear_att
= {
950 .aspectMask
= VK_IMAGE_ASPECT_COLOR_BIT
,
951 .colorAttachment
= i
, /* Use attachment index relative to subpass */
952 .clearValue
= cmd_state
->attachments
[a
].clear_value
,
955 emit_clear(cmd_buffer
, &clear_att
, &clear_rect
);
956 cmd_state
->attachments
[a
].pending_clear_aspects
= 0;
959 uint32_t ds
= cmd_state
->subpass
->depth_stencil_attachment
.attachment
;
961 if (ds
!= VK_ATTACHMENT_UNUSED
) {
963 if (cmd_state
->attachments
[ds
].pending_clear_aspects
) {
965 VkClearAttachment clear_att
= {
966 .aspectMask
= cmd_state
->attachments
[ds
].pending_clear_aspects
,
967 .clearValue
= cmd_state
->attachments
[ds
].clear_value
,
970 emit_clear(cmd_buffer
, &clear_att
, &clear_rect
);
971 cmd_state
->attachments
[ds
].pending_clear_aspects
= 0;
975 radv_meta_restore(&saved_state
, cmd_buffer
);
979 radv_cmd_clear_image(struct radv_cmd_buffer
*cmd_buffer
,
980 struct radv_image
*image
,
981 VkImageLayout image_layout
,
982 const VkClearValue
*clear_value
,
983 uint32_t range_count
,
984 const VkImageSubresourceRange
*ranges
)
986 VkDevice device_h
= radv_device_to_handle(cmd_buffer
->device
);
987 VkFormat format
= image
->vk_format
;
988 VkClearValue internal_clear_value
= *clear_value
;
990 if (format
== VK_FORMAT_E5B9G9R9_UFLOAT_PACK32
) {
992 format
= VK_FORMAT_R32_UINT
;
993 value
= float3_to_rgb9e5(clear_value
->color
.float32
);
994 internal_clear_value
.color
.uint32
[0] = value
;
997 for (uint32_t r
= 0; r
< range_count
; r
++) {
998 const VkImageSubresourceRange
*range
= &ranges
[r
];
999 for (uint32_t l
= 0; l
< radv_get_levelCount(image
, range
); ++l
) {
1000 const uint32_t layer_count
= image
->type
== VK_IMAGE_TYPE_3D
?
1001 radv_minify(image
->extent
.depth
, range
->baseMipLevel
+ l
) :
1002 radv_get_layerCount(image
, range
);
1003 for (uint32_t s
= 0; s
< layer_count
; ++s
) {
1004 struct radv_image_view iview
;
1005 radv_image_view_init(&iview
, cmd_buffer
->device
,
1006 &(VkImageViewCreateInfo
) {
1007 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
1008 .image
= radv_image_to_handle(image
),
1009 .viewType
= radv_meta_get_view_type(image
),
1011 .subresourceRange
= {
1012 .aspectMask
= range
->aspectMask
,
1013 .baseMipLevel
= range
->baseMipLevel
+ l
,
1015 .baseArrayLayer
= range
->baseArrayLayer
+ s
,
1019 cmd_buffer
, VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
);
1022 radv_CreateFramebuffer(device_h
,
1023 &(VkFramebufferCreateInfo
) {
1024 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
1025 .attachmentCount
= 1,
1026 .pAttachments
= (VkImageView
[]) {
1027 radv_image_view_to_handle(&iview
),
1029 .width
= iview
.extent
.width
,
1030 .height
= iview
.extent
.height
,
1033 &cmd_buffer
->pool
->alloc
,
1036 VkAttachmentDescription att_desc
= {
1037 .format
= iview
.vk_format
,
1038 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1039 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1040 .stencilLoadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1041 .stencilStoreOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1042 .initialLayout
= image_layout
,
1043 .finalLayout
= image_layout
,
1046 VkSubpassDescription subpass_desc
= {
1047 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
1048 .inputAttachmentCount
= 0,
1049 .colorAttachmentCount
= 0,
1050 .pColorAttachments
= NULL
,
1051 .pResolveAttachments
= NULL
,
1052 .pDepthStencilAttachment
= NULL
,
1053 .preserveAttachmentCount
= 0,
1054 .pPreserveAttachments
= NULL
,
1057 const VkAttachmentReference att_ref
= {
1059 .layout
= image_layout
,
1062 if (range
->aspectMask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
1063 subpass_desc
.colorAttachmentCount
= 1;
1064 subpass_desc
.pColorAttachments
= &att_ref
;
1066 subpass_desc
.pDepthStencilAttachment
= &att_ref
;
1070 radv_CreateRenderPass(device_h
,
1071 &(VkRenderPassCreateInfo
) {
1072 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
1073 .attachmentCount
= 1,
1074 .pAttachments
= &att_desc
,
1076 .pSubpasses
= &subpass_desc
,
1078 &cmd_buffer
->pool
->alloc
,
1081 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
1082 &(VkRenderPassBeginInfo
) {
1083 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
1085 .offset
= { 0, 0, },
1087 .width
= iview
.extent
.width
,
1088 .height
= iview
.extent
.height
,
1093 .clearValueCount
= 0,
1094 .pClearValues
= NULL
,
1096 VK_SUBPASS_CONTENTS_INLINE
);
1098 VkClearAttachment clear_att
= {
1099 .aspectMask
= range
->aspectMask
,
1100 .colorAttachment
= 0,
1101 .clearValue
= internal_clear_value
,
1104 VkClearRect clear_rect
= {
1107 .extent
= { iview
.extent
.width
, iview
.extent
.height
},
1109 .baseArrayLayer
= range
->baseArrayLayer
,
1110 .layerCount
= 1, /* FINISHME: clear multi-layer framebuffer */
1113 emit_clear(cmd_buffer
, &clear_att
, &clear_rect
);
1115 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
));
1116 radv_DestroyRenderPass(device_h
, pass
,
1117 &cmd_buffer
->pool
->alloc
);
1118 radv_DestroyFramebuffer(device_h
, fb
,
1119 &cmd_buffer
->pool
->alloc
);
1125 void radv_CmdClearColorImage(
1126 VkCommandBuffer commandBuffer
,
1128 VkImageLayout imageLayout
,
1129 const VkClearColorValue
* pColor
,
1130 uint32_t rangeCount
,
1131 const VkImageSubresourceRange
* pRanges
)
1133 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1134 RADV_FROM_HANDLE(radv_image
, image
, image_h
);
1135 struct radv_meta_saved_state saved_state
;
1137 radv_meta_save_graphics_reset_vport_scissor(&saved_state
, cmd_buffer
);
1139 radv_cmd_clear_image(cmd_buffer
, image
, imageLayout
,
1140 (const VkClearValue
*) pColor
,
1141 rangeCount
, pRanges
);
1143 radv_meta_restore(&saved_state
, cmd_buffer
);
1146 void radv_CmdClearDepthStencilImage(
1147 VkCommandBuffer commandBuffer
,
1149 VkImageLayout imageLayout
,
1150 const VkClearDepthStencilValue
* pDepthStencil
,
1151 uint32_t rangeCount
,
1152 const VkImageSubresourceRange
* pRanges
)
1154 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1155 RADV_FROM_HANDLE(radv_image
, image
, image_h
);
1156 struct radv_meta_saved_state saved_state
;
1158 radv_meta_save_graphics_reset_vport_scissor(&saved_state
, cmd_buffer
);
1160 radv_cmd_clear_image(cmd_buffer
, image
, imageLayout
,
1161 (const VkClearValue
*) pDepthStencil
,
1162 rangeCount
, pRanges
);
1164 radv_meta_restore(&saved_state
, cmd_buffer
);
1167 void radv_CmdClearAttachments(
1168 VkCommandBuffer commandBuffer
,
1169 uint32_t attachmentCount
,
1170 const VkClearAttachment
* pAttachments
,
1172 const VkClearRect
* pRects
)
1174 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1175 struct radv_meta_saved_state saved_state
;
1177 if (!cmd_buffer
->state
.subpass
)
1180 radv_meta_save_graphics_reset_vport_scissor(&saved_state
, cmd_buffer
);
1182 /* FINISHME: We can do better than this dumb loop. It thrashes too much
1185 for (uint32_t a
= 0; a
< attachmentCount
; ++a
) {
1186 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
1187 emit_clear(cmd_buffer
, &pAttachments
[a
], &pRects
[r
]);
1191 radv_meta_restore(&saved_state
, cmd_buffer
);