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radv: skip draw calls with 0-sized index buffers
[mesa.git] / src / amd / vulkan / radv_meta_clear.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_debug.h"
25 #include "radv_meta.h"
26 #include "radv_private.h"
27 #include "nir/nir_builder.h"
28
29 #include "util/format_rgb9e5.h"
30 #include "vk_format.h"
31
32 enum {
33 DEPTH_CLEAR_SLOW,
34 DEPTH_CLEAR_FAST_EXPCLEAR,
35 DEPTH_CLEAR_FAST_NO_EXPCLEAR
36 };
37
38 static void
39 build_color_shaders(struct nir_shader **out_vs,
40 struct nir_shader **out_fs,
41 uint32_t frag_output)
42 {
43 nir_builder vs_b;
44 nir_builder fs_b;
45
46 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
47 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
48
49 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
50 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
51
52 const struct glsl_type *position_type = glsl_vec4_type();
53 const struct glsl_type *color_type = glsl_vec4_type();
54
55 nir_variable *vs_out_pos =
56 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
57 "gl_Position");
58 vs_out_pos->data.location = VARYING_SLOT_POS;
59
60 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
61 nir_intrinsic_set_base(in_color_load, 0);
62 nir_intrinsic_set_range(in_color_load, 16);
63 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
64 in_color_load->num_components = 4;
65 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
66 nir_builder_instr_insert(&fs_b, &in_color_load->instr);
67
68 nir_variable *fs_out_color =
69 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
70 "f_color");
71 fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
72
73 nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
74
75 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
76 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
77
78 const struct glsl_type *layer_type = glsl_int_type();
79 nir_variable *vs_out_layer =
80 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
81 "v_layer");
82 vs_out_layer->data.location = VARYING_SLOT_LAYER;
83 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
84 nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
85 nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
86
87 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
88 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
89
90 *out_vs = vs_b.shader;
91 *out_fs = fs_b.shader;
92 }
93
94 static VkResult
95 create_pipeline(struct radv_device *device,
96 struct radv_render_pass *render_pass,
97 uint32_t samples,
98 struct nir_shader *vs_nir,
99 struct nir_shader *fs_nir,
100 const VkPipelineVertexInputStateCreateInfo *vi_state,
101 const VkPipelineDepthStencilStateCreateInfo *ds_state,
102 const VkPipelineColorBlendStateCreateInfo *cb_state,
103 const VkPipelineLayout layout,
104 const struct radv_graphics_pipeline_create_info *extra,
105 const VkAllocationCallbacks *alloc,
106 VkPipeline *pipeline)
107 {
108 VkDevice device_h = radv_device_to_handle(device);
109 VkResult result;
110
111 struct radv_shader_module vs_m = { .nir = vs_nir };
112 struct radv_shader_module fs_m = { .nir = fs_nir };
113
114 result = radv_graphics_pipeline_create(device_h,
115 radv_pipeline_cache_to_handle(&device->meta_state.cache),
116 &(VkGraphicsPipelineCreateInfo) {
117 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
118 .stageCount = fs_nir ? 2 : 1,
119 .pStages = (VkPipelineShaderStageCreateInfo[]) {
120 {
121 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
122 .stage = VK_SHADER_STAGE_VERTEX_BIT,
123 .module = radv_shader_module_to_handle(&vs_m),
124 .pName = "main",
125 },
126 {
127 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
128 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
129 .module = radv_shader_module_to_handle(&fs_m),
130 .pName = "main",
131 },
132 },
133 .pVertexInputState = vi_state,
134 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
135 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
136 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
137 .primitiveRestartEnable = false,
138 },
139 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
140 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
141 .viewportCount = 1,
142 .scissorCount = 1,
143 },
144 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
145 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
146 .rasterizerDiscardEnable = false,
147 .polygonMode = VK_POLYGON_MODE_FILL,
148 .cullMode = VK_CULL_MODE_NONE,
149 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
150 .depthBiasEnable = false,
151 },
152 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
153 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
154 .rasterizationSamples = samples,
155 .sampleShadingEnable = false,
156 .pSampleMask = NULL,
157 .alphaToCoverageEnable = false,
158 .alphaToOneEnable = false,
159 },
160 .pDepthStencilState = ds_state,
161 .pColorBlendState = cb_state,
162 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
163 /* The meta clear pipeline declares all state as dynamic.
164 * As a consequence, vkCmdBindPipeline writes no dynamic state
165 * to the cmd buffer. Therefore, at the end of the meta clear,
166 * we need only restore dynamic state was vkCmdSet.
167 */
168 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
169 .dynamicStateCount = 8,
170 .pDynamicStates = (VkDynamicState[]) {
171 /* Everything except stencil write mask */
172 VK_DYNAMIC_STATE_VIEWPORT,
173 VK_DYNAMIC_STATE_SCISSOR,
174 VK_DYNAMIC_STATE_LINE_WIDTH,
175 VK_DYNAMIC_STATE_DEPTH_BIAS,
176 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
177 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
178 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
179 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
180 },
181 },
182 .layout = layout,
183 .flags = 0,
184 .renderPass = radv_render_pass_to_handle(render_pass),
185 .subpass = 0,
186 },
187 extra,
188 alloc,
189 pipeline);
190
191 ralloc_free(vs_nir);
192 ralloc_free(fs_nir);
193
194 return result;
195 }
196
197 static VkResult
198 create_color_renderpass(struct radv_device *device,
199 VkFormat vk_format,
200 uint32_t samples,
201 VkRenderPass *pass)
202 {
203 mtx_lock(&device->meta_state.mtx);
204 if (*pass) {
205 mtx_unlock (&device->meta_state.mtx);
206 return VK_SUCCESS;
207 }
208
209 VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
210 &(VkRenderPassCreateInfo) {
211 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
212 .attachmentCount = 1,
213 .pAttachments = &(VkAttachmentDescription) {
214 .format = vk_format,
215 .samples = samples,
216 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
217 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
218 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
219 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
220 },
221 .subpassCount = 1,
222 .pSubpasses = &(VkSubpassDescription) {
223 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
224 .inputAttachmentCount = 0,
225 .colorAttachmentCount = 1,
226 .pColorAttachments = &(VkAttachmentReference) {
227 .attachment = 0,
228 .layout = VK_IMAGE_LAYOUT_GENERAL,
229 },
230 .pResolveAttachments = NULL,
231 .pDepthStencilAttachment = &(VkAttachmentReference) {
232 .attachment = VK_ATTACHMENT_UNUSED,
233 .layout = VK_IMAGE_LAYOUT_GENERAL,
234 },
235 .preserveAttachmentCount = 0,
236 .pPreserveAttachments = NULL,
237 },
238 .dependencyCount = 0,
239 }, &device->meta_state.alloc, pass);
240 mtx_unlock(&device->meta_state.mtx);
241 return result;
242 }
243
244 static VkResult
245 create_color_pipeline(struct radv_device *device,
246 uint32_t samples,
247 uint32_t frag_output,
248 VkPipeline *pipeline,
249 VkRenderPass pass)
250 {
251 struct nir_shader *vs_nir;
252 struct nir_shader *fs_nir;
253 VkResult result;
254
255 mtx_lock(&device->meta_state.mtx);
256 if (*pipeline) {
257 mtx_unlock(&device->meta_state.mtx);
258 return VK_SUCCESS;
259 }
260
261 build_color_shaders(&vs_nir, &fs_nir, frag_output);
262
263 const VkPipelineVertexInputStateCreateInfo vi_state = {
264 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
265 .vertexBindingDescriptionCount = 0,
266 .vertexAttributeDescriptionCount = 0,
267 };
268
269 const VkPipelineDepthStencilStateCreateInfo ds_state = {
270 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
271 .depthTestEnable = false,
272 .depthWriteEnable = false,
273 .depthBoundsTestEnable = false,
274 .stencilTestEnable = false,
275 };
276
277 VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
278 blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
279 .blendEnable = false,
280 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
281 VK_COLOR_COMPONENT_R_BIT |
282 VK_COLOR_COMPONENT_G_BIT |
283 VK_COLOR_COMPONENT_B_BIT,
284 };
285
286 const VkPipelineColorBlendStateCreateInfo cb_state = {
287 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
288 .logicOpEnable = false,
289 .attachmentCount = MAX_RTS,
290 .pAttachments = blend_attachment_state
291 };
292
293
294 struct radv_graphics_pipeline_create_info extra = {
295 .use_rectlist = true,
296 };
297 result = create_pipeline(device, radv_render_pass_from_handle(pass),
298 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
299 device->meta_state.clear_color_p_layout,
300 &extra, &device->meta_state.alloc, pipeline);
301
302 mtx_unlock(&device->meta_state.mtx);
303 return result;
304 }
305
306 static void
307 finish_meta_clear_htile_mask_state(struct radv_device *device)
308 {
309 struct radv_meta_state *state = &device->meta_state;
310
311 radv_DestroyPipeline(radv_device_to_handle(device),
312 state->clear_htile_mask_pipeline,
313 &state->alloc);
314 radv_DestroyPipelineLayout(radv_device_to_handle(device),
315 state->clear_htile_mask_p_layout,
316 &state->alloc);
317 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
318 state->clear_htile_mask_ds_layout,
319 &state->alloc);
320 }
321
322 void
323 radv_device_finish_meta_clear_state(struct radv_device *device)
324 {
325 struct radv_meta_state *state = &device->meta_state;
326
327 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
328 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
329 radv_DestroyPipeline(radv_device_to_handle(device),
330 state->clear[i].color_pipelines[j],
331 &state->alloc);
332 radv_DestroyRenderPass(radv_device_to_handle(device),
333 state->clear[i].render_pass[j],
334 &state->alloc);
335 }
336
337 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
338 radv_DestroyPipeline(radv_device_to_handle(device),
339 state->clear[i].depth_only_pipeline[j],
340 &state->alloc);
341 radv_DestroyPipeline(radv_device_to_handle(device),
342 state->clear[i].stencil_only_pipeline[j],
343 &state->alloc);
344 radv_DestroyPipeline(radv_device_to_handle(device),
345 state->clear[i].depthstencil_pipeline[j],
346 &state->alloc);
347 }
348 radv_DestroyRenderPass(radv_device_to_handle(device),
349 state->clear[i].depthstencil_rp,
350 &state->alloc);
351 }
352 radv_DestroyPipelineLayout(radv_device_to_handle(device),
353 state->clear_color_p_layout,
354 &state->alloc);
355 radv_DestroyPipelineLayout(radv_device_to_handle(device),
356 state->clear_depth_p_layout,
357 &state->alloc);
358
359 finish_meta_clear_htile_mask_state(device);
360 }
361
362 static void
363 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
364 const VkClearAttachment *clear_att,
365 const VkClearRect *clear_rect,
366 uint32_t view_mask)
367 {
368 struct radv_device *device = cmd_buffer->device;
369 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
370 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
371 const uint32_t subpass_att = clear_att->colorAttachment;
372 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
373 const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
374 uint32_t samples, samples_log2;
375 VkFormat format;
376 unsigned fs_key;
377 VkClearColorValue clear_value = clear_att->clearValue.color;
378 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
379 VkPipeline pipeline;
380
381 /* When a framebuffer is bound to the current command buffer, get the
382 * number of samples from it. Otherwise, get the number of samples from
383 * the render pass because it's likely a secondary command buffer.
384 */
385 if (iview) {
386 samples = iview->image->info.samples;
387 format = iview->vk_format;
388 } else {
389 samples = cmd_buffer->state.pass->attachments[pass_att].samples;
390 format = cmd_buffer->state.pass->attachments[pass_att].format;
391 }
392
393 samples_log2 = ffs(samples) - 1;
394 fs_key = radv_format_meta_fs_key(format);
395
396 if (fs_key == -1) {
397 radv_finishme("color clears incomplete");
398 return;
399 }
400
401 if (device->meta_state.clear[samples_log2].render_pass[fs_key] == VK_NULL_HANDLE) {
402 VkResult ret = create_color_renderpass(device, radv_fs_key_format_exemplars[fs_key],
403 samples,
404 &device->meta_state.clear[samples_log2].render_pass[fs_key]);
405 if (ret != VK_SUCCESS) {
406 cmd_buffer->record_result = ret;
407 return;
408 }
409 }
410
411 if (device->meta_state.clear[samples_log2].color_pipelines[fs_key] == VK_NULL_HANDLE) {
412 VkResult ret = create_color_pipeline(device, samples, 0,
413 &device->meta_state.clear[samples_log2].color_pipelines[fs_key],
414 device->meta_state.clear[samples_log2].render_pass[fs_key]);
415 if (ret != VK_SUCCESS) {
416 cmd_buffer->record_result = ret;
417 return;
418 }
419 }
420
421 pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
422 if (!pipeline) {
423 radv_finishme("color clears incomplete");
424 return;
425 }
426 assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
427 assert(pipeline);
428 assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
429 assert(clear_att->colorAttachment < subpass->color_count);
430
431 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
432 device->meta_state.clear_color_p_layout,
433 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
434 &clear_value);
435
436 struct radv_subpass clear_subpass = {
437 .color_count = 1,
438 .color_attachments = (struct radv_subpass_attachment[]) {
439 subpass->color_attachments[clear_att->colorAttachment]
440 },
441 .depth_stencil_attachment = NULL,
442 };
443
444 radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass);
445
446 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
447 pipeline);
448
449 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
450 .x = clear_rect->rect.offset.x,
451 .y = clear_rect->rect.offset.y,
452 .width = clear_rect->rect.extent.width,
453 .height = clear_rect->rect.extent.height,
454 .minDepth = 0.0f,
455 .maxDepth = 1.0f
456 });
457
458 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
459
460 if (view_mask) {
461 unsigned i;
462 for_each_bit(i, view_mask)
463 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
464 } else {
465 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
466 }
467
468 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
469 }
470
471
472 static void
473 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
474 {
475 nir_builder vs_b, fs_b;
476
477 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
478 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
479
480 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
481 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
482 const struct glsl_type *position_out_type = glsl_vec4_type();
483
484 nir_variable *vs_out_pos =
485 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
486 "gl_Position");
487 vs_out_pos->data.location = VARYING_SLOT_POS;
488
489 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
490 nir_intrinsic_set_base(in_color_load, 0);
491 nir_intrinsic_set_range(in_color_load, 4);
492 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
493 in_color_load->num_components = 1;
494 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
495 nir_builder_instr_insert(&vs_b, &in_color_load->instr);
496
497 nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
498 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
499
500 const struct glsl_type *layer_type = glsl_int_type();
501 nir_variable *vs_out_layer =
502 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
503 "v_layer");
504 vs_out_layer->data.location = VARYING_SLOT_LAYER;
505 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
506 nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
507 nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
508
509 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
510 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
511
512 *out_vs = vs_b.shader;
513 *out_fs = fs_b.shader;
514 }
515
516 static VkResult
517 create_depthstencil_renderpass(struct radv_device *device,
518 uint32_t samples,
519 VkRenderPass *render_pass)
520 {
521 mtx_lock(&device->meta_state.mtx);
522 if (*render_pass) {
523 mtx_unlock(&device->meta_state.mtx);
524 return VK_SUCCESS;
525 }
526
527 VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
528 &(VkRenderPassCreateInfo) {
529 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
530 .attachmentCount = 1,
531 .pAttachments = &(VkAttachmentDescription) {
532 .format = VK_FORMAT_D32_SFLOAT_S8_UINT,
533 .samples = samples,
534 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
535 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
536 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
537 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
538 },
539 .subpassCount = 1,
540 .pSubpasses = &(VkSubpassDescription) {
541 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
542 .inputAttachmentCount = 0,
543 .colorAttachmentCount = 0,
544 .pColorAttachments = NULL,
545 .pResolveAttachments = NULL,
546 .pDepthStencilAttachment = &(VkAttachmentReference) {
547 .attachment = 0,
548 .layout = VK_IMAGE_LAYOUT_GENERAL,
549 },
550 .preserveAttachmentCount = 0,
551 .pPreserveAttachments = NULL,
552 },
553 .dependencyCount = 0,
554 }, &device->meta_state.alloc, render_pass);
555 mtx_unlock(&device->meta_state.mtx);
556 return result;
557 }
558
559 static VkResult
560 create_depthstencil_pipeline(struct radv_device *device,
561 VkImageAspectFlags aspects,
562 uint32_t samples,
563 int index,
564 VkPipeline *pipeline,
565 VkRenderPass render_pass)
566 {
567 struct nir_shader *vs_nir, *fs_nir;
568 VkResult result;
569
570 mtx_lock(&device->meta_state.mtx);
571 if (*pipeline) {
572 mtx_unlock(&device->meta_state.mtx);
573 return VK_SUCCESS;
574 }
575
576 build_depthstencil_shader(&vs_nir, &fs_nir);
577
578 const VkPipelineVertexInputStateCreateInfo vi_state = {
579 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
580 .vertexBindingDescriptionCount = 0,
581 .vertexAttributeDescriptionCount = 0,
582 };
583
584 const VkPipelineDepthStencilStateCreateInfo ds_state = {
585 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
586 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
587 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
588 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
589 .depthBoundsTestEnable = false,
590 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
591 .front = {
592 .passOp = VK_STENCIL_OP_REPLACE,
593 .compareOp = VK_COMPARE_OP_ALWAYS,
594 .writeMask = UINT32_MAX,
595 .reference = 0, /* dynamic */
596 },
597 .back = { 0 /* dont care */ },
598 };
599
600 const VkPipelineColorBlendStateCreateInfo cb_state = {
601 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
602 .logicOpEnable = false,
603 .attachmentCount = 0,
604 .pAttachments = NULL,
605 };
606
607 struct radv_graphics_pipeline_create_info extra = {
608 .use_rectlist = true,
609 };
610
611 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
612 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
613 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
614 }
615 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
616 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
617 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
618 }
619 result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
620 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
621 device->meta_state.clear_depth_p_layout,
622 &extra, &device->meta_state.alloc, pipeline);
623
624 mtx_unlock(&device->meta_state.mtx);
625 return result;
626 }
627
628 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
629 const struct radv_image_view *iview,
630 VkImageAspectFlags aspects,
631 VkImageLayout layout,
632 const VkClearRect *clear_rect,
633 VkClearDepthStencilValue clear_value)
634 {
635 if (!iview)
636 return false;
637
638 uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
639 cmd_buffer->queue_family_index,
640 cmd_buffer->queue_family_index);
641 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
642 clear_rect->rect.extent.width != iview->extent.width ||
643 clear_rect->rect.extent.height != iview->extent.height)
644 return false;
645 if (radv_image_is_tc_compat_htile(iview->image) &&
646 (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && clear_value.depth != 0.0 &&
647 clear_value.depth != 1.0) ||
648 ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0)))
649 return false;
650 if (radv_image_has_htile(iview->image) &&
651 iview->base_mip == 0 &&
652 iview->base_layer == 0 &&
653 iview->layer_count == iview->image->info.array_size &&
654 radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
655 radv_image_extent_compare(iview->image, &iview->extent))
656 return true;
657 return false;
658 }
659
660 static VkPipeline
661 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
662 struct radv_meta_state *meta_state,
663 const struct radv_image_view *iview,
664 int samples_log2,
665 VkImageAspectFlags aspects,
666 VkImageLayout layout,
667 const VkClearRect *clear_rect,
668 VkClearDepthStencilValue clear_value)
669 {
670 bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, clear_rect, clear_value);
671 int index = DEPTH_CLEAR_SLOW;
672 VkPipeline *pipeline;
673
674 if (fast) {
675 /* we don't know the previous clear values, so we always have
676 * the NO_EXPCLEAR path */
677 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
678 }
679
680 switch (aspects) {
681 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
682 pipeline = &meta_state->clear[samples_log2].depthstencil_pipeline[index];
683 break;
684 case VK_IMAGE_ASPECT_DEPTH_BIT:
685 pipeline = &meta_state->clear[samples_log2].depth_only_pipeline[index];
686 break;
687 case VK_IMAGE_ASPECT_STENCIL_BIT:
688 pipeline = &meta_state->clear[samples_log2].stencil_only_pipeline[index];
689 break;
690 default:
691 unreachable("expected depth or stencil aspect");
692 }
693
694 if (cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp == VK_NULL_HANDLE) {
695 VkResult ret = create_depthstencil_renderpass(cmd_buffer->device, 1u << samples_log2,
696 &cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
697 if (ret != VK_SUCCESS) {
698 cmd_buffer->record_result = ret;
699 return VK_NULL_HANDLE;
700 }
701 }
702
703 if (*pipeline == VK_NULL_HANDLE) {
704 VkResult ret = create_depthstencil_pipeline(cmd_buffer->device, aspects, 1u << samples_log2, index,
705 pipeline, cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
706 if (ret != VK_SUCCESS) {
707 cmd_buffer->record_result = ret;
708 return VK_NULL_HANDLE;
709 }
710 }
711 return *pipeline;
712 }
713
714 static void
715 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
716 const VkClearAttachment *clear_att,
717 const VkClearRect *clear_rect,
718 struct radv_subpass_attachment *ds_att,
719 uint32_t view_mask)
720 {
721 struct radv_device *device = cmd_buffer->device;
722 struct radv_meta_state *meta_state = &device->meta_state;
723 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
724 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
725 const uint32_t pass_att = ds_att->attachment;
726 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
727 VkImageAspectFlags aspects = clear_att->aspectMask;
728 const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
729 uint32_t samples, samples_log2;
730 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
731
732 /* When a framebuffer is bound to the current command buffer, get the
733 * number of samples from it. Otherwise, get the number of samples from
734 * the render pass because it's likely a secondary command buffer.
735 */
736 if (iview) {
737 samples = iview->image->info.samples;
738 } else {
739 samples = cmd_buffer->state.pass->attachments[pass_att].samples;
740 }
741
742 samples_log2 = ffs(samples) - 1;
743
744 assert(pass_att != VK_ATTACHMENT_UNUSED);
745
746 if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
747 clear_value.depth = 1.0f;
748
749 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
750 device->meta_state.clear_depth_p_layout,
751 VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
752 &clear_value.depth);
753
754 uint32_t prev_reference = cmd_buffer->state.dynamic.stencil_reference.front;
755 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
756 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
757 clear_value.stencil);
758 }
759
760 VkPipeline pipeline = pick_depthstencil_pipeline(cmd_buffer,
761 meta_state,
762 iview,
763 samples_log2,
764 aspects,
765 ds_att->layout,
766 clear_rect,
767 clear_value);
768 if (!pipeline)
769 return;
770
771 struct radv_subpass clear_subpass = {
772 .color_count = 0,
773 .color_attachments = NULL,
774 .depth_stencil_attachment = ds_att,
775 };
776
777 radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass);
778
779 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
780 pipeline);
781
782 if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
783 ds_att->layout, clear_rect, clear_value))
784 radv_update_ds_clear_metadata(cmd_buffer, iview->image,
785 clear_value, aspects);
786
787 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
788 .x = clear_rect->rect.offset.x,
789 .y = clear_rect->rect.offset.y,
790 .width = clear_rect->rect.extent.width,
791 .height = clear_rect->rect.extent.height,
792 .minDepth = 0.0f,
793 .maxDepth = 1.0f
794 });
795
796 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
797
798 if (view_mask) {
799 unsigned i;
800 for_each_bit(i, view_mask)
801 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
802 } else {
803 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
804 }
805
806 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
807 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
808 prev_reference);
809 }
810
811 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
812 }
813
814 static uint32_t
815 clear_htile_mask(struct radv_cmd_buffer *cmd_buffer,
816 struct radeon_winsys_bo *bo, uint64_t offset, uint64_t size,
817 uint32_t htile_value, uint32_t htile_mask)
818 {
819 struct radv_device *device = cmd_buffer->device;
820 struct radv_meta_state *state = &device->meta_state;
821 uint64_t block_count = round_up_u64(size, 1024);
822 struct radv_meta_saved_state saved_state;
823
824 radv_meta_save(&saved_state, cmd_buffer,
825 RADV_META_SAVE_COMPUTE_PIPELINE |
826 RADV_META_SAVE_CONSTANTS |
827 RADV_META_SAVE_DESCRIPTORS);
828
829 struct radv_buffer dst_buffer = {
830 .bo = bo,
831 .offset = offset,
832 .size = size
833 };
834
835 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
836 VK_PIPELINE_BIND_POINT_COMPUTE,
837 state->clear_htile_mask_pipeline);
838
839 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
840 state->clear_htile_mask_p_layout,
841 0, /* set */
842 1, /* descriptorWriteCount */
843 (VkWriteDescriptorSet[]) {
844 {
845 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
846 .dstBinding = 0,
847 .dstArrayElement = 0,
848 .descriptorCount = 1,
849 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
850 .pBufferInfo = &(VkDescriptorBufferInfo) {
851 .buffer = radv_buffer_to_handle(&dst_buffer),
852 .offset = 0,
853 .range = size
854 }
855 }
856 });
857
858 const unsigned constants[2] = {
859 htile_value & htile_mask,
860 ~htile_mask,
861 };
862
863 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
864 state->clear_htile_mask_p_layout,
865 VK_SHADER_STAGE_COMPUTE_BIT, 0, 8,
866 constants);
867
868 radv_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer), block_count, 1, 1);
869
870 radv_meta_restore(&saved_state, cmd_buffer);
871
872 return RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
873 RADV_CMD_FLAG_INV_VCACHE |
874 RADV_CMD_FLAG_WB_L2;
875 }
876
877 static uint32_t
878 radv_get_htile_fast_clear_value(const struct radv_image *image,
879 VkClearDepthStencilValue value)
880 {
881 uint32_t clear_value;
882
883 if (!image->planes[0].surface.has_stencil) {
884 clear_value = value.depth ? 0xfffffff0 : 0;
885 } else {
886 clear_value = value.depth ? 0xfffc0000 : 0;
887 }
888
889 return clear_value;
890 }
891
892 static uint32_t
893 radv_get_htile_mask(const struct radv_image *image, VkImageAspectFlags aspects)
894 {
895 uint32_t mask = 0;
896
897 if (!image->planes[0].surface.has_stencil) {
898 /* All the HTILE buffer is used when there is no stencil. */
899 mask = UINT32_MAX;
900 } else {
901 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
902 mask |= 0xfffffc0f;
903 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
904 mask |= 0x000003f0;
905 }
906
907 return mask;
908 }
909
910 static bool
911 radv_is_fast_clear_depth_allowed(VkClearDepthStencilValue value)
912 {
913 return value.depth == 1.0f || value.depth == 0.0f;
914 }
915
916 static bool
917 radv_is_fast_clear_stencil_allowed(VkClearDepthStencilValue value)
918 {
919 return value.stencil == 0;
920 }
921
922 /**
923 * Determine if the given image can be fast cleared.
924 */
925 static bool
926 radv_image_can_fast_clear(struct radv_device *device, struct radv_image *image)
927 {
928 if (device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
929 return false;
930
931 if (vk_format_is_color(image->vk_format)) {
932 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
933 return false;
934
935 /* RB+ doesn't work with CMASK fast clear on Stoney. */
936 if (!radv_image_has_dcc(image) &&
937 device->physical_device->rad_info.family == CHIP_STONEY)
938 return false;
939 } else {
940 if (!radv_image_has_htile(image))
941 return false;
942 }
943
944 /* Do not fast clears 3D images. */
945 if (image->type == VK_IMAGE_TYPE_3D)
946 return false;
947
948 return true;
949 }
950
951 /**
952 * Determine if the given image view can be fast cleared.
953 */
954 static bool
955 radv_image_view_can_fast_clear(struct radv_device *device,
956 const struct radv_image_view *iview)
957 {
958 struct radv_image *image;
959
960 if (!iview)
961 return false;
962 image = iview->image;
963
964 /* Only fast clear if the image itself can be fast cleared. */
965 if (!radv_image_can_fast_clear(device, image))
966 return false;
967
968 /* Only fast clear if all layers are bound. */
969 if (iview->base_layer > 0 ||
970 iview->layer_count != image->info.array_size)
971 return false;
972
973 /* Only fast clear if the view covers the whole image. */
974 if (!radv_image_extent_compare(image, &iview->extent))
975 return false;
976
977 return true;
978 }
979
980 static bool
981 radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer,
982 const struct radv_image_view *iview,
983 VkImageLayout image_layout,
984 VkImageAspectFlags aspects,
985 const VkClearRect *clear_rect,
986 const VkClearDepthStencilValue clear_value,
987 uint32_t view_mask)
988 {
989 if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview))
990 return false;
991
992 if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
993 return false;
994
995 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
996 clear_rect->rect.extent.width != iview->image->info.width ||
997 clear_rect->rect.extent.height != iview->image->info.height)
998 return false;
999
1000 if (view_mask && (iview->image->info.array_size >= 32 ||
1001 (1u << iview->image->info.array_size) - 1u != view_mask))
1002 return false;
1003 if (!view_mask && clear_rect->baseArrayLayer != 0)
1004 return false;
1005 if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
1006 return false;
1007
1008 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX9 &&
1009 (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT) ||
1010 ((vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1011 !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))))
1012 return false;
1013
1014 if (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1015 !radv_is_fast_clear_depth_allowed(clear_value)) ||
1016 ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1017 !radv_is_fast_clear_stencil_allowed(clear_value)))
1018 return false;
1019
1020 return true;
1021 }
1022
1023 static void
1024 radv_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer,
1025 const struct radv_image_view *iview,
1026 const VkClearAttachment *clear_att,
1027 enum radv_cmd_flush_bits *pre_flush,
1028 enum radv_cmd_flush_bits *post_flush)
1029 {
1030 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
1031 VkImageAspectFlags aspects = clear_att->aspectMask;
1032 uint32_t clear_word, flush_bits;
1033 uint32_t htile_mask;
1034
1035 clear_word = radv_get_htile_fast_clear_value(iview->image, clear_value);
1036 htile_mask = radv_get_htile_mask(iview->image, aspects);
1037
1038 if (pre_flush) {
1039 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1040 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
1041 *pre_flush |= cmd_buffer->state.flush_bits;
1042 }
1043
1044 if (htile_mask == UINT_MAX) {
1045 /* Clear the whole HTILE buffer. */
1046 flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
1047 iview->image->offset + iview->image->htile_offset,
1048 iview->image->planes[0].surface.htile_size, clear_word);
1049 } else {
1050 /* Only clear depth or stencil bytes in the HTILE buffer. */
1051 /* TODO: Implement that path for GFX10. */
1052 assert(cmd_buffer->device->physical_device->rad_info.chip_class == GFX9);
1053 flush_bits = clear_htile_mask(cmd_buffer, iview->image->bo,
1054 iview->image->offset + iview->image->htile_offset,
1055 iview->image->planes[0].surface.htile_size, clear_word,
1056 htile_mask);
1057 }
1058
1059 radv_update_ds_clear_metadata(cmd_buffer, iview->image, clear_value, aspects);
1060 if (post_flush) {
1061 *post_flush |= flush_bits;
1062 }
1063 }
1064
1065 static nir_shader *
1066 build_clear_htile_mask_shader()
1067 {
1068 nir_builder b;
1069
1070 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
1071 b.shader->info.name = ralloc_strdup(b.shader, "meta_clear_htile_mask");
1072 b.shader->info.cs.local_size[0] = 64;
1073 b.shader->info.cs.local_size[1] = 1;
1074 b.shader->info.cs.local_size[2] = 1;
1075
1076 nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
1077 nir_ssa_def *wg_id = nir_load_work_group_id(&b);
1078 nir_ssa_def *block_size = nir_imm_ivec4(&b,
1079 b.shader->info.cs.local_size[0],
1080 b.shader->info.cs.local_size[1],
1081 b.shader->info.cs.local_size[2], 0);
1082
1083 nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
1084
1085 nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16));
1086 offset = nir_channel(&b, offset, 0);
1087
1088 nir_intrinsic_instr *buf =
1089 nir_intrinsic_instr_create(b.shader,
1090 nir_intrinsic_vulkan_resource_index);
1091
1092 buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
1093 buf->num_components = 1;
1094 nir_intrinsic_set_desc_set(buf, 0);
1095 nir_intrinsic_set_binding(buf, 0);
1096 nir_ssa_dest_init(&buf->instr, &buf->dest, buf->num_components, 32, NULL);
1097 nir_builder_instr_insert(&b, &buf->instr);
1098
1099 nir_intrinsic_instr *constants =
1100 nir_intrinsic_instr_create(b.shader,
1101 nir_intrinsic_load_push_constant);
1102 nir_intrinsic_set_base(constants, 0);
1103 nir_intrinsic_set_range(constants, 8);
1104 constants->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
1105 constants->num_components = 2;
1106 nir_ssa_dest_init(&constants->instr, &constants->dest, 2, 32, "constants");
1107 nir_builder_instr_insert(&b, &constants->instr);
1108
1109 nir_intrinsic_instr *load =
1110 nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
1111 load->src[0] = nir_src_for_ssa(&buf->dest.ssa);
1112 load->src[1] = nir_src_for_ssa(offset);
1113 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
1114 load->num_components = 4;
1115 nir_builder_instr_insert(&b, &load->instr);
1116
1117 /* data = (data & ~htile_mask) | (htile_value & htile_mask) */
1118 nir_ssa_def *data =
1119 nir_iand(&b, &load->dest.ssa,
1120 nir_channel(&b, &constants->dest.ssa, 1));
1121 data = nir_ior(&b, data, nir_channel(&b, &constants->dest.ssa, 0));
1122
1123 nir_intrinsic_instr *store =
1124 nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
1125 store->src[0] = nir_src_for_ssa(data);
1126 store->src[1] = nir_src_for_ssa(&buf->dest.ssa);
1127 store->src[2] = nir_src_for_ssa(offset);
1128 nir_intrinsic_set_write_mask(store, 0xf);
1129 nir_intrinsic_set_access(store, ACCESS_NON_READABLE);
1130 store->num_components = 4;
1131 nir_builder_instr_insert(&b, &store->instr);
1132
1133 return b.shader;
1134 }
1135
1136 static VkResult
1137 init_meta_clear_htile_mask_state(struct radv_device *device)
1138 {
1139 struct radv_meta_state *state = &device->meta_state;
1140 struct radv_shader_module cs = { .nir = NULL };
1141 VkResult result;
1142
1143 cs.nir = build_clear_htile_mask_shader();
1144
1145 VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1146 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1147 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1148 .bindingCount = 1,
1149 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1150 {
1151 .binding = 0,
1152 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
1153 .descriptorCount = 1,
1154 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
1155 .pImmutableSamplers = NULL
1156 },
1157 }
1158 };
1159
1160 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1161 &ds_layout_info, &state->alloc,
1162 &state->clear_htile_mask_ds_layout);
1163 if (result != VK_SUCCESS)
1164 goto fail;
1165
1166 VkPipelineLayoutCreateInfo p_layout_info = {
1167 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1168 .setLayoutCount = 1,
1169 .pSetLayouts = &state->clear_htile_mask_ds_layout,
1170 .pushConstantRangeCount = 1,
1171 .pPushConstantRanges = &(VkPushConstantRange){
1172 VK_SHADER_STAGE_COMPUTE_BIT, 0, 8,
1173 },
1174 };
1175
1176 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1177 &p_layout_info, &state->alloc,
1178 &state->clear_htile_mask_p_layout);
1179 if (result != VK_SUCCESS)
1180 goto fail;
1181
1182 VkPipelineShaderStageCreateInfo shader_stage = {
1183 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1184 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
1185 .module = radv_shader_module_to_handle(&cs),
1186 .pName = "main",
1187 .pSpecializationInfo = NULL,
1188 };
1189
1190 VkComputePipelineCreateInfo pipeline_info = {
1191 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
1192 .stage = shader_stage,
1193 .flags = 0,
1194 .layout = state->clear_htile_mask_p_layout,
1195 };
1196
1197 result = radv_CreateComputePipelines(radv_device_to_handle(device),
1198 radv_pipeline_cache_to_handle(&state->cache),
1199 1, &pipeline_info, NULL,
1200 &state->clear_htile_mask_pipeline);
1201
1202 ralloc_free(cs.nir);
1203 return result;
1204 fail:
1205 ralloc_free(cs.nir);
1206 return result;
1207 }
1208
1209 VkResult
1210 radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand)
1211 {
1212 VkResult res;
1213 struct radv_meta_state *state = &device->meta_state;
1214
1215 VkPipelineLayoutCreateInfo pl_color_create_info = {
1216 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1217 .setLayoutCount = 0,
1218 .pushConstantRangeCount = 1,
1219 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
1220 };
1221
1222 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1223 &pl_color_create_info,
1224 &device->meta_state.alloc,
1225 &device->meta_state.clear_color_p_layout);
1226 if (res != VK_SUCCESS)
1227 goto fail;
1228
1229 VkPipelineLayoutCreateInfo pl_depth_create_info = {
1230 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1231 .setLayoutCount = 0,
1232 .pushConstantRangeCount = 1,
1233 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
1234 };
1235
1236 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1237 &pl_depth_create_info,
1238 &device->meta_state.alloc,
1239 &device->meta_state.clear_depth_p_layout);
1240 if (res != VK_SUCCESS)
1241 goto fail;
1242
1243 res = init_meta_clear_htile_mask_state(device);
1244 if (res != VK_SUCCESS)
1245 goto fail;
1246
1247 if (on_demand)
1248 return VK_SUCCESS;
1249
1250 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
1251 uint32_t samples = 1 << i;
1252 for (uint32_t j = 0; j < NUM_META_FS_KEYS; ++j) {
1253 VkFormat format = radv_fs_key_format_exemplars[j];
1254 unsigned fs_key = radv_format_meta_fs_key(format);
1255 assert(!state->clear[i].color_pipelines[fs_key]);
1256
1257 res = create_color_renderpass(device, format, samples,
1258 &state->clear[i].render_pass[fs_key]);
1259 if (res != VK_SUCCESS)
1260 goto fail;
1261
1262 res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
1263 state->clear[i].render_pass[fs_key]);
1264 if (res != VK_SUCCESS)
1265 goto fail;
1266
1267 }
1268
1269 res = create_depthstencil_renderpass(device,
1270 samples,
1271 &state->clear[i].depthstencil_rp);
1272 if (res != VK_SUCCESS)
1273 goto fail;
1274
1275 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
1276 res = create_depthstencil_pipeline(device,
1277 VK_IMAGE_ASPECT_DEPTH_BIT,
1278 samples,
1279 j,
1280 &state->clear[i].depth_only_pipeline[j],
1281 state->clear[i].depthstencil_rp);
1282 if (res != VK_SUCCESS)
1283 goto fail;
1284
1285 res = create_depthstencil_pipeline(device,
1286 VK_IMAGE_ASPECT_STENCIL_BIT,
1287 samples,
1288 j,
1289 &state->clear[i].stencil_only_pipeline[j],
1290 state->clear[i].depthstencil_rp);
1291 if (res != VK_SUCCESS)
1292 goto fail;
1293
1294 res = create_depthstencil_pipeline(device,
1295 VK_IMAGE_ASPECT_DEPTH_BIT |
1296 VK_IMAGE_ASPECT_STENCIL_BIT,
1297 samples,
1298 j,
1299 &state->clear[i].depthstencil_pipeline[j],
1300 state->clear[i].depthstencil_rp);
1301 if (res != VK_SUCCESS)
1302 goto fail;
1303 }
1304 }
1305 return VK_SUCCESS;
1306
1307 fail:
1308 radv_device_finish_meta_clear_state(device);
1309 return res;
1310 }
1311
1312 static uint32_t
1313 radv_get_cmask_fast_clear_value(const struct radv_image *image)
1314 {
1315 uint32_t value = 0; /* Default value when no DCC. */
1316
1317 /* The fast-clear value is different for images that have both DCC and
1318 * CMASK metadata.
1319 */
1320 if (radv_image_has_dcc(image)) {
1321 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
1322 return image->info.samples > 1 ? 0xcccccccc : 0xffffffff;
1323 }
1324
1325 return value;
1326 }
1327
1328 uint32_t
1329 radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
1330 struct radv_image *image,
1331 const VkImageSubresourceRange *range, uint32_t value)
1332 {
1333 uint64_t offset = image->offset + image->cmask.offset;
1334 uint64_t size;
1335
1336 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1337 /* TODO: clear layers. */
1338 size = image->cmask.size;
1339 } else {
1340 offset += image->cmask.slice_size * range->baseArrayLayer;
1341 size = image->cmask.slice_size * radv_get_layerCount(image, range);
1342 }
1343
1344 return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
1345 }
1346
1347
1348 uint32_t
1349 radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
1350 struct radv_image *image,
1351 const VkImageSubresourceRange *range, uint32_t value)
1352 {
1353 uint64_t offset = image->offset + image->fmask.offset;
1354 uint64_t size;
1355
1356 /* MSAA images do not support mipmap levels. */
1357 assert(range->baseMipLevel == 0 &&
1358 radv_get_levelCount(image, range) == 1);
1359
1360 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1361 /* TODO: clear layers. */
1362 size = image->fmask.size;
1363 } else {
1364 offset += image->fmask.slice_size * range->baseArrayLayer;
1365 size = image->fmask.slice_size * radv_get_layerCount(image, range);
1366 }
1367
1368 return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
1369 }
1370
1371 uint32_t
1372 radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
1373 struct radv_image *image,
1374 const VkImageSubresourceRange *range, uint32_t value)
1375 {
1376 uint32_t level_count = radv_get_levelCount(image, range);
1377 uint32_t flush_bits = 0;
1378
1379 /* Mark the image as being compressed. */
1380 radv_update_dcc_metadata(cmd_buffer, image, range, true);
1381
1382 for (uint32_t l = 0; l < level_count; l++) {
1383 uint64_t offset = image->offset + image->dcc_offset;
1384 uint32_t level = range->baseMipLevel + l;
1385 uint64_t size;
1386
1387 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1388 /* Mipmap levels aren't implemented. */
1389 assert(level == 0);
1390 size = image->planes[0].surface.dcc_size;
1391 } else {
1392 const struct legacy_surf_level *surf_level =
1393 &image->planes[0].surface.u.legacy.level[level];
1394
1395 /* If dcc_fast_clear_size is 0 (which might happens for
1396 * mipmaps) the fill buffer operation below is a no-op.
1397 * This can only happen during initialization as the
1398 * fast clear path fallbacks to slow clears if one
1399 * level can't be fast cleared.
1400 */
1401 offset += surf_level->dcc_offset +
1402 surf_level->dcc_slice_fast_clear_size * range->baseArrayLayer;
1403 size = surf_level->dcc_slice_fast_clear_size * radv_get_layerCount(image, range);
1404 }
1405
1406 flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
1407 size, value);
1408 }
1409
1410 return flush_bits;
1411 }
1412
1413 uint32_t
1414 radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
1415 const VkImageSubresourceRange *range, uint32_t value)
1416 {
1417 unsigned layer_count = radv_get_layerCount(image, range);
1418 uint64_t size = image->planes[0].surface.htile_slice_size * layer_count;
1419 uint64_t offset = image->offset + image->htile_offset +
1420 image->planes[0].surface.htile_slice_size * range->baseArrayLayer;
1421
1422 return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
1423 }
1424
1425 enum {
1426 RADV_DCC_CLEAR_REG = 0x20202020U,
1427 RADV_DCC_CLEAR_MAIN_1 = 0x80808080U,
1428 RADV_DCC_CLEAR_SECONDARY_1 = 0x40404040U
1429 };
1430
1431 static void vi_get_fast_clear_parameters(VkFormat format,
1432 const VkClearColorValue *clear_value,
1433 uint32_t* reset_value,
1434 bool *can_avoid_fast_clear_elim)
1435 {
1436 bool values[4] = {};
1437 int extra_channel;
1438 bool main_value = false;
1439 bool extra_value = false;
1440 int i;
1441 *can_avoid_fast_clear_elim = false;
1442
1443 *reset_value = RADV_DCC_CLEAR_REG;
1444
1445 const struct vk_format_description *desc = vk_format_description(format);
1446 if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
1447 format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
1448 format == VK_FORMAT_B5G6R5_UNORM_PACK16)
1449 extra_channel = -1;
1450 else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
1451 if (radv_translate_colorswap(format, false) <= 1)
1452 extra_channel = desc->nr_channels - 1;
1453 else
1454 extra_channel = 0;
1455 } else
1456 return;
1457
1458 for (i = 0; i < 4; i++) {
1459 int index = desc->swizzle[i] - VK_SWIZZLE_X;
1460 if (desc->swizzle[i] < VK_SWIZZLE_X ||
1461 desc->swizzle[i] > VK_SWIZZLE_W)
1462 continue;
1463
1464 if (desc->channel[i].pure_integer &&
1465 desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
1466 /* Use the maximum value for clamping the clear color. */
1467 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
1468
1469 values[i] = clear_value->int32[i] != 0;
1470 if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
1471 return;
1472 } else if (desc->channel[i].pure_integer &&
1473 desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
1474 /* Use the maximum value for clamping the clear color. */
1475 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
1476
1477 values[i] = clear_value->uint32[i] != 0U;
1478 if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
1479 return;
1480 } else {
1481 values[i] = clear_value->float32[i] != 0.0F;
1482 if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
1483 return;
1484 }
1485
1486 if (index == extra_channel)
1487 extra_value = values[i];
1488 else
1489 main_value = values[i];
1490 }
1491
1492 for (int i = 0; i < 4; ++i)
1493 if (values[i] != main_value &&
1494 desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
1495 desc->swizzle[i] >= VK_SWIZZLE_X &&
1496 desc->swizzle[i] <= VK_SWIZZLE_W)
1497 return;
1498
1499 *can_avoid_fast_clear_elim = true;
1500 *reset_value = 0;
1501 if (main_value)
1502 *reset_value |= RADV_DCC_CLEAR_MAIN_1;
1503
1504 if (extra_value)
1505 *reset_value |= RADV_DCC_CLEAR_SECONDARY_1;
1506 return;
1507 }
1508
1509 static bool
1510 radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1511 const struct radv_image_view *iview,
1512 VkImageLayout image_layout,
1513 const VkClearRect *clear_rect,
1514 VkClearColorValue clear_value,
1515 uint32_t view_mask)
1516 {
1517 uint32_t clear_color[2];
1518
1519 if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview))
1520 return false;
1521
1522 if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
1523 return false;
1524
1525 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
1526 clear_rect->rect.extent.width != iview->image->info.width ||
1527 clear_rect->rect.extent.height != iview->image->info.height)
1528 return false;
1529
1530 if (view_mask && (iview->image->info.array_size >= 32 ||
1531 (1u << iview->image->info.array_size) - 1u != view_mask))
1532 return false;
1533 if (!view_mask && clear_rect->baseArrayLayer != 0)
1534 return false;
1535 if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
1536 return false;
1537
1538 /* DCC */
1539 if (!radv_format_pack_clear_color(iview->vk_format,
1540 clear_color, &clear_value))
1541 return false;
1542
1543 if (radv_dcc_enabled(iview->image, iview->base_mip)) {
1544 bool can_avoid_fast_clear_elim;
1545 uint32_t reset_value;
1546
1547 vi_get_fast_clear_parameters(iview->vk_format,
1548 &clear_value, &reset_value,
1549 &can_avoid_fast_clear_elim);
1550
1551 if (iview->image->info.samples > 1) {
1552 /* DCC fast clear with MSAA should clear CMASK. */
1553 /* FIXME: This doesn't work for now. There is a
1554 * hardware bug with fast clears and DCC for MSAA
1555 * textures. AMDVLK has a workaround but it doesn't
1556 * seem to work here. Note that we might emit useless
1557 * CB flushes but that shouldn't matter.
1558 */
1559 if (!can_avoid_fast_clear_elim)
1560 return false;
1561 }
1562
1563 if (iview->image->info.levels > 1 &&
1564 cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
1565 for (uint32_t l = 0; l < iview->level_count; l++) {
1566 uint32_t level = iview->base_mip + l;
1567 struct legacy_surf_level *surf_level =
1568 &iview->image->planes[0].surface.u.legacy.level[level];
1569
1570 /* Do not fast clears if one level can't be
1571 * fast cleared.
1572 */
1573 if (!surf_level->dcc_fast_clear_size)
1574 return false;
1575 }
1576 }
1577 }
1578
1579 return true;
1580 }
1581
1582
1583 static void
1584 radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1585 const struct radv_image_view *iview,
1586 const VkClearAttachment *clear_att,
1587 uint32_t subpass_att,
1588 enum radv_cmd_flush_bits *pre_flush,
1589 enum radv_cmd_flush_bits *post_flush)
1590 {
1591 VkClearColorValue clear_value = clear_att->clearValue.color;
1592 uint32_t clear_color[2], flush_bits = 0;
1593 uint32_t cmask_clear_value;
1594 VkImageSubresourceRange range = {
1595 .aspectMask = iview->aspect_mask,
1596 .baseMipLevel = iview->base_mip,
1597 .levelCount = iview->level_count,
1598 .baseArrayLayer = iview->base_layer,
1599 .layerCount = iview->layer_count,
1600 };
1601
1602 if (pre_flush) {
1603 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1604 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
1605 *pre_flush |= cmd_buffer->state.flush_bits;
1606 }
1607
1608 /* DCC */
1609 radv_format_pack_clear_color(iview->vk_format, clear_color, &clear_value);
1610
1611 cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
1612
1613 /* clear cmask buffer */
1614 if (radv_dcc_enabled(iview->image, iview->base_mip)) {
1615 uint32_t reset_value;
1616 bool can_avoid_fast_clear_elim;
1617 bool need_decompress_pass = false;
1618
1619 vi_get_fast_clear_parameters(iview->vk_format,
1620 &clear_value, &reset_value,
1621 &can_avoid_fast_clear_elim);
1622
1623 if (radv_image_has_cmask(iview->image)) {
1624 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1625 &range, cmask_clear_value);
1626
1627 need_decompress_pass = true;
1628 }
1629
1630 if (!can_avoid_fast_clear_elim)
1631 need_decompress_pass = true;
1632
1633 flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, &range,
1634 reset_value);
1635
1636 radv_update_fce_metadata(cmd_buffer, iview->image, &range,
1637 need_decompress_pass);
1638 } else {
1639 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1640 &range, cmask_clear_value);
1641 }
1642
1643 if (post_flush) {
1644 *post_flush |= flush_bits;
1645 }
1646
1647 radv_update_color_clear_metadata(cmd_buffer, iview, subpass_att,
1648 clear_color);
1649 }
1650
1651 /**
1652 * The parameters mean that same as those in vkCmdClearAttachments.
1653 */
1654 static void
1655 emit_clear(struct radv_cmd_buffer *cmd_buffer,
1656 const VkClearAttachment *clear_att,
1657 const VkClearRect *clear_rect,
1658 enum radv_cmd_flush_bits *pre_flush,
1659 enum radv_cmd_flush_bits *post_flush,
1660 uint32_t view_mask,
1661 bool ds_resolve_clear)
1662 {
1663 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
1664 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1665 VkImageAspectFlags aspects = clear_att->aspectMask;
1666
1667 if (aspects & VK_IMAGE_ASPECT_COLOR_BIT) {
1668 const uint32_t subpass_att = clear_att->colorAttachment;
1669 assert(subpass_att < subpass->color_count);
1670 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
1671 if (pass_att == VK_ATTACHMENT_UNUSED)
1672 return;
1673
1674 VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
1675 const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
1676 VkClearColorValue clear_value = clear_att->clearValue.color;
1677
1678 if (radv_can_fast_clear_color(cmd_buffer, iview, image_layout,
1679 clear_rect, clear_value, view_mask)) {
1680 radv_fast_clear_color(cmd_buffer, iview, clear_att,
1681 subpass_att, pre_flush,
1682 post_flush);
1683 } else {
1684 emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask);
1685 }
1686 } else {
1687 struct radv_subpass_attachment *ds_att = subpass->depth_stencil_attachment;
1688
1689 if (ds_resolve_clear)
1690 ds_att = subpass->ds_resolve_attachment;
1691
1692 if (!ds_att || ds_att->attachment == VK_ATTACHMENT_UNUSED)
1693 return;
1694
1695 VkImageLayout image_layout = ds_att->layout;
1696 const struct radv_image_view *iview = fb ? fb->attachments[ds_att->attachment].attachment : NULL;
1697 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
1698
1699 assert(aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
1700 VK_IMAGE_ASPECT_STENCIL_BIT));
1701
1702 if (radv_can_fast_clear_depth(cmd_buffer, iview, image_layout,
1703 aspects, clear_rect, clear_value,
1704 view_mask)) {
1705 radv_fast_clear_depth(cmd_buffer, iview, clear_att,
1706 pre_flush, post_flush);
1707 } else {
1708 emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect,
1709 ds_att, view_mask);
1710 }
1711 }
1712 }
1713
1714 static inline bool
1715 radv_attachment_needs_clear(struct radv_cmd_state *cmd_state, uint32_t a)
1716 {
1717 uint32_t view_mask = cmd_state->subpass->view_mask;
1718 return (a != VK_ATTACHMENT_UNUSED &&
1719 cmd_state->attachments[a].pending_clear_aspects &&
1720 (!view_mask || (view_mask & ~cmd_state->attachments[a].cleared_views)));
1721 }
1722
1723 static bool
1724 radv_subpass_needs_clear(struct radv_cmd_buffer *cmd_buffer)
1725 {
1726 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1727 uint32_t a;
1728
1729 if (!cmd_state->subpass)
1730 return false;
1731
1732 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1733 a = cmd_state->subpass->color_attachments[i].attachment;
1734 if (radv_attachment_needs_clear(cmd_state, a))
1735 return true;
1736 }
1737
1738 if (cmd_state->subpass->depth_stencil_attachment) {
1739 a = cmd_state->subpass->depth_stencil_attachment->attachment;
1740 if (radv_attachment_needs_clear(cmd_state, a))
1741 return true;
1742 }
1743
1744 if (!cmd_state->subpass->ds_resolve_attachment)
1745 return false;
1746
1747 a = cmd_state->subpass->ds_resolve_attachment->attachment;
1748 return radv_attachment_needs_clear(cmd_state, a);
1749 }
1750
1751 static void
1752 radv_subpass_clear_attachment(struct radv_cmd_buffer *cmd_buffer,
1753 struct radv_attachment_state *attachment,
1754 const VkClearAttachment *clear_att,
1755 enum radv_cmd_flush_bits *pre_flush,
1756 enum radv_cmd_flush_bits *post_flush,
1757 bool ds_resolve_clear)
1758 {
1759 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1760 uint32_t view_mask = cmd_state->subpass->view_mask;
1761
1762 VkClearRect clear_rect = {
1763 .rect = cmd_state->render_area,
1764 .baseArrayLayer = 0,
1765 .layerCount = cmd_state->framebuffer->layers,
1766 };
1767
1768 emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush,
1769 view_mask & ~attachment->cleared_views, ds_resolve_clear);
1770 if (view_mask)
1771 attachment->cleared_views |= view_mask;
1772 else
1773 attachment->pending_clear_aspects = 0;
1774 }
1775
1776 /**
1777 * Emit any pending attachment clears for the current subpass.
1778 *
1779 * @see radv_attachment_state::pending_clear_aspects
1780 */
1781 void
1782 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1783 {
1784 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1785 struct radv_meta_saved_state saved_state;
1786 enum radv_cmd_flush_bits pre_flush = 0;
1787 enum radv_cmd_flush_bits post_flush = 0;
1788
1789 if (!radv_subpass_needs_clear(cmd_buffer))
1790 return;
1791
1792 radv_meta_save(&saved_state, cmd_buffer,
1793 RADV_META_SAVE_GRAPHICS_PIPELINE |
1794 RADV_META_SAVE_CONSTANTS);
1795
1796 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1797 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1798
1799 if (!radv_attachment_needs_clear(cmd_state, a))
1800 continue;
1801
1802 assert(cmd_state->attachments[a].pending_clear_aspects ==
1803 VK_IMAGE_ASPECT_COLOR_BIT);
1804
1805 VkClearAttachment clear_att = {
1806 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1807 .colorAttachment = i, /* Use attachment index relative to subpass */
1808 .clearValue = cmd_state->attachments[a].clear_value,
1809 };
1810
1811 radv_subpass_clear_attachment(cmd_buffer,
1812 &cmd_state->attachments[a],
1813 &clear_att, &pre_flush,
1814 &post_flush, false);
1815 }
1816
1817 if (cmd_state->subpass->depth_stencil_attachment) {
1818 uint32_t ds = cmd_state->subpass->depth_stencil_attachment->attachment;
1819 if (radv_attachment_needs_clear(cmd_state, ds)) {
1820 VkClearAttachment clear_att = {
1821 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1822 .clearValue = cmd_state->attachments[ds].clear_value,
1823 };
1824
1825 radv_subpass_clear_attachment(cmd_buffer,
1826 &cmd_state->attachments[ds],
1827 &clear_att, &pre_flush,
1828 &post_flush, false);
1829 }
1830 }
1831
1832 if (cmd_state->subpass->ds_resolve_attachment) {
1833 uint32_t ds_resolve = cmd_state->subpass->ds_resolve_attachment->attachment;
1834 if (radv_attachment_needs_clear(cmd_state, ds_resolve)) {
1835 VkClearAttachment clear_att = {
1836 .aspectMask = cmd_state->attachments[ds_resolve].pending_clear_aspects,
1837 .clearValue = cmd_state->attachments[ds_resolve].clear_value,
1838 };
1839
1840 radv_subpass_clear_attachment(cmd_buffer,
1841 &cmd_state->attachments[ds_resolve],
1842 &clear_att, &pre_flush,
1843 &post_flush, true);
1844 }
1845 }
1846
1847 radv_meta_restore(&saved_state, cmd_buffer);
1848 cmd_buffer->state.flush_bits |= post_flush;
1849 }
1850
1851 static void
1852 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1853 struct radv_image *image,
1854 VkImageLayout image_layout,
1855 const VkImageSubresourceRange *range,
1856 VkFormat format, int level, int layer,
1857 const VkClearValue *clear_val)
1858 {
1859 VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1860 struct radv_image_view iview;
1861 uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level);
1862 uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level);
1863
1864 radv_image_view_init(&iview, cmd_buffer->device,
1865 &(VkImageViewCreateInfo) {
1866 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1867 .image = radv_image_to_handle(image),
1868 .viewType = radv_meta_get_view_type(image),
1869 .format = format,
1870 .subresourceRange = {
1871 .aspectMask = range->aspectMask,
1872 .baseMipLevel = range->baseMipLevel + level,
1873 .levelCount = 1,
1874 .baseArrayLayer = range->baseArrayLayer + layer,
1875 .layerCount = 1
1876 },
1877 });
1878
1879 VkFramebuffer fb;
1880 radv_CreateFramebuffer(device_h,
1881 &(VkFramebufferCreateInfo) {
1882 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1883 .attachmentCount = 1,
1884 .pAttachments = (VkImageView[]) {
1885 radv_image_view_to_handle(&iview),
1886 },
1887 .width = width,
1888 .height = height,
1889 .layers = 1
1890 },
1891 &cmd_buffer->pool->alloc,
1892 &fb);
1893
1894 VkAttachmentDescription att_desc = {
1895 .format = iview.vk_format,
1896 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1897 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1898 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1899 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1900 .initialLayout = image_layout,
1901 .finalLayout = image_layout,
1902 };
1903
1904 VkSubpassDescription subpass_desc = {
1905 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1906 .inputAttachmentCount = 0,
1907 .colorAttachmentCount = 0,
1908 .pColorAttachments = NULL,
1909 .pResolveAttachments = NULL,
1910 .pDepthStencilAttachment = NULL,
1911 .preserveAttachmentCount = 0,
1912 .pPreserveAttachments = NULL,
1913 };
1914
1915 const VkAttachmentReference att_ref = {
1916 .attachment = 0,
1917 .layout = image_layout,
1918 };
1919
1920 if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1921 subpass_desc.colorAttachmentCount = 1;
1922 subpass_desc.pColorAttachments = &att_ref;
1923 } else {
1924 subpass_desc.pDepthStencilAttachment = &att_ref;
1925 }
1926
1927 VkRenderPass pass;
1928 radv_CreateRenderPass(device_h,
1929 &(VkRenderPassCreateInfo) {
1930 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1931 .attachmentCount = 1,
1932 .pAttachments = &att_desc,
1933 .subpassCount = 1,
1934 .pSubpasses = &subpass_desc,
1935 },
1936 &cmd_buffer->pool->alloc,
1937 &pass);
1938
1939 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1940 &(VkRenderPassBeginInfo) {
1941 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1942 .renderArea = {
1943 .offset = { 0, 0, },
1944 .extent = {
1945 .width = width,
1946 .height = height,
1947 },
1948 },
1949 .renderPass = pass,
1950 .framebuffer = fb,
1951 .clearValueCount = 0,
1952 .pClearValues = NULL,
1953 },
1954 VK_SUBPASS_CONTENTS_INLINE);
1955
1956 VkClearAttachment clear_att = {
1957 .aspectMask = range->aspectMask,
1958 .colorAttachment = 0,
1959 .clearValue = *clear_val,
1960 };
1961
1962 VkClearRect clear_rect = {
1963 .rect = {
1964 .offset = { 0, 0 },
1965 .extent = { width, height },
1966 },
1967 .baseArrayLayer = range->baseArrayLayer,
1968 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1969 };
1970
1971 emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0, false);
1972
1973 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1974 radv_DestroyRenderPass(device_h, pass,
1975 &cmd_buffer->pool->alloc);
1976 radv_DestroyFramebuffer(device_h, fb,
1977 &cmd_buffer->pool->alloc);
1978 }
1979
1980 /**
1981 * Return TRUE if a fast color or depth clear has been performed.
1982 */
1983 static bool
1984 radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer,
1985 struct radv_image *image,
1986 VkFormat format,
1987 VkImageLayout image_layout,
1988 const VkImageSubresourceRange *range,
1989 const VkClearValue *clear_val)
1990 {
1991 struct radv_image_view iview;
1992
1993 radv_image_view_init(&iview, cmd_buffer->device,
1994 &(VkImageViewCreateInfo) {
1995 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1996 .image = radv_image_to_handle(image),
1997 .viewType = radv_meta_get_view_type(image),
1998 .format = image->vk_format,
1999 .subresourceRange = {
2000 .aspectMask = range->aspectMask,
2001 .baseMipLevel = range->baseMipLevel,
2002 .levelCount = range->levelCount,
2003 .baseArrayLayer = range->baseArrayLayer,
2004 .layerCount = range->layerCount,
2005 },
2006 });
2007
2008 VkClearRect clear_rect = {
2009 .rect = {
2010 .offset = { 0, 0 },
2011 .extent = {
2012 radv_minify(image->info.width, range->baseMipLevel),
2013 radv_minify(image->info.height, range->baseMipLevel),
2014 },
2015 },
2016 .baseArrayLayer = range->baseArrayLayer,
2017 .layerCount = range->layerCount,
2018 };
2019
2020 VkClearAttachment clear_att = {
2021 .aspectMask = range->aspectMask,
2022 .colorAttachment = 0,
2023 .clearValue = *clear_val,
2024 };
2025
2026 if (vk_format_is_color(format)) {
2027 if (radv_can_fast_clear_color(cmd_buffer, &iview,
2028 image_layout, &clear_rect,
2029 clear_att.clearValue.color, 0)) {
2030 radv_fast_clear_color(cmd_buffer, &iview, &clear_att,
2031 clear_att.colorAttachment,
2032 NULL, NULL);
2033 return true;
2034 }
2035 } else {
2036 if (radv_can_fast_clear_depth(cmd_buffer, &iview, image_layout,
2037 range->aspectMask, &clear_rect,
2038 clear_att.clearValue.depthStencil, 0)) {
2039 radv_fast_clear_depth(cmd_buffer, &iview, &clear_att,
2040 NULL, NULL);
2041 return true;
2042 }
2043 }
2044
2045 return false;
2046 }
2047
2048 static void
2049 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
2050 struct radv_image *image,
2051 VkImageLayout image_layout,
2052 const VkClearValue *clear_value,
2053 uint32_t range_count,
2054 const VkImageSubresourceRange *ranges,
2055 bool cs)
2056 {
2057 VkFormat format = image->vk_format;
2058 VkClearValue internal_clear_value = *clear_value;
2059
2060 if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
2061 uint32_t value;
2062 format = VK_FORMAT_R32_UINT;
2063 value = float3_to_rgb9e5(clear_value->color.float32);
2064 internal_clear_value.color.uint32[0] = value;
2065 }
2066
2067 if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
2068 uint8_t r, g;
2069 format = VK_FORMAT_R8_UINT;
2070 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
2071 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
2072 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
2073 }
2074
2075 if (format == VK_FORMAT_R32G32B32_UINT ||
2076 format == VK_FORMAT_R32G32B32_SINT ||
2077 format == VK_FORMAT_R32G32B32_SFLOAT)
2078 cs = true;
2079
2080 for (uint32_t r = 0; r < range_count; r++) {
2081 const VkImageSubresourceRange *range = &ranges[r];
2082
2083 /* Try to perform a fast clear first, otherwise fallback to
2084 * the legacy path.
2085 */
2086 if (!cs &&
2087 radv_fast_clear_range(cmd_buffer, image, format,
2088 image_layout, range,
2089 &internal_clear_value)) {
2090 continue;
2091 }
2092
2093 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
2094 const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
2095 radv_minify(image->info.depth, range->baseMipLevel + l) :
2096 radv_get_layerCount(image, range);
2097 for (uint32_t s = 0; s < layer_count; ++s) {
2098
2099 if (cs) {
2100 struct radv_meta_blit2d_surf surf;
2101 surf.format = format;
2102 surf.image = image;
2103 surf.level = range->baseMipLevel + l;
2104 surf.layer = range->baseArrayLayer + s;
2105 surf.aspect_mask = range->aspectMask;
2106 radv_meta_clear_image_cs(cmd_buffer, &surf,
2107 &internal_clear_value.color);
2108 } else {
2109 radv_clear_image_layer(cmd_buffer, image, image_layout,
2110 range, format, l, s, &internal_clear_value);
2111 }
2112 }
2113 }
2114 }
2115 }
2116
2117 void radv_CmdClearColorImage(
2118 VkCommandBuffer commandBuffer,
2119 VkImage image_h,
2120 VkImageLayout imageLayout,
2121 const VkClearColorValue* pColor,
2122 uint32_t rangeCount,
2123 const VkImageSubresourceRange* pRanges)
2124 {
2125 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2126 RADV_FROM_HANDLE(radv_image, image, image_h);
2127 struct radv_meta_saved_state saved_state;
2128 bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
2129
2130 if (cs) {
2131 radv_meta_save(&saved_state, cmd_buffer,
2132 RADV_META_SAVE_COMPUTE_PIPELINE |
2133 RADV_META_SAVE_CONSTANTS |
2134 RADV_META_SAVE_DESCRIPTORS);
2135 } else {
2136 radv_meta_save(&saved_state, cmd_buffer,
2137 RADV_META_SAVE_GRAPHICS_PIPELINE |
2138 RADV_META_SAVE_CONSTANTS);
2139 }
2140
2141 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
2142 (const VkClearValue *) pColor,
2143 rangeCount, pRanges, cs);
2144
2145 radv_meta_restore(&saved_state, cmd_buffer);
2146 }
2147
2148 void radv_CmdClearDepthStencilImage(
2149 VkCommandBuffer commandBuffer,
2150 VkImage image_h,
2151 VkImageLayout imageLayout,
2152 const VkClearDepthStencilValue* pDepthStencil,
2153 uint32_t rangeCount,
2154 const VkImageSubresourceRange* pRanges)
2155 {
2156 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2157 RADV_FROM_HANDLE(radv_image, image, image_h);
2158 struct radv_meta_saved_state saved_state;
2159
2160 radv_meta_save(&saved_state, cmd_buffer,
2161 RADV_META_SAVE_GRAPHICS_PIPELINE |
2162 RADV_META_SAVE_CONSTANTS);
2163
2164 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
2165 (const VkClearValue *) pDepthStencil,
2166 rangeCount, pRanges, false);
2167
2168 radv_meta_restore(&saved_state, cmd_buffer);
2169 }
2170
2171 void radv_CmdClearAttachments(
2172 VkCommandBuffer commandBuffer,
2173 uint32_t attachmentCount,
2174 const VkClearAttachment* pAttachments,
2175 uint32_t rectCount,
2176 const VkClearRect* pRects)
2177 {
2178 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2179 struct radv_meta_saved_state saved_state;
2180 enum radv_cmd_flush_bits pre_flush = 0;
2181 enum radv_cmd_flush_bits post_flush = 0;
2182
2183 if (!cmd_buffer->state.subpass)
2184 return;
2185
2186 radv_meta_save(&saved_state, cmd_buffer,
2187 RADV_META_SAVE_GRAPHICS_PIPELINE |
2188 RADV_META_SAVE_CONSTANTS);
2189
2190 /* FINISHME: We can do better than this dumb loop. It thrashes too much
2191 * state.
2192 */
2193 for (uint32_t a = 0; a < attachmentCount; ++a) {
2194 for (uint32_t r = 0; r < rectCount; ++r) {
2195 emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush,
2196 cmd_buffer->state.subpass->view_mask, false);
2197 }
2198 }
2199
2200 radv_meta_restore(&saved_state, cmd_buffer);
2201 cmd_buffer->state.flush_bits |= post_flush;
2202 }