2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "radv_debug.h"
25 #include "radv_meta.h"
26 #include "radv_private.h"
27 #include "nir/nir_builder.h"
29 #include "util/format_rgb9e5.h"
30 #include "vk_format.h"
34 DEPTH_CLEAR_FAST_EXPCLEAR
,
35 DEPTH_CLEAR_FAST_NO_EXPCLEAR
39 build_color_shaders(struct nir_shader
**out_vs
,
40 struct nir_shader
**out_fs
,
46 nir_builder_init_simple_shader(&vs_b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
47 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
49 vs_b
.shader
->info
.name
= ralloc_strdup(vs_b
.shader
, "meta_clear_color_vs");
50 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "meta_clear_color_fs");
52 const struct glsl_type
*position_type
= glsl_vec4_type();
53 const struct glsl_type
*color_type
= glsl_vec4_type();
55 nir_variable
*vs_out_pos
=
56 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, position_type
,
58 vs_out_pos
->data
.location
= VARYING_SLOT_POS
;
60 nir_intrinsic_instr
*in_color_load
= nir_intrinsic_instr_create(fs_b
.shader
, nir_intrinsic_load_push_constant
);
61 nir_intrinsic_set_base(in_color_load
, 0);
62 nir_intrinsic_set_range(in_color_load
, 16);
63 in_color_load
->src
[0] = nir_src_for_ssa(nir_imm_int(&fs_b
, 0));
64 in_color_load
->num_components
= 4;
65 nir_ssa_dest_init(&in_color_load
->instr
, &in_color_load
->dest
, 4, 32, "clear color");
66 nir_builder_instr_insert(&fs_b
, &in_color_load
->instr
);
68 nir_variable
*fs_out_color
=
69 nir_variable_create(fs_b
.shader
, nir_var_shader_out
, color_type
,
71 fs_out_color
->data
.location
= FRAG_RESULT_DATA0
+ frag_output
;
73 nir_store_var(&fs_b
, fs_out_color
, &in_color_load
->dest
.ssa
, 0xf);
75 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices(&vs_b
);
76 nir_store_var(&vs_b
, vs_out_pos
, outvec
, 0xf);
78 const struct glsl_type
*layer_type
= glsl_int_type();
79 nir_variable
*vs_out_layer
=
80 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, layer_type
,
82 vs_out_layer
->data
.location
= VARYING_SLOT_LAYER
;
83 vs_out_layer
->data
.interpolation
= INTERP_MODE_FLAT
;
84 nir_ssa_def
*inst_id
= nir_load_system_value(&vs_b
, nir_intrinsic_load_instance_id
, 0);
85 nir_ssa_def
*base_instance
= nir_load_system_value(&vs_b
, nir_intrinsic_load_base_instance
, 0);
87 nir_ssa_def
*layer_id
= nir_iadd(&vs_b
, inst_id
, base_instance
);
88 nir_store_var(&vs_b
, vs_out_layer
, layer_id
, 0x1);
90 *out_vs
= vs_b
.shader
;
91 *out_fs
= fs_b
.shader
;
95 create_pipeline(struct radv_device
*device
,
96 struct radv_render_pass
*render_pass
,
98 struct nir_shader
*vs_nir
,
99 struct nir_shader
*fs_nir
,
100 const VkPipelineVertexInputStateCreateInfo
*vi_state
,
101 const VkPipelineDepthStencilStateCreateInfo
*ds_state
,
102 const VkPipelineColorBlendStateCreateInfo
*cb_state
,
103 const VkPipelineLayout layout
,
104 const struct radv_graphics_pipeline_create_info
*extra
,
105 const VkAllocationCallbacks
*alloc
,
106 struct radv_pipeline
**pipeline
)
108 VkDevice device_h
= radv_device_to_handle(device
);
111 struct radv_shader_module vs_m
= { .nir
= vs_nir
};
112 struct radv_shader_module fs_m
= { .nir
= fs_nir
};
114 VkPipeline pipeline_h
= VK_NULL_HANDLE
;
115 result
= radv_graphics_pipeline_create(device_h
,
116 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
117 &(VkGraphicsPipelineCreateInfo
) {
118 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
119 .stageCount
= fs_nir
? 2 : 1,
120 .pStages
= (VkPipelineShaderStageCreateInfo
[]) {
122 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
123 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
124 .module
= radv_shader_module_to_handle(&vs_m
),
128 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
129 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
130 .module
= radv_shader_module_to_handle(&fs_m
),
134 .pVertexInputState
= vi_state
,
135 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
136 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
137 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
138 .primitiveRestartEnable
= false,
140 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
141 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
145 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
146 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
147 .rasterizerDiscardEnable
= false,
148 .polygonMode
= VK_POLYGON_MODE_FILL
,
149 .cullMode
= VK_CULL_MODE_NONE
,
150 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
,
151 .depthBiasEnable
= false,
153 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
154 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
155 .rasterizationSamples
= samples
,
156 .sampleShadingEnable
= false,
158 .alphaToCoverageEnable
= false,
159 .alphaToOneEnable
= false,
161 .pDepthStencilState
= ds_state
,
162 .pColorBlendState
= cb_state
,
163 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
164 /* The meta clear pipeline declares all state as dynamic.
165 * As a consequence, vkCmdBindPipeline writes no dynamic state
166 * to the cmd buffer. Therefore, at the end of the meta clear,
167 * we need only restore dynamic state was vkCmdSet.
169 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
170 .dynamicStateCount
= 8,
171 .pDynamicStates
= (VkDynamicState
[]) {
172 /* Everything except stencil write mask */
173 VK_DYNAMIC_STATE_VIEWPORT
,
174 VK_DYNAMIC_STATE_SCISSOR
,
175 VK_DYNAMIC_STATE_LINE_WIDTH
,
176 VK_DYNAMIC_STATE_DEPTH_BIAS
,
177 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
178 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
179 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
180 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
185 .renderPass
= radv_render_pass_to_handle(render_pass
),
195 *pipeline
= radv_pipeline_from_handle(pipeline_h
);
201 create_color_renderpass(struct radv_device
*device
,
206 return radv_CreateRenderPass(radv_device_to_handle(device
),
207 &(VkRenderPassCreateInfo
) {
208 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
209 .attachmentCount
= 1,
210 .pAttachments
= &(VkAttachmentDescription
) {
213 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
214 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
215 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
216 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
219 .pSubpasses
= &(VkSubpassDescription
) {
220 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
221 .inputAttachmentCount
= 0,
222 .colorAttachmentCount
= 1,
223 .pColorAttachments
= &(VkAttachmentReference
) {
225 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
227 .pResolveAttachments
= NULL
,
228 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
229 .attachment
= VK_ATTACHMENT_UNUSED
,
230 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
232 .preserveAttachmentCount
= 1,
233 .pPreserveAttachments
= (uint32_t[]) { 0 },
235 .dependencyCount
= 0,
236 }, &device
->meta_state
.alloc
, pass
);
240 create_color_pipeline(struct radv_device
*device
,
242 uint32_t frag_output
,
243 struct radv_pipeline
**pipeline
,
246 struct nir_shader
*vs_nir
;
247 struct nir_shader
*fs_nir
;
249 build_color_shaders(&vs_nir
, &fs_nir
, frag_output
);
251 const VkPipelineVertexInputStateCreateInfo vi_state
= {
252 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
253 .vertexBindingDescriptionCount
= 0,
254 .vertexAttributeDescriptionCount
= 0,
257 const VkPipelineDepthStencilStateCreateInfo ds_state
= {
258 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
259 .depthTestEnable
= false,
260 .depthWriteEnable
= false,
261 .depthBoundsTestEnable
= false,
262 .stencilTestEnable
= false,
265 VkPipelineColorBlendAttachmentState blend_attachment_state
[MAX_RTS
] = { 0 };
266 blend_attachment_state
[frag_output
] = (VkPipelineColorBlendAttachmentState
) {
267 .blendEnable
= false,
268 .colorWriteMask
= VK_COLOR_COMPONENT_A_BIT
|
269 VK_COLOR_COMPONENT_R_BIT
|
270 VK_COLOR_COMPONENT_G_BIT
|
271 VK_COLOR_COMPONENT_B_BIT
,
274 const VkPipelineColorBlendStateCreateInfo cb_state
= {
275 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
276 .logicOpEnable
= false,
277 .attachmentCount
= MAX_RTS
,
278 .pAttachments
= blend_attachment_state
282 struct radv_graphics_pipeline_create_info extra
= {
283 .use_rectlist
= true,
285 result
= create_pipeline(device
, radv_render_pass_from_handle(pass
),
286 samples
, vs_nir
, fs_nir
, &vi_state
, &ds_state
, &cb_state
,
287 device
->meta_state
.clear_color_p_layout
,
288 &extra
, &device
->meta_state
.alloc
, pipeline
);
294 destroy_pipeline(struct radv_device
*device
, struct radv_pipeline
*pipeline
)
299 radv_DestroyPipeline(radv_device_to_handle(device
),
300 radv_pipeline_to_handle(pipeline
),
301 &device
->meta_state
.alloc
);
306 destroy_render_pass(struct radv_device
*device
, VkRenderPass renderpass
)
308 radv_DestroyRenderPass(radv_device_to_handle(device
), renderpass
,
309 &device
->meta_state
.alloc
);
313 radv_device_finish_meta_clear_state(struct radv_device
*device
)
315 struct radv_meta_state
*state
= &device
->meta_state
;
317 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->clear
); ++i
) {
318 for (uint32_t j
= 0; j
< ARRAY_SIZE(state
->clear
[i
].color_pipelines
); ++j
) {
319 destroy_pipeline(device
, state
->clear
[i
].color_pipelines
[j
]);
320 destroy_render_pass(device
, state
->clear
[i
].render_pass
[j
]);
323 for (uint32_t j
= 0; j
< NUM_DEPTH_CLEAR_PIPELINES
; j
++) {
324 destroy_pipeline(device
, state
->clear
[i
].depth_only_pipeline
[j
]);
325 destroy_pipeline(device
, state
->clear
[i
].stencil_only_pipeline
[j
]);
326 destroy_pipeline(device
, state
->clear
[i
].depthstencil_pipeline
[j
]);
328 destroy_render_pass(device
, state
->clear
[i
].depthstencil_rp
);
330 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
331 state
->clear_color_p_layout
,
333 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
334 state
->clear_depth_p_layout
,
339 emit_color_clear(struct radv_cmd_buffer
*cmd_buffer
,
340 const VkClearAttachment
*clear_att
,
341 const VkClearRect
*clear_rect
,
344 struct radv_device
*device
= cmd_buffer
->device
;
345 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
346 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
347 const uint32_t subpass_att
= clear_att
->colorAttachment
;
348 const uint32_t pass_att
= subpass
->color_attachments
[subpass_att
].attachment
;
349 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
350 const uint32_t samples
= iview
->image
->info
.samples
;
351 const uint32_t samples_log2
= ffs(samples
) - 1;
352 unsigned fs_key
= radv_format_meta_fs_key(iview
->vk_format
);
353 struct radv_pipeline
*pipeline
;
354 VkClearColorValue clear_value
= clear_att
->clearValue
.color
;
355 VkCommandBuffer cmd_buffer_h
= radv_cmd_buffer_to_handle(cmd_buffer
);
356 VkPipeline pipeline_h
;
359 radv_finishme("color clears incomplete");
362 pipeline
= device
->meta_state
.clear
[samples_log2
].color_pipelines
[fs_key
];
363 pipeline_h
= radv_pipeline_to_handle(pipeline
);
366 radv_finishme("color clears incomplete");
369 assert(samples_log2
< ARRAY_SIZE(device
->meta_state
.clear
));
371 assert(clear_att
->aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
);
372 assert(clear_att
->colorAttachment
< subpass
->color_count
);
374 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
375 device
->meta_state
.clear_color_p_layout
,
376 VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 16,
379 struct radv_subpass clear_subpass
= {
381 .color_attachments
= (VkAttachmentReference
[]) {
382 subpass
->color_attachments
[clear_att
->colorAttachment
]
384 .depth_stencil_attachment
= (VkAttachmentReference
) { VK_ATTACHMENT_UNUSED
, VK_IMAGE_LAYOUT_UNDEFINED
}
387 radv_cmd_buffer_set_subpass(cmd_buffer
, &clear_subpass
, false);
389 if (cmd_buffer
->state
.pipeline
!= pipeline
) {
390 radv_CmdBindPipeline(cmd_buffer_h
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
394 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
395 .x
= clear_rect
->rect
.offset
.x
,
396 .y
= clear_rect
->rect
.offset
.y
,
397 .width
= clear_rect
->rect
.extent
.width
,
398 .height
= clear_rect
->rect
.extent
.height
,
403 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &clear_rect
->rect
);
407 for_each_bit(i
, view_mask
)
408 radv_CmdDraw(cmd_buffer_h
, 3, 1, 0, i
);
410 radv_CmdDraw(cmd_buffer_h
, 3, clear_rect
->layerCount
, 0, clear_rect
->baseArrayLayer
);
413 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
418 build_depthstencil_shader(struct nir_shader
**out_vs
, struct nir_shader
**out_fs
)
420 nir_builder vs_b
, fs_b
;
422 nir_builder_init_simple_shader(&vs_b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
423 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
425 vs_b
.shader
->info
.name
= ralloc_strdup(vs_b
.shader
, "meta_clear_depthstencil_vs");
426 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "meta_clear_depthstencil_fs");
427 const struct glsl_type
*position_out_type
= glsl_vec4_type();
429 nir_variable
*vs_out_pos
=
430 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, position_out_type
,
432 vs_out_pos
->data
.location
= VARYING_SLOT_POS
;
434 nir_intrinsic_instr
*in_color_load
= nir_intrinsic_instr_create(vs_b
.shader
, nir_intrinsic_load_push_constant
);
435 nir_intrinsic_set_base(in_color_load
, 0);
436 nir_intrinsic_set_range(in_color_load
, 4);
437 in_color_load
->src
[0] = nir_src_for_ssa(nir_imm_int(&vs_b
, 0));
438 in_color_load
->num_components
= 1;
439 nir_ssa_dest_init(&in_color_load
->instr
, &in_color_load
->dest
, 1, 32, "depth value");
440 nir_builder_instr_insert(&vs_b
, &in_color_load
->instr
);
442 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices_comp2(&vs_b
, &in_color_load
->dest
.ssa
);
443 nir_store_var(&vs_b
, vs_out_pos
, outvec
, 0xf);
445 const struct glsl_type
*layer_type
= glsl_int_type();
446 nir_variable
*vs_out_layer
=
447 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, layer_type
,
449 vs_out_layer
->data
.location
= VARYING_SLOT_LAYER
;
450 vs_out_layer
->data
.interpolation
= INTERP_MODE_FLAT
;
451 nir_ssa_def
*inst_id
= nir_load_system_value(&vs_b
, nir_intrinsic_load_instance_id
, 0);
452 nir_ssa_def
*base_instance
= nir_load_system_value(&vs_b
, nir_intrinsic_load_base_instance
, 0);
454 nir_ssa_def
*layer_id
= nir_iadd(&vs_b
, inst_id
, base_instance
);
455 nir_store_var(&vs_b
, vs_out_layer
, layer_id
, 0x1);
457 *out_vs
= vs_b
.shader
;
458 *out_fs
= fs_b
.shader
;
462 create_depthstencil_renderpass(struct radv_device
*device
,
464 VkRenderPass
*render_pass
)
466 return radv_CreateRenderPass(radv_device_to_handle(device
),
467 &(VkRenderPassCreateInfo
) {
468 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
469 .attachmentCount
= 1,
470 .pAttachments
= &(VkAttachmentDescription
) {
471 .format
= VK_FORMAT_D32_SFLOAT_S8_UINT
,
473 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
474 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
475 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
476 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
479 .pSubpasses
= &(VkSubpassDescription
) {
480 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
481 .inputAttachmentCount
= 0,
482 .colorAttachmentCount
= 0,
483 .pColorAttachments
= NULL
,
484 .pResolveAttachments
= NULL
,
485 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
487 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
489 .preserveAttachmentCount
= 1,
490 .pPreserveAttachments
= (uint32_t[]) { 0 },
492 .dependencyCount
= 0,
493 }, &device
->meta_state
.alloc
, render_pass
);
497 create_depthstencil_pipeline(struct radv_device
*device
,
498 VkImageAspectFlags aspects
,
501 struct radv_pipeline
**pipeline
,
502 VkRenderPass render_pass
)
504 struct nir_shader
*vs_nir
, *fs_nir
;
506 build_depthstencil_shader(&vs_nir
, &fs_nir
);
508 const VkPipelineVertexInputStateCreateInfo vi_state
= {
509 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
510 .vertexBindingDescriptionCount
= 0,
511 .vertexAttributeDescriptionCount
= 0,
514 const VkPipelineDepthStencilStateCreateInfo ds_state
= {
515 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
516 .depthTestEnable
= (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
),
517 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
518 .depthWriteEnable
= (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
),
519 .depthBoundsTestEnable
= false,
520 .stencilTestEnable
= (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
),
522 .passOp
= VK_STENCIL_OP_REPLACE
,
523 .compareOp
= VK_COMPARE_OP_ALWAYS
,
524 .writeMask
= UINT32_MAX
,
525 .reference
= 0, /* dynamic */
527 .back
= { 0 /* dont care */ },
530 const VkPipelineColorBlendStateCreateInfo cb_state
= {
531 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
532 .logicOpEnable
= false,
533 .attachmentCount
= 0,
534 .pAttachments
= NULL
,
537 struct radv_graphics_pipeline_create_info extra
= {
538 .use_rectlist
= true,
541 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
542 extra
.db_depth_clear
= index
== DEPTH_CLEAR_SLOW
? false : true;
543 extra
.db_depth_disable_expclear
= index
== DEPTH_CLEAR_FAST_NO_EXPCLEAR
? true : false;
545 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
546 extra
.db_stencil_clear
= index
== DEPTH_CLEAR_SLOW
? false : true;
547 extra
.db_stencil_disable_expclear
= index
== DEPTH_CLEAR_FAST_NO_EXPCLEAR
? true : false;
549 result
= create_pipeline(device
, radv_render_pass_from_handle(render_pass
),
550 samples
, vs_nir
, fs_nir
, &vi_state
, &ds_state
, &cb_state
,
551 device
->meta_state
.clear_depth_p_layout
,
552 &extra
, &device
->meta_state
.alloc
, pipeline
);
556 static bool depth_view_can_fast_clear(struct radv_cmd_buffer
*cmd_buffer
,
557 const struct radv_image_view
*iview
,
558 VkImageLayout layout
,
559 const VkClearRect
*clear_rect
)
561 uint32_t queue_mask
= radv_image_queue_family_mask(iview
->image
,
562 cmd_buffer
->queue_family_index
,
563 cmd_buffer
->queue_family_index
);
564 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
565 clear_rect
->rect
.extent
.width
!= iview
->extent
.width
||
566 clear_rect
->rect
.extent
.height
!= iview
->extent
.height
)
568 if (iview
->image
->surface
.htile_size
&&
569 iview
->base_mip
== 0 &&
570 iview
->base_layer
== 0 &&
571 radv_layout_is_htile_compressed(iview
->image
, layout
, queue_mask
) &&
572 !radv_image_extent_compare(iview
->image
, &iview
->extent
))
577 static struct radv_pipeline
*
578 pick_depthstencil_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
579 struct radv_meta_state
*meta_state
,
580 const struct radv_image_view
*iview
,
582 VkImageAspectFlags aspects
,
583 VkImageLayout layout
,
584 const VkClearRect
*clear_rect
,
585 VkClearDepthStencilValue clear_value
)
587 bool fast
= depth_view_can_fast_clear(cmd_buffer
, iview
, layout
, clear_rect
);
588 int index
= DEPTH_CLEAR_SLOW
;
591 /* we don't know the previous clear values, so we always have
592 * the NO_EXPCLEAR path */
593 index
= DEPTH_CLEAR_FAST_NO_EXPCLEAR
;
597 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
598 return meta_state
->clear
[samples_log2
].depthstencil_pipeline
[index
];
599 case VK_IMAGE_ASPECT_DEPTH_BIT
:
600 return meta_state
->clear
[samples_log2
].depth_only_pipeline
[index
];
601 case VK_IMAGE_ASPECT_STENCIL_BIT
:
602 return meta_state
->clear
[samples_log2
].stencil_only_pipeline
[index
];
604 unreachable("expected depth or stencil aspect");
608 emit_depthstencil_clear(struct radv_cmd_buffer
*cmd_buffer
,
609 const VkClearAttachment
*clear_att
,
610 const VkClearRect
*clear_rect
)
612 struct radv_device
*device
= cmd_buffer
->device
;
613 struct radv_meta_state
*meta_state
= &device
->meta_state
;
614 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
615 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
616 const uint32_t pass_att
= subpass
->depth_stencil_attachment
.attachment
;
617 VkClearDepthStencilValue clear_value
= clear_att
->clearValue
.depthStencil
;
618 VkImageAspectFlags aspects
= clear_att
->aspectMask
;
619 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
620 const uint32_t samples
= iview
->image
->info
.samples
;
621 const uint32_t samples_log2
= ffs(samples
) - 1;
622 VkCommandBuffer cmd_buffer_h
= radv_cmd_buffer_to_handle(cmd_buffer
);
624 assert(aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
||
625 aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
||
626 aspects
== (VK_IMAGE_ASPECT_DEPTH_BIT
|
627 VK_IMAGE_ASPECT_STENCIL_BIT
));
628 assert(pass_att
!= VK_ATTACHMENT_UNUSED
);
630 if (!(aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
631 clear_value
.depth
= 1.0f
;
633 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
634 device
->meta_state
.clear_depth_p_layout
,
635 VK_SHADER_STAGE_VERTEX_BIT
, 0, 4,
638 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
639 radv_CmdSetStencilReference(cmd_buffer_h
, VK_STENCIL_FACE_FRONT_BIT
,
640 clear_value
.stencil
);
643 struct radv_pipeline
*pipeline
= pick_depthstencil_pipeline(cmd_buffer
,
648 subpass
->depth_stencil_attachment
.layout
,
651 if (cmd_buffer
->state
.pipeline
!= pipeline
) {
652 radv_CmdBindPipeline(cmd_buffer_h
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
653 radv_pipeline_to_handle(pipeline
));
656 if (depth_view_can_fast_clear(cmd_buffer
, iview
, subpass
->depth_stencil_attachment
.layout
, clear_rect
))
657 radv_set_depth_clear_regs(cmd_buffer
, iview
->image
, clear_value
, aspects
);
659 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
660 .x
= clear_rect
->rect
.offset
.x
,
661 .y
= clear_rect
->rect
.offset
.y
,
662 .width
= clear_rect
->rect
.extent
.width
,
663 .height
= clear_rect
->rect
.extent
.height
,
668 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &clear_rect
->rect
);
670 radv_CmdDraw(cmd_buffer_h
, 3, clear_rect
->layerCount
, 0, clear_rect
->baseArrayLayer
);
674 emit_fast_htile_clear(struct radv_cmd_buffer
*cmd_buffer
,
675 const VkClearAttachment
*clear_att
,
676 const VkClearRect
*clear_rect
,
677 enum radv_cmd_flush_bits
*pre_flush
,
678 enum radv_cmd_flush_bits
*post_flush
)
680 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
681 const uint32_t pass_att
= subpass
->depth_stencil_attachment
.attachment
;
682 VkImageLayout image_layout
= subpass
->depth_stencil_attachment
.layout
;
683 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
684 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
685 VkClearDepthStencilValue clear_value
= clear_att
->clearValue
.depthStencil
;
686 VkImageAspectFlags aspects
= clear_att
->aspectMask
;
689 if (!iview
->image
->surface
.htile_size
)
692 if (cmd_buffer
->device
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
)
695 if (!radv_layout_is_htile_compressed(iview
->image
, image_layout
, radv_image_queue_family_mask(iview
->image
, cmd_buffer
->queue_family_index
, cmd_buffer
->queue_family_index
)))
698 /* don't fast clear 3D */
699 if (iview
->image
->type
== VK_IMAGE_TYPE_3D
)
702 /* all layers are bound */
703 if (iview
->base_layer
> 0)
705 if (iview
->image
->info
.array_size
!= iview
->layer_count
)
708 if (iview
->image
->info
.levels
> 1)
711 if (!radv_image_extent_compare(iview
->image
, &iview
->extent
))
714 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
715 clear_rect
->rect
.extent
.width
!= iview
->image
->info
.width
||
716 clear_rect
->rect
.extent
.height
!= iview
->image
->info
.height
)
719 if (clear_rect
->baseArrayLayer
!= 0)
721 if (clear_rect
->layerCount
!= iview
->image
->info
.array_size
)
724 if ((clear_value
.depth
!= 0.0 && clear_value
.depth
!= 1.0) || !(aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
727 if (vk_format_aspects(iview
->image
->vk_format
) & VK_IMAGE_ASPECT_STENCIL_BIT
) {
728 if (clear_value
.stencil
!= 0 || !(aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
))
730 clear_word
= clear_value
.depth
? 0xfffc0000 : 0;
732 clear_word
= clear_value
.depth
? 0xfffffff0 : 0;
735 cmd_buffer
->state
.flush_bits
|= (RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
736 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
) & ~ *pre_flush
;
737 *pre_flush
|= cmd_buffer
->state
.flush_bits
;
739 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
740 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
742 radv_fill_buffer(cmd_buffer
, iview
->image
->bo
,
743 iview
->image
->offset
+ iview
->image
->htile_offset
,
744 iview
->image
->surface
.htile_size
, clear_word
);
747 radv_set_depth_clear_regs(cmd_buffer
, iview
->image
, clear_value
, aspects
);
749 *post_flush
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
750 RADV_CMD_FLAG_INV_VMEM_L1
|
751 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
753 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
754 RADV_CMD_FLAG_INV_VMEM_L1
|
755 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
761 static VkFormat pipeline_formats
[] = {
762 VK_FORMAT_R8G8B8A8_UNORM
,
763 VK_FORMAT_R8G8B8A8_UINT
,
764 VK_FORMAT_R8G8B8A8_SINT
,
765 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
766 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
767 VK_FORMAT_R16G16B16A16_UNORM
,
768 VK_FORMAT_R16G16B16A16_SNORM
,
769 VK_FORMAT_R16G16B16A16_UINT
,
770 VK_FORMAT_R16G16B16A16_SINT
,
771 VK_FORMAT_R32_SFLOAT
,
772 VK_FORMAT_R32G32_SFLOAT
,
773 VK_FORMAT_R32G32B32A32_SFLOAT
777 radv_device_init_meta_clear_state(struct radv_device
*device
)
780 struct radv_meta_state
*state
= &device
->meta_state
;
782 memset(&device
->meta_state
.clear
, 0, sizeof(device
->meta_state
.clear
));
784 VkPipelineLayoutCreateInfo pl_color_create_info
= {
785 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
787 .pushConstantRangeCount
= 1,
788 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 16},
791 res
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
792 &pl_color_create_info
,
793 &device
->meta_state
.alloc
,
794 &device
->meta_state
.clear_color_p_layout
);
795 if (res
!= VK_SUCCESS
)
798 VkPipelineLayoutCreateInfo pl_depth_create_info
= {
799 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
801 .pushConstantRangeCount
= 1,
802 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_VERTEX_BIT
, 0, 4},
805 res
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
806 &pl_depth_create_info
,
807 &device
->meta_state
.alloc
,
808 &device
->meta_state
.clear_depth_p_layout
);
809 if (res
!= VK_SUCCESS
)
812 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->clear
); ++i
) {
813 uint32_t samples
= 1 << i
;
814 for (uint32_t j
= 0; j
< ARRAY_SIZE(pipeline_formats
); ++j
) {
815 VkFormat format
= pipeline_formats
[j
];
816 unsigned fs_key
= radv_format_meta_fs_key(format
);
817 assert(!state
->clear
[i
].color_pipelines
[fs_key
]);
819 res
= create_color_renderpass(device
, format
, samples
,
820 &state
->clear
[i
].render_pass
[fs_key
]);
821 if (res
!= VK_SUCCESS
)
824 res
= create_color_pipeline(device
, samples
, 0, &state
->clear
[i
].color_pipelines
[fs_key
],
825 state
->clear
[i
].render_pass
[fs_key
]);
826 if (res
!= VK_SUCCESS
)
831 res
= create_depthstencil_renderpass(device
,
833 &state
->clear
[i
].depthstencil_rp
);
834 if (res
!= VK_SUCCESS
)
837 for (uint32_t j
= 0; j
< NUM_DEPTH_CLEAR_PIPELINES
; j
++) {
838 res
= create_depthstencil_pipeline(device
,
839 VK_IMAGE_ASPECT_DEPTH_BIT
,
842 &state
->clear
[i
].depth_only_pipeline
[j
],
843 state
->clear
[i
].depthstencil_rp
);
844 if (res
!= VK_SUCCESS
)
847 res
= create_depthstencil_pipeline(device
,
848 VK_IMAGE_ASPECT_STENCIL_BIT
,
851 &state
->clear
[i
].stencil_only_pipeline
[j
],
852 state
->clear
[i
].depthstencil_rp
);
853 if (res
!= VK_SUCCESS
)
856 res
= create_depthstencil_pipeline(device
,
857 VK_IMAGE_ASPECT_DEPTH_BIT
|
858 VK_IMAGE_ASPECT_STENCIL_BIT
,
861 &state
->clear
[i
].depthstencil_pipeline
[j
],
862 state
->clear
[i
].depthstencil_rp
);
863 if (res
!= VK_SUCCESS
)
870 radv_device_finish_meta_clear_state(device
);
874 static void vi_get_fast_clear_parameters(VkFormat format
,
875 const VkClearColorValue
*clear_value
,
876 uint32_t* reset_value
,
877 bool *can_avoid_fast_clear_elim
)
881 bool main_value
= false;
882 bool extra_value
= false;
884 *can_avoid_fast_clear_elim
= false;
886 *reset_value
= 0x20202020U
;
888 const struct vk_format_description
*desc
= vk_format_description(format
);
889 if (format
== VK_FORMAT_B10G11R11_UFLOAT_PACK32
||
890 format
== VK_FORMAT_R5G6B5_UNORM_PACK16
||
891 format
== VK_FORMAT_B5G6R5_UNORM_PACK16
)
893 else if (desc
->layout
== VK_FORMAT_LAYOUT_PLAIN
) {
894 if (radv_translate_colorswap(format
, false) <= 1)
895 extra_channel
= desc
->nr_channels
- 1;
901 for (i
= 0; i
< 4; i
++) {
902 int index
= desc
->swizzle
[i
] - VK_SWIZZLE_X
;
903 if (desc
->swizzle
[i
] < VK_SWIZZLE_X
||
904 desc
->swizzle
[i
] > VK_SWIZZLE_W
)
907 if (desc
->channel
[i
].pure_integer
&&
908 desc
->channel
[i
].type
== VK_FORMAT_TYPE_SIGNED
) {
909 /* Use the maximum value for clamping the clear color. */
910 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
912 values
[i
] = clear_value
->int32
[i
] != 0;
913 if (clear_value
->int32
[i
] != 0 && MIN2(clear_value
->int32
[i
], max
) != max
)
915 } else if (desc
->channel
[i
].pure_integer
&&
916 desc
->channel
[i
].type
== VK_FORMAT_TYPE_UNSIGNED
) {
917 /* Use the maximum value for clamping the clear color. */
918 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
920 values
[i
] = clear_value
->uint32
[i
] != 0U;
921 if (clear_value
->uint32
[i
] != 0U && MIN2(clear_value
->uint32
[i
], max
) != max
)
924 values
[i
] = clear_value
->float32
[i
] != 0.0F
;
925 if (clear_value
->float32
[i
] != 0.0F
&& clear_value
->float32
[i
] != 1.0F
)
929 if (index
== extra_channel
)
930 extra_value
= values
[i
];
932 main_value
= values
[i
];
935 for (int i
= 0; i
< 4; ++i
)
936 if (values
[i
] != main_value
&&
937 desc
->swizzle
[i
] - VK_SWIZZLE_X
!= extra_channel
&&
938 desc
->swizzle
[i
] >= VK_SWIZZLE_X
&&
939 desc
->swizzle
[i
] <= VK_SWIZZLE_W
)
942 *can_avoid_fast_clear_elim
= true;
944 *reset_value
|= 0x80808080U
;
947 *reset_value
|= 0x40404040U
;
952 emit_fast_color_clear(struct radv_cmd_buffer
*cmd_buffer
,
953 const VkClearAttachment
*clear_att
,
954 const VkClearRect
*clear_rect
,
955 enum radv_cmd_flush_bits
*pre_flush
,
956 enum radv_cmd_flush_bits
*post_flush
,
959 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
960 const uint32_t subpass_att
= clear_att
->colorAttachment
;
961 const uint32_t pass_att
= subpass
->color_attachments
[subpass_att
].attachment
;
962 VkImageLayout image_layout
= subpass
->color_attachments
[subpass_att
].layout
;
963 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
964 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
965 VkClearColorValue clear_value
= clear_att
->clearValue
.color
;
966 uint32_t clear_color
[2];
969 if (!iview
->image
->cmask
.size
&& !iview
->image
->surface
.dcc_size
)
972 if (cmd_buffer
->device
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
)
975 if (!radv_layout_can_fast_clear(iview
->image
, image_layout
, radv_image_queue_family_mask(iview
->image
, cmd_buffer
->queue_family_index
, cmd_buffer
->queue_family_index
)))
978 /* don't fast clear 3D */
979 if (iview
->image
->type
== VK_IMAGE_TYPE_3D
)
982 /* all layers are bound */
983 if (iview
->base_layer
> 0)
985 if (iview
->image
->info
.array_size
!= iview
->layer_count
)
988 if (iview
->image
->info
.levels
> 1)
991 if (iview
->image
->surface
.is_linear
)
993 if (!radv_image_extent_compare(iview
->image
, &iview
->extent
))
996 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
997 clear_rect
->rect
.extent
.width
!= iview
->image
->info
.width
||
998 clear_rect
->rect
.extent
.height
!= iview
->image
->info
.height
)
1001 if (view_mask
&& (iview
->image
->info
.array_size
>= 32 ||
1002 (1u << iview
->image
->info
.array_size
) - 1u != view_mask
))
1004 if (!view_mask
&& clear_rect
->baseArrayLayer
!= 0)
1006 if (!view_mask
&& clear_rect
->layerCount
!= iview
->image
->info
.array_size
)
1009 /* RB+ doesn't work with CMASK fast clear on Stoney. */
1010 if (!iview
->image
->surface
.dcc_size
&&
1011 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_STONEY
)
1015 ret
= radv_format_pack_clear_color(iview
->image
->vk_format
,
1016 clear_color
, &clear_value
);
1021 cmd_buffer
->state
.flush_bits
|= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1022 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
) & ~ *pre_flush
;
1023 *pre_flush
|= cmd_buffer
->state
.flush_bits
;
1025 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1026 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1027 /* clear cmask buffer */
1028 if (iview
->image
->surface
.dcc_size
) {
1029 uint32_t reset_value
;
1030 bool can_avoid_fast_clear_elim
;
1031 vi_get_fast_clear_parameters(iview
->image
->vk_format
,
1032 &clear_value
, &reset_value
,
1033 &can_avoid_fast_clear_elim
);
1035 radv_fill_buffer(cmd_buffer
, iview
->image
->bo
,
1036 iview
->image
->offset
+ iview
->image
->dcc_offset
,
1037 iview
->image
->surface
.dcc_size
, reset_value
);
1038 radv_set_dcc_need_cmask_elim_pred(cmd_buffer
, iview
->image
,
1039 !can_avoid_fast_clear_elim
);
1042 if (iview
->image
->surface
.bpe
> 8) {
1043 /* 128 bit formats not supported */
1046 radv_fill_buffer(cmd_buffer
, iview
->image
->bo
,
1047 iview
->image
->offset
+ iview
->image
->cmask
.offset
,
1048 iview
->image
->cmask
.size
, 0);
1052 *post_flush
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
1053 RADV_CMD_FLAG_INV_VMEM_L1
|
1054 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
1056 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
1057 RADV_CMD_FLAG_INV_VMEM_L1
|
1058 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
1060 radv_set_color_clear_regs(cmd_buffer
, iview
->image
, subpass_att
, clear_color
);
1068 * The parameters mean that same as those in vkCmdClearAttachments.
1071 emit_clear(struct radv_cmd_buffer
*cmd_buffer
,
1072 const VkClearAttachment
*clear_att
,
1073 const VkClearRect
*clear_rect
,
1074 enum radv_cmd_flush_bits
*pre_flush
,
1075 enum radv_cmd_flush_bits
*post_flush
,
1078 if (clear_att
->aspectMask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
1079 if (!emit_fast_color_clear(cmd_buffer
, clear_att
, clear_rect
,
1080 pre_flush
, post_flush
, view_mask
))
1081 emit_color_clear(cmd_buffer
, clear_att
, clear_rect
, view_mask
);
1083 assert(clear_att
->aspectMask
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
1084 VK_IMAGE_ASPECT_STENCIL_BIT
));
1085 if (!emit_fast_htile_clear(cmd_buffer
, clear_att
, clear_rect
,
1086 pre_flush
, post_flush
))
1087 emit_depthstencil_clear(cmd_buffer
, clear_att
, clear_rect
);
1092 subpass_needs_clear(const struct radv_cmd_buffer
*cmd_buffer
)
1094 const struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1097 if (!cmd_state
->subpass
)
1099 uint32_t view_mask
= cmd_state
->subpass
->view_mask
;
1100 ds
= cmd_state
->subpass
->depth_stencil_attachment
.attachment
;
1101 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
1102 uint32_t a
= cmd_state
->subpass
->color_attachments
[i
].attachment
;
1103 if (a
!= VK_ATTACHMENT_UNUSED
&&
1104 cmd_state
->attachments
[a
].pending_clear_aspects
&&
1105 (!view_mask
|| (view_mask
& ~cmd_state
->attachments
[a
].cleared_views
))) {
1110 if (ds
!= VK_ATTACHMENT_UNUSED
&&
1111 cmd_state
->attachments
[ds
].pending_clear_aspects
&&
1112 (!view_mask
|| (view_mask
& ~cmd_state
->attachments
[ds
].cleared_views
))) {
1120 * Emit any pending attachment clears for the current subpass.
1122 * @see radv_attachment_state::pending_clear_aspects
1125 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
)
1127 struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1128 struct radv_meta_saved_state saved_state
;
1129 enum radv_cmd_flush_bits pre_flush
= 0;
1130 enum radv_cmd_flush_bits post_flush
= 0;
1131 uint32_t view_mask
= cmd_buffer
->state
.subpass
->view_mask
;
1133 if (!subpass_needs_clear(cmd_buffer
))
1136 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state
, cmd_buffer
);
1138 VkClearRect clear_rect
= {
1139 .rect
= cmd_state
->render_area
,
1140 .baseArrayLayer
= 0,
1141 .layerCount
= cmd_state
->framebuffer
->layers
,
1144 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
1145 uint32_t a
= cmd_state
->subpass
->color_attachments
[i
].attachment
;
1147 if (a
== VK_ATTACHMENT_UNUSED
||
1148 !cmd_state
->attachments
[a
].pending_clear_aspects
||
1149 (view_mask
&& !(view_mask
& ~cmd_state
->attachments
[a
].cleared_views
)))
1152 assert(cmd_state
->attachments
[a
].pending_clear_aspects
==
1153 VK_IMAGE_ASPECT_COLOR_BIT
);
1155 VkClearAttachment clear_att
= {
1156 .aspectMask
= VK_IMAGE_ASPECT_COLOR_BIT
,
1157 .colorAttachment
= i
, /* Use attachment index relative to subpass */
1158 .clearValue
= cmd_state
->attachments
[a
].clear_value
,
1161 emit_clear(cmd_buffer
, &clear_att
, &clear_rect
, &pre_flush
, &post_flush
,
1162 view_mask
& ~cmd_state
->attachments
[a
].cleared_views
);
1164 cmd_state
->attachments
[a
].cleared_views
|= view_mask
;
1166 cmd_state
->attachments
[a
].pending_clear_aspects
= 0;
1169 uint32_t ds
= cmd_state
->subpass
->depth_stencil_attachment
.attachment
;
1171 if (ds
!= VK_ATTACHMENT_UNUSED
) {
1173 if (cmd_state
->attachments
[ds
].pending_clear_aspects
&&
1174 (!view_mask
|| (view_mask
& ~cmd_state
->attachments
[ds
].cleared_views
))) {
1176 VkClearAttachment clear_att
= {
1177 .aspectMask
= cmd_state
->attachments
[ds
].pending_clear_aspects
,
1178 .clearValue
= cmd_state
->attachments
[ds
].clear_value
,
1181 emit_clear(cmd_buffer
, &clear_att
, &clear_rect
,
1182 &pre_flush
, &post_flush
,
1183 view_mask
& ~cmd_state
->attachments
[ds
].cleared_views
);
1185 cmd_state
->attachments
[ds
].cleared_views
|= view_mask
;
1187 cmd_state
->attachments
[ds
].pending_clear_aspects
= 0;
1191 radv_meta_restore(&saved_state
, cmd_buffer
);
1192 cmd_buffer
->state
.flush_bits
|= post_flush
;
1196 radv_clear_image_layer(struct radv_cmd_buffer
*cmd_buffer
,
1197 struct radv_image
*image
,
1198 VkImageLayout image_layout
,
1199 const VkImageSubresourceRange
*range
,
1200 VkFormat format
, int level
, int layer
,
1201 const VkClearValue
*clear_val
)
1203 VkDevice device_h
= radv_device_to_handle(cmd_buffer
->device
);
1204 struct radv_image_view iview
;
1205 radv_image_view_init(&iview
, cmd_buffer
->device
,
1206 &(VkImageViewCreateInfo
) {
1207 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
1208 .image
= radv_image_to_handle(image
),
1209 .viewType
= radv_meta_get_view_type(image
),
1211 .subresourceRange
= {
1212 .aspectMask
= range
->aspectMask
,
1213 .baseMipLevel
= range
->baseMipLevel
+ level
,
1215 .baseArrayLayer
= range
->baseArrayLayer
+ layer
,
1221 radv_CreateFramebuffer(device_h
,
1222 &(VkFramebufferCreateInfo
) {
1223 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
1224 .attachmentCount
= 1,
1225 .pAttachments
= (VkImageView
[]) {
1226 radv_image_view_to_handle(&iview
),
1228 .width
= iview
.extent
.width
,
1229 .height
= iview
.extent
.height
,
1232 &cmd_buffer
->pool
->alloc
,
1235 VkAttachmentDescription att_desc
= {
1236 .format
= iview
.vk_format
,
1237 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1238 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1239 .stencilLoadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1240 .stencilStoreOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1241 .initialLayout
= image_layout
,
1242 .finalLayout
= image_layout
,
1245 VkSubpassDescription subpass_desc
= {
1246 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
1247 .inputAttachmentCount
= 0,
1248 .colorAttachmentCount
= 0,
1249 .pColorAttachments
= NULL
,
1250 .pResolveAttachments
= NULL
,
1251 .pDepthStencilAttachment
= NULL
,
1252 .preserveAttachmentCount
= 0,
1253 .pPreserveAttachments
= NULL
,
1256 const VkAttachmentReference att_ref
= {
1258 .layout
= image_layout
,
1261 if (range
->aspectMask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
1262 subpass_desc
.colorAttachmentCount
= 1;
1263 subpass_desc
.pColorAttachments
= &att_ref
;
1265 subpass_desc
.pDepthStencilAttachment
= &att_ref
;
1269 radv_CreateRenderPass(device_h
,
1270 &(VkRenderPassCreateInfo
) {
1271 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
1272 .attachmentCount
= 1,
1273 .pAttachments
= &att_desc
,
1275 .pSubpasses
= &subpass_desc
,
1277 &cmd_buffer
->pool
->alloc
,
1280 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
1281 &(VkRenderPassBeginInfo
) {
1282 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
1284 .offset
= { 0, 0, },
1286 .width
= iview
.extent
.width
,
1287 .height
= iview
.extent
.height
,
1292 .clearValueCount
= 0,
1293 .pClearValues
= NULL
,
1295 VK_SUBPASS_CONTENTS_INLINE
);
1297 VkClearAttachment clear_att
= {
1298 .aspectMask
= range
->aspectMask
,
1299 .colorAttachment
= 0,
1300 .clearValue
= *clear_val
,
1303 VkClearRect clear_rect
= {
1306 .extent
= { iview
.extent
.width
, iview
.extent
.height
},
1308 .baseArrayLayer
= range
->baseArrayLayer
,
1309 .layerCount
= 1, /* FINISHME: clear multi-layer framebuffer */
1312 emit_clear(cmd_buffer
, &clear_att
, &clear_rect
, NULL
, NULL
, 0);
1314 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
));
1315 radv_DestroyRenderPass(device_h
, pass
,
1316 &cmd_buffer
->pool
->alloc
);
1317 radv_DestroyFramebuffer(device_h
, fb
,
1318 &cmd_buffer
->pool
->alloc
);
1321 radv_cmd_clear_image(struct radv_cmd_buffer
*cmd_buffer
,
1322 struct radv_image
*image
,
1323 VkImageLayout image_layout
,
1324 const VkClearValue
*clear_value
,
1325 uint32_t range_count
,
1326 const VkImageSubresourceRange
*ranges
,
1329 VkFormat format
= image
->vk_format
;
1330 VkClearValue internal_clear_value
= *clear_value
;
1332 if (format
== VK_FORMAT_E5B9G9R9_UFLOAT_PACK32
) {
1334 format
= VK_FORMAT_R32_UINT
;
1335 value
= float3_to_rgb9e5(clear_value
->color
.float32
);
1336 internal_clear_value
.color
.uint32
[0] = value
;
1339 if (format
== VK_FORMAT_R4G4_UNORM_PACK8
) {
1341 format
= VK_FORMAT_R8_UINT
;
1342 r
= float_to_ubyte(clear_value
->color
.float32
[0]) >> 4;
1343 g
= float_to_ubyte(clear_value
->color
.float32
[1]) >> 4;
1344 internal_clear_value
.color
.uint32
[0] = (r
<< 4) | (g
& 0xf);
1347 for (uint32_t r
= 0; r
< range_count
; r
++) {
1348 const VkImageSubresourceRange
*range
= &ranges
[r
];
1349 for (uint32_t l
= 0; l
< radv_get_levelCount(image
, range
); ++l
) {
1350 const uint32_t layer_count
= image
->type
== VK_IMAGE_TYPE_3D
?
1351 radv_minify(image
->info
.depth
, range
->baseMipLevel
+ l
) :
1352 radv_get_layerCount(image
, range
);
1353 for (uint32_t s
= 0; s
< layer_count
; ++s
) {
1356 struct radv_meta_blit2d_surf surf
;
1357 surf
.format
= format
;
1359 surf
.level
= range
->baseMipLevel
+ l
;
1360 surf
.layer
= range
->baseArrayLayer
+ s
;
1361 surf
.aspect_mask
= range
->aspectMask
;
1362 radv_meta_clear_image_cs(cmd_buffer
, &surf
,
1363 &internal_clear_value
.color
);
1365 radv_clear_image_layer(cmd_buffer
, image
, image_layout
,
1366 range
, format
, l
, s
, &internal_clear_value
);
1373 union meta_saved_state
{
1374 struct radv_meta_saved_state gfx
;
1375 struct radv_meta_saved_compute_state compute
;
1378 void radv_CmdClearColorImage(
1379 VkCommandBuffer commandBuffer
,
1381 VkImageLayout imageLayout
,
1382 const VkClearColorValue
* pColor
,
1383 uint32_t rangeCount
,
1384 const VkImageSubresourceRange
* pRanges
)
1386 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1387 RADV_FROM_HANDLE(radv_image
, image
, image_h
);
1388 union meta_saved_state saved_state
;
1389 bool cs
= cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
;
1392 radv_meta_begin_cleari(cmd_buffer
, &saved_state
.compute
);
1394 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state
.gfx
, cmd_buffer
);
1396 radv_cmd_clear_image(cmd_buffer
, image
, imageLayout
,
1397 (const VkClearValue
*) pColor
,
1398 rangeCount
, pRanges
, cs
);
1401 radv_meta_end_cleari(cmd_buffer
, &saved_state
.compute
);
1403 radv_meta_restore(&saved_state
.gfx
, cmd_buffer
);
1406 void radv_CmdClearDepthStencilImage(
1407 VkCommandBuffer commandBuffer
,
1409 VkImageLayout imageLayout
,
1410 const VkClearDepthStencilValue
* pDepthStencil
,
1411 uint32_t rangeCount
,
1412 const VkImageSubresourceRange
* pRanges
)
1414 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1415 RADV_FROM_HANDLE(radv_image
, image
, image_h
);
1416 struct radv_meta_saved_state saved_state
;
1418 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state
, cmd_buffer
);
1420 radv_cmd_clear_image(cmd_buffer
, image
, imageLayout
,
1421 (const VkClearValue
*) pDepthStencil
,
1422 rangeCount
, pRanges
, false);
1424 radv_meta_restore(&saved_state
, cmd_buffer
);
1427 void radv_CmdClearAttachments(
1428 VkCommandBuffer commandBuffer
,
1429 uint32_t attachmentCount
,
1430 const VkClearAttachment
* pAttachments
,
1432 const VkClearRect
* pRects
)
1434 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1435 struct radv_meta_saved_state saved_state
;
1436 enum radv_cmd_flush_bits pre_flush
= 0;
1437 enum radv_cmd_flush_bits post_flush
= 0;
1439 if (!cmd_buffer
->state
.subpass
)
1442 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state
, cmd_buffer
);
1444 /* FINISHME: We can do better than this dumb loop. It thrashes too much
1447 for (uint32_t a
= 0; a
< attachmentCount
; ++a
) {
1448 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
1449 emit_clear(cmd_buffer
, &pAttachments
[a
], &pRects
[r
], &pre_flush
, &post_flush
,
1450 cmd_buffer
->state
.subpass
->view_mask
);
1454 radv_meta_restore(&saved_state
, cmd_buffer
);
1455 cmd_buffer
->state
.flush_bits
|= post_flush
;