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[mesa.git] / src / amd / vulkan / radv_meta_clear.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_debug.h"
25 #include "radv_meta.h"
26 #include "radv_private.h"
27 #include "nir/nir_builder.h"
28
29 #include "util/format_rgb9e5.h"
30 #include "vk_format.h"
31
32 enum {
33 DEPTH_CLEAR_SLOW,
34 DEPTH_CLEAR_FAST_EXPCLEAR,
35 DEPTH_CLEAR_FAST_NO_EXPCLEAR
36 };
37
38 static void
39 build_color_shaders(struct nir_shader **out_vs,
40 struct nir_shader **out_fs,
41 uint32_t frag_output)
42 {
43 nir_builder vs_b;
44 nir_builder fs_b;
45
46 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
47 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
48
49 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
50 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
51
52 const struct glsl_type *position_type = glsl_vec4_type();
53 const struct glsl_type *color_type = glsl_vec4_type();
54
55 nir_variable *vs_out_pos =
56 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
57 "gl_Position");
58 vs_out_pos->data.location = VARYING_SLOT_POS;
59
60 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
61 nir_intrinsic_set_base(in_color_load, 0);
62 nir_intrinsic_set_range(in_color_load, 16);
63 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
64 in_color_load->num_components = 4;
65 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
66 nir_builder_instr_insert(&fs_b, &in_color_load->instr);
67
68 nir_variable *fs_out_color =
69 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
70 "f_color");
71 fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
72
73 nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
74
75 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
76 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
77
78 const struct glsl_type *layer_type = glsl_int_type();
79 nir_variable *vs_out_layer =
80 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
81 "v_layer");
82 vs_out_layer->data.location = VARYING_SLOT_LAYER;
83 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
84 nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
85 nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
86
87 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
88 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
89
90 *out_vs = vs_b.shader;
91 *out_fs = fs_b.shader;
92 }
93
94 static VkResult
95 create_pipeline(struct radv_device *device,
96 struct radv_render_pass *render_pass,
97 uint32_t samples,
98 struct nir_shader *vs_nir,
99 struct nir_shader *fs_nir,
100 const VkPipelineVertexInputStateCreateInfo *vi_state,
101 const VkPipelineDepthStencilStateCreateInfo *ds_state,
102 const VkPipelineColorBlendStateCreateInfo *cb_state,
103 const VkPipelineLayout layout,
104 const struct radv_graphics_pipeline_create_info *extra,
105 const VkAllocationCallbacks *alloc,
106 VkPipeline *pipeline)
107 {
108 VkDevice device_h = radv_device_to_handle(device);
109 VkResult result;
110
111 struct radv_shader_module vs_m = { .nir = vs_nir };
112 struct radv_shader_module fs_m = { .nir = fs_nir };
113
114 result = radv_graphics_pipeline_create(device_h,
115 radv_pipeline_cache_to_handle(&device->meta_state.cache),
116 &(VkGraphicsPipelineCreateInfo) {
117 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
118 .stageCount = fs_nir ? 2 : 1,
119 .pStages = (VkPipelineShaderStageCreateInfo[]) {
120 {
121 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
122 .stage = VK_SHADER_STAGE_VERTEX_BIT,
123 .module = radv_shader_module_to_handle(&vs_m),
124 .pName = "main",
125 },
126 {
127 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
128 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
129 .module = radv_shader_module_to_handle(&fs_m),
130 .pName = "main",
131 },
132 },
133 .pVertexInputState = vi_state,
134 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
135 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
136 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
137 .primitiveRestartEnable = false,
138 },
139 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
140 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
141 .viewportCount = 1,
142 .scissorCount = 1,
143 },
144 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
145 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
146 .rasterizerDiscardEnable = false,
147 .polygonMode = VK_POLYGON_MODE_FILL,
148 .cullMode = VK_CULL_MODE_NONE,
149 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
150 .depthBiasEnable = false,
151 },
152 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
153 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
154 .rasterizationSamples = samples,
155 .sampleShadingEnable = false,
156 .pSampleMask = NULL,
157 .alphaToCoverageEnable = false,
158 .alphaToOneEnable = false,
159 },
160 .pDepthStencilState = ds_state,
161 .pColorBlendState = cb_state,
162 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
163 /* The meta clear pipeline declares all state as dynamic.
164 * As a consequence, vkCmdBindPipeline writes no dynamic state
165 * to the cmd buffer. Therefore, at the end of the meta clear,
166 * we need only restore dynamic state was vkCmdSet.
167 */
168 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
169 .dynamicStateCount = 8,
170 .pDynamicStates = (VkDynamicState[]) {
171 /* Everything except stencil write mask */
172 VK_DYNAMIC_STATE_VIEWPORT,
173 VK_DYNAMIC_STATE_SCISSOR,
174 VK_DYNAMIC_STATE_LINE_WIDTH,
175 VK_DYNAMIC_STATE_DEPTH_BIAS,
176 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
177 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
178 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
179 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
180 },
181 },
182 .layout = layout,
183 .flags = 0,
184 .renderPass = radv_render_pass_to_handle(render_pass),
185 .subpass = 0,
186 },
187 extra,
188 alloc,
189 pipeline);
190
191 ralloc_free(vs_nir);
192 ralloc_free(fs_nir);
193
194 return result;
195 }
196
197 static VkResult
198 create_color_renderpass(struct radv_device *device,
199 VkFormat vk_format,
200 uint32_t samples,
201 VkRenderPass *pass)
202 {
203 mtx_lock(&device->meta_state.mtx);
204 if (*pass) {
205 mtx_unlock (&device->meta_state.mtx);
206 return VK_SUCCESS;
207 }
208
209 VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
210 &(VkRenderPassCreateInfo) {
211 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
212 .attachmentCount = 1,
213 .pAttachments = &(VkAttachmentDescription) {
214 .format = vk_format,
215 .samples = samples,
216 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
217 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
218 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
219 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
220 },
221 .subpassCount = 1,
222 .pSubpasses = &(VkSubpassDescription) {
223 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
224 .inputAttachmentCount = 0,
225 .colorAttachmentCount = 1,
226 .pColorAttachments = &(VkAttachmentReference) {
227 .attachment = 0,
228 .layout = VK_IMAGE_LAYOUT_GENERAL,
229 },
230 .pResolveAttachments = NULL,
231 .pDepthStencilAttachment = &(VkAttachmentReference) {
232 .attachment = VK_ATTACHMENT_UNUSED,
233 .layout = VK_IMAGE_LAYOUT_GENERAL,
234 },
235 .preserveAttachmentCount = 1,
236 .pPreserveAttachments = (uint32_t[]) { 0 },
237 },
238 .dependencyCount = 0,
239 }, &device->meta_state.alloc, pass);
240 mtx_unlock(&device->meta_state.mtx);
241 return result;
242 }
243
244 static VkResult
245 create_color_pipeline(struct radv_device *device,
246 uint32_t samples,
247 uint32_t frag_output,
248 VkPipeline *pipeline,
249 VkRenderPass pass)
250 {
251 struct nir_shader *vs_nir;
252 struct nir_shader *fs_nir;
253 VkResult result;
254
255 mtx_lock(&device->meta_state.mtx);
256 if (*pipeline) {
257 mtx_unlock(&device->meta_state.mtx);
258 return VK_SUCCESS;
259 }
260
261 build_color_shaders(&vs_nir, &fs_nir, frag_output);
262
263 const VkPipelineVertexInputStateCreateInfo vi_state = {
264 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
265 .vertexBindingDescriptionCount = 0,
266 .vertexAttributeDescriptionCount = 0,
267 };
268
269 const VkPipelineDepthStencilStateCreateInfo ds_state = {
270 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
271 .depthTestEnable = false,
272 .depthWriteEnable = false,
273 .depthBoundsTestEnable = false,
274 .stencilTestEnable = false,
275 };
276
277 VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
278 blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
279 .blendEnable = false,
280 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
281 VK_COLOR_COMPONENT_R_BIT |
282 VK_COLOR_COMPONENT_G_BIT |
283 VK_COLOR_COMPONENT_B_BIT,
284 };
285
286 const VkPipelineColorBlendStateCreateInfo cb_state = {
287 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
288 .logicOpEnable = false,
289 .attachmentCount = MAX_RTS,
290 .pAttachments = blend_attachment_state
291 };
292
293
294 struct radv_graphics_pipeline_create_info extra = {
295 .use_rectlist = true,
296 };
297 result = create_pipeline(device, radv_render_pass_from_handle(pass),
298 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
299 device->meta_state.clear_color_p_layout,
300 &extra, &device->meta_state.alloc, pipeline);
301
302 mtx_unlock(&device->meta_state.mtx);
303 return result;
304 }
305
306 static void
307 finish_meta_clear_htile_mask_state(struct radv_device *device)
308 {
309 struct radv_meta_state *state = &device->meta_state;
310
311 radv_DestroyPipeline(radv_device_to_handle(device),
312 state->clear_htile_mask_pipeline,
313 &state->alloc);
314 radv_DestroyPipelineLayout(radv_device_to_handle(device),
315 state->clear_htile_mask_p_layout,
316 &state->alloc);
317 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
318 state->clear_htile_mask_ds_layout,
319 &state->alloc);
320 }
321
322 void
323 radv_device_finish_meta_clear_state(struct radv_device *device)
324 {
325 struct radv_meta_state *state = &device->meta_state;
326
327 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
328 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
329 radv_DestroyPipeline(radv_device_to_handle(device),
330 state->clear[i].color_pipelines[j],
331 &state->alloc);
332 radv_DestroyRenderPass(radv_device_to_handle(device),
333 state->clear[i].render_pass[j],
334 &state->alloc);
335 }
336
337 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
338 radv_DestroyPipeline(radv_device_to_handle(device),
339 state->clear[i].depth_only_pipeline[j],
340 &state->alloc);
341 radv_DestroyPipeline(radv_device_to_handle(device),
342 state->clear[i].stencil_only_pipeline[j],
343 &state->alloc);
344 radv_DestroyPipeline(radv_device_to_handle(device),
345 state->clear[i].depthstencil_pipeline[j],
346 &state->alloc);
347 }
348 radv_DestroyRenderPass(radv_device_to_handle(device),
349 state->clear[i].depthstencil_rp,
350 &state->alloc);
351 }
352 radv_DestroyPipelineLayout(radv_device_to_handle(device),
353 state->clear_color_p_layout,
354 &state->alloc);
355 radv_DestroyPipelineLayout(radv_device_to_handle(device),
356 state->clear_depth_p_layout,
357 &state->alloc);
358
359 finish_meta_clear_htile_mask_state(device);
360 }
361
362 static void
363 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
364 const VkClearAttachment *clear_att,
365 const VkClearRect *clear_rect,
366 uint32_t view_mask)
367 {
368 struct radv_device *device = cmd_buffer->device;
369 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
370 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
371 const uint32_t subpass_att = clear_att->colorAttachment;
372 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
373 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
374 const uint32_t samples = iview->image->info.samples;
375 const uint32_t samples_log2 = ffs(samples) - 1;
376 unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
377 VkClearColorValue clear_value = clear_att->clearValue.color;
378 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
379 VkPipeline pipeline;
380
381 if (fs_key == -1) {
382 radv_finishme("color clears incomplete");
383 return;
384 }
385
386 if (device->meta_state.clear[samples_log2].render_pass[fs_key] == VK_NULL_HANDLE) {
387 VkResult ret = create_color_renderpass(device, radv_fs_key_format_exemplars[fs_key],
388 samples,
389 &device->meta_state.clear[samples_log2].render_pass[fs_key]);
390 if (ret != VK_SUCCESS) {
391 cmd_buffer->record_result = ret;
392 return;
393 }
394 }
395
396 if (device->meta_state.clear[samples_log2].color_pipelines[fs_key] == VK_NULL_HANDLE) {
397 VkResult ret = create_color_pipeline(device, samples, 0,
398 &device->meta_state.clear[samples_log2].color_pipelines[fs_key],
399 device->meta_state.clear[samples_log2].render_pass[fs_key]);
400 if (ret != VK_SUCCESS) {
401 cmd_buffer->record_result = ret;
402 return;
403 }
404 }
405
406 pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
407 if (!pipeline) {
408 radv_finishme("color clears incomplete");
409 return;
410 }
411 assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
412 assert(pipeline);
413 assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
414 assert(clear_att->colorAttachment < subpass->color_count);
415
416 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
417 device->meta_state.clear_color_p_layout,
418 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
419 &clear_value);
420
421 struct radv_subpass clear_subpass = {
422 .color_count = 1,
423 .color_attachments = (struct radv_subpass_attachment[]) {
424 subpass->color_attachments[clear_att->colorAttachment]
425 },
426 .depth_stencil_attachment = (struct radv_subpass_attachment) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
427 };
428
429 radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
430
431 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
432 pipeline);
433
434 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
435 .x = clear_rect->rect.offset.x,
436 .y = clear_rect->rect.offset.y,
437 .width = clear_rect->rect.extent.width,
438 .height = clear_rect->rect.extent.height,
439 .minDepth = 0.0f,
440 .maxDepth = 1.0f
441 });
442
443 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
444
445 if (view_mask) {
446 unsigned i;
447 for_each_bit(i, view_mask)
448 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
449 } else {
450 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
451 }
452
453 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
454 }
455
456
457 static void
458 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
459 {
460 nir_builder vs_b, fs_b;
461
462 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
463 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
464
465 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
466 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
467 const struct glsl_type *position_out_type = glsl_vec4_type();
468
469 nir_variable *vs_out_pos =
470 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
471 "gl_Position");
472 vs_out_pos->data.location = VARYING_SLOT_POS;
473
474 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
475 nir_intrinsic_set_base(in_color_load, 0);
476 nir_intrinsic_set_range(in_color_load, 4);
477 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
478 in_color_load->num_components = 1;
479 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
480 nir_builder_instr_insert(&vs_b, &in_color_load->instr);
481
482 nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
483 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
484
485 const struct glsl_type *layer_type = glsl_int_type();
486 nir_variable *vs_out_layer =
487 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
488 "v_layer");
489 vs_out_layer->data.location = VARYING_SLOT_LAYER;
490 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
491 nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
492 nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
493
494 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
495 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
496
497 *out_vs = vs_b.shader;
498 *out_fs = fs_b.shader;
499 }
500
501 static VkResult
502 create_depthstencil_renderpass(struct radv_device *device,
503 uint32_t samples,
504 VkRenderPass *render_pass)
505 {
506 mtx_lock(&device->meta_state.mtx);
507 if (*render_pass) {
508 mtx_unlock(&device->meta_state.mtx);
509 return VK_SUCCESS;
510 }
511
512 VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
513 &(VkRenderPassCreateInfo) {
514 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
515 .attachmentCount = 1,
516 .pAttachments = &(VkAttachmentDescription) {
517 .format = VK_FORMAT_D32_SFLOAT_S8_UINT,
518 .samples = samples,
519 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
520 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
521 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
522 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
523 },
524 .subpassCount = 1,
525 .pSubpasses = &(VkSubpassDescription) {
526 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
527 .inputAttachmentCount = 0,
528 .colorAttachmentCount = 0,
529 .pColorAttachments = NULL,
530 .pResolveAttachments = NULL,
531 .pDepthStencilAttachment = &(VkAttachmentReference) {
532 .attachment = 0,
533 .layout = VK_IMAGE_LAYOUT_GENERAL,
534 },
535 .preserveAttachmentCount = 1,
536 .pPreserveAttachments = (uint32_t[]) { 0 },
537 },
538 .dependencyCount = 0,
539 }, &device->meta_state.alloc, render_pass);
540 mtx_unlock(&device->meta_state.mtx);
541 return result;
542 }
543
544 static VkResult
545 create_depthstencil_pipeline(struct radv_device *device,
546 VkImageAspectFlags aspects,
547 uint32_t samples,
548 int index,
549 VkPipeline *pipeline,
550 VkRenderPass render_pass)
551 {
552 struct nir_shader *vs_nir, *fs_nir;
553 VkResult result;
554
555 mtx_lock(&device->meta_state.mtx);
556 if (*pipeline) {
557 mtx_unlock(&device->meta_state.mtx);
558 return VK_SUCCESS;
559 }
560
561 build_depthstencil_shader(&vs_nir, &fs_nir);
562
563 const VkPipelineVertexInputStateCreateInfo vi_state = {
564 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
565 .vertexBindingDescriptionCount = 0,
566 .vertexAttributeDescriptionCount = 0,
567 };
568
569 const VkPipelineDepthStencilStateCreateInfo ds_state = {
570 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
571 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
572 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
573 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
574 .depthBoundsTestEnable = false,
575 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
576 .front = {
577 .passOp = VK_STENCIL_OP_REPLACE,
578 .compareOp = VK_COMPARE_OP_ALWAYS,
579 .writeMask = UINT32_MAX,
580 .reference = 0, /* dynamic */
581 },
582 .back = { 0 /* dont care */ },
583 };
584
585 const VkPipelineColorBlendStateCreateInfo cb_state = {
586 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
587 .logicOpEnable = false,
588 .attachmentCount = 0,
589 .pAttachments = NULL,
590 };
591
592 struct radv_graphics_pipeline_create_info extra = {
593 .use_rectlist = true,
594 };
595
596 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
597 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
598 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
599 }
600 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
601 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
602 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
603 }
604 result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
605 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
606 device->meta_state.clear_depth_p_layout,
607 &extra, &device->meta_state.alloc, pipeline);
608
609 mtx_unlock(&device->meta_state.mtx);
610 return result;
611 }
612
613 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
614 const struct radv_image_view *iview,
615 VkImageAspectFlags aspects,
616 VkImageLayout layout,
617 const VkClearRect *clear_rect,
618 VkClearDepthStencilValue clear_value)
619 {
620 uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
621 cmd_buffer->queue_family_index,
622 cmd_buffer->queue_family_index);
623 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
624 clear_rect->rect.extent.width != iview->extent.width ||
625 clear_rect->rect.extent.height != iview->extent.height)
626 return false;
627 if (radv_image_is_tc_compat_htile(iview->image) &&
628 (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && clear_value.depth != 0.0 &&
629 clear_value.depth != 1.0) ||
630 ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0)))
631 return false;
632 if (radv_image_has_htile(iview->image) &&
633 iview->base_mip == 0 &&
634 iview->base_layer == 0 &&
635 radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
636 !radv_image_extent_compare(iview->image, &iview->extent))
637 return true;
638 return false;
639 }
640
641 static VkPipeline
642 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
643 struct radv_meta_state *meta_state,
644 const struct radv_image_view *iview,
645 int samples_log2,
646 VkImageAspectFlags aspects,
647 VkImageLayout layout,
648 const VkClearRect *clear_rect,
649 VkClearDepthStencilValue clear_value)
650 {
651 bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, clear_rect, clear_value);
652 int index = DEPTH_CLEAR_SLOW;
653 VkPipeline *pipeline;
654
655 if (fast) {
656 /* we don't know the previous clear values, so we always have
657 * the NO_EXPCLEAR path */
658 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
659 }
660
661 switch (aspects) {
662 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
663 pipeline = &meta_state->clear[samples_log2].depthstencil_pipeline[index];
664 break;
665 case VK_IMAGE_ASPECT_DEPTH_BIT:
666 pipeline = &meta_state->clear[samples_log2].depth_only_pipeline[index];
667 break;
668 case VK_IMAGE_ASPECT_STENCIL_BIT:
669 pipeline = &meta_state->clear[samples_log2].stencil_only_pipeline[index];
670 break;
671 default:
672 unreachable("expected depth or stencil aspect");
673 }
674
675 if (cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp == VK_NULL_HANDLE) {
676 VkResult ret = create_depthstencil_renderpass(cmd_buffer->device, 1u << samples_log2,
677 &cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
678 if (ret != VK_SUCCESS) {
679 cmd_buffer->record_result = ret;
680 return VK_NULL_HANDLE;
681 }
682 }
683
684 if (*pipeline == VK_NULL_HANDLE) {
685 VkResult ret = create_depthstencil_pipeline(cmd_buffer->device, aspects, 1u << samples_log2, index,
686 pipeline, cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
687 if (ret != VK_SUCCESS) {
688 cmd_buffer->record_result = ret;
689 return VK_NULL_HANDLE;
690 }
691 }
692 return *pipeline;
693 }
694
695 static void
696 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
697 const VkClearAttachment *clear_att,
698 const VkClearRect *clear_rect,
699 uint32_t view_mask)
700 {
701 struct radv_device *device = cmd_buffer->device;
702 struct radv_meta_state *meta_state = &device->meta_state;
703 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
704 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
705 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
706 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
707 VkImageAspectFlags aspects = clear_att->aspectMask;
708 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
709 const uint32_t samples = iview->image->info.samples;
710 const uint32_t samples_log2 = ffs(samples) - 1;
711 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
712
713 assert(pass_att != VK_ATTACHMENT_UNUSED);
714
715 if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
716 clear_value.depth = 1.0f;
717
718 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
719 device->meta_state.clear_depth_p_layout,
720 VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
721 &clear_value.depth);
722
723 uint32_t prev_reference = cmd_buffer->state.dynamic.stencil_reference.front;
724 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
725 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
726 clear_value.stencil);
727 }
728
729 VkPipeline pipeline = pick_depthstencil_pipeline(cmd_buffer,
730 meta_state,
731 iview,
732 samples_log2,
733 aspects,
734 subpass->depth_stencil_attachment.layout,
735 clear_rect,
736 clear_value);
737 if (!pipeline)
738 return;
739
740 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
741 pipeline);
742
743 if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
744 subpass->depth_stencil_attachment.layout,
745 clear_rect, clear_value))
746 radv_update_ds_clear_metadata(cmd_buffer, iview->image,
747 clear_value, aspects);
748
749 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
750 .x = clear_rect->rect.offset.x,
751 .y = clear_rect->rect.offset.y,
752 .width = clear_rect->rect.extent.width,
753 .height = clear_rect->rect.extent.height,
754 .minDepth = 0.0f,
755 .maxDepth = 1.0f
756 });
757
758 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
759
760 if (view_mask) {
761 unsigned i;
762 for_each_bit(i, view_mask)
763 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
764 } else {
765 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
766 }
767
768 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
769 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
770 prev_reference);
771 }
772 }
773
774 static uint32_t
775 clear_htile_mask(struct radv_cmd_buffer *cmd_buffer,
776 struct radeon_winsys_bo *bo, uint64_t offset, uint64_t size,
777 uint32_t htile_value, uint32_t htile_mask)
778 {
779 struct radv_device *device = cmd_buffer->device;
780 struct radv_meta_state *state = &device->meta_state;
781 uint64_t block_count = round_up_u64(size, 1024);
782 struct radv_meta_saved_state saved_state;
783
784 radv_meta_save(&saved_state, cmd_buffer,
785 RADV_META_SAVE_COMPUTE_PIPELINE |
786 RADV_META_SAVE_CONSTANTS |
787 RADV_META_SAVE_DESCRIPTORS);
788
789 struct radv_buffer dst_buffer = {
790 .bo = bo,
791 .offset = offset,
792 .size = size
793 };
794
795 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
796 VK_PIPELINE_BIND_POINT_COMPUTE,
797 state->clear_htile_mask_pipeline);
798
799 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
800 state->clear_htile_mask_p_layout,
801 0, /* set */
802 1, /* descriptorWriteCount */
803 (VkWriteDescriptorSet[]) {
804 {
805 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
806 .dstBinding = 0,
807 .dstArrayElement = 0,
808 .descriptorCount = 1,
809 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
810 .pBufferInfo = &(VkDescriptorBufferInfo) {
811 .buffer = radv_buffer_to_handle(&dst_buffer),
812 .offset = 0,
813 .range = size
814 }
815 }
816 });
817
818 const unsigned constants[2] = {
819 htile_value & htile_mask,
820 ~htile_mask,
821 };
822
823 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
824 state->clear_htile_mask_p_layout,
825 VK_SHADER_STAGE_COMPUTE_BIT, 0, 8,
826 constants);
827
828 radv_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer), block_count, 1, 1);
829
830 radv_meta_restore(&saved_state, cmd_buffer);
831
832 return RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
833 RADV_CMD_FLAG_INV_VMEM_L1 |
834 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
835 }
836
837 static uint32_t
838 radv_get_htile_fast_clear_value(const struct radv_image *image,
839 VkClearDepthStencilValue value)
840 {
841 uint32_t clear_value;
842
843 if (!image->surface.has_stencil) {
844 clear_value = value.depth ? 0xfffffff0 : 0;
845 } else {
846 clear_value = value.depth ? 0xfffc0000 : 0;
847 }
848
849 return clear_value;
850 }
851
852 static uint32_t
853 radv_get_htile_mask(const struct radv_image *image, VkImageAspectFlags aspects)
854 {
855 uint32_t mask = 0;
856
857 if (!image->surface.has_stencil) {
858 /* All the HTILE buffer is used when there is no stencil. */
859 mask = UINT32_MAX;
860 } else {
861 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
862 mask |= 0xfffffc0f;
863 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
864 mask |= 0x000003f0;
865 }
866
867 return mask;
868 }
869
870 static bool
871 radv_is_fast_clear_depth_allowed(VkClearDepthStencilValue value)
872 {
873 return value.depth == 1.0f || value.depth == 0.0f;
874 }
875
876 static bool
877 radv_is_fast_clear_stencil_allowed(VkClearDepthStencilValue value)
878 {
879 return value.stencil == 0;
880 }
881
882 /**
883 * Determine if the given image can be fast cleared.
884 */
885 static bool
886 radv_image_can_fast_clear(struct radv_device *device, struct radv_image *image)
887 {
888 if (device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
889 return false;
890
891 if (vk_format_is_color(image->vk_format)) {
892 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
893 return false;
894
895 /* RB+ doesn't work with CMASK fast clear on Stoney. */
896 if (!radv_image_has_dcc(image) &&
897 device->physical_device->rad_info.family == CHIP_STONEY)
898 return false;
899 } else {
900 if (!radv_image_has_htile(image))
901 return false;
902
903 /* GFX8 only supports 32-bit depth surfaces but we can enable
904 * TC-compat HTILE for 16-bit surfaces if no Z planes are
905 * compressed. Though, fast HTILE clears don't seem to work.
906 */
907 if (device->physical_device->rad_info.chip_class == VI &&
908 image->vk_format == VK_FORMAT_D16_UNORM)
909 return false;
910 }
911
912 /* Do not fast clears 3D images. */
913 if (image->type == VK_IMAGE_TYPE_3D)
914 return false;
915
916 return true;
917 }
918
919 /**
920 * Determine if the given image view can be fast cleared.
921 */
922 static bool
923 radv_image_view_can_fast_clear(struct radv_device *device,
924 const struct radv_image_view *iview)
925 {
926 struct radv_image *image = iview->image;
927
928 /* Only fast clear if the image itself can be fast cleared. */
929 if (!radv_image_can_fast_clear(device, image))
930 return false;
931
932 /* Only fast clear if all layers are bound. */
933 if (iview->base_layer > 0 ||
934 iview->layer_count != image->info.array_size)
935 return false;
936
937 /* Only fast clear if the view covers the whole image. */
938 if (!radv_image_extent_compare(image, &iview->extent))
939 return false;
940
941 return true;
942 }
943
944 static bool
945 radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer,
946 const struct radv_image_view *iview,
947 VkImageLayout image_layout,
948 VkImageAspectFlags aspects,
949 const VkClearRect *clear_rect,
950 const VkClearDepthStencilValue clear_value,
951 uint32_t view_mask)
952 {
953 if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview))
954 return false;
955
956 if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
957 return false;
958
959 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
960 clear_rect->rect.extent.width != iview->image->info.width ||
961 clear_rect->rect.extent.height != iview->image->info.height)
962 return false;
963
964 if (view_mask && (iview->image->info.array_size >= 32 ||
965 (1u << iview->image->info.array_size) - 1u != view_mask))
966 return false;
967 if (!view_mask && clear_rect->baseArrayLayer != 0)
968 return false;
969 if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
970 return false;
971
972 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 &&
973 (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT) ||
974 ((vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) &&
975 !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))))
976 return false;
977
978 if (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
979 !radv_is_fast_clear_depth_allowed(clear_value)) ||
980 ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
981 !radv_is_fast_clear_stencil_allowed(clear_value)))
982 return false;
983
984 return true;
985 }
986
987 static void
988 radv_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer,
989 const struct radv_image_view *iview,
990 const VkClearAttachment *clear_att,
991 enum radv_cmd_flush_bits *pre_flush,
992 enum radv_cmd_flush_bits *post_flush)
993 {
994 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
995 VkImageAspectFlags aspects = clear_att->aspectMask;
996 uint32_t clear_word, flush_bits;
997 uint32_t htile_mask;
998
999 clear_word = radv_get_htile_fast_clear_value(iview->image, clear_value);
1000 htile_mask = radv_get_htile_mask(iview->image, aspects);
1001
1002 if (pre_flush) {
1003 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1004 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
1005 *pre_flush |= cmd_buffer->state.flush_bits;
1006 }
1007
1008 if (htile_mask == UINT_MAX) {
1009 /* Clear the whole HTILE buffer. */
1010 flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
1011 iview->image->offset + iview->image->htile_offset,
1012 iview->image->surface.htile_size, clear_word);
1013 } else {
1014 /* Only clear depth or stencil bytes in the HTILE buffer. */
1015 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9);
1016 flush_bits = clear_htile_mask(cmd_buffer, iview->image->bo,
1017 iview->image->offset + iview->image->htile_offset,
1018 iview->image->surface.htile_size, clear_word,
1019 htile_mask);
1020 }
1021
1022 radv_update_ds_clear_metadata(cmd_buffer, iview->image, clear_value, aspects);
1023 if (post_flush) {
1024 *post_flush |= flush_bits;
1025 }
1026 }
1027
1028 static nir_shader *
1029 build_clear_htile_mask_shader()
1030 {
1031 nir_builder b;
1032
1033 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
1034 b.shader->info.name = ralloc_strdup(b.shader, "meta_clear_htile_mask");
1035 b.shader->info.cs.local_size[0] = 64;
1036 b.shader->info.cs.local_size[1] = 1;
1037 b.shader->info.cs.local_size[2] = 1;
1038
1039 nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
1040 nir_ssa_def *wg_id = nir_load_work_group_id(&b);
1041 nir_ssa_def *block_size = nir_imm_ivec4(&b,
1042 b.shader->info.cs.local_size[0],
1043 b.shader->info.cs.local_size[1],
1044 b.shader->info.cs.local_size[2], 0);
1045
1046 nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
1047
1048 nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16));
1049 offset = nir_channel(&b, offset, 0);
1050
1051 nir_intrinsic_instr *buf =
1052 nir_intrinsic_instr_create(b.shader,
1053 nir_intrinsic_vulkan_resource_index);
1054
1055 buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
1056 nir_intrinsic_set_desc_set(buf, 0);
1057 nir_intrinsic_set_binding(buf, 0);
1058 nir_ssa_dest_init(&buf->instr, &buf->dest, 1, 32, NULL);
1059 nir_builder_instr_insert(&b, &buf->instr);
1060
1061 nir_intrinsic_instr *constants =
1062 nir_intrinsic_instr_create(b.shader,
1063 nir_intrinsic_load_push_constant);
1064 nir_intrinsic_set_base(constants, 0);
1065 nir_intrinsic_set_range(constants, 8);
1066 constants->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
1067 constants->num_components = 2;
1068 nir_ssa_dest_init(&constants->instr, &constants->dest, 2, 32, "constants");
1069 nir_builder_instr_insert(&b, &constants->instr);
1070
1071 nir_intrinsic_instr *load =
1072 nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
1073 load->src[0] = nir_src_for_ssa(&buf->dest.ssa);
1074 load->src[1] = nir_src_for_ssa(offset);
1075 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
1076 load->num_components = 4;
1077 nir_builder_instr_insert(&b, &load->instr);
1078
1079 /* data = (data & ~htile_mask) | (htile_value & htile_mask) */
1080 nir_ssa_def *data =
1081 nir_iand(&b, &load->dest.ssa,
1082 nir_channel(&b, &constants->dest.ssa, 1));
1083 data = nir_ior(&b, data, nir_channel(&b, &constants->dest.ssa, 0));
1084
1085 nir_intrinsic_instr *store =
1086 nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
1087 store->src[0] = nir_src_for_ssa(data);
1088 store->src[1] = nir_src_for_ssa(&buf->dest.ssa);
1089 store->src[2] = nir_src_for_ssa(offset);
1090 nir_intrinsic_set_write_mask(store, 0xf);
1091 store->num_components = 4;
1092 nir_builder_instr_insert(&b, &store->instr);
1093
1094 return b.shader;
1095 }
1096
1097 static VkResult
1098 init_meta_clear_htile_mask_state(struct radv_device *device)
1099 {
1100 struct radv_meta_state *state = &device->meta_state;
1101 struct radv_shader_module cs = { .nir = NULL };
1102 VkResult result;
1103
1104 cs.nir = build_clear_htile_mask_shader();
1105
1106 VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1107 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1108 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1109 .bindingCount = 1,
1110 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1111 {
1112 .binding = 0,
1113 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
1114 .descriptorCount = 1,
1115 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
1116 .pImmutableSamplers = NULL
1117 },
1118 }
1119 };
1120
1121 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1122 &ds_layout_info, &state->alloc,
1123 &state->clear_htile_mask_ds_layout);
1124 if (result != VK_SUCCESS)
1125 goto fail;
1126
1127 VkPipelineLayoutCreateInfo p_layout_info = {
1128 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1129 .setLayoutCount = 1,
1130 .pSetLayouts = &state->clear_htile_mask_ds_layout,
1131 .pushConstantRangeCount = 1,
1132 .pPushConstantRanges = &(VkPushConstantRange){
1133 VK_SHADER_STAGE_COMPUTE_BIT, 0, 8,
1134 },
1135 };
1136
1137 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1138 &p_layout_info, &state->alloc,
1139 &state->clear_htile_mask_p_layout);
1140 if (result != VK_SUCCESS)
1141 goto fail;
1142
1143 VkPipelineShaderStageCreateInfo shader_stage = {
1144 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1145 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
1146 .module = radv_shader_module_to_handle(&cs),
1147 .pName = "main",
1148 .pSpecializationInfo = NULL,
1149 };
1150
1151 VkComputePipelineCreateInfo pipeline_info = {
1152 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
1153 .stage = shader_stage,
1154 .flags = 0,
1155 .layout = state->clear_htile_mask_p_layout,
1156 };
1157
1158 result = radv_CreateComputePipelines(radv_device_to_handle(device),
1159 radv_pipeline_cache_to_handle(&state->cache),
1160 1, &pipeline_info, NULL,
1161 &state->clear_htile_mask_pipeline);
1162
1163 ralloc_free(cs.nir);
1164 return result;
1165 fail:
1166 ralloc_free(cs.nir);
1167 return result;
1168 }
1169
1170 VkResult
1171 radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand)
1172 {
1173 VkResult res;
1174 struct radv_meta_state *state = &device->meta_state;
1175
1176 VkPipelineLayoutCreateInfo pl_color_create_info = {
1177 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1178 .setLayoutCount = 0,
1179 .pushConstantRangeCount = 1,
1180 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
1181 };
1182
1183 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1184 &pl_color_create_info,
1185 &device->meta_state.alloc,
1186 &device->meta_state.clear_color_p_layout);
1187 if (res != VK_SUCCESS)
1188 goto fail;
1189
1190 VkPipelineLayoutCreateInfo pl_depth_create_info = {
1191 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1192 .setLayoutCount = 0,
1193 .pushConstantRangeCount = 1,
1194 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
1195 };
1196
1197 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1198 &pl_depth_create_info,
1199 &device->meta_state.alloc,
1200 &device->meta_state.clear_depth_p_layout);
1201 if (res != VK_SUCCESS)
1202 goto fail;
1203
1204 res = init_meta_clear_htile_mask_state(device);
1205 if (res != VK_SUCCESS)
1206 goto fail;
1207
1208 if (on_demand)
1209 return VK_SUCCESS;
1210
1211 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
1212 uint32_t samples = 1 << i;
1213 for (uint32_t j = 0; j < NUM_META_FS_KEYS; ++j) {
1214 VkFormat format = radv_fs_key_format_exemplars[j];
1215 unsigned fs_key = radv_format_meta_fs_key(format);
1216 assert(!state->clear[i].color_pipelines[fs_key]);
1217
1218 res = create_color_renderpass(device, format, samples,
1219 &state->clear[i].render_pass[fs_key]);
1220 if (res != VK_SUCCESS)
1221 goto fail;
1222
1223 res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
1224 state->clear[i].render_pass[fs_key]);
1225 if (res != VK_SUCCESS)
1226 goto fail;
1227
1228 }
1229
1230 res = create_depthstencil_renderpass(device,
1231 samples,
1232 &state->clear[i].depthstencil_rp);
1233 if (res != VK_SUCCESS)
1234 goto fail;
1235
1236 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
1237 res = create_depthstencil_pipeline(device,
1238 VK_IMAGE_ASPECT_DEPTH_BIT,
1239 samples,
1240 j,
1241 &state->clear[i].depth_only_pipeline[j],
1242 state->clear[i].depthstencil_rp);
1243 if (res != VK_SUCCESS)
1244 goto fail;
1245
1246 res = create_depthstencil_pipeline(device,
1247 VK_IMAGE_ASPECT_STENCIL_BIT,
1248 samples,
1249 j,
1250 &state->clear[i].stencil_only_pipeline[j],
1251 state->clear[i].depthstencil_rp);
1252 if (res != VK_SUCCESS)
1253 goto fail;
1254
1255 res = create_depthstencil_pipeline(device,
1256 VK_IMAGE_ASPECT_DEPTH_BIT |
1257 VK_IMAGE_ASPECT_STENCIL_BIT,
1258 samples,
1259 j,
1260 &state->clear[i].depthstencil_pipeline[j],
1261 state->clear[i].depthstencil_rp);
1262 if (res != VK_SUCCESS)
1263 goto fail;
1264 }
1265 }
1266 return VK_SUCCESS;
1267
1268 fail:
1269 radv_device_finish_meta_clear_state(device);
1270 return res;
1271 }
1272
1273 static uint32_t
1274 radv_get_cmask_fast_clear_value(const struct radv_image *image)
1275 {
1276 uint32_t value = 0; /* Default value when no DCC. */
1277
1278 /* The fast-clear value is different for images that have both DCC and
1279 * CMASK metadata.
1280 */
1281 if (radv_image_has_dcc(image)) {
1282 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
1283 return image->info.samples > 1 ? 0xcccccccc : 0xffffffff;
1284 }
1285
1286 return value;
1287 }
1288
1289 uint32_t
1290 radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
1291 struct radv_image *image, uint32_t value)
1292 {
1293 return radv_fill_buffer(cmd_buffer, image->bo,
1294 image->offset + image->cmask.offset,
1295 image->cmask.size, value);
1296 }
1297
1298 uint32_t
1299 radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
1300 struct radv_image *image, uint32_t value)
1301 {
1302 return radv_fill_buffer(cmd_buffer, image->bo,
1303 image->offset + image->fmask.offset,
1304 image->fmask.size, value);
1305 }
1306
1307 uint32_t
1308 radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
1309 struct radv_image *image, uint32_t value)
1310 {
1311 /* Mark the image as being compressed. */
1312 radv_update_dcc_metadata(cmd_buffer, image, true);
1313
1314 return radv_fill_buffer(cmd_buffer, image->bo,
1315 image->offset + image->dcc_offset,
1316 image->surface.dcc_size, value);
1317 }
1318
1319 static void vi_get_fast_clear_parameters(VkFormat format,
1320 const VkClearColorValue *clear_value,
1321 uint32_t* reset_value,
1322 bool *can_avoid_fast_clear_elim)
1323 {
1324 bool values[4] = {};
1325 int extra_channel;
1326 bool main_value = false;
1327 bool extra_value = false;
1328 int i;
1329 *can_avoid_fast_clear_elim = false;
1330
1331 *reset_value = 0x20202020U;
1332
1333 const struct vk_format_description *desc = vk_format_description(format);
1334 if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
1335 format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
1336 format == VK_FORMAT_B5G6R5_UNORM_PACK16)
1337 extra_channel = -1;
1338 else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
1339 if (radv_translate_colorswap(format, false) <= 1)
1340 extra_channel = desc->nr_channels - 1;
1341 else
1342 extra_channel = 0;
1343 } else
1344 return;
1345
1346 for (i = 0; i < 4; i++) {
1347 int index = desc->swizzle[i] - VK_SWIZZLE_X;
1348 if (desc->swizzle[i] < VK_SWIZZLE_X ||
1349 desc->swizzle[i] > VK_SWIZZLE_W)
1350 continue;
1351
1352 if (desc->channel[i].pure_integer &&
1353 desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
1354 /* Use the maximum value for clamping the clear color. */
1355 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
1356
1357 values[i] = clear_value->int32[i] != 0;
1358 if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
1359 return;
1360 } else if (desc->channel[i].pure_integer &&
1361 desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
1362 /* Use the maximum value for clamping the clear color. */
1363 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
1364
1365 values[i] = clear_value->uint32[i] != 0U;
1366 if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
1367 return;
1368 } else {
1369 values[i] = clear_value->float32[i] != 0.0F;
1370 if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
1371 return;
1372 }
1373
1374 if (index == extra_channel)
1375 extra_value = values[i];
1376 else
1377 main_value = values[i];
1378 }
1379
1380 for (int i = 0; i < 4; ++i)
1381 if (values[i] != main_value &&
1382 desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
1383 desc->swizzle[i] >= VK_SWIZZLE_X &&
1384 desc->swizzle[i] <= VK_SWIZZLE_W)
1385 return;
1386
1387 *can_avoid_fast_clear_elim = true;
1388 if (main_value)
1389 *reset_value |= 0x80808080U;
1390
1391 if (extra_value)
1392 *reset_value |= 0x40404040U;
1393 return;
1394 }
1395
1396 static bool
1397 radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1398 const struct radv_image_view *iview,
1399 VkImageLayout image_layout,
1400 const VkClearRect *clear_rect,
1401 VkClearColorValue clear_value,
1402 uint32_t view_mask)
1403 {
1404 uint32_t clear_color[2];
1405
1406 if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview))
1407 return false;
1408
1409 if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
1410 return false;
1411
1412 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
1413 clear_rect->rect.extent.width != iview->image->info.width ||
1414 clear_rect->rect.extent.height != iview->image->info.height)
1415 return false;
1416
1417 if (view_mask && (iview->image->info.array_size >= 32 ||
1418 (1u << iview->image->info.array_size) - 1u != view_mask))
1419 return false;
1420 if (!view_mask && clear_rect->baseArrayLayer != 0)
1421 return false;
1422 if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
1423 return false;
1424
1425 /* DCC */
1426 if (!radv_format_pack_clear_color(iview->vk_format,
1427 clear_color, &clear_value))
1428 return false;
1429
1430 if (radv_image_has_dcc(iview->image)) {
1431 bool can_avoid_fast_clear_elim;
1432 uint32_t reset_value;
1433
1434 vi_get_fast_clear_parameters(iview->vk_format,
1435 &clear_value, &reset_value,
1436 &can_avoid_fast_clear_elim);
1437
1438 if (iview->image->info.samples > 1) {
1439 /* DCC fast clear with MSAA should clear CMASK. */
1440 /* FIXME: This doesn't work for now. There is a
1441 * hardware bug with fast clears and DCC for MSAA
1442 * textures. AMDVLK has a workaround but it doesn't
1443 * seem to work here. Note that we might emit useless
1444 * CB flushes but that shouldn't matter.
1445 */
1446 if (!can_avoid_fast_clear_elim)
1447 return false;
1448 }
1449 }
1450
1451 return true;
1452 }
1453
1454
1455 static void
1456 radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1457 const struct radv_image_view *iview,
1458 const VkClearAttachment *clear_att,
1459 uint32_t subpass_att,
1460 enum radv_cmd_flush_bits *pre_flush,
1461 enum radv_cmd_flush_bits *post_flush)
1462 {
1463 VkClearColorValue clear_value = clear_att->clearValue.color;
1464 uint32_t clear_color[2], flush_bits = 0;
1465 uint32_t cmask_clear_value;
1466
1467 if (pre_flush) {
1468 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1469 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
1470 *pre_flush |= cmd_buffer->state.flush_bits;
1471 }
1472
1473 /* DCC */
1474 radv_format_pack_clear_color(iview->vk_format, clear_color, &clear_value);
1475
1476 cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
1477
1478 /* clear cmask buffer */
1479 if (radv_image_has_dcc(iview->image)) {
1480 uint32_t reset_value;
1481 bool can_avoid_fast_clear_elim;
1482 bool need_decompress_pass = false;
1483
1484 vi_get_fast_clear_parameters(iview->vk_format,
1485 &clear_value, &reset_value,
1486 &can_avoid_fast_clear_elim);
1487
1488 if (radv_image_has_cmask(iview->image)) {
1489 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1490 cmask_clear_value);
1491
1492 need_decompress_pass = true;
1493 }
1494
1495 if (!can_avoid_fast_clear_elim)
1496 need_decompress_pass = true;
1497
1498 flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, reset_value);
1499
1500 radv_update_fce_metadata(cmd_buffer, iview->image,
1501 need_decompress_pass);
1502 } else {
1503 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1504 cmask_clear_value);
1505 }
1506
1507 if (post_flush) {
1508 *post_flush |= flush_bits;
1509 }
1510
1511 radv_update_color_clear_metadata(cmd_buffer, iview->image, subpass_att,
1512 clear_color);
1513 }
1514
1515 /**
1516 * The parameters mean that same as those in vkCmdClearAttachments.
1517 */
1518 static void
1519 emit_clear(struct radv_cmd_buffer *cmd_buffer,
1520 const VkClearAttachment *clear_att,
1521 const VkClearRect *clear_rect,
1522 enum radv_cmd_flush_bits *pre_flush,
1523 enum radv_cmd_flush_bits *post_flush,
1524 uint32_t view_mask)
1525 {
1526 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
1527 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1528 VkImageAspectFlags aspects = clear_att->aspectMask;
1529
1530 if (aspects & VK_IMAGE_ASPECT_COLOR_BIT) {
1531 const uint32_t subpass_att = clear_att->colorAttachment;
1532 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
1533 VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
1534 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
1535 VkClearColorValue clear_value = clear_att->clearValue.color;
1536
1537 if (radv_can_fast_clear_color(cmd_buffer, iview, image_layout,
1538 clear_rect, clear_value, view_mask)) {
1539 radv_fast_clear_color(cmd_buffer, iview, clear_att,
1540 subpass_att, pre_flush,
1541 post_flush);
1542 } else {
1543 emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask);
1544 }
1545 } else {
1546 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
1547 VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
1548 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
1549 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
1550
1551 assert(aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
1552 VK_IMAGE_ASPECT_STENCIL_BIT));
1553
1554 if (radv_can_fast_clear_depth(cmd_buffer, iview, image_layout,
1555 aspects, clear_rect, clear_value,
1556 view_mask)) {
1557 radv_fast_clear_depth(cmd_buffer, iview, clear_att,
1558 pre_flush, post_flush);
1559 } else {
1560 emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect,
1561 view_mask);
1562 }
1563 }
1564 }
1565
1566 static inline bool
1567 radv_attachment_needs_clear(struct radv_cmd_state *cmd_state, uint32_t a)
1568 {
1569 uint32_t view_mask = cmd_state->subpass->view_mask;
1570 return (a != VK_ATTACHMENT_UNUSED &&
1571 cmd_state->attachments[a].pending_clear_aspects &&
1572 (!view_mask || (view_mask & ~cmd_state->attachments[a].cleared_views)));
1573 }
1574
1575 static bool
1576 radv_subpass_needs_clear(struct radv_cmd_buffer *cmd_buffer)
1577 {
1578 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1579 uint32_t a;
1580
1581 if (!cmd_state->subpass)
1582 return false;
1583
1584 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1585 a = cmd_state->subpass->color_attachments[i].attachment;
1586 if (radv_attachment_needs_clear(cmd_state, a))
1587 return true;
1588 }
1589
1590 a = cmd_state->subpass->depth_stencil_attachment.attachment;
1591 return radv_attachment_needs_clear(cmd_state, a);
1592 }
1593
1594 static void
1595 radv_subpass_clear_attachment(struct radv_cmd_buffer *cmd_buffer,
1596 struct radv_attachment_state *attachment,
1597 const VkClearAttachment *clear_att,
1598 enum radv_cmd_flush_bits *pre_flush,
1599 enum radv_cmd_flush_bits *post_flush)
1600 {
1601 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1602 uint32_t view_mask = cmd_state->subpass->view_mask;
1603
1604 VkClearRect clear_rect = {
1605 .rect = cmd_state->render_area,
1606 .baseArrayLayer = 0,
1607 .layerCount = cmd_state->framebuffer->layers,
1608 };
1609
1610 emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush,
1611 view_mask & ~attachment->cleared_views);
1612 if (view_mask)
1613 attachment->cleared_views |= view_mask;
1614 else
1615 attachment->pending_clear_aspects = 0;
1616 }
1617
1618 /**
1619 * Emit any pending attachment clears for the current subpass.
1620 *
1621 * @see radv_attachment_state::pending_clear_aspects
1622 */
1623 void
1624 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1625 {
1626 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1627 struct radv_meta_saved_state saved_state;
1628 enum radv_cmd_flush_bits pre_flush = 0;
1629 enum radv_cmd_flush_bits post_flush = 0;
1630
1631 if (!radv_subpass_needs_clear(cmd_buffer))
1632 return;
1633
1634 radv_meta_save(&saved_state, cmd_buffer,
1635 RADV_META_SAVE_GRAPHICS_PIPELINE |
1636 RADV_META_SAVE_CONSTANTS);
1637
1638 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1639 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1640
1641 if (!radv_attachment_needs_clear(cmd_state, a))
1642 continue;
1643
1644 assert(cmd_state->attachments[a].pending_clear_aspects ==
1645 VK_IMAGE_ASPECT_COLOR_BIT);
1646
1647 VkClearAttachment clear_att = {
1648 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1649 .colorAttachment = i, /* Use attachment index relative to subpass */
1650 .clearValue = cmd_state->attachments[a].clear_value,
1651 };
1652
1653 radv_subpass_clear_attachment(cmd_buffer,
1654 &cmd_state->attachments[a],
1655 &clear_att, &pre_flush,
1656 &post_flush);
1657 }
1658
1659 uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1660 if (radv_attachment_needs_clear(cmd_state, ds)) {
1661 VkClearAttachment clear_att = {
1662 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1663 .clearValue = cmd_state->attachments[ds].clear_value,
1664 };
1665
1666 radv_subpass_clear_attachment(cmd_buffer,
1667 &cmd_state->attachments[ds],
1668 &clear_att, &pre_flush,
1669 &post_flush);
1670 }
1671
1672 radv_meta_restore(&saved_state, cmd_buffer);
1673 cmd_buffer->state.flush_bits |= post_flush;
1674 }
1675
1676 static void
1677 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1678 struct radv_image *image,
1679 VkImageLayout image_layout,
1680 const VkImageSubresourceRange *range,
1681 VkFormat format, int level, int layer,
1682 const VkClearValue *clear_val)
1683 {
1684 VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1685 struct radv_image_view iview;
1686 uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level);
1687 uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level);
1688
1689 radv_image_view_init(&iview, cmd_buffer->device,
1690 &(VkImageViewCreateInfo) {
1691 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1692 .image = radv_image_to_handle(image),
1693 .viewType = radv_meta_get_view_type(image),
1694 .format = format,
1695 .subresourceRange = {
1696 .aspectMask = range->aspectMask,
1697 .baseMipLevel = range->baseMipLevel + level,
1698 .levelCount = 1,
1699 .baseArrayLayer = range->baseArrayLayer + layer,
1700 .layerCount = 1
1701 },
1702 });
1703
1704 VkFramebuffer fb;
1705 radv_CreateFramebuffer(device_h,
1706 &(VkFramebufferCreateInfo) {
1707 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1708 .attachmentCount = 1,
1709 .pAttachments = (VkImageView[]) {
1710 radv_image_view_to_handle(&iview),
1711 },
1712 .width = width,
1713 .height = height,
1714 .layers = 1
1715 },
1716 &cmd_buffer->pool->alloc,
1717 &fb);
1718
1719 VkAttachmentDescription att_desc = {
1720 .format = iview.vk_format,
1721 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1722 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1723 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1724 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1725 .initialLayout = image_layout,
1726 .finalLayout = image_layout,
1727 };
1728
1729 VkSubpassDescription subpass_desc = {
1730 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1731 .inputAttachmentCount = 0,
1732 .colorAttachmentCount = 0,
1733 .pColorAttachments = NULL,
1734 .pResolveAttachments = NULL,
1735 .pDepthStencilAttachment = NULL,
1736 .preserveAttachmentCount = 0,
1737 .pPreserveAttachments = NULL,
1738 };
1739
1740 const VkAttachmentReference att_ref = {
1741 .attachment = 0,
1742 .layout = image_layout,
1743 };
1744
1745 if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1746 subpass_desc.colorAttachmentCount = 1;
1747 subpass_desc.pColorAttachments = &att_ref;
1748 } else {
1749 subpass_desc.pDepthStencilAttachment = &att_ref;
1750 }
1751
1752 VkRenderPass pass;
1753 radv_CreateRenderPass(device_h,
1754 &(VkRenderPassCreateInfo) {
1755 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1756 .attachmentCount = 1,
1757 .pAttachments = &att_desc,
1758 .subpassCount = 1,
1759 .pSubpasses = &subpass_desc,
1760 },
1761 &cmd_buffer->pool->alloc,
1762 &pass);
1763
1764 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1765 &(VkRenderPassBeginInfo) {
1766 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1767 .renderArea = {
1768 .offset = { 0, 0, },
1769 .extent = {
1770 .width = width,
1771 .height = height,
1772 },
1773 },
1774 .renderPass = pass,
1775 .framebuffer = fb,
1776 .clearValueCount = 0,
1777 .pClearValues = NULL,
1778 },
1779 VK_SUBPASS_CONTENTS_INLINE);
1780
1781 VkClearAttachment clear_att = {
1782 .aspectMask = range->aspectMask,
1783 .colorAttachment = 0,
1784 .clearValue = *clear_val,
1785 };
1786
1787 VkClearRect clear_rect = {
1788 .rect = {
1789 .offset = { 0, 0 },
1790 .extent = { width, height },
1791 },
1792 .baseArrayLayer = range->baseArrayLayer,
1793 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1794 };
1795
1796 emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0);
1797
1798 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1799 radv_DestroyRenderPass(device_h, pass,
1800 &cmd_buffer->pool->alloc);
1801 radv_DestroyFramebuffer(device_h, fb,
1802 &cmd_buffer->pool->alloc);
1803 }
1804
1805 /**
1806 * Return TRUE if a fast color or depth clear has been performed.
1807 */
1808 static bool
1809 radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer,
1810 struct radv_image *image,
1811 VkFormat format,
1812 VkImageLayout image_layout,
1813 const VkImageSubresourceRange *range,
1814 const VkClearValue *clear_val)
1815 {
1816 struct radv_image_view iview;
1817
1818 radv_image_view_init(&iview, cmd_buffer->device,
1819 &(VkImageViewCreateInfo) {
1820 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1821 .image = radv_image_to_handle(image),
1822 .viewType = radv_meta_get_view_type(image),
1823 .format = image->vk_format,
1824 .subresourceRange = {
1825 .aspectMask = range->aspectMask,
1826 .baseMipLevel = range->baseMipLevel,
1827 .levelCount = range->levelCount,
1828 .baseArrayLayer = range->baseArrayLayer,
1829 .layerCount = range->layerCount,
1830 },
1831 });
1832
1833 VkClearRect clear_rect = {
1834 .rect = {
1835 .offset = { 0, 0 },
1836 .extent = {
1837 radv_minify(image->info.width, range->baseMipLevel),
1838 radv_minify(image->info.height, range->baseMipLevel),
1839 },
1840 },
1841 .baseArrayLayer = range->baseArrayLayer,
1842 .layerCount = range->layerCount,
1843 };
1844
1845 VkClearAttachment clear_att = {
1846 .aspectMask = range->aspectMask,
1847 .colorAttachment = 0,
1848 .clearValue = *clear_val,
1849 };
1850
1851 if (vk_format_is_color(format)) {
1852 if (radv_can_fast_clear_color(cmd_buffer, &iview,
1853 image_layout, &clear_rect,
1854 clear_att.clearValue.color, 0)) {
1855 radv_fast_clear_color(cmd_buffer, &iview, &clear_att,
1856 clear_att.colorAttachment,
1857 NULL, NULL);
1858 return true;
1859 }
1860 } else {
1861 if (radv_can_fast_clear_depth(cmd_buffer, &iview, image_layout,
1862 range->aspectMask, &clear_rect,
1863 clear_att.clearValue.depthStencil, 0)) {
1864 radv_fast_clear_depth(cmd_buffer, &iview, &clear_att,
1865 NULL, NULL);
1866 return true;
1867 }
1868 }
1869
1870 return false;
1871 }
1872
1873 static void
1874 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
1875 struct radv_image *image,
1876 VkImageLayout image_layout,
1877 const VkClearValue *clear_value,
1878 uint32_t range_count,
1879 const VkImageSubresourceRange *ranges,
1880 bool cs)
1881 {
1882 VkFormat format = image->vk_format;
1883 VkClearValue internal_clear_value = *clear_value;
1884
1885 if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
1886 uint32_t value;
1887 format = VK_FORMAT_R32_UINT;
1888 value = float3_to_rgb9e5(clear_value->color.float32);
1889 internal_clear_value.color.uint32[0] = value;
1890 }
1891
1892 if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
1893 uint8_t r, g;
1894 format = VK_FORMAT_R8_UINT;
1895 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
1896 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
1897 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
1898 }
1899
1900 if (format == VK_FORMAT_R32G32B32_UINT ||
1901 format == VK_FORMAT_R32G32B32_SINT ||
1902 format == VK_FORMAT_R32G32B32_SFLOAT)
1903 cs = true;
1904
1905 for (uint32_t r = 0; r < range_count; r++) {
1906 const VkImageSubresourceRange *range = &ranges[r];
1907
1908 /* Try to perform a fast clear first, otherwise fallback to
1909 * the legacy path.
1910 */
1911 if (!cs &&
1912 radv_fast_clear_range(cmd_buffer, image, format,
1913 image_layout, range,
1914 &internal_clear_value)) {
1915 continue;
1916 }
1917
1918 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
1919 const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
1920 radv_minify(image->info.depth, range->baseMipLevel + l) :
1921 radv_get_layerCount(image, range);
1922 for (uint32_t s = 0; s < layer_count; ++s) {
1923
1924 if (cs) {
1925 struct radv_meta_blit2d_surf surf;
1926 surf.format = format;
1927 surf.image = image;
1928 surf.level = range->baseMipLevel + l;
1929 surf.layer = range->baseArrayLayer + s;
1930 surf.aspect_mask = range->aspectMask;
1931 radv_meta_clear_image_cs(cmd_buffer, &surf,
1932 &internal_clear_value.color);
1933 } else {
1934 radv_clear_image_layer(cmd_buffer, image, image_layout,
1935 range, format, l, s, &internal_clear_value);
1936 }
1937 }
1938 }
1939 }
1940 }
1941
1942 void radv_CmdClearColorImage(
1943 VkCommandBuffer commandBuffer,
1944 VkImage image_h,
1945 VkImageLayout imageLayout,
1946 const VkClearColorValue* pColor,
1947 uint32_t rangeCount,
1948 const VkImageSubresourceRange* pRanges)
1949 {
1950 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1951 RADV_FROM_HANDLE(radv_image, image, image_h);
1952 struct radv_meta_saved_state saved_state;
1953 bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1954
1955 if (cs) {
1956 radv_meta_save(&saved_state, cmd_buffer,
1957 RADV_META_SAVE_COMPUTE_PIPELINE |
1958 RADV_META_SAVE_CONSTANTS |
1959 RADV_META_SAVE_DESCRIPTORS);
1960 } else {
1961 radv_meta_save(&saved_state, cmd_buffer,
1962 RADV_META_SAVE_GRAPHICS_PIPELINE |
1963 RADV_META_SAVE_CONSTANTS);
1964 }
1965
1966 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1967 (const VkClearValue *) pColor,
1968 rangeCount, pRanges, cs);
1969
1970 radv_meta_restore(&saved_state, cmd_buffer);
1971 }
1972
1973 void radv_CmdClearDepthStencilImage(
1974 VkCommandBuffer commandBuffer,
1975 VkImage image_h,
1976 VkImageLayout imageLayout,
1977 const VkClearDepthStencilValue* pDepthStencil,
1978 uint32_t rangeCount,
1979 const VkImageSubresourceRange* pRanges)
1980 {
1981 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1982 RADV_FROM_HANDLE(radv_image, image, image_h);
1983 struct radv_meta_saved_state saved_state;
1984
1985 radv_meta_save(&saved_state, cmd_buffer,
1986 RADV_META_SAVE_GRAPHICS_PIPELINE |
1987 RADV_META_SAVE_CONSTANTS);
1988
1989 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1990 (const VkClearValue *) pDepthStencil,
1991 rangeCount, pRanges, false);
1992
1993 radv_meta_restore(&saved_state, cmd_buffer);
1994 }
1995
1996 void radv_CmdClearAttachments(
1997 VkCommandBuffer commandBuffer,
1998 uint32_t attachmentCount,
1999 const VkClearAttachment* pAttachments,
2000 uint32_t rectCount,
2001 const VkClearRect* pRects)
2002 {
2003 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2004 struct radv_meta_saved_state saved_state;
2005 enum radv_cmd_flush_bits pre_flush = 0;
2006 enum radv_cmd_flush_bits post_flush = 0;
2007
2008 if (!cmd_buffer->state.subpass)
2009 return;
2010
2011 radv_meta_save(&saved_state, cmd_buffer,
2012 RADV_META_SAVE_GRAPHICS_PIPELINE |
2013 RADV_META_SAVE_CONSTANTS);
2014
2015 /* FINISHME: We can do better than this dumb loop. It thrashes too much
2016 * state.
2017 */
2018 for (uint32_t a = 0; a < attachmentCount; ++a) {
2019 for (uint32_t r = 0; r < rectCount; ++r) {
2020 emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush,
2021 cmd_buffer->state.subpass->view_mask);
2022 }
2023 }
2024
2025 radv_meta_restore(&saved_state, cmd_buffer);
2026 cmd_buffer->state.flush_bits |= post_flush;
2027 }