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bab79b530211f5c72679ed4fba85b9afbd5d66a4
[mesa.git] / src / amd / vulkan / radv_meta_clear.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_debug.h"
25 #include "radv_meta.h"
26 #include "radv_private.h"
27 #include "nir/nir_builder.h"
28
29 #include "util/format_rgb9e5.h"
30 #include "vk_format.h"
31
32 enum {
33 DEPTH_CLEAR_SLOW,
34 DEPTH_CLEAR_FAST_EXPCLEAR,
35 DEPTH_CLEAR_FAST_NO_EXPCLEAR
36 };
37
38 static void
39 build_color_shaders(struct nir_shader **out_vs,
40 struct nir_shader **out_fs,
41 uint32_t frag_output)
42 {
43 nir_builder vs_b;
44 nir_builder fs_b;
45
46 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
47 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
48
49 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
50 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
51
52 const struct glsl_type *position_type = glsl_vec4_type();
53 const struct glsl_type *color_type = glsl_vec4_type();
54
55 nir_variable *vs_out_pos =
56 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
57 "gl_Position");
58 vs_out_pos->data.location = VARYING_SLOT_POS;
59
60 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
61 nir_intrinsic_set_base(in_color_load, 0);
62 nir_intrinsic_set_range(in_color_load, 16);
63 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
64 in_color_load->num_components = 4;
65 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
66 nir_builder_instr_insert(&fs_b, &in_color_load->instr);
67
68 nir_variable *fs_out_color =
69 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
70 "f_color");
71 fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
72
73 nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
74
75 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
76 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
77
78 const struct glsl_type *layer_type = glsl_int_type();
79 nir_variable *vs_out_layer =
80 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
81 "v_layer");
82 vs_out_layer->data.location = VARYING_SLOT_LAYER;
83 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
84 nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
85 nir_ssa_def *base_instance = nir_load_system_value(&vs_b, nir_intrinsic_load_base_instance, 0);
86
87 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
88 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
89
90 *out_vs = vs_b.shader;
91 *out_fs = fs_b.shader;
92 }
93
94 static VkResult
95 create_pipeline(struct radv_device *device,
96 struct radv_render_pass *render_pass,
97 uint32_t samples,
98 struct nir_shader *vs_nir,
99 struct nir_shader *fs_nir,
100 const VkPipelineVertexInputStateCreateInfo *vi_state,
101 const VkPipelineDepthStencilStateCreateInfo *ds_state,
102 const VkPipelineColorBlendStateCreateInfo *cb_state,
103 const VkPipelineLayout layout,
104 const struct radv_graphics_pipeline_create_info *extra,
105 const VkAllocationCallbacks *alloc,
106 VkPipeline *pipeline)
107 {
108 VkDevice device_h = radv_device_to_handle(device);
109 VkResult result;
110
111 struct radv_shader_module vs_m = { .nir = vs_nir };
112 struct radv_shader_module fs_m = { .nir = fs_nir };
113
114 result = radv_graphics_pipeline_create(device_h,
115 radv_pipeline_cache_to_handle(&device->meta_state.cache),
116 &(VkGraphicsPipelineCreateInfo) {
117 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
118 .stageCount = fs_nir ? 2 : 1,
119 .pStages = (VkPipelineShaderStageCreateInfo[]) {
120 {
121 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
122 .stage = VK_SHADER_STAGE_VERTEX_BIT,
123 .module = radv_shader_module_to_handle(&vs_m),
124 .pName = "main",
125 },
126 {
127 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
128 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
129 .module = radv_shader_module_to_handle(&fs_m),
130 .pName = "main",
131 },
132 },
133 .pVertexInputState = vi_state,
134 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
135 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
136 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
137 .primitiveRestartEnable = false,
138 },
139 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
140 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
141 .viewportCount = 1,
142 .scissorCount = 1,
143 },
144 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
145 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
146 .rasterizerDiscardEnable = false,
147 .polygonMode = VK_POLYGON_MODE_FILL,
148 .cullMode = VK_CULL_MODE_NONE,
149 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
150 .depthBiasEnable = false,
151 },
152 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
153 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
154 .rasterizationSamples = samples,
155 .sampleShadingEnable = false,
156 .pSampleMask = NULL,
157 .alphaToCoverageEnable = false,
158 .alphaToOneEnable = false,
159 },
160 .pDepthStencilState = ds_state,
161 .pColorBlendState = cb_state,
162 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
163 /* The meta clear pipeline declares all state as dynamic.
164 * As a consequence, vkCmdBindPipeline writes no dynamic state
165 * to the cmd buffer. Therefore, at the end of the meta clear,
166 * we need only restore dynamic state was vkCmdSet.
167 */
168 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
169 .dynamicStateCount = 8,
170 .pDynamicStates = (VkDynamicState[]) {
171 /* Everything except stencil write mask */
172 VK_DYNAMIC_STATE_VIEWPORT,
173 VK_DYNAMIC_STATE_SCISSOR,
174 VK_DYNAMIC_STATE_LINE_WIDTH,
175 VK_DYNAMIC_STATE_DEPTH_BIAS,
176 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
177 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
178 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
179 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
180 },
181 },
182 .layout = layout,
183 .flags = 0,
184 .renderPass = radv_render_pass_to_handle(render_pass),
185 .subpass = 0,
186 },
187 extra,
188 alloc,
189 pipeline);
190
191 ralloc_free(vs_nir);
192 ralloc_free(fs_nir);
193
194 return result;
195 }
196
197 static VkResult
198 create_color_renderpass(struct radv_device *device,
199 VkFormat vk_format,
200 uint32_t samples,
201 VkRenderPass *pass)
202 {
203 return radv_CreateRenderPass(radv_device_to_handle(device),
204 &(VkRenderPassCreateInfo) {
205 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
206 .attachmentCount = 1,
207 .pAttachments = &(VkAttachmentDescription) {
208 .format = vk_format,
209 .samples = samples,
210 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
211 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
212 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
213 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
214 },
215 .subpassCount = 1,
216 .pSubpasses = &(VkSubpassDescription) {
217 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
218 .inputAttachmentCount = 0,
219 .colorAttachmentCount = 1,
220 .pColorAttachments = &(VkAttachmentReference) {
221 .attachment = 0,
222 .layout = VK_IMAGE_LAYOUT_GENERAL,
223 },
224 .pResolveAttachments = NULL,
225 .pDepthStencilAttachment = &(VkAttachmentReference) {
226 .attachment = VK_ATTACHMENT_UNUSED,
227 .layout = VK_IMAGE_LAYOUT_GENERAL,
228 },
229 .preserveAttachmentCount = 1,
230 .pPreserveAttachments = (uint32_t[]) { 0 },
231 },
232 .dependencyCount = 0,
233 }, &device->meta_state.alloc, pass);
234 }
235
236 static VkResult
237 create_color_pipeline(struct radv_device *device,
238 uint32_t samples,
239 uint32_t frag_output,
240 VkPipeline *pipeline,
241 VkRenderPass pass)
242 {
243 struct nir_shader *vs_nir;
244 struct nir_shader *fs_nir;
245 VkResult result;
246 build_color_shaders(&vs_nir, &fs_nir, frag_output);
247
248 const VkPipelineVertexInputStateCreateInfo vi_state = {
249 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
250 .vertexBindingDescriptionCount = 0,
251 .vertexAttributeDescriptionCount = 0,
252 };
253
254 const VkPipelineDepthStencilStateCreateInfo ds_state = {
255 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
256 .depthTestEnable = false,
257 .depthWriteEnable = false,
258 .depthBoundsTestEnable = false,
259 .stencilTestEnable = false,
260 };
261
262 VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
263 blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
264 .blendEnable = false,
265 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
266 VK_COLOR_COMPONENT_R_BIT |
267 VK_COLOR_COMPONENT_G_BIT |
268 VK_COLOR_COMPONENT_B_BIT,
269 };
270
271 const VkPipelineColorBlendStateCreateInfo cb_state = {
272 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
273 .logicOpEnable = false,
274 .attachmentCount = MAX_RTS,
275 .pAttachments = blend_attachment_state
276 };
277
278
279 struct radv_graphics_pipeline_create_info extra = {
280 .use_rectlist = true,
281 };
282 result = create_pipeline(device, radv_render_pass_from_handle(pass),
283 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
284 device->meta_state.clear_color_p_layout,
285 &extra, &device->meta_state.alloc, pipeline);
286
287 return result;
288 }
289
290 static void
291 destroy_render_pass(struct radv_device *device, VkRenderPass renderpass)
292 {
293 radv_DestroyRenderPass(radv_device_to_handle(device), renderpass,
294 &device->meta_state.alloc);
295 }
296
297 void
298 radv_device_finish_meta_clear_state(struct radv_device *device)
299 {
300 struct radv_meta_state *state = &device->meta_state;
301
302 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
303 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
304 radv_DestroyPipeline(radv_device_to_handle(device),
305 state->clear[i].color_pipelines[j],
306 &device->meta_state.alloc);
307 destroy_render_pass(device, state->clear[i].render_pass[j]);
308 }
309
310 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
311 radv_DestroyPipeline(radv_device_to_handle(device),
312 state->clear[i].depth_only_pipeline[j],
313 &device->meta_state.alloc);
314 radv_DestroyPipeline(radv_device_to_handle(device),
315 state->clear[i].stencil_only_pipeline[j],
316 &device->meta_state.alloc);
317 radv_DestroyPipeline(radv_device_to_handle(device),
318 state->clear[i].depthstencil_pipeline[j],
319 &device->meta_state.alloc);
320 }
321 destroy_render_pass(device, state->clear[i].depthstencil_rp);
322 }
323 radv_DestroyPipelineLayout(radv_device_to_handle(device),
324 state->clear_color_p_layout,
325 &state->alloc);
326 radv_DestroyPipelineLayout(radv_device_to_handle(device),
327 state->clear_depth_p_layout,
328 &state->alloc);
329 }
330
331 static void
332 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
333 const VkClearAttachment *clear_att,
334 const VkClearRect *clear_rect,
335 uint32_t view_mask)
336 {
337 struct radv_device *device = cmd_buffer->device;
338 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
339 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
340 const uint32_t subpass_att = clear_att->colorAttachment;
341 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
342 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
343 const uint32_t samples = iview->image->info.samples;
344 const uint32_t samples_log2 = ffs(samples) - 1;
345 unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
346 VkClearColorValue clear_value = clear_att->clearValue.color;
347 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
348 VkPipeline pipeline;
349
350 if (fs_key == -1) {
351 radv_finishme("color clears incomplete");
352 return;
353 }
354
355 pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
356 if (!pipeline) {
357 radv_finishme("color clears incomplete");
358 return;
359 }
360 assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
361 assert(pipeline);
362 assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
363 assert(clear_att->colorAttachment < subpass->color_count);
364
365 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
366 device->meta_state.clear_color_p_layout,
367 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
368 &clear_value);
369
370 struct radv_subpass clear_subpass = {
371 .color_count = 1,
372 .color_attachments = (VkAttachmentReference[]) {
373 subpass->color_attachments[clear_att->colorAttachment]
374 },
375 .depth_stencil_attachment = (VkAttachmentReference) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
376 };
377
378 radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
379
380 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
381 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
382 pipeline);
383 }
384
385 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
386 .x = clear_rect->rect.offset.x,
387 .y = clear_rect->rect.offset.y,
388 .width = clear_rect->rect.extent.width,
389 .height = clear_rect->rect.extent.height,
390 .minDepth = 0.0f,
391 .maxDepth = 1.0f
392 });
393
394 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
395
396 if (view_mask) {
397 unsigned i;
398 for_each_bit(i, view_mask)
399 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
400 } else {
401 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
402 }
403
404 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
405 }
406
407
408 static void
409 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
410 {
411 nir_builder vs_b, fs_b;
412
413 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
414 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
415
416 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
417 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
418 const struct glsl_type *position_out_type = glsl_vec4_type();
419
420 nir_variable *vs_out_pos =
421 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
422 "gl_Position");
423 vs_out_pos->data.location = VARYING_SLOT_POS;
424
425 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
426 nir_intrinsic_set_base(in_color_load, 0);
427 nir_intrinsic_set_range(in_color_load, 4);
428 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
429 in_color_load->num_components = 1;
430 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
431 nir_builder_instr_insert(&vs_b, &in_color_load->instr);
432
433 nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
434 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
435
436 const struct glsl_type *layer_type = glsl_int_type();
437 nir_variable *vs_out_layer =
438 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
439 "v_layer");
440 vs_out_layer->data.location = VARYING_SLOT_LAYER;
441 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
442 nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
443 nir_ssa_def *base_instance = nir_load_system_value(&vs_b, nir_intrinsic_load_base_instance, 0);
444
445 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
446 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
447
448 *out_vs = vs_b.shader;
449 *out_fs = fs_b.shader;
450 }
451
452 static VkResult
453 create_depthstencil_renderpass(struct radv_device *device,
454 uint32_t samples,
455 VkRenderPass *render_pass)
456 {
457 return radv_CreateRenderPass(radv_device_to_handle(device),
458 &(VkRenderPassCreateInfo) {
459 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
460 .attachmentCount = 1,
461 .pAttachments = &(VkAttachmentDescription) {
462 .format = VK_FORMAT_D32_SFLOAT_S8_UINT,
463 .samples = samples,
464 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
465 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
466 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
467 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
468 },
469 .subpassCount = 1,
470 .pSubpasses = &(VkSubpassDescription) {
471 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
472 .inputAttachmentCount = 0,
473 .colorAttachmentCount = 0,
474 .pColorAttachments = NULL,
475 .pResolveAttachments = NULL,
476 .pDepthStencilAttachment = &(VkAttachmentReference) {
477 .attachment = 0,
478 .layout = VK_IMAGE_LAYOUT_GENERAL,
479 },
480 .preserveAttachmentCount = 1,
481 .pPreserveAttachments = (uint32_t[]) { 0 },
482 },
483 .dependencyCount = 0,
484 }, &device->meta_state.alloc, render_pass);
485 }
486
487 static VkResult
488 create_depthstencil_pipeline(struct radv_device *device,
489 VkImageAspectFlags aspects,
490 uint32_t samples,
491 int index,
492 VkPipeline *pipeline,
493 VkRenderPass render_pass)
494 {
495 struct nir_shader *vs_nir, *fs_nir;
496 VkResult result;
497 build_depthstencil_shader(&vs_nir, &fs_nir);
498
499 const VkPipelineVertexInputStateCreateInfo vi_state = {
500 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
501 .vertexBindingDescriptionCount = 0,
502 .vertexAttributeDescriptionCount = 0,
503 };
504
505 const VkPipelineDepthStencilStateCreateInfo ds_state = {
506 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
507 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
508 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
509 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
510 .depthBoundsTestEnable = false,
511 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
512 .front = {
513 .passOp = VK_STENCIL_OP_REPLACE,
514 .compareOp = VK_COMPARE_OP_ALWAYS,
515 .writeMask = UINT32_MAX,
516 .reference = 0, /* dynamic */
517 },
518 .back = { 0 /* dont care */ },
519 };
520
521 const VkPipelineColorBlendStateCreateInfo cb_state = {
522 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
523 .logicOpEnable = false,
524 .attachmentCount = 0,
525 .pAttachments = NULL,
526 };
527
528 struct radv_graphics_pipeline_create_info extra = {
529 .use_rectlist = true,
530 };
531
532 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
533 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
534 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
535 }
536 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
537 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
538 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
539 }
540 result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
541 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
542 device->meta_state.clear_depth_p_layout,
543 &extra, &device->meta_state.alloc, pipeline);
544 return result;
545 }
546
547 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
548 const struct radv_image_view *iview,
549 VkImageLayout layout,
550 const VkClearRect *clear_rect)
551 {
552 uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
553 cmd_buffer->queue_family_index,
554 cmd_buffer->queue_family_index);
555 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
556 clear_rect->rect.extent.width != iview->extent.width ||
557 clear_rect->rect.extent.height != iview->extent.height)
558 return false;
559 if (iview->image->surface.htile_size &&
560 iview->base_mip == 0 &&
561 iview->base_layer == 0 &&
562 radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
563 !radv_image_extent_compare(iview->image, &iview->extent))
564 return true;
565 return false;
566 }
567
568 static VkPipeline
569 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
570 struct radv_meta_state *meta_state,
571 const struct radv_image_view *iview,
572 int samples_log2,
573 VkImageAspectFlags aspects,
574 VkImageLayout layout,
575 const VkClearRect *clear_rect,
576 VkClearDepthStencilValue clear_value)
577 {
578 bool fast = depth_view_can_fast_clear(cmd_buffer, iview, layout, clear_rect);
579 int index = DEPTH_CLEAR_SLOW;
580
581 if (fast) {
582 /* we don't know the previous clear values, so we always have
583 * the NO_EXPCLEAR path */
584 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
585 }
586
587 switch (aspects) {
588 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
589 return meta_state->clear[samples_log2].depthstencil_pipeline[index];
590 case VK_IMAGE_ASPECT_DEPTH_BIT:
591 return meta_state->clear[samples_log2].depth_only_pipeline[index];
592 case VK_IMAGE_ASPECT_STENCIL_BIT:
593 return meta_state->clear[samples_log2].stencil_only_pipeline[index];
594 }
595 unreachable("expected depth or stencil aspect");
596 }
597
598 static void
599 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
600 const VkClearAttachment *clear_att,
601 const VkClearRect *clear_rect)
602 {
603 struct radv_device *device = cmd_buffer->device;
604 struct radv_meta_state *meta_state = &device->meta_state;
605 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
606 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
607 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
608 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
609 VkImageAspectFlags aspects = clear_att->aspectMask;
610 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
611 const uint32_t samples = iview->image->info.samples;
612 const uint32_t samples_log2 = ffs(samples) - 1;
613 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
614
615 assert(aspects == VK_IMAGE_ASPECT_DEPTH_BIT ||
616 aspects == VK_IMAGE_ASPECT_STENCIL_BIT ||
617 aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
618 VK_IMAGE_ASPECT_STENCIL_BIT));
619 assert(pass_att != VK_ATTACHMENT_UNUSED);
620
621 if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
622 clear_value.depth = 1.0f;
623
624 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
625 device->meta_state.clear_depth_p_layout,
626 VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
627 &clear_value.depth);
628
629 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
630 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
631 clear_value.stencil);
632 }
633
634 VkPipeline pipeline = pick_depthstencil_pipeline(cmd_buffer,
635 meta_state,
636 iview,
637 samples_log2,
638 aspects,
639 subpass->depth_stencil_attachment.layout,
640 clear_rect,
641 clear_value);
642
643 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
644 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
645 pipeline);
646 }
647
648 if (depth_view_can_fast_clear(cmd_buffer, iview, subpass->depth_stencil_attachment.layout, clear_rect))
649 radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
650
651 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
652 .x = clear_rect->rect.offset.x,
653 .y = clear_rect->rect.offset.y,
654 .width = clear_rect->rect.extent.width,
655 .height = clear_rect->rect.extent.height,
656 .minDepth = 0.0f,
657 .maxDepth = 1.0f
658 });
659
660 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
661
662 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
663 }
664
665 static bool
666 emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
667 const VkClearAttachment *clear_att,
668 const VkClearRect *clear_rect,
669 enum radv_cmd_flush_bits *pre_flush,
670 enum radv_cmd_flush_bits *post_flush)
671 {
672 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
673 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
674 VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
675 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
676 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
677 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
678 VkImageAspectFlags aspects = clear_att->aspectMask;
679 uint32_t clear_word;
680
681 if (!iview->image->surface.htile_size)
682 return false;
683
684 if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
685 return false;
686
687 if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
688 goto fail;
689
690 /* don't fast clear 3D */
691 if (iview->image->type == VK_IMAGE_TYPE_3D)
692 goto fail;
693
694 /* all layers are bound */
695 if (iview->base_layer > 0)
696 goto fail;
697 if (iview->image->info.array_size != iview->layer_count)
698 goto fail;
699
700 if (iview->image->info.levels > 1)
701 goto fail;
702
703 if (!radv_image_extent_compare(iview->image, &iview->extent))
704 goto fail;
705
706 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
707 clear_rect->rect.extent.width != iview->image->info.width ||
708 clear_rect->rect.extent.height != iview->image->info.height)
709 goto fail;
710
711 if (clear_rect->baseArrayLayer != 0)
712 goto fail;
713 if (clear_rect->layerCount != iview->image->info.array_size)
714 goto fail;
715
716 if ((clear_value.depth != 0.0 && clear_value.depth != 1.0) || !(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
717 goto fail;
718
719 if (vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) {
720 if (clear_value.stencil != 0 || !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))
721 goto fail;
722 clear_word = clear_value.depth ? 0xfffc0000 : 0;
723 } else
724 clear_word = clear_value.depth ? 0xfffffff0 : 0;
725
726 if (pre_flush) {
727 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
728 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
729 *pre_flush |= cmd_buffer->state.flush_bits;
730 } else
731 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
732 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
733
734 radv_fill_buffer(cmd_buffer, iview->image->bo,
735 iview->image->offset + iview->image->htile_offset,
736 iview->image->surface.htile_size, clear_word);
737
738
739 radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
740 if (post_flush)
741 *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
742 RADV_CMD_FLAG_INV_VMEM_L1 |
743 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
744 else
745 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
746 RADV_CMD_FLAG_INV_VMEM_L1 |
747 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
748 return true;
749 fail:
750 return false;
751 }
752
753 static VkFormat pipeline_formats[] = {
754 VK_FORMAT_R8G8B8A8_UNORM,
755 VK_FORMAT_R8G8B8A8_UINT,
756 VK_FORMAT_R8G8B8A8_SINT,
757 VK_FORMAT_A2R10G10B10_UINT_PACK32,
758 VK_FORMAT_A2R10G10B10_SINT_PACK32,
759 VK_FORMAT_R16G16B16A16_UNORM,
760 VK_FORMAT_R16G16B16A16_SNORM,
761 VK_FORMAT_R16G16B16A16_UINT,
762 VK_FORMAT_R16G16B16A16_SINT,
763 VK_FORMAT_R32_SFLOAT,
764 VK_FORMAT_R32G32_SFLOAT,
765 VK_FORMAT_R32G32B32A32_SFLOAT
766 };
767
768 VkResult
769 radv_device_init_meta_clear_state(struct radv_device *device)
770 {
771 VkResult res;
772 struct radv_meta_state *state = &device->meta_state;
773
774 memset(&device->meta_state.clear, 0, sizeof(device->meta_state.clear));
775
776 VkPipelineLayoutCreateInfo pl_color_create_info = {
777 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
778 .setLayoutCount = 0,
779 .pushConstantRangeCount = 1,
780 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
781 };
782
783 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
784 &pl_color_create_info,
785 &device->meta_state.alloc,
786 &device->meta_state.clear_color_p_layout);
787 if (res != VK_SUCCESS)
788 goto fail;
789
790 VkPipelineLayoutCreateInfo pl_depth_create_info = {
791 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
792 .setLayoutCount = 0,
793 .pushConstantRangeCount = 1,
794 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
795 };
796
797 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
798 &pl_depth_create_info,
799 &device->meta_state.alloc,
800 &device->meta_state.clear_depth_p_layout);
801 if (res != VK_SUCCESS)
802 goto fail;
803
804 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
805 uint32_t samples = 1 << i;
806 for (uint32_t j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
807 VkFormat format = pipeline_formats[j];
808 unsigned fs_key = radv_format_meta_fs_key(format);
809 assert(!state->clear[i].color_pipelines[fs_key]);
810
811 res = create_color_renderpass(device, format, samples,
812 &state->clear[i].render_pass[fs_key]);
813 if (res != VK_SUCCESS)
814 goto fail;
815
816 res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
817 state->clear[i].render_pass[fs_key]);
818 if (res != VK_SUCCESS)
819 goto fail;
820
821 }
822
823 res = create_depthstencil_renderpass(device,
824 samples,
825 &state->clear[i].depthstencil_rp);
826 if (res != VK_SUCCESS)
827 goto fail;
828
829 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
830 res = create_depthstencil_pipeline(device,
831 VK_IMAGE_ASPECT_DEPTH_BIT,
832 samples,
833 j,
834 &state->clear[i].depth_only_pipeline[j],
835 state->clear[i].depthstencil_rp);
836 if (res != VK_SUCCESS)
837 goto fail;
838
839 res = create_depthstencil_pipeline(device,
840 VK_IMAGE_ASPECT_STENCIL_BIT,
841 samples,
842 j,
843 &state->clear[i].stencil_only_pipeline[j],
844 state->clear[i].depthstencil_rp);
845 if (res != VK_SUCCESS)
846 goto fail;
847
848 res = create_depthstencil_pipeline(device,
849 VK_IMAGE_ASPECT_DEPTH_BIT |
850 VK_IMAGE_ASPECT_STENCIL_BIT,
851 samples,
852 j,
853 &state->clear[i].depthstencil_pipeline[j],
854 state->clear[i].depthstencil_rp);
855 if (res != VK_SUCCESS)
856 goto fail;
857 }
858 }
859 return VK_SUCCESS;
860
861 fail:
862 radv_device_finish_meta_clear_state(device);
863 return res;
864 }
865
866 static void vi_get_fast_clear_parameters(VkFormat format,
867 const VkClearColorValue *clear_value,
868 uint32_t* reset_value,
869 bool *can_avoid_fast_clear_elim)
870 {
871 bool values[4] = {};
872 int extra_channel;
873 bool main_value = false;
874 bool extra_value = false;
875 int i;
876 *can_avoid_fast_clear_elim = false;
877
878 *reset_value = 0x20202020U;
879
880 const struct vk_format_description *desc = vk_format_description(format);
881 if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
882 format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
883 format == VK_FORMAT_B5G6R5_UNORM_PACK16)
884 extra_channel = -1;
885 else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
886 if (radv_translate_colorswap(format, false) <= 1)
887 extra_channel = desc->nr_channels - 1;
888 else
889 extra_channel = 0;
890 } else
891 return;
892
893 for (i = 0; i < 4; i++) {
894 int index = desc->swizzle[i] - VK_SWIZZLE_X;
895 if (desc->swizzle[i] < VK_SWIZZLE_X ||
896 desc->swizzle[i] > VK_SWIZZLE_W)
897 continue;
898
899 if (desc->channel[i].pure_integer &&
900 desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
901 /* Use the maximum value for clamping the clear color. */
902 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
903
904 values[i] = clear_value->int32[i] != 0;
905 if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
906 return;
907 } else if (desc->channel[i].pure_integer &&
908 desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
909 /* Use the maximum value for clamping the clear color. */
910 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
911
912 values[i] = clear_value->uint32[i] != 0U;
913 if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
914 return;
915 } else {
916 values[i] = clear_value->float32[i] != 0.0F;
917 if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
918 return;
919 }
920
921 if (index == extra_channel)
922 extra_value = values[i];
923 else
924 main_value = values[i];
925 }
926
927 for (int i = 0; i < 4; ++i)
928 if (values[i] != main_value &&
929 desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
930 desc->swizzle[i] >= VK_SWIZZLE_X &&
931 desc->swizzle[i] <= VK_SWIZZLE_W)
932 return;
933
934 *can_avoid_fast_clear_elim = true;
935 if (main_value)
936 *reset_value |= 0x80808080U;
937
938 if (extra_value)
939 *reset_value |= 0x40404040U;
940 return;
941 }
942
943 static bool
944 emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
945 const VkClearAttachment *clear_att,
946 const VkClearRect *clear_rect,
947 enum radv_cmd_flush_bits *pre_flush,
948 enum radv_cmd_flush_bits *post_flush,
949 uint32_t view_mask)
950 {
951 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
952 const uint32_t subpass_att = clear_att->colorAttachment;
953 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
954 VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
955 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
956 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
957 VkClearColorValue clear_value = clear_att->clearValue.color;
958 uint32_t clear_color[2];
959 bool ret;
960
961 if (!iview->image->cmask.size && !iview->image->surface.dcc_size)
962 return false;
963
964 if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
965 return false;
966
967 if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
968 goto fail;
969
970 /* don't fast clear 3D */
971 if (iview->image->type == VK_IMAGE_TYPE_3D)
972 goto fail;
973
974 /* all layers are bound */
975 if (iview->base_layer > 0)
976 goto fail;
977 if (iview->image->info.array_size != iview->layer_count)
978 goto fail;
979
980 if (iview->image->info.levels > 1)
981 goto fail;
982
983 if (iview->image->surface.is_linear)
984 goto fail;
985 if (!radv_image_extent_compare(iview->image, &iview->extent))
986 goto fail;
987
988 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
989 clear_rect->rect.extent.width != iview->image->info.width ||
990 clear_rect->rect.extent.height != iview->image->info.height)
991 goto fail;
992
993 if (view_mask && (iview->image->info.array_size >= 32 ||
994 (1u << iview->image->info.array_size) - 1u != view_mask))
995 goto fail;
996 if (!view_mask && clear_rect->baseArrayLayer != 0)
997 goto fail;
998 if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
999 goto fail;
1000
1001 /* RB+ doesn't work with CMASK fast clear on Stoney. */
1002 if (!iview->image->surface.dcc_size &&
1003 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY)
1004 goto fail;
1005
1006 /* DCC */
1007 ret = radv_format_pack_clear_color(iview->image->vk_format,
1008 clear_color, &clear_value);
1009 if (ret == false)
1010 goto fail;
1011
1012 if (pre_flush) {
1013 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1014 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
1015 *pre_flush |= cmd_buffer->state.flush_bits;
1016 } else
1017 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1018 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1019 /* clear cmask buffer */
1020 if (iview->image->surface.dcc_size) {
1021 uint32_t reset_value;
1022 bool can_avoid_fast_clear_elim;
1023 vi_get_fast_clear_parameters(iview->image->vk_format,
1024 &clear_value, &reset_value,
1025 &can_avoid_fast_clear_elim);
1026
1027 radv_fill_buffer(cmd_buffer, iview->image->bo,
1028 iview->image->offset + iview->image->dcc_offset,
1029 iview->image->surface.dcc_size, reset_value);
1030 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
1031 !can_avoid_fast_clear_elim);
1032 } else {
1033
1034 if (iview->image->surface.bpe > 8) {
1035 /* 128 bit formats not supported */
1036 return false;
1037 }
1038 radv_fill_buffer(cmd_buffer, iview->image->bo,
1039 iview->image->offset + iview->image->cmask.offset,
1040 iview->image->cmask.size, 0);
1041 }
1042
1043 if (post_flush)
1044 *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1045 RADV_CMD_FLAG_INV_VMEM_L1 |
1046 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1047 else
1048 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1049 RADV_CMD_FLAG_INV_VMEM_L1 |
1050 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1051
1052 radv_set_color_clear_regs(cmd_buffer, iview->image, subpass_att, clear_color);
1053
1054 return true;
1055 fail:
1056 return false;
1057 }
1058
1059 /**
1060 * The parameters mean that same as those in vkCmdClearAttachments.
1061 */
1062 static void
1063 emit_clear(struct radv_cmd_buffer *cmd_buffer,
1064 const VkClearAttachment *clear_att,
1065 const VkClearRect *clear_rect,
1066 enum radv_cmd_flush_bits *pre_flush,
1067 enum radv_cmd_flush_bits *post_flush,
1068 uint32_t view_mask)
1069 {
1070 if (clear_att->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1071 if (!emit_fast_color_clear(cmd_buffer, clear_att, clear_rect,
1072 pre_flush, post_flush, view_mask))
1073 emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask);
1074 } else {
1075 assert(clear_att->aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT |
1076 VK_IMAGE_ASPECT_STENCIL_BIT));
1077 if (!emit_fast_htile_clear(cmd_buffer, clear_att, clear_rect,
1078 pre_flush, post_flush))
1079 emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
1080 }
1081 }
1082
1083 static bool
1084 subpass_needs_clear(const struct radv_cmd_buffer *cmd_buffer)
1085 {
1086 const struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1087 uint32_t ds;
1088
1089 if (!cmd_state->subpass)
1090 return false;
1091 uint32_t view_mask = cmd_state->subpass->view_mask;
1092 ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1093 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1094 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1095 if (a != VK_ATTACHMENT_UNUSED &&
1096 cmd_state->attachments[a].pending_clear_aspects &&
1097 (!view_mask || (view_mask & ~cmd_state->attachments[a].cleared_views))) {
1098 return true;
1099 }
1100 }
1101
1102 if (ds != VK_ATTACHMENT_UNUSED &&
1103 cmd_state->attachments[ds].pending_clear_aspects &&
1104 (!view_mask || (view_mask & ~cmd_state->attachments[ds].cleared_views))) {
1105 return true;
1106 }
1107
1108 return false;
1109 }
1110
1111 /**
1112 * Emit any pending attachment clears for the current subpass.
1113 *
1114 * @see radv_attachment_state::pending_clear_aspects
1115 */
1116 void
1117 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1118 {
1119 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1120 struct radv_meta_saved_state saved_state;
1121 enum radv_cmd_flush_bits pre_flush = 0;
1122 enum radv_cmd_flush_bits post_flush = 0;
1123 uint32_t view_mask = cmd_buffer->state.subpass->view_mask;
1124
1125 if (!subpass_needs_clear(cmd_buffer))
1126 return;
1127
1128 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
1129
1130 VkClearRect clear_rect = {
1131 .rect = cmd_state->render_area,
1132 .baseArrayLayer = 0,
1133 .layerCount = cmd_state->framebuffer->layers,
1134 };
1135
1136 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1137 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1138
1139 if (a == VK_ATTACHMENT_UNUSED ||
1140 !cmd_state->attachments[a].pending_clear_aspects ||
1141 (view_mask && !(view_mask & ~cmd_state->attachments[a].cleared_views)))
1142 continue;
1143
1144 assert(cmd_state->attachments[a].pending_clear_aspects ==
1145 VK_IMAGE_ASPECT_COLOR_BIT);
1146
1147 VkClearAttachment clear_att = {
1148 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1149 .colorAttachment = i, /* Use attachment index relative to subpass */
1150 .clearValue = cmd_state->attachments[a].clear_value,
1151 };
1152
1153 emit_clear(cmd_buffer, &clear_att, &clear_rect, &pre_flush, &post_flush,
1154 view_mask & ~cmd_state->attachments[a].cleared_views);
1155 if (view_mask)
1156 cmd_state->attachments[a].cleared_views |= view_mask;
1157 else
1158 cmd_state->attachments[a].pending_clear_aspects = 0;
1159 }
1160
1161 uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1162
1163 if (ds != VK_ATTACHMENT_UNUSED) {
1164
1165 if (cmd_state->attachments[ds].pending_clear_aspects &&
1166 (!view_mask || (view_mask & ~cmd_state->attachments[ds].cleared_views))) {
1167
1168 VkClearAttachment clear_att = {
1169 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1170 .clearValue = cmd_state->attachments[ds].clear_value,
1171 };
1172
1173 emit_clear(cmd_buffer, &clear_att, &clear_rect,
1174 &pre_flush, &post_flush,
1175 view_mask & ~cmd_state->attachments[ds].cleared_views);
1176 if (view_mask)
1177 cmd_state->attachments[ds].cleared_views |= view_mask;
1178 else
1179 cmd_state->attachments[ds].pending_clear_aspects = 0;
1180 }
1181 }
1182
1183 radv_meta_restore(&saved_state, cmd_buffer);
1184 cmd_buffer->state.flush_bits |= post_flush;
1185 }
1186
1187 static void
1188 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1189 struct radv_image *image,
1190 VkImageLayout image_layout,
1191 const VkImageSubresourceRange *range,
1192 VkFormat format, int level, int layer,
1193 const VkClearValue *clear_val)
1194 {
1195 VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1196 struct radv_image_view iview;
1197 uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level);
1198 uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level);
1199
1200 radv_image_view_init(&iview, cmd_buffer->device,
1201 &(VkImageViewCreateInfo) {
1202 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1203 .image = radv_image_to_handle(image),
1204 .viewType = radv_meta_get_view_type(image),
1205 .format = format,
1206 .subresourceRange = {
1207 .aspectMask = range->aspectMask,
1208 .baseMipLevel = range->baseMipLevel + level,
1209 .levelCount = 1,
1210 .baseArrayLayer = range->baseArrayLayer + layer,
1211 .layerCount = 1
1212 },
1213 });
1214
1215 VkFramebuffer fb;
1216 radv_CreateFramebuffer(device_h,
1217 &(VkFramebufferCreateInfo) {
1218 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1219 .attachmentCount = 1,
1220 .pAttachments = (VkImageView[]) {
1221 radv_image_view_to_handle(&iview),
1222 },
1223 .width = width,
1224 .height = height,
1225 .layers = 1
1226 },
1227 &cmd_buffer->pool->alloc,
1228 &fb);
1229
1230 VkAttachmentDescription att_desc = {
1231 .format = iview.vk_format,
1232 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1233 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1234 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1235 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1236 .initialLayout = image_layout,
1237 .finalLayout = image_layout,
1238 };
1239
1240 VkSubpassDescription subpass_desc = {
1241 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1242 .inputAttachmentCount = 0,
1243 .colorAttachmentCount = 0,
1244 .pColorAttachments = NULL,
1245 .pResolveAttachments = NULL,
1246 .pDepthStencilAttachment = NULL,
1247 .preserveAttachmentCount = 0,
1248 .pPreserveAttachments = NULL,
1249 };
1250
1251 const VkAttachmentReference att_ref = {
1252 .attachment = 0,
1253 .layout = image_layout,
1254 };
1255
1256 if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1257 subpass_desc.colorAttachmentCount = 1;
1258 subpass_desc.pColorAttachments = &att_ref;
1259 } else {
1260 subpass_desc.pDepthStencilAttachment = &att_ref;
1261 }
1262
1263 VkRenderPass pass;
1264 radv_CreateRenderPass(device_h,
1265 &(VkRenderPassCreateInfo) {
1266 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1267 .attachmentCount = 1,
1268 .pAttachments = &att_desc,
1269 .subpassCount = 1,
1270 .pSubpasses = &subpass_desc,
1271 },
1272 &cmd_buffer->pool->alloc,
1273 &pass);
1274
1275 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1276 &(VkRenderPassBeginInfo) {
1277 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1278 .renderArea = {
1279 .offset = { 0, 0, },
1280 .extent = {
1281 .width = width,
1282 .height = height,
1283 },
1284 },
1285 .renderPass = pass,
1286 .framebuffer = fb,
1287 .clearValueCount = 0,
1288 .pClearValues = NULL,
1289 },
1290 VK_SUBPASS_CONTENTS_INLINE);
1291
1292 VkClearAttachment clear_att = {
1293 .aspectMask = range->aspectMask,
1294 .colorAttachment = 0,
1295 .clearValue = *clear_val,
1296 };
1297
1298 VkClearRect clear_rect = {
1299 .rect = {
1300 .offset = { 0, 0 },
1301 .extent = { width, height },
1302 },
1303 .baseArrayLayer = range->baseArrayLayer,
1304 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1305 };
1306
1307 emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0);
1308
1309 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1310 radv_DestroyRenderPass(device_h, pass,
1311 &cmd_buffer->pool->alloc);
1312 radv_DestroyFramebuffer(device_h, fb,
1313 &cmd_buffer->pool->alloc);
1314 }
1315 static void
1316 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
1317 struct radv_image *image,
1318 VkImageLayout image_layout,
1319 const VkClearValue *clear_value,
1320 uint32_t range_count,
1321 const VkImageSubresourceRange *ranges,
1322 bool cs)
1323 {
1324 VkFormat format = image->vk_format;
1325 VkClearValue internal_clear_value = *clear_value;
1326
1327 if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
1328 uint32_t value;
1329 format = VK_FORMAT_R32_UINT;
1330 value = float3_to_rgb9e5(clear_value->color.float32);
1331 internal_clear_value.color.uint32[0] = value;
1332 }
1333
1334 if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
1335 uint8_t r, g;
1336 format = VK_FORMAT_R8_UINT;
1337 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
1338 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
1339 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
1340 }
1341
1342 for (uint32_t r = 0; r < range_count; r++) {
1343 const VkImageSubresourceRange *range = &ranges[r];
1344 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
1345 const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
1346 radv_minify(image->info.depth, range->baseMipLevel + l) :
1347 radv_get_layerCount(image, range);
1348 for (uint32_t s = 0; s < layer_count; ++s) {
1349
1350 if (cs) {
1351 struct radv_meta_blit2d_surf surf;
1352 surf.format = format;
1353 surf.image = image;
1354 surf.level = range->baseMipLevel + l;
1355 surf.layer = range->baseArrayLayer + s;
1356 surf.aspect_mask = range->aspectMask;
1357 radv_meta_clear_image_cs(cmd_buffer, &surf,
1358 &internal_clear_value.color);
1359 } else {
1360 radv_clear_image_layer(cmd_buffer, image, image_layout,
1361 range, format, l, s, &internal_clear_value);
1362 }
1363 }
1364 }
1365 }
1366 }
1367
1368 union meta_saved_state {
1369 struct radv_meta_saved_state gfx;
1370 struct radv_meta_saved_compute_state compute;
1371 };
1372
1373 void radv_CmdClearColorImage(
1374 VkCommandBuffer commandBuffer,
1375 VkImage image_h,
1376 VkImageLayout imageLayout,
1377 const VkClearColorValue* pColor,
1378 uint32_t rangeCount,
1379 const VkImageSubresourceRange* pRanges)
1380 {
1381 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1382 RADV_FROM_HANDLE(radv_image, image, image_h);
1383 union meta_saved_state saved_state;
1384 bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1385
1386 if (cs)
1387 radv_meta_save_compute(&saved_state.compute, cmd_buffer, 16);
1388 else
1389 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state.gfx, cmd_buffer);
1390
1391 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1392 (const VkClearValue *) pColor,
1393 rangeCount, pRanges, cs);
1394
1395 if (cs)
1396 radv_meta_restore_compute(&saved_state.compute, cmd_buffer);
1397 else
1398 radv_meta_restore(&saved_state.gfx, cmd_buffer);
1399 }
1400
1401 void radv_CmdClearDepthStencilImage(
1402 VkCommandBuffer commandBuffer,
1403 VkImage image_h,
1404 VkImageLayout imageLayout,
1405 const VkClearDepthStencilValue* pDepthStencil,
1406 uint32_t rangeCount,
1407 const VkImageSubresourceRange* pRanges)
1408 {
1409 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1410 RADV_FROM_HANDLE(radv_image, image, image_h);
1411 struct radv_meta_saved_state saved_state;
1412
1413 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
1414
1415 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1416 (const VkClearValue *) pDepthStencil,
1417 rangeCount, pRanges, false);
1418
1419 radv_meta_restore(&saved_state, cmd_buffer);
1420 }
1421
1422 void radv_CmdClearAttachments(
1423 VkCommandBuffer commandBuffer,
1424 uint32_t attachmentCount,
1425 const VkClearAttachment* pAttachments,
1426 uint32_t rectCount,
1427 const VkClearRect* pRects)
1428 {
1429 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1430 struct radv_meta_saved_state saved_state;
1431 enum radv_cmd_flush_bits pre_flush = 0;
1432 enum radv_cmd_flush_bits post_flush = 0;
1433
1434 if (!cmd_buffer->state.subpass)
1435 return;
1436
1437 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
1438
1439 /* FINISHME: We can do better than this dumb loop. It thrashes too much
1440 * state.
1441 */
1442 for (uint32_t a = 0; a < attachmentCount; ++a) {
1443 for (uint32_t r = 0; r < rectCount; ++r) {
1444 emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush,
1445 cmd_buffer->state.subpass->view_mask);
1446 }
1447 }
1448
1449 radv_meta_restore(&saved_state, cmd_buffer);
1450 cmd_buffer->state.flush_bits |= post_flush;
1451 }