src/amd/vulkan/radv_meta_clear.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "radv_debug.h"
  25 #include "radv_meta.h"
  26 #include "radv_private.h"
  27 #include "nir/nir_builder.h"
  28
  29 #include "util/format_rgb9e5.h"
  30 #include "vk_format.h"
  31
  32 enum {
  33         DEPTH_CLEAR_SLOW,
  34         DEPTH_CLEAR_FAST_EXPCLEAR,
  35         DEPTH_CLEAR_FAST_NO_EXPCLEAR
  36 };
  37
  38 static void
  39 build_color_shaders(struct nir_shader **out_vs,
  40                     struct nir_shader **out_fs,
  41                     uint32_t frag_output)
  42 {
  43         nir_builder vs_b;
  44         nir_builder fs_b;
  45
  46         nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
  47         nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
  48
  49         vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
  50         fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
  51
  52         const struct glsl_type *position_type = glsl_vec4_type();
  53         const struct glsl_type *color_type = glsl_vec4_type();
  54
  55         nir_variable *vs_out_pos =
  56                 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
  57                                     "gl_Position");
  58         vs_out_pos->data.location = VARYING_SLOT_POS;
  59
  60         nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
  61         nir_intrinsic_set_base(in_color_load, 0);
  62         nir_intrinsic_set_range(in_color_load, 16);
  63         in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
  64         in_color_load->num_components = 4;
  65         nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
  66         nir_builder_instr_insert(&fs_b, &in_color_load->instr);
  67
  68         nir_variable *fs_out_color =
  69                 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
  70                                     "f_color");
  71         fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
  72
  73         nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
  74
  75         nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
  76         nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
  77
  78         const struct glsl_type *layer_type = glsl_int_type();
  79         nir_variable *vs_out_layer =
  80                 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
  81                                     "v_layer");
  82         vs_out_layer->data.location = VARYING_SLOT_LAYER;
  83         vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
  84         nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
  85         nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
  86
  87         nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
  88         nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
  89
  90         *out_vs = vs_b.shader;
  91         *out_fs = fs_b.shader;
  92 }
  93
  94 static VkResult
  95 create_pipeline(struct radv_device *device,
  96                 struct radv_render_pass *render_pass,
  97                 uint32_t samples,
  98                 struct nir_shader *vs_nir,
  99                 struct nir_shader *fs_nir,
 100                 const VkPipelineVertexInputStateCreateInfo *vi_state,
 101                 const VkPipelineDepthStencilStateCreateInfo *ds_state,
 102                 const VkPipelineColorBlendStateCreateInfo *cb_state,
 103                 const VkPipelineLayout layout,
 104                 const struct radv_graphics_pipeline_create_info *extra,
 105                 const VkAllocationCallbacks *alloc,
 106                 VkPipeline *pipeline)
 107 {
 108         VkDevice device_h = radv_device_to_handle(device);
 109         VkResult result;
 110
 111         struct radv_shader_module vs_m = { .nir = vs_nir };
 112         struct radv_shader_module fs_m = { .nir = fs_nir };
 113
 114         result = radv_graphics_pipeline_create(device_h,
 115                                                radv_pipeline_cache_to_handle(&device->meta_state.cache),
 116                                                &(VkGraphicsPipelineCreateInfo) {
 117                                                        .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
 118                                                                .stageCount = fs_nir ? 2 : 1,
 119                                                                .pStages = (VkPipelineShaderStageCreateInfo[]) {
 120                                                                {
 121                                                                        .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
 122                                                                        .stage = VK_SHADER_STAGE_VERTEX_BIT,
 123                                                                        .module = radv_shader_module_to_handle(&vs_m),
 124                                                                        .pName = "main",
 125                                                                },
 126                                                                {
 127                                                                        .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
 128                                                                        .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
 129                                                                        .module = radv_shader_module_to_handle(&fs_m),
 130                                                                        .pName = "main",
 131                                                                },
 132                                                        },
 133                                                                .pVertexInputState = vi_state,
 134                                                                         .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
 135                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
 136                                                                .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
 137                                                                .primitiveRestartEnable = false,
 138                                                        },
 139                                                                         .pViewportState = &(VkPipelineViewportStateCreateInfo) {
 140                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
 141                                                                .viewportCount = 1,
 142                                                                .scissorCount = 1,
 143                                                        },
 144                                                                                  .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
 145                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
 146                                                                .rasterizerDiscardEnable = false,
 147                                                                .polygonMode = VK_POLYGON_MODE_FILL,
 148                                                                .cullMode = VK_CULL_MODE_NONE,
 149                                                                .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
 150                                                                .depthBiasEnable = false,
 151                                                        },
 152                                                                                           .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
 153                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
 154                                                                .rasterizationSamples = samples,
 155                                                                .sampleShadingEnable = false,
 156                                                                .pSampleMask = NULL,
 157                                                                .alphaToCoverageEnable = false,
 158                                                                .alphaToOneEnable = false,
 159                                                        },
 160                                                                                                    .pDepthStencilState = ds_state,
 161                                                                                                             .pColorBlendState = cb_state,
 162                                                                                                             .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
 163                                                                /* The meta clear pipeline declares all state as dynamic.
 164                                                                 * As a consequence, vkCmdBindPipeline writes no dynamic state
 165                                                                 * to the cmd buffer. Therefore, at the end of the meta clear,
 166                                                                 * we need only restore dynamic state was vkCmdSet.
 167                                                                 */
 168                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
 169                                                                .dynamicStateCount = 8,
 170                                                                .pDynamicStates = (VkDynamicState[]) {
 171                                                                        /* Everything except stencil write mask */
 172                                                                        VK_DYNAMIC_STATE_VIEWPORT,
 173                                                                        VK_DYNAMIC_STATE_SCISSOR,
 174                                                                        VK_DYNAMIC_STATE_LINE_WIDTH,
 175                                                                        VK_DYNAMIC_STATE_DEPTH_BIAS,
 176                                                                        VK_DYNAMIC_STATE_BLEND_CONSTANTS,
 177                                                                        VK_DYNAMIC_STATE_DEPTH_BOUNDS,
 178                                                                        VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
 179                                                                        VK_DYNAMIC_STATE_STENCIL_REFERENCE,
 180                                                                },
 181                                                        },
 182                                                     .layout = layout,
 183                                                     .flags = 0,
 184                                                     .renderPass = radv_render_pass_to_handle(render_pass),
 185                                                     .subpass = 0,
 186                                                 },
 187                                                extra,
 188                                                alloc,
 189                                                pipeline);
 190
 191         ralloc_free(vs_nir);
 192         ralloc_free(fs_nir);
 193
 194         return result;
 195 }
 196
 197 static VkResult
 198 create_color_renderpass(struct radv_device *device,
 199                         VkFormat vk_format,
 200                         uint32_t samples,
 201                         VkRenderPass *pass)
 202 {
 203         mtx_lock(&device->meta_state.mtx);
 204         if (*pass) {
 205                 mtx_unlock (&device->meta_state.mtx);
 206                 return VK_SUCCESS;
 207         }
 208
 209         VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
 210                                        &(VkRenderPassCreateInfo) {
 211                                                .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
 212                                                        .attachmentCount = 1,
 213                                                        .pAttachments = &(VkAttachmentDescription) {
 214                                                        .format = vk_format,
 215                                                        .samples = samples,
 216                                                        .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
 217                                                        .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
 218                                                        .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
 219                                                        .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
 220                                                },
 221                                                        .subpassCount = 1,
 222                                                                 .pSubpasses = &(VkSubpassDescription) {
 223                                                        .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
 224                                                        .inputAttachmentCount = 0,
 225                                                        .colorAttachmentCount = 1,
 226                                                        .pColorAttachments = &(VkAttachmentReference) {
 227                                                                .attachment = 0,
 228                                                                .layout = VK_IMAGE_LAYOUT_GENERAL,
 229                                                        },
 230                                                        .pResolveAttachments = NULL,
 231                                                        .pDepthStencilAttachment = &(VkAttachmentReference) {
 232                                                                .attachment = VK_ATTACHMENT_UNUSED,
 233                                                                .layout = VK_IMAGE_LAYOUT_GENERAL,
 234                                                        },
 235                                                        .preserveAttachmentCount = 1,
 236                                                        .pPreserveAttachments = (uint32_t[]) { 0 },
 237                                                },
 238                                                                 .dependencyCount = 0,
 239                                                                          }, &device->meta_state.alloc, pass);
 240         mtx_unlock(&device->meta_state.mtx);
 241         return result;
 242 }
 243
 244 static VkResult
 245 create_color_pipeline(struct radv_device *device,
 246                       uint32_t samples,
 247                       uint32_t frag_output,
 248                       VkPipeline *pipeline,
 249                       VkRenderPass pass)
 250 {
 251         struct nir_shader *vs_nir;
 252         struct nir_shader *fs_nir;
 253         VkResult result;
 254
 255         mtx_lock(&device->meta_state.mtx);
 256         if (*pipeline) {
 257                 mtx_unlock(&device->meta_state.mtx);
 258                 return VK_SUCCESS;
 259         }
 260
 261         build_color_shaders(&vs_nir, &fs_nir, frag_output);
 262
 263         const VkPipelineVertexInputStateCreateInfo vi_state = {
 264                 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
 265                 .vertexBindingDescriptionCount = 0,
 266                 .vertexAttributeDescriptionCount = 0,
 267         };
 268
 269         const VkPipelineDepthStencilStateCreateInfo ds_state = {
 270                 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
 271                 .depthTestEnable = false,
 272                 .depthWriteEnable = false,
 273                 .depthBoundsTestEnable = false,
 274                 .stencilTestEnable = false,
 275         };
 276
 277         VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
 278         blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
 279                 .blendEnable = false,
 280                 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
 281                 VK_COLOR_COMPONENT_R_BIT |
 282                 VK_COLOR_COMPONENT_G_BIT |
 283                 VK_COLOR_COMPONENT_B_BIT,
 284         };
 285
 286         const VkPipelineColorBlendStateCreateInfo cb_state = {
 287                 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
 288                 .logicOpEnable = false,
 289                 .attachmentCount = MAX_RTS,
 290                 .pAttachments = blend_attachment_state
 291         };
 292
 293
 294         struct radv_graphics_pipeline_create_info extra = {
 295                 .use_rectlist = true,
 296         };
 297         result = create_pipeline(device, radv_render_pass_from_handle(pass),
 298                                  samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
 299                                  device->meta_state.clear_color_p_layout,
 300                                  &extra, &device->meta_state.alloc, pipeline);
 301
 302         mtx_unlock(&device->meta_state.mtx);
 303         return result;
 304 }
 305
 306 static void
 307 finish_meta_clear_htile_mask_state(struct radv_device *device)
 308 {
 309         struct radv_meta_state *state = &device->meta_state;
 310
 311         radv_DestroyPipeline(radv_device_to_handle(device),
 312                              state->clear_htile_mask_pipeline,
 313                              &state->alloc);
 314         radv_DestroyPipelineLayout(radv_device_to_handle(device),
 315                                    state->clear_htile_mask_p_layout,
 316                                    &state->alloc);
 317         radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
 318                                         state->clear_htile_mask_ds_layout,
 319                                         &state->alloc);
 320 }
 321
 322 void
 323 radv_device_finish_meta_clear_state(struct radv_device *device)
 324 {
 325         struct radv_meta_state *state = &device->meta_state;
 326
 327         for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
 328                 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
 329                         radv_DestroyPipeline(radv_device_to_handle(device),
 330                                              state->clear[i].color_pipelines[j],
 331                                              &state->alloc);
 332                         radv_DestroyRenderPass(radv_device_to_handle(device),
 333                                                state->clear[i].render_pass[j],
 334                                                &state->alloc);
 335                 }
 336
 337                 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
 338                         radv_DestroyPipeline(radv_device_to_handle(device),
 339                                              state->clear[i].depth_only_pipeline[j],
 340                                              &state->alloc);
 341                         radv_DestroyPipeline(radv_device_to_handle(device),
 342                                              state->clear[i].stencil_only_pipeline[j],
 343                                              &state->alloc);
 344                         radv_DestroyPipeline(radv_device_to_handle(device),
 345                                              state->clear[i].depthstencil_pipeline[j],
 346                                              &state->alloc);
 347                 }
 348                 radv_DestroyRenderPass(radv_device_to_handle(device),
 349                                       state->clear[i].depthstencil_rp,
 350                                       &state->alloc);
 351         }
 352         radv_DestroyPipelineLayout(radv_device_to_handle(device),
 353                                    state->clear_color_p_layout,
 354                                    &state->alloc);
 355         radv_DestroyPipelineLayout(radv_device_to_handle(device),
 356                                    state->clear_depth_p_layout,
 357                                    &state->alloc);
 358
 359         finish_meta_clear_htile_mask_state(device);
 360 }
 361
 362 static void
 363 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
 364                  const VkClearAttachment *clear_att,
 365                  const VkClearRect *clear_rect,
 366                  uint32_t view_mask)
 367 {
 368         struct radv_device *device = cmd_buffer->device;
 369         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 370         const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
 371         const uint32_t subpass_att = clear_att->colorAttachment;
 372         const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
 373         const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
 374         const uint32_t samples = iview->image->info.samples;
 375         const uint32_t samples_log2 = ffs(samples) - 1;
 376         unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
 377         VkClearColorValue clear_value = clear_att->clearValue.color;
 378         VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
 379         VkPipeline pipeline;
 380
 381         if (fs_key == -1) {
 382                 radv_finishme("color clears incomplete");
 383                 return;
 384         }
 385
 386         if (device->meta_state.clear[samples_log2].render_pass[fs_key] == VK_NULL_HANDLE) {
 387                 VkResult ret = create_color_renderpass(device, radv_fs_key_format_exemplars[fs_key],
 388                                                        samples,
 389                                                        &device->meta_state.clear[samples_log2].render_pass[fs_key]);
 390                 if (ret != VK_SUCCESS) {
 391                         cmd_buffer->record_result = ret;
 392                         return;
 393                 }
 394         }
 395
 396         if (device->meta_state.clear[samples_log2].color_pipelines[fs_key] == VK_NULL_HANDLE) {
 397                 VkResult ret = create_color_pipeline(device, samples, 0,
 398                                                      &device->meta_state.clear[samples_log2].color_pipelines[fs_key],
 399                                                      device->meta_state.clear[samples_log2].render_pass[fs_key]);
 400                 if (ret != VK_SUCCESS) {
 401                         cmd_buffer->record_result = ret;
 402                         return;
 403                 }
 404         }
 405
 406         pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
 407         if (!pipeline) {
 408                 radv_finishme("color clears incomplete");
 409                 return;
 410         }
 411         assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
 412         assert(pipeline);
 413         assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
 414         assert(clear_att->colorAttachment < subpass->color_count);
 415
 416         radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
 417                               device->meta_state.clear_color_p_layout,
 418                               VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
 419                               &clear_value);
 420
 421         struct radv_subpass clear_subpass = {
 422                 .color_count = 1,
 423                 .color_attachments = (struct radv_subpass_attachment[]) {
 424                         subpass->color_attachments[clear_att->colorAttachment]
 425                 },
 426                 .depth_stencil_attachment = (struct radv_subpass_attachment) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
 427         };
 428
 429         radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
 430
 431         radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
 432                              pipeline);
 433
 434         radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
 435                         .x = clear_rect->rect.offset.x,
 436                         .y = clear_rect->rect.offset.y,
 437                         .width = clear_rect->rect.extent.width,
 438                         .height = clear_rect->rect.extent.height,
 439                         .minDepth = 0.0f,
 440                         .maxDepth = 1.0f
 441                 });
 442
 443         radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
 444
 445         if (view_mask) {
 446                 unsigned i;
 447                 for_each_bit(i, view_mask)
 448                         radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
 449         } else {
 450                 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
 451         }
 452
 453         radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
 454 }
 455
 456
 457 static void
 458 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
 459 {
 460         nir_builder vs_b, fs_b;
 461
 462         nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
 463         nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
 464
 465         vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
 466         fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
 467         const struct glsl_type *position_out_type = glsl_vec4_type();
 468
 469         nir_variable *vs_out_pos =
 470                 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
 471                                     "gl_Position");
 472         vs_out_pos->data.location = VARYING_SLOT_POS;
 473
 474         nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
 475         nir_intrinsic_set_base(in_color_load, 0);
 476         nir_intrinsic_set_range(in_color_load, 4);
 477         in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
 478         in_color_load->num_components = 1;
 479         nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
 480         nir_builder_instr_insert(&vs_b, &in_color_load->instr);
 481
 482         nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
 483         nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
 484
 485         const struct glsl_type *layer_type = glsl_int_type();
 486         nir_variable *vs_out_layer =
 487                 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
 488                                     "v_layer");
 489         vs_out_layer->data.location = VARYING_SLOT_LAYER;
 490         vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
 491         nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
 492         nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
 493
 494         nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
 495         nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
 496
 497         *out_vs = vs_b.shader;
 498         *out_fs = fs_b.shader;
 499 }
 500
 501 static VkResult
 502 create_depthstencil_renderpass(struct radv_device *device,
 503                                uint32_t samples,
 504                                VkRenderPass *render_pass)
 505 {
 506         mtx_lock(&device->meta_state.mtx);
 507         if (*render_pass) {
 508                 mtx_unlock(&device->meta_state.mtx);
 509                 return VK_SUCCESS;
 510         }
 511
 512         VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
 513                                        &(VkRenderPassCreateInfo) {
 514                                                .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
 515                                                        .attachmentCount = 1,
 516                                                        .pAttachments = &(VkAttachmentDescription) {
 517                                                        .format = VK_FORMAT_D32_SFLOAT_S8_UINT,
 518                                                        .samples = samples,
 519                                                        .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
 520                                                        .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
 521                                                        .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
 522                                                        .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
 523                                                },
 524                                                        .subpassCount = 1,
 525                                                                 .pSubpasses = &(VkSubpassDescription) {
 526                                                        .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
 527                                                        .inputAttachmentCount = 0,
 528                                                        .colorAttachmentCount = 0,
 529                                                        .pColorAttachments = NULL,
 530                                                        .pResolveAttachments = NULL,
 531                                                        .pDepthStencilAttachment = &(VkAttachmentReference) {
 532                                                                .attachment = 0,
 533                                                                .layout = VK_IMAGE_LAYOUT_GENERAL,
 534                                                        },
 535                                                        .preserveAttachmentCount = 1,
 536                                                        .pPreserveAttachments = (uint32_t[]) { 0 },
 537                                                },
 538                                                                 .dependencyCount = 0,
 539                                                                          }, &device->meta_state.alloc, render_pass);
 540         mtx_unlock(&device->meta_state.mtx);
 541         return result;
 542 }
 543
 544 static VkResult
 545 create_depthstencil_pipeline(struct radv_device *device,
 546                              VkImageAspectFlags aspects,
 547                              uint32_t samples,
 548                              int index,
 549                              VkPipeline *pipeline,
 550                              VkRenderPass render_pass)
 551 {
 552         struct nir_shader *vs_nir, *fs_nir;
 553         VkResult result;
 554
 555         mtx_lock(&device->meta_state.mtx);
 556         if (*pipeline) {
 557                 mtx_unlock(&device->meta_state.mtx);
 558                 return VK_SUCCESS;
 559         }
 560
 561         build_depthstencil_shader(&vs_nir, &fs_nir);
 562
 563         const VkPipelineVertexInputStateCreateInfo vi_state = {
 564                 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
 565                 .vertexBindingDescriptionCount = 0,
 566                 .vertexAttributeDescriptionCount = 0,
 567         };
 568
 569         const VkPipelineDepthStencilStateCreateInfo ds_state = {
 570                 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
 571                 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
 572                 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
 573                 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
 574                 .depthBoundsTestEnable = false,
 575                 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
 576                 .front = {
 577                         .passOp = VK_STENCIL_OP_REPLACE,
 578                         .compareOp = VK_COMPARE_OP_ALWAYS,
 579                         .writeMask = UINT32_MAX,
 580                         .reference = 0, /* dynamic */
 581                 },
 582                 .back = { 0 /* dont care */ },
 583         };
 584
 585         const VkPipelineColorBlendStateCreateInfo cb_state = {
 586                 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
 587                 .logicOpEnable = false,
 588                 .attachmentCount = 0,
 589                 .pAttachments = NULL,
 590         };
 591
 592         struct radv_graphics_pipeline_create_info extra = {
 593                 .use_rectlist = true,
 594         };
 595
 596         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
 597                 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
 598                 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
 599         }
 600         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
 601                 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
 602                 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
 603         }
 604         result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
 605                                  samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
 606                                  device->meta_state.clear_depth_p_layout,
 607                                  &extra, &device->meta_state.alloc, pipeline);
 608
 609         mtx_unlock(&device->meta_state.mtx);
 610         return result;
 611 }
 612
 613 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
 614                                       const struct radv_image_view *iview,
 615                                       VkImageAspectFlags aspects,
 616                                       VkImageLayout layout,
 617                                       const VkClearRect *clear_rect,
 618                                       VkClearDepthStencilValue clear_value)
 619 {
 620         uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
 621                                                            cmd_buffer->queue_family_index,
 622                                                            cmd_buffer->queue_family_index);
 623         if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
 624             clear_rect->rect.extent.width != iview->extent.width ||
 625             clear_rect->rect.extent.height != iview->extent.height)
 626                 return false;
 627         if (radv_image_is_tc_compat_htile(iview->image) &&
 628             (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && clear_value.depth != 0.0 &&
 629               clear_value.depth != 1.0) ||
 630              ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0)))
 631                 return false;
 632         if (radv_image_has_htile(iview->image) &&
 633             iview->base_mip == 0 &&
 634             iview->base_layer == 0 &&
 635             radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
 636             !radv_image_extent_compare(iview->image, &iview->extent))
 637                 return true;
 638         return false;
 639 }
 640
 641 static VkPipeline
 642 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
 643                            struct radv_meta_state *meta_state,
 644                            const struct radv_image_view *iview,
 645                            int samples_log2,
 646                            VkImageAspectFlags aspects,
 647                            VkImageLayout layout,
 648                            const VkClearRect *clear_rect,
 649                            VkClearDepthStencilValue clear_value)
 650 {
 651         bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, clear_rect, clear_value);
 652         int index = DEPTH_CLEAR_SLOW;
 653         VkPipeline *pipeline;
 654
 655         if (fast) {
 656                 /* we don't know the previous clear values, so we always have
 657                  * the NO_EXPCLEAR path */
 658                 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
 659         }
 660
 661         switch (aspects) {
 662         case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
 663                 pipeline = &meta_state->clear[samples_log2].depthstencil_pipeline[index];
 664                 break;
 665         case VK_IMAGE_ASPECT_DEPTH_BIT:
 666                 pipeline = &meta_state->clear[samples_log2].depth_only_pipeline[index];
 667                 break;
 668         case VK_IMAGE_ASPECT_STENCIL_BIT:
 669                 pipeline = &meta_state->clear[samples_log2].stencil_only_pipeline[index];
 670                 break;
 671         default:
 672                 unreachable("expected depth or stencil aspect");
 673         }
 674
 675         if (cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp == VK_NULL_HANDLE) {
 676                 VkResult ret = create_depthstencil_renderpass(cmd_buffer->device, 1u << samples_log2,
 677                                                               &cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
 678                 if (ret != VK_SUCCESS) {
 679                         cmd_buffer->record_result = ret;
 680                         return VK_NULL_HANDLE;
 681                 }
 682         }
 683
 684         if (*pipeline == VK_NULL_HANDLE) {
 685                 VkResult ret = create_depthstencil_pipeline(cmd_buffer->device, aspects, 1u << samples_log2, index,
 686                                                             pipeline, cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
 687                 if (ret != VK_SUCCESS) {
 688                         cmd_buffer->record_result = ret;
 689                         return VK_NULL_HANDLE;
 690                 }
 691         }
 692         return *pipeline;
 693 }
 694
 695 static void
 696 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
 697                         const VkClearAttachment *clear_att,
 698                         const VkClearRect *clear_rect)
 699 {
 700         struct radv_device *device = cmd_buffer->device;
 701         struct radv_meta_state *meta_state = &device->meta_state;
 702         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 703         const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
 704         const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
 705         VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
 706         VkImageAspectFlags aspects = clear_att->aspectMask;
 707         const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
 708         const uint32_t samples = iview->image->info.samples;
 709         const uint32_t samples_log2 = ffs(samples) - 1;
 710         VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
 711
 712         assert(pass_att != VK_ATTACHMENT_UNUSED);
 713
 714         if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
 715                 clear_value.depth = 1.0f;
 716
 717         radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
 718                               device->meta_state.clear_depth_p_layout,
 719                               VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
 720                               &clear_value.depth);
 721
 722         uint32_t prev_reference = cmd_buffer->state.dynamic.stencil_reference.front;
 723         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
 724                 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
 725                                                   clear_value.stencil);
 726         }
 727
 728         VkPipeline pipeline = pick_depthstencil_pipeline(cmd_buffer,
 729                                                          meta_state,
 730                                                          iview,
 731                                                          samples_log2,
 732                                                          aspects,
 733                                                          subpass->depth_stencil_attachment.layout,
 734                                                          clear_rect,
 735                                                          clear_value);
 736         if (!pipeline)
 737                 return;
 738
 739         radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
 740                              pipeline);
 741
 742         if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
 743                                       subpass->depth_stencil_attachment.layout,
 744                                       clear_rect, clear_value))
 745                 radv_update_ds_clear_metadata(cmd_buffer, iview->image,
 746                                               clear_value, aspects);
 747
 748         radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
 749                         .x = clear_rect->rect.offset.x,
 750                         .y = clear_rect->rect.offset.y,
 751                         .width = clear_rect->rect.extent.width,
 752                         .height = clear_rect->rect.extent.height,
 753                         .minDepth = 0.0f,
 754                         .maxDepth = 1.0f
 755                 });
 756
 757         radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
 758
 759         radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
 760
 761         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
 762                 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
 763                                                   prev_reference);
 764         }
 765 }
 766
 767 static uint32_t
 768 clear_htile_mask(struct radv_cmd_buffer *cmd_buffer,
 769                  struct radeon_winsys_bo *bo, uint64_t offset, uint64_t size,
 770                  uint32_t htile_value, uint32_t htile_mask)
 771 {
 772         struct radv_device *device = cmd_buffer->device;
 773         struct radv_meta_state *state = &device->meta_state;
 774         uint64_t block_count = round_up_u64(size, 1024);
 775         struct radv_meta_saved_state saved_state;
 776
 777         radv_meta_save(&saved_state, cmd_buffer,
 778                        RADV_META_SAVE_COMPUTE_PIPELINE |
 779                        RADV_META_SAVE_CONSTANTS |
 780                        RADV_META_SAVE_DESCRIPTORS);
 781
 782         struct radv_buffer dst_buffer = {
 783                 .bo = bo,
 784                 .offset = offset,
 785                 .size = size
 786         };
 787
 788         radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
 789                              VK_PIPELINE_BIND_POINT_COMPUTE,
 790                              state->clear_htile_mask_pipeline);
 791
 792         radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
 793                                       state->clear_htile_mask_p_layout,
 794                                       0, /* set */
 795                                       1, /* descriptorWriteCount */
 796                                       (VkWriteDescriptorSet[]) {
 797                                               {
 798                                                       .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
 799                                                       .dstBinding = 0,
 800                                                       .dstArrayElement = 0,
 801                                                       .descriptorCount = 1,
 802                                                       .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
 803                                                       .pBufferInfo = &(VkDescriptorBufferInfo) {
 804                                                               .buffer = radv_buffer_to_handle(&dst_buffer),
 805                                                               .offset = 0,
 806                                                               .range = size
 807                                                       }
 808                                               }
 809                                       });
 810
 811         const unsigned constants[2] = {
 812                 htile_value & htile_mask,
 813                 ~htile_mask,
 814         };
 815
 816         radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
 817                               state->clear_htile_mask_p_layout,
 818                               VK_SHADER_STAGE_COMPUTE_BIT, 0, 8,
 819                               constants);
 820
 821         radv_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer), block_count, 1, 1);
 822
 823         radv_meta_restore(&saved_state, cmd_buffer);
 824
 825         return RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
 826                RADV_CMD_FLAG_INV_VMEM_L1 |
 827                RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
 828 }
 829
 830 static uint32_t
 831 radv_get_htile_fast_clear_value(const struct radv_image *image,
 832                                 VkClearDepthStencilValue value)
 833 {
 834         uint32_t clear_value;
 835
 836         if (!image->surface.has_stencil) {
 837                 clear_value = value.depth ? 0xfffffff0 : 0;
 838         } else {
 839                 clear_value = value.depth ? 0xfffc0000 : 0;
 840         }
 841
 842         return clear_value;
 843 }
 844
 845 static uint32_t
 846 radv_get_htile_mask(const struct radv_image *image, VkImageAspectFlags aspects)
 847 {
 848         uint32_t mask = 0;
 849
 850         if (!image->surface.has_stencil) {
 851                 /* All the HTILE buffer is used when there is no stencil. */
 852                 mask = UINT32_MAX;
 853         } else {
 854                 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
 855                         mask |= 0xfffffc0f;
 856                 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
 857                         mask |= 0x000003f0;
 858         }
 859
 860         return mask;
 861 }
 862
 863 static bool
 864 radv_is_fast_clear_depth_allowed(VkClearDepthStencilValue value)
 865 {
 866         return value.depth == 1.0f || value.depth == 0.0f;
 867 }
 868
 869 static bool
 870 radv_is_fast_clear_stencil_allowed(VkClearDepthStencilValue value)
 871 {
 872         return value.stencil == 0;
 873 }
 874
 875 /**
 876  * Determine if the given image can be fast cleared.
 877  */
 878 static bool
 879 radv_image_can_fast_clear(struct radv_device *device,  struct radv_image *image)
 880 {
 881         if (device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
 882                 return false;
 883
 884         if (vk_format_is_color(image->vk_format)) {
 885                 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
 886                         return false;
 887
 888                 /* RB+ doesn't work with CMASK fast clear on Stoney. */
 889                 if (!radv_image_has_dcc(image) &&
 890                     device->physical_device->rad_info.family == CHIP_STONEY)
 891                         return false;
 892         } else {
 893                 if (!radv_image_has_htile(image))
 894                         return false;
 895
 896                 /* GFX8 only supports 32-bit depth surfaces but we can enable
 897                  * TC-compat HTILE for 16-bit surfaces if no Z planes are
 898                  * compressed. Though, fast HTILE clears don't seem to work.
 899                  */
 900                 if (device->physical_device->rad_info.chip_class == VI &&
 901                     image->vk_format == VK_FORMAT_D16_UNORM)
 902                         return false;
 903         }
 904
 905         /* Do not fast clears 3D images. */
 906         if (image->type == VK_IMAGE_TYPE_3D)
 907                 return false;
 908
 909         return true;
 910 }
 911
 912 static bool
 913 emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
 914                       const VkClearAttachment *clear_att,
 915                       const VkClearRect *clear_rect,
 916                       enum radv_cmd_flush_bits *pre_flush,
 917                       enum radv_cmd_flush_bits *post_flush)
 918 {
 919         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 920         const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
 921         VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
 922         const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
 923         const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
 924         VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
 925         VkImageAspectFlags aspects = clear_att->aspectMask;
 926         uint32_t clear_word, flush_bits;
 927         uint32_t htile_mask;
 928
 929         if (!radv_image_can_fast_clear(cmd_buffer->device, iview->image))
 930                 return false;
 931
 932         if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
 933                 return false;
 934
 935         /* all layers are bound */
 936         if (iview->base_layer > 0)
 937                 return false;
 938         if (iview->image->info.array_size != iview->layer_count)
 939                 return false;
 940
 941         if (!radv_image_extent_compare(iview->image, &iview->extent))
 942                 return false;
 943
 944         if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
 945             clear_rect->rect.extent.width != iview->image->info.width ||
 946             clear_rect->rect.extent.height != iview->image->info.height)
 947                 return false;
 948
 949         if (clear_rect->baseArrayLayer != 0)
 950                 return false;
 951         if (clear_rect->layerCount != iview->image->info.array_size)
 952                 return false;
 953
 954         if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 &&
 955             (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT) ||
 956             ((vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) &&
 957              !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))))
 958                 return false;
 959
 960         if (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
 961             !radv_is_fast_clear_depth_allowed(clear_value)) ||
 962             ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
 963              !radv_is_fast_clear_stencil_allowed(clear_value)))
 964                 return false;
 965
 966         clear_word = radv_get_htile_fast_clear_value(iview->image, clear_value);
 967         htile_mask = radv_get_htile_mask(iview->image, aspects);
 968
 969         if (pre_flush) {
 970                 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
 971                                                  RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
 972                 *pre_flush |= cmd_buffer->state.flush_bits;
 973         }
 974
 975         if (htile_mask == UINT_MAX) {
 976                 /* Clear the whole HTILE buffer. */
 977                 flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
 978                                               iview->image->offset + iview->image->htile_offset,
 979                                               iview->image->surface.htile_size, clear_word);
 980         } else {
 981                 /* Only clear depth or stencil bytes in the HTILE buffer. */
 982                 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9);
 983                 flush_bits = clear_htile_mask(cmd_buffer, iview->image->bo,
 984                                               iview->image->offset + iview->image->htile_offset,
 985                                               iview->image->surface.htile_size, clear_word,
 986                                               htile_mask);
 987         }
 988
 989         radv_update_ds_clear_metadata(cmd_buffer, iview->image, clear_value, aspects);
 990         if (post_flush) {
 991                 *post_flush |= flush_bits;
 992         }
 993
 994         return true;
 995 }
 996
 997 static nir_shader *
 998 build_clear_htile_mask_shader()
 999 {
1000         nir_builder b;
1001
1002         nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
1003         b.shader->info.name = ralloc_strdup(b.shader, "meta_clear_htile_mask");
1004         b.shader->info.cs.local_size[0] = 64;
1005         b.shader->info.cs.local_size[1] = 1;
1006         b.shader->info.cs.local_size[2] = 1;
1007
1008         nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
1009         nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
1010         nir_ssa_def *block_size = nir_imm_ivec4(&b,
1011                                                 b.shader->info.cs.local_size[0],
1012                                                 b.shader->info.cs.local_size[1],
1013                                                 b.shader->info.cs.local_size[2], 0);
1014
1015         nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
1016
1017         nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16));
1018         offset = nir_channel(&b, offset, 0);
1019
1020         nir_intrinsic_instr *buf =
1021                 nir_intrinsic_instr_create(b.shader,
1022                                            nir_intrinsic_vulkan_resource_index);
1023
1024         buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
1025         nir_intrinsic_set_desc_set(buf, 0);
1026         nir_intrinsic_set_binding(buf, 0);
1027         nir_ssa_dest_init(&buf->instr, &buf->dest, 1, 32, NULL);
1028         nir_builder_instr_insert(&b, &buf->instr);
1029
1030         nir_intrinsic_instr *constants =
1031                 nir_intrinsic_instr_create(b.shader,
1032                                            nir_intrinsic_load_push_constant);
1033         nir_intrinsic_set_base(constants, 0);
1034         nir_intrinsic_set_range(constants, 8);
1035         constants->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
1036         constants->num_components = 2;
1037         nir_ssa_dest_init(&constants->instr, &constants->dest, 2, 32, "constants");
1038         nir_builder_instr_insert(&b, &constants->instr);
1039
1040         nir_intrinsic_instr *load =
1041                 nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
1042         load->src[0] = nir_src_for_ssa(&buf->dest.ssa);
1043         load->src[1] = nir_src_for_ssa(offset);
1044         nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
1045         load->num_components = 4;
1046         nir_builder_instr_insert(&b, &load->instr);
1047
1048         /* data = (data & ~htile_mask) | (htile_value & htile_mask) */
1049         nir_ssa_def *data =
1050                 nir_iand(&b, &load->dest.ssa,
1051                          nir_channel(&b, &constants->dest.ssa, 1));
1052         data = nir_ior(&b, data, nir_channel(&b, &constants->dest.ssa, 0));
1053
1054         nir_intrinsic_instr *store =
1055                 nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
1056         store->src[0] = nir_src_for_ssa(data);
1057         store->src[1] = nir_src_for_ssa(&buf->dest.ssa);
1058         store->src[2] = nir_src_for_ssa(offset);
1059         nir_intrinsic_set_write_mask(store, 0xf);
1060         store->num_components = 4;
1061         nir_builder_instr_insert(&b, &store->instr);
1062
1063         return b.shader;
1064 }
1065
1066 static VkResult
1067 init_meta_clear_htile_mask_state(struct radv_device *device)
1068 {
1069         struct radv_meta_state *state = &device->meta_state;
1070         struct radv_shader_module cs = { .nir = NULL };
1071         VkResult result;
1072
1073         cs.nir = build_clear_htile_mask_shader();
1074
1075         VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1076                 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1077                 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1078                 .bindingCount = 1,
1079                 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1080                         {
1081                                 .binding = 0,
1082                                 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
1083                                 .descriptorCount = 1,
1084                                 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
1085                                 .pImmutableSamplers = NULL
1086                         },
1087                 }
1088         };
1089
1090         result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1091                                                 &ds_layout_info, &state->alloc,
1092                                                 &state->clear_htile_mask_ds_layout);
1093         if (result != VK_SUCCESS)
1094                 goto fail;
1095
1096         VkPipelineLayoutCreateInfo p_layout_info = {
1097                 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1098                 .setLayoutCount = 1,
1099                 .pSetLayouts = &state->clear_htile_mask_ds_layout,
1100                 .pushConstantRangeCount = 1,
1101                 .pPushConstantRanges = &(VkPushConstantRange){
1102                         VK_SHADER_STAGE_COMPUTE_BIT, 0, 8,
1103                 },
1104         };
1105
1106         result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1107                                           &p_layout_info, &state->alloc,
1108                                           &state->clear_htile_mask_p_layout);
1109         if (result != VK_SUCCESS)
1110                 goto fail;
1111
1112         VkPipelineShaderStageCreateInfo shader_stage = {
1113                 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1114                 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
1115                 .module = radv_shader_module_to_handle(&cs),
1116                 .pName = "main",
1117                 .pSpecializationInfo = NULL,
1118         };
1119
1120         VkComputePipelineCreateInfo pipeline_info = {
1121                 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
1122                 .stage = shader_stage,
1123                 .flags = 0,
1124                 .layout = state->clear_htile_mask_p_layout,
1125         };
1126
1127         result = radv_CreateComputePipelines(radv_device_to_handle(device),
1128                                              radv_pipeline_cache_to_handle(&state->cache),
1129                                              1, &pipeline_info, NULL,
1130                                              &state->clear_htile_mask_pipeline);
1131
1132         ralloc_free(cs.nir);
1133         return result;
1134 fail:
1135         ralloc_free(cs.nir);
1136         return result;
1137 }
1138
1139 VkResult
1140 radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand)
1141 {
1142         VkResult res;
1143         struct radv_meta_state *state = &device->meta_state;
1144
1145         VkPipelineLayoutCreateInfo pl_color_create_info = {
1146                 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1147                 .setLayoutCount = 0,
1148                 .pushConstantRangeCount = 1,
1149                 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
1150         };
1151
1152         res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1153                                         &pl_color_create_info,
1154                                         &device->meta_state.alloc,
1155                                         &device->meta_state.clear_color_p_layout);
1156         if (res != VK_SUCCESS)
1157                 goto fail;
1158
1159         VkPipelineLayoutCreateInfo pl_depth_create_info = {
1160                 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1161                 .setLayoutCount = 0,
1162                 .pushConstantRangeCount = 1,
1163                 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
1164         };
1165
1166         res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1167                                         &pl_depth_create_info,
1168                                         &device->meta_state.alloc,
1169                                         &device->meta_state.clear_depth_p_layout);
1170         if (res != VK_SUCCESS)
1171                 goto fail;
1172
1173         res = init_meta_clear_htile_mask_state(device);
1174         if (res != VK_SUCCESS)
1175                 goto fail;
1176
1177         if (on_demand)
1178                 return VK_SUCCESS;
1179
1180         for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
1181                 uint32_t samples = 1 << i;
1182                 for (uint32_t j = 0; j < NUM_META_FS_KEYS; ++j) {
1183                         VkFormat format = radv_fs_key_format_exemplars[j];
1184                         unsigned fs_key = radv_format_meta_fs_key(format);
1185                         assert(!state->clear[i].color_pipelines[fs_key]);
1186
1187                         res = create_color_renderpass(device, format, samples,
1188                                                       &state->clear[i].render_pass[fs_key]);
1189                         if (res != VK_SUCCESS)
1190                                 goto fail;
1191
1192                         res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
1193                                                     state->clear[i].render_pass[fs_key]);
1194                         if (res != VK_SUCCESS)
1195                                 goto fail;
1196
1197                 }
1198
1199                 res = create_depthstencil_renderpass(device,
1200                                                      samples,
1201                                                      &state->clear[i].depthstencil_rp);
1202                 if (res != VK_SUCCESS)
1203                         goto fail;
1204
1205                 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
1206                         res = create_depthstencil_pipeline(device,
1207                                                            VK_IMAGE_ASPECT_DEPTH_BIT,
1208                                                            samples,
1209                                                            j,
1210                                                            &state->clear[i].depth_only_pipeline[j],
1211                                                            state->clear[i].depthstencil_rp);
1212                         if (res != VK_SUCCESS)
1213                                 goto fail;
1214
1215                         res = create_depthstencil_pipeline(device,
1216                                                            VK_IMAGE_ASPECT_STENCIL_BIT,
1217                                                            samples,
1218                                                            j,
1219                                                            &state->clear[i].stencil_only_pipeline[j],
1220                                                            state->clear[i].depthstencil_rp);
1221                         if (res != VK_SUCCESS)
1222                                 goto fail;
1223
1224                         res = create_depthstencil_pipeline(device,
1225                                                            VK_IMAGE_ASPECT_DEPTH_BIT |
1226                                                            VK_IMAGE_ASPECT_STENCIL_BIT,
1227                                                            samples,
1228                                                            j,
1229                                                            &state->clear[i].depthstencil_pipeline[j],
1230                                                            state->clear[i].depthstencil_rp);
1231                         if (res != VK_SUCCESS)
1232                                 goto fail;
1233                 }
1234         }
1235         return VK_SUCCESS;
1236
1237 fail:
1238         radv_device_finish_meta_clear_state(device);
1239         return res;
1240 }
1241
1242 static uint32_t
1243 radv_get_cmask_fast_clear_value(const struct radv_image *image)
1244 {
1245         uint32_t value = 0; /* Default value when no DCC. */
1246
1247         /* The fast-clear value is different for images that have both DCC and
1248          * CMASK metadata.
1249          */
1250         if (radv_image_has_dcc(image)) {
1251                 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
1252                 return image->info.samples > 1 ? 0xcccccccc : 0xffffffff;
1253         }
1254
1255         return value;
1256 }
1257
1258 uint32_t
1259 radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
1260                  struct radv_image *image, uint32_t value)
1261 {
1262         return radv_fill_buffer(cmd_buffer, image->bo,
1263                                 image->offset + image->cmask.offset,
1264                                 image->cmask.size, value);
1265 }
1266
1267 uint32_t
1268 radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
1269                struct radv_image *image, uint32_t value)
1270 {
1271         return radv_fill_buffer(cmd_buffer, image->bo,
1272                                 image->offset + image->dcc_offset,
1273                                 image->surface.dcc_size, value);
1274 }
1275
1276 static void vi_get_fast_clear_parameters(VkFormat format,
1277                                          const VkClearColorValue *clear_value,
1278                                          uint32_t* reset_value,
1279                                          bool *can_avoid_fast_clear_elim)
1280 {
1281         bool values[4] = {};
1282         int extra_channel;
1283         bool main_value = false;
1284         bool extra_value = false;
1285         int i;
1286         *can_avoid_fast_clear_elim = false;
1287
1288         *reset_value = 0x20202020U;
1289
1290         const struct vk_format_description *desc = vk_format_description(format);
1291         if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
1292             format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
1293             format == VK_FORMAT_B5G6R5_UNORM_PACK16)
1294                 extra_channel = -1;
1295         else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
1296                 if (radv_translate_colorswap(format, false) <= 1)
1297                         extra_channel = desc->nr_channels - 1;
1298                 else
1299                         extra_channel = 0;
1300         } else
1301                 return;
1302
1303         for (i = 0; i < 4; i++) {
1304                 int index = desc->swizzle[i] - VK_SWIZZLE_X;
1305                 if (desc->swizzle[i] < VK_SWIZZLE_X ||
1306                     desc->swizzle[i] > VK_SWIZZLE_W)
1307                         continue;
1308
1309                 if (desc->channel[i].pure_integer &&
1310                     desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
1311                         /* Use the maximum value for clamping the clear color. */
1312                         int max = u_bit_consecutive(0, desc->channel[i].size - 1);
1313
1314                         values[i] = clear_value->int32[i] != 0;
1315                         if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
1316                                 return;
1317                 } else if (desc->channel[i].pure_integer &&
1318                            desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
1319                         /* Use the maximum value for clamping the clear color. */
1320                         unsigned max = u_bit_consecutive(0, desc->channel[i].size);
1321
1322                         values[i] = clear_value->uint32[i] != 0U;
1323                         if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
1324                                 return;
1325                 } else {
1326                         values[i] = clear_value->float32[i] != 0.0F;
1327                         if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
1328                                 return;
1329                 }
1330
1331                 if (index == extra_channel)
1332                         extra_value = values[i];
1333                 else
1334                         main_value = values[i];
1335         }
1336
1337         for (int i = 0; i < 4; ++i)
1338                 if (values[i] != main_value &&
1339                     desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
1340                     desc->swizzle[i] >= VK_SWIZZLE_X &&
1341                     desc->swizzle[i] <= VK_SWIZZLE_W)
1342                         return;
1343
1344         *can_avoid_fast_clear_elim = true;
1345         if (main_value)
1346                 *reset_value |= 0x80808080U;
1347
1348         if (extra_value)
1349                 *reset_value |= 0x40404040U;
1350         return;
1351 }
1352
1353 static bool
1354 emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
1355                       const VkClearAttachment *clear_att,
1356                       const VkClearRect *clear_rect,
1357                       enum radv_cmd_flush_bits *pre_flush,
1358                       enum radv_cmd_flush_bits *post_flush,
1359                       uint32_t view_mask)
1360 {
1361         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1362         const uint32_t subpass_att = clear_att->colorAttachment;
1363         const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
1364         VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
1365         const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
1366         const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
1367         VkClearColorValue clear_value = clear_att->clearValue.color;
1368         uint32_t clear_color[2], flush_bits = 0;
1369         uint32_t cmask_clear_value;
1370         bool ret;
1371
1372         if (!radv_image_can_fast_clear(cmd_buffer->device, iview->image))
1373                 return false;
1374
1375         if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
1376                 return false;
1377
1378         /* all layers are bound */
1379         if (iview->base_layer > 0)
1380                 return false;
1381         if (iview->image->info.array_size != iview->layer_count)
1382                 return false;
1383
1384         if (!radv_image_extent_compare(iview->image, &iview->extent))
1385                 return false;
1386
1387         if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
1388             clear_rect->rect.extent.width != iview->image->info.width ||
1389             clear_rect->rect.extent.height != iview->image->info.height)
1390                 return false;
1391
1392         if (view_mask && (iview->image->info.array_size >= 32 ||
1393                          (1u << iview->image->info.array_size) - 1u != view_mask))
1394                 return false;
1395         if (!view_mask && clear_rect->baseArrayLayer != 0)
1396                 return false;
1397         if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
1398                 return false;
1399
1400         /* DCC */
1401         ret = radv_format_pack_clear_color(iview->vk_format,
1402                                            clear_color, &clear_value);
1403         if (ret == false)
1404                 return false;
1405
1406         if (pre_flush) {
1407                 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1408                                                  RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
1409                 *pre_flush |= cmd_buffer->state.flush_bits;
1410         }
1411
1412         cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
1413
1414         /* clear cmask buffer */
1415         if (radv_image_has_dcc(iview->image)) {
1416                 uint32_t reset_value;
1417                 bool can_avoid_fast_clear_elim;
1418                 bool need_decompress_pass = false;
1419
1420                 vi_get_fast_clear_parameters(iview->vk_format,
1421                                              &clear_value, &reset_value,
1422                                              &can_avoid_fast_clear_elim);
1423
1424                 if (iview->image->info.samples > 1) {
1425                         /* DCC fast clear with MSAA should clear CMASK. */
1426                         /* FIXME: This doesn't work for now. There is a
1427                          * hardware bug with fast clears and DCC for MSAA
1428                          * textures. AMDVLK has a workaround but it doesn't
1429                          * seem to work here. Note that we might emit useless
1430                          * CB flushes but that shouldn't matter.
1431                          */
1432                         if (!can_avoid_fast_clear_elim)
1433                                 return false;
1434
1435                         assert(radv_image_has_cmask(iview->image));
1436
1437                         flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1438                                                       cmask_clear_value);
1439
1440                         need_decompress_pass = true;
1441                 }
1442
1443                 if (!can_avoid_fast_clear_elim)
1444                         need_decompress_pass = true;
1445
1446                 flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, reset_value);
1447
1448                 radv_update_fce_metadata(cmd_buffer, iview->image,
1449                                          need_decompress_pass);
1450         } else {
1451                 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1452                                               cmask_clear_value);
1453         }
1454
1455         if (post_flush) {
1456                 *post_flush |= flush_bits;
1457         }
1458
1459         radv_update_color_clear_metadata(cmd_buffer, iview->image, subpass_att,
1460                                          clear_color);
1461
1462         return true;
1463 }
1464
1465 /**
1466  * The parameters mean that same as those in vkCmdClearAttachments.
1467  */
1468 static void
1469 emit_clear(struct radv_cmd_buffer *cmd_buffer,
1470            const VkClearAttachment *clear_att,
1471            const VkClearRect *clear_rect,
1472            enum radv_cmd_flush_bits *pre_flush,
1473            enum radv_cmd_flush_bits *post_flush,
1474            uint32_t view_mask)
1475 {
1476         if (clear_att->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1477                 if (!emit_fast_color_clear(cmd_buffer, clear_att, clear_rect,
1478                                            pre_flush, post_flush, view_mask))
1479                         emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask);
1480         } else {
1481                 assert(clear_att->aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT |
1482                                                 VK_IMAGE_ASPECT_STENCIL_BIT));
1483                 if (!emit_fast_htile_clear(cmd_buffer, clear_att, clear_rect,
1484                                            pre_flush, post_flush))
1485                         emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
1486         }
1487 }
1488
1489 static inline bool
1490 radv_attachment_needs_clear(struct radv_cmd_state *cmd_state, uint32_t a)
1491 {
1492         uint32_t view_mask = cmd_state->subpass->view_mask;
1493         return (a != VK_ATTACHMENT_UNUSED &&
1494                 cmd_state->attachments[a].pending_clear_aspects &&
1495                 (!view_mask || (view_mask & ~cmd_state->attachments[a].cleared_views)));
1496 }
1497
1498 static bool
1499 radv_subpass_needs_clear(struct radv_cmd_buffer *cmd_buffer)
1500 {
1501         struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1502         uint32_t a;
1503
1504         if (!cmd_state->subpass)
1505                 return false;
1506
1507         for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1508                 a = cmd_state->subpass->color_attachments[i].attachment;
1509                 if (radv_attachment_needs_clear(cmd_state, a))
1510                         return true;
1511         }
1512
1513         a = cmd_state->subpass->depth_stencil_attachment.attachment;
1514         return radv_attachment_needs_clear(cmd_state, a);
1515 }
1516
1517 static void
1518 radv_subpass_clear_attachment(struct radv_cmd_buffer *cmd_buffer,
1519                               struct radv_attachment_state *attachment,
1520                               const VkClearAttachment *clear_att,
1521                               enum radv_cmd_flush_bits *pre_flush,
1522                               enum radv_cmd_flush_bits *post_flush)
1523 {
1524         struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1525         uint32_t view_mask = cmd_state->subpass->view_mask;
1526
1527         VkClearRect clear_rect = {
1528                 .rect = cmd_state->render_area,
1529                 .baseArrayLayer = 0,
1530                 .layerCount = cmd_state->framebuffer->layers,
1531         };
1532
1533         emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush,
1534                    view_mask & ~attachment->cleared_views);
1535         if (view_mask)
1536                 attachment->cleared_views |= view_mask;
1537         else
1538                 attachment->pending_clear_aspects = 0;
1539 }
1540
1541 /**
1542  * Emit any pending attachment clears for the current subpass.
1543  *
1544  * @see radv_attachment_state::pending_clear_aspects
1545  */
1546 void
1547 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1548 {
1549         struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1550         struct radv_meta_saved_state saved_state;
1551         enum radv_cmd_flush_bits pre_flush = 0;
1552         enum radv_cmd_flush_bits post_flush = 0;
1553
1554         if (!radv_subpass_needs_clear(cmd_buffer))
1555                 return;
1556
1557         radv_meta_save(&saved_state, cmd_buffer,
1558                        RADV_META_SAVE_GRAPHICS_PIPELINE |
1559                        RADV_META_SAVE_CONSTANTS);
1560
1561         for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1562                 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1563
1564                 if (!radv_attachment_needs_clear(cmd_state, a))
1565                         continue;
1566
1567                 assert(cmd_state->attachments[a].pending_clear_aspects ==
1568                        VK_IMAGE_ASPECT_COLOR_BIT);
1569
1570                 VkClearAttachment clear_att = {
1571                         .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1572                         .colorAttachment = i, /* Use attachment index relative to subpass */
1573                         .clearValue = cmd_state->attachments[a].clear_value,
1574                 };
1575
1576                 radv_subpass_clear_attachment(cmd_buffer,
1577                                               &cmd_state->attachments[a],
1578                                               &clear_att, &pre_flush,
1579                                               &post_flush);
1580         }
1581
1582         uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1583         if (radv_attachment_needs_clear(cmd_state, ds)) {
1584                 VkClearAttachment clear_att = {
1585                         .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1586                         .clearValue = cmd_state->attachments[ds].clear_value,
1587                 };
1588
1589                 radv_subpass_clear_attachment(cmd_buffer,
1590                                               &cmd_state->attachments[ds],
1591                                               &clear_att, &pre_flush,
1592                                               &post_flush);
1593         }
1594
1595         radv_meta_restore(&saved_state, cmd_buffer);
1596         cmd_buffer->state.flush_bits |= post_flush;
1597 }
1598
1599 static void
1600 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1601                        struct radv_image *image,
1602                        VkImageLayout image_layout,
1603                        const VkImageSubresourceRange *range,
1604                        VkFormat format, int level, int layer,
1605                        const VkClearValue *clear_val)
1606 {
1607         VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1608         struct radv_image_view iview;
1609         uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level);
1610         uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level);
1611
1612         radv_image_view_init(&iview, cmd_buffer->device,
1613                              &(VkImageViewCreateInfo) {
1614                                      .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1615                                              .image = radv_image_to_handle(image),
1616                                              .viewType = radv_meta_get_view_type(image),
1617                                              .format = format,
1618                                              .subresourceRange = {
1619                                              .aspectMask = range->aspectMask,
1620                                              .baseMipLevel = range->baseMipLevel + level,
1621                                              .levelCount = 1,
1622                                              .baseArrayLayer = range->baseArrayLayer + layer,
1623                                              .layerCount = 1
1624                                      },
1625                              });
1626
1627         VkFramebuffer fb;
1628         radv_CreateFramebuffer(device_h,
1629                                &(VkFramebufferCreateInfo) {
1630                                        .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1631                                                .attachmentCount = 1,
1632                                                .pAttachments = (VkImageView[]) {
1633                                                radv_image_view_to_handle(&iview),
1634                                        },
1635                                                .width = width,
1636                                                .height = height,
1637                                                .layers = 1
1638                                },
1639                                &cmd_buffer->pool->alloc,
1640                                &fb);
1641
1642         VkAttachmentDescription att_desc = {
1643                 .format = iview.vk_format,
1644                 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1645                 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1646                 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1647                 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1648                 .initialLayout = image_layout,
1649                 .finalLayout = image_layout,
1650         };
1651
1652         VkSubpassDescription subpass_desc = {
1653                 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1654                 .inputAttachmentCount = 0,
1655                 .colorAttachmentCount = 0,
1656                 .pColorAttachments = NULL,
1657                 .pResolveAttachments = NULL,
1658                 .pDepthStencilAttachment = NULL,
1659                 .preserveAttachmentCount = 0,
1660                 .pPreserveAttachments = NULL,
1661         };
1662
1663         const VkAttachmentReference att_ref = {
1664                 .attachment = 0,
1665                 .layout = image_layout,
1666         };
1667
1668         if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1669                 subpass_desc.colorAttachmentCount = 1;
1670                 subpass_desc.pColorAttachments = &att_ref;
1671         } else {
1672                 subpass_desc.pDepthStencilAttachment = &att_ref;
1673         }
1674
1675         VkRenderPass pass;
1676         radv_CreateRenderPass(device_h,
1677                               &(VkRenderPassCreateInfo) {
1678                                       .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1679                                               .attachmentCount = 1,
1680                                               .pAttachments = &att_desc,
1681                                               .subpassCount = 1,
1682                                               .pSubpasses = &subpass_desc,
1683                                               },
1684                               &cmd_buffer->pool->alloc,
1685                               &pass);
1686
1687         radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1688                                 &(VkRenderPassBeginInfo) {
1689                                         .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1690                                                 .renderArea = {
1691                                                 .offset = { 0, 0, },
1692                                                 .extent = {
1693                                                         .width = width,
1694                                                         .height = height,
1695                                                 },
1696                                         },
1697                                                 .renderPass = pass,
1698                                                 .framebuffer = fb,
1699                                                 .clearValueCount = 0,
1700                                                 .pClearValues = NULL,
1701                                                 },
1702                                 VK_SUBPASS_CONTENTS_INLINE);
1703
1704         VkClearAttachment clear_att = {
1705                 .aspectMask = range->aspectMask,
1706                 .colorAttachment = 0,
1707                 .clearValue = *clear_val,
1708         };
1709
1710         VkClearRect clear_rect = {
1711                 .rect = {
1712                         .offset = { 0, 0 },
1713                         .extent = { width, height },
1714                 },
1715                 .baseArrayLayer = range->baseArrayLayer,
1716                 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1717         };
1718
1719         emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0);
1720
1721         radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1722         radv_DestroyRenderPass(device_h, pass,
1723                                &cmd_buffer->pool->alloc);
1724         radv_DestroyFramebuffer(device_h, fb,
1725                                 &cmd_buffer->pool->alloc);
1726 }
1727 static void
1728 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
1729                      struct radv_image *image,
1730                      VkImageLayout image_layout,
1731                      const VkClearValue *clear_value,
1732                      uint32_t range_count,
1733                      const VkImageSubresourceRange *ranges,
1734                      bool cs)
1735 {
1736         VkFormat format = image->vk_format;
1737         VkClearValue internal_clear_value = *clear_value;
1738
1739         if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
1740                 uint32_t value;
1741                 format = VK_FORMAT_R32_UINT;
1742                 value = float3_to_rgb9e5(clear_value->color.float32);
1743                 internal_clear_value.color.uint32[0] = value;
1744         }
1745
1746         if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
1747                 uint8_t r, g;
1748                 format = VK_FORMAT_R8_UINT;
1749                 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
1750                 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
1751                 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
1752         }
1753
1754         for (uint32_t r = 0; r < range_count; r++) {
1755                 const VkImageSubresourceRange *range = &ranges[r];
1756                 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
1757                         const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
1758                                 radv_minify(image->info.depth, range->baseMipLevel + l) :
1759                                 radv_get_layerCount(image, range);
1760                         for (uint32_t s = 0; s < layer_count; ++s) {
1761
1762                                 if (cs ||
1763                                     (format == VK_FORMAT_R32G32B32_UINT ||
1764                                      format == VK_FORMAT_R32G32B32_SINT ||
1765                                      format == VK_FORMAT_R32G32B32_SFLOAT)) {
1766                                         struct radv_meta_blit2d_surf surf;
1767                                         surf.format = format;
1768                                         surf.image = image;
1769                                         surf.level = range->baseMipLevel + l;
1770                                         surf.layer = range->baseArrayLayer + s;
1771                                         surf.aspect_mask = range->aspectMask;
1772                                         radv_meta_clear_image_cs(cmd_buffer, &surf,
1773                                                                  &internal_clear_value.color);
1774                                 } else {
1775                                         radv_clear_image_layer(cmd_buffer, image, image_layout,
1776                                                                range, format, l, s, &internal_clear_value);
1777                                 }
1778                         }
1779                 }
1780         }
1781 }
1782
1783 void radv_CmdClearColorImage(
1784         VkCommandBuffer                             commandBuffer,
1785         VkImage                                     image_h,
1786         VkImageLayout                               imageLayout,
1787         const VkClearColorValue*                    pColor,
1788         uint32_t                                    rangeCount,
1789         const VkImageSubresourceRange*              pRanges)
1790 {
1791         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1792         RADV_FROM_HANDLE(radv_image, image, image_h);
1793         struct radv_meta_saved_state saved_state;
1794         bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1795
1796         if (cs) {
1797                 radv_meta_save(&saved_state, cmd_buffer,
1798                                RADV_META_SAVE_COMPUTE_PIPELINE |
1799                                RADV_META_SAVE_CONSTANTS |
1800                                RADV_META_SAVE_DESCRIPTORS);
1801         } else {
1802                 radv_meta_save(&saved_state, cmd_buffer,
1803                                RADV_META_SAVE_GRAPHICS_PIPELINE |
1804                                RADV_META_SAVE_CONSTANTS);
1805         }
1806
1807         radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1808                              (const VkClearValue *) pColor,
1809                              rangeCount, pRanges, cs);
1810
1811         radv_meta_restore(&saved_state, cmd_buffer);
1812 }
1813
1814 void radv_CmdClearDepthStencilImage(
1815         VkCommandBuffer                             commandBuffer,
1816         VkImage                                     image_h,
1817         VkImageLayout                               imageLayout,
1818         const VkClearDepthStencilValue*             pDepthStencil,
1819         uint32_t                                    rangeCount,
1820         const VkImageSubresourceRange*              pRanges)
1821 {
1822         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1823         RADV_FROM_HANDLE(radv_image, image, image_h);
1824         struct radv_meta_saved_state saved_state;
1825
1826         radv_meta_save(&saved_state, cmd_buffer,
1827                        RADV_META_SAVE_GRAPHICS_PIPELINE |
1828                        RADV_META_SAVE_CONSTANTS);
1829
1830         radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1831                              (const VkClearValue *) pDepthStencil,
1832                              rangeCount, pRanges, false);
1833
1834         radv_meta_restore(&saved_state, cmd_buffer);
1835 }
1836
1837 void radv_CmdClearAttachments(
1838         VkCommandBuffer                             commandBuffer,
1839         uint32_t                                    attachmentCount,
1840         const VkClearAttachment*                    pAttachments,
1841         uint32_t                                    rectCount,
1842         const VkClearRect*                          pRects)
1843 {
1844         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1845         struct radv_meta_saved_state saved_state;
1846         enum radv_cmd_flush_bits pre_flush = 0;
1847         enum radv_cmd_flush_bits post_flush = 0;
1848
1849         if (!cmd_buffer->state.subpass)
1850                 return;
1851
1852         radv_meta_save(&saved_state, cmd_buffer,
1853                        RADV_META_SAVE_GRAPHICS_PIPELINE |
1854                        RADV_META_SAVE_CONSTANTS);
1855
1856         /* FINISHME: We can do better than this dumb loop. It thrashes too much
1857          * state.
1858          */
1859         for (uint32_t a = 0; a < attachmentCount; ++a) {
1860                 for (uint32_t r = 0; r < rectCount; ++r) {
1861                         emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush,
1862                                    cmd_buffer->state.subpass->view_mask);
1863                 }
1864         }
1865
1866         radv_meta_restore(&saved_state, cmd_buffer);
1867         cmd_buffer->state.flush_bits |= post_flush;
1868 }