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radv: fixup tess eval shader when combined.
[mesa.git] / src / amd / vulkan / radv_meta_clear.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_debug.h"
25 #include "radv_meta.h"
26 #include "radv_private.h"
27 #include "nir/nir_builder.h"
28
29 #include "util/format_rgb9e5.h"
30 #include "vk_format.h"
31
32 enum {
33 DEPTH_CLEAR_SLOW,
34 DEPTH_CLEAR_FAST_EXPCLEAR,
35 DEPTH_CLEAR_FAST_NO_EXPCLEAR
36 };
37
38 static void
39 build_color_shaders(struct nir_shader **out_vs,
40 struct nir_shader **out_fs,
41 uint32_t frag_output)
42 {
43 nir_builder vs_b;
44 nir_builder fs_b;
45
46 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
47 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
48
49 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
50 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
51
52 const struct glsl_type *position_type = glsl_vec4_type();
53 const struct glsl_type *color_type = glsl_vec4_type();
54
55 nir_variable *vs_out_pos =
56 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
57 "gl_Position");
58 vs_out_pos->data.location = VARYING_SLOT_POS;
59
60 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
61 nir_intrinsic_set_base(in_color_load, 0);
62 nir_intrinsic_set_range(in_color_load, 16);
63 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
64 in_color_load->num_components = 4;
65 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
66 nir_builder_instr_insert(&fs_b, &in_color_load->instr);
67
68 nir_variable *fs_out_color =
69 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
70 "f_color");
71 fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
72
73 nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
74
75 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
76 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
77
78 const struct glsl_type *layer_type = glsl_int_type();
79 nir_variable *vs_out_layer =
80 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
81 "v_layer");
82 vs_out_layer->data.location = VARYING_SLOT_LAYER;
83 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
84 nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
85 nir_ssa_def *base_instance = nir_load_system_value(&vs_b, nir_intrinsic_load_base_instance, 0);
86
87 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
88 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
89
90 *out_vs = vs_b.shader;
91 *out_fs = fs_b.shader;
92 }
93
94 static VkResult
95 create_pipeline(struct radv_device *device,
96 struct radv_render_pass *render_pass,
97 uint32_t samples,
98 struct nir_shader *vs_nir,
99 struct nir_shader *fs_nir,
100 const VkPipelineVertexInputStateCreateInfo *vi_state,
101 const VkPipelineDepthStencilStateCreateInfo *ds_state,
102 const VkPipelineColorBlendStateCreateInfo *cb_state,
103 const VkPipelineLayout layout,
104 const struct radv_graphics_pipeline_create_info *extra,
105 const VkAllocationCallbacks *alloc,
106 VkPipeline *pipeline)
107 {
108 VkDevice device_h = radv_device_to_handle(device);
109 VkResult result;
110
111 struct radv_shader_module vs_m = { .nir = vs_nir };
112 struct radv_shader_module fs_m = { .nir = fs_nir };
113
114 result = radv_graphics_pipeline_create(device_h,
115 radv_pipeline_cache_to_handle(&device->meta_state.cache),
116 &(VkGraphicsPipelineCreateInfo) {
117 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
118 .stageCount = fs_nir ? 2 : 1,
119 .pStages = (VkPipelineShaderStageCreateInfo[]) {
120 {
121 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
122 .stage = VK_SHADER_STAGE_VERTEX_BIT,
123 .module = radv_shader_module_to_handle(&vs_m),
124 .pName = "main",
125 },
126 {
127 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
128 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
129 .module = radv_shader_module_to_handle(&fs_m),
130 .pName = "main",
131 },
132 },
133 .pVertexInputState = vi_state,
134 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
135 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
136 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
137 .primitiveRestartEnable = false,
138 },
139 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
140 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
141 .viewportCount = 1,
142 .scissorCount = 1,
143 },
144 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
145 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
146 .rasterizerDiscardEnable = false,
147 .polygonMode = VK_POLYGON_MODE_FILL,
148 .cullMode = VK_CULL_MODE_NONE,
149 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
150 .depthBiasEnable = false,
151 },
152 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
153 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
154 .rasterizationSamples = samples,
155 .sampleShadingEnable = false,
156 .pSampleMask = NULL,
157 .alphaToCoverageEnable = false,
158 .alphaToOneEnable = false,
159 },
160 .pDepthStencilState = ds_state,
161 .pColorBlendState = cb_state,
162 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
163 /* The meta clear pipeline declares all state as dynamic.
164 * As a consequence, vkCmdBindPipeline writes no dynamic state
165 * to the cmd buffer. Therefore, at the end of the meta clear,
166 * we need only restore dynamic state was vkCmdSet.
167 */
168 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
169 .dynamicStateCount = 8,
170 .pDynamicStates = (VkDynamicState[]) {
171 /* Everything except stencil write mask */
172 VK_DYNAMIC_STATE_VIEWPORT,
173 VK_DYNAMIC_STATE_SCISSOR,
174 VK_DYNAMIC_STATE_LINE_WIDTH,
175 VK_DYNAMIC_STATE_DEPTH_BIAS,
176 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
177 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
178 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
179 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
180 },
181 },
182 .layout = layout,
183 .flags = 0,
184 .renderPass = radv_render_pass_to_handle(render_pass),
185 .subpass = 0,
186 },
187 extra,
188 alloc,
189 pipeline);
190
191 ralloc_free(vs_nir);
192 ralloc_free(fs_nir);
193
194 return result;
195 }
196
197 static VkResult
198 create_color_renderpass(struct radv_device *device,
199 VkFormat vk_format,
200 uint32_t samples,
201 VkRenderPass *pass)
202 {
203 return radv_CreateRenderPass(radv_device_to_handle(device),
204 &(VkRenderPassCreateInfo) {
205 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
206 .attachmentCount = 1,
207 .pAttachments = &(VkAttachmentDescription) {
208 .format = vk_format,
209 .samples = samples,
210 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
211 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
212 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
213 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
214 },
215 .subpassCount = 1,
216 .pSubpasses = &(VkSubpassDescription) {
217 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
218 .inputAttachmentCount = 0,
219 .colorAttachmentCount = 1,
220 .pColorAttachments = &(VkAttachmentReference) {
221 .attachment = 0,
222 .layout = VK_IMAGE_LAYOUT_GENERAL,
223 },
224 .pResolveAttachments = NULL,
225 .pDepthStencilAttachment = &(VkAttachmentReference) {
226 .attachment = VK_ATTACHMENT_UNUSED,
227 .layout = VK_IMAGE_LAYOUT_GENERAL,
228 },
229 .preserveAttachmentCount = 1,
230 .pPreserveAttachments = (uint32_t[]) { 0 },
231 },
232 .dependencyCount = 0,
233 }, &device->meta_state.alloc, pass);
234 }
235
236 static VkResult
237 create_color_pipeline(struct radv_device *device,
238 uint32_t samples,
239 uint32_t frag_output,
240 VkPipeline *pipeline,
241 VkRenderPass pass)
242 {
243 struct nir_shader *vs_nir;
244 struct nir_shader *fs_nir;
245 VkResult result;
246 build_color_shaders(&vs_nir, &fs_nir, frag_output);
247
248 const VkPipelineVertexInputStateCreateInfo vi_state = {
249 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
250 .vertexBindingDescriptionCount = 0,
251 .vertexAttributeDescriptionCount = 0,
252 };
253
254 const VkPipelineDepthStencilStateCreateInfo ds_state = {
255 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
256 .depthTestEnable = false,
257 .depthWriteEnable = false,
258 .depthBoundsTestEnable = false,
259 .stencilTestEnable = false,
260 };
261
262 VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
263 blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
264 .blendEnable = false,
265 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
266 VK_COLOR_COMPONENT_R_BIT |
267 VK_COLOR_COMPONENT_G_BIT |
268 VK_COLOR_COMPONENT_B_BIT,
269 };
270
271 const VkPipelineColorBlendStateCreateInfo cb_state = {
272 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
273 .logicOpEnable = false,
274 .attachmentCount = MAX_RTS,
275 .pAttachments = blend_attachment_state
276 };
277
278
279 struct radv_graphics_pipeline_create_info extra = {
280 .use_rectlist = true,
281 };
282 result = create_pipeline(device, radv_render_pass_from_handle(pass),
283 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
284 device->meta_state.clear_color_p_layout,
285 &extra, &device->meta_state.alloc, pipeline);
286
287 return result;
288 }
289
290 void
291 radv_device_finish_meta_clear_state(struct radv_device *device)
292 {
293 struct radv_meta_state *state = &device->meta_state;
294
295 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
296 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
297 radv_DestroyPipeline(radv_device_to_handle(device),
298 state->clear[i].color_pipelines[j],
299 &state->alloc);
300 radv_DestroyRenderPass(radv_device_to_handle(device),
301 state->clear[i].render_pass[j],
302 &state->alloc);
303 }
304
305 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
306 radv_DestroyPipeline(radv_device_to_handle(device),
307 state->clear[i].depth_only_pipeline[j],
308 &state->alloc);
309 radv_DestroyPipeline(radv_device_to_handle(device),
310 state->clear[i].stencil_only_pipeline[j],
311 &state->alloc);
312 radv_DestroyPipeline(radv_device_to_handle(device),
313 state->clear[i].depthstencil_pipeline[j],
314 &state->alloc);
315 }
316 radv_DestroyRenderPass(radv_device_to_handle(device),
317 state->clear[i].depthstencil_rp,
318 &state->alloc);
319 }
320 radv_DestroyPipelineLayout(radv_device_to_handle(device),
321 state->clear_color_p_layout,
322 &state->alloc);
323 radv_DestroyPipelineLayout(radv_device_to_handle(device),
324 state->clear_depth_p_layout,
325 &state->alloc);
326 }
327
328 static void
329 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
330 const VkClearAttachment *clear_att,
331 const VkClearRect *clear_rect,
332 uint32_t view_mask)
333 {
334 struct radv_device *device = cmd_buffer->device;
335 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
336 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
337 const uint32_t subpass_att = clear_att->colorAttachment;
338 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
339 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
340 const uint32_t samples = iview->image->info.samples;
341 const uint32_t samples_log2 = ffs(samples) - 1;
342 unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
343 VkClearColorValue clear_value = clear_att->clearValue.color;
344 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
345 VkPipeline pipeline;
346
347 if (fs_key == -1) {
348 radv_finishme("color clears incomplete");
349 return;
350 }
351
352 pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
353 if (!pipeline) {
354 radv_finishme("color clears incomplete");
355 return;
356 }
357 assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
358 assert(pipeline);
359 assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
360 assert(clear_att->colorAttachment < subpass->color_count);
361
362 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
363 device->meta_state.clear_color_p_layout,
364 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
365 &clear_value);
366
367 struct radv_subpass clear_subpass = {
368 .color_count = 1,
369 .color_attachments = (VkAttachmentReference[]) {
370 subpass->color_attachments[clear_att->colorAttachment]
371 },
372 .depth_stencil_attachment = (VkAttachmentReference) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
373 };
374
375 radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
376
377 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
378 pipeline);
379
380 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
381 .x = clear_rect->rect.offset.x,
382 .y = clear_rect->rect.offset.y,
383 .width = clear_rect->rect.extent.width,
384 .height = clear_rect->rect.extent.height,
385 .minDepth = 0.0f,
386 .maxDepth = 1.0f
387 });
388
389 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
390
391 if (view_mask) {
392 unsigned i;
393 for_each_bit(i, view_mask)
394 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
395 } else {
396 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
397 }
398
399 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
400 }
401
402
403 static void
404 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
405 {
406 nir_builder vs_b, fs_b;
407
408 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
409 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
410
411 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
412 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
413 const struct glsl_type *position_out_type = glsl_vec4_type();
414
415 nir_variable *vs_out_pos =
416 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
417 "gl_Position");
418 vs_out_pos->data.location = VARYING_SLOT_POS;
419
420 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
421 nir_intrinsic_set_base(in_color_load, 0);
422 nir_intrinsic_set_range(in_color_load, 4);
423 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
424 in_color_load->num_components = 1;
425 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
426 nir_builder_instr_insert(&vs_b, &in_color_load->instr);
427
428 nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
429 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
430
431 const struct glsl_type *layer_type = glsl_int_type();
432 nir_variable *vs_out_layer =
433 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
434 "v_layer");
435 vs_out_layer->data.location = VARYING_SLOT_LAYER;
436 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
437 nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
438 nir_ssa_def *base_instance = nir_load_system_value(&vs_b, nir_intrinsic_load_base_instance, 0);
439
440 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
441 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
442
443 *out_vs = vs_b.shader;
444 *out_fs = fs_b.shader;
445 }
446
447 static VkResult
448 create_depthstencil_renderpass(struct radv_device *device,
449 uint32_t samples,
450 VkRenderPass *render_pass)
451 {
452 return radv_CreateRenderPass(radv_device_to_handle(device),
453 &(VkRenderPassCreateInfo) {
454 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
455 .attachmentCount = 1,
456 .pAttachments = &(VkAttachmentDescription) {
457 .format = VK_FORMAT_D32_SFLOAT_S8_UINT,
458 .samples = samples,
459 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
460 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
461 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
462 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
463 },
464 .subpassCount = 1,
465 .pSubpasses = &(VkSubpassDescription) {
466 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
467 .inputAttachmentCount = 0,
468 .colorAttachmentCount = 0,
469 .pColorAttachments = NULL,
470 .pResolveAttachments = NULL,
471 .pDepthStencilAttachment = &(VkAttachmentReference) {
472 .attachment = 0,
473 .layout = VK_IMAGE_LAYOUT_GENERAL,
474 },
475 .preserveAttachmentCount = 1,
476 .pPreserveAttachments = (uint32_t[]) { 0 },
477 },
478 .dependencyCount = 0,
479 }, &device->meta_state.alloc, render_pass);
480 }
481
482 static VkResult
483 create_depthstencil_pipeline(struct radv_device *device,
484 VkImageAspectFlags aspects,
485 uint32_t samples,
486 int index,
487 VkPipeline *pipeline,
488 VkRenderPass render_pass)
489 {
490 struct nir_shader *vs_nir, *fs_nir;
491 VkResult result;
492 build_depthstencil_shader(&vs_nir, &fs_nir);
493
494 const VkPipelineVertexInputStateCreateInfo vi_state = {
495 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
496 .vertexBindingDescriptionCount = 0,
497 .vertexAttributeDescriptionCount = 0,
498 };
499
500 const VkPipelineDepthStencilStateCreateInfo ds_state = {
501 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
502 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
503 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
504 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
505 .depthBoundsTestEnable = false,
506 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
507 .front = {
508 .passOp = VK_STENCIL_OP_REPLACE,
509 .compareOp = VK_COMPARE_OP_ALWAYS,
510 .writeMask = UINT32_MAX,
511 .reference = 0, /* dynamic */
512 },
513 .back = { 0 /* dont care */ },
514 };
515
516 const VkPipelineColorBlendStateCreateInfo cb_state = {
517 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
518 .logicOpEnable = false,
519 .attachmentCount = 0,
520 .pAttachments = NULL,
521 };
522
523 struct radv_graphics_pipeline_create_info extra = {
524 .use_rectlist = true,
525 };
526
527 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
528 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
529 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
530 }
531 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
532 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
533 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
534 }
535 result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
536 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
537 device->meta_state.clear_depth_p_layout,
538 &extra, &device->meta_state.alloc, pipeline);
539 return result;
540 }
541
542 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
543 const struct radv_image_view *iview,
544 VkImageAspectFlags aspects,
545 VkImageLayout layout,
546 const VkClearRect *clear_rect,
547 VkClearDepthStencilValue clear_value)
548 {
549 uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
550 cmd_buffer->queue_family_index,
551 cmd_buffer->queue_family_index);
552 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
553 clear_rect->rect.extent.width != iview->extent.width ||
554 clear_rect->rect.extent.height != iview->extent.height)
555 return false;
556 if (iview->image->tc_compatible_htile &&
557 (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && clear_value.depth != 0.0 &&
558 clear_value.depth != 1.0) ||
559 ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0)))
560 return false;
561 if (iview->image->surface.htile_size &&
562 iview->base_mip == 0 &&
563 iview->base_layer == 0 &&
564 radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
565 !radv_image_extent_compare(iview->image, &iview->extent))
566 return true;
567 return false;
568 }
569
570 static VkPipeline
571 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
572 struct radv_meta_state *meta_state,
573 const struct radv_image_view *iview,
574 int samples_log2,
575 VkImageAspectFlags aspects,
576 VkImageLayout layout,
577 const VkClearRect *clear_rect,
578 VkClearDepthStencilValue clear_value)
579 {
580 bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, clear_rect, clear_value);
581 int index = DEPTH_CLEAR_SLOW;
582
583 if (fast) {
584 /* we don't know the previous clear values, so we always have
585 * the NO_EXPCLEAR path */
586 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
587 }
588
589 switch (aspects) {
590 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
591 return meta_state->clear[samples_log2].depthstencil_pipeline[index];
592 case VK_IMAGE_ASPECT_DEPTH_BIT:
593 return meta_state->clear[samples_log2].depth_only_pipeline[index];
594 case VK_IMAGE_ASPECT_STENCIL_BIT:
595 return meta_state->clear[samples_log2].stencil_only_pipeline[index];
596 }
597 unreachable("expected depth or stencil aspect");
598 }
599
600 static void
601 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
602 const VkClearAttachment *clear_att,
603 const VkClearRect *clear_rect)
604 {
605 struct radv_device *device = cmd_buffer->device;
606 struct radv_meta_state *meta_state = &device->meta_state;
607 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
608 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
609 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
610 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
611 VkImageAspectFlags aspects = clear_att->aspectMask;
612 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
613 const uint32_t samples = iview->image->info.samples;
614 const uint32_t samples_log2 = ffs(samples) - 1;
615 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
616
617 assert(aspects == VK_IMAGE_ASPECT_DEPTH_BIT ||
618 aspects == VK_IMAGE_ASPECT_STENCIL_BIT ||
619 aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
620 VK_IMAGE_ASPECT_STENCIL_BIT));
621 assert(pass_att != VK_ATTACHMENT_UNUSED);
622
623 if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
624 clear_value.depth = 1.0f;
625
626 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
627 device->meta_state.clear_depth_p_layout,
628 VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
629 &clear_value.depth);
630
631 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
632 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
633 clear_value.stencil);
634 }
635
636 VkPipeline pipeline = pick_depthstencil_pipeline(cmd_buffer,
637 meta_state,
638 iview,
639 samples_log2,
640 aspects,
641 subpass->depth_stencil_attachment.layout,
642 clear_rect,
643 clear_value);
644
645 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
646 pipeline);
647
648 if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
649 subpass->depth_stencil_attachment.layout,
650 clear_rect, clear_value))
651 radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
652
653 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
654 .x = clear_rect->rect.offset.x,
655 .y = clear_rect->rect.offset.y,
656 .width = clear_rect->rect.extent.width,
657 .height = clear_rect->rect.extent.height,
658 .minDepth = 0.0f,
659 .maxDepth = 1.0f
660 });
661
662 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
663
664 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
665 }
666
667 static bool
668 emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
669 const VkClearAttachment *clear_att,
670 const VkClearRect *clear_rect,
671 enum radv_cmd_flush_bits *pre_flush,
672 enum radv_cmd_flush_bits *post_flush)
673 {
674 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
675 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
676 VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
677 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
678 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
679 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
680 VkImageAspectFlags aspects = clear_att->aspectMask;
681 uint32_t clear_word;
682
683 if (!iview->image->surface.htile_size)
684 return false;
685
686 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
687 return false;
688
689 if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
690 goto fail;
691
692 /* don't fast clear 3D */
693 if (iview->image->type == VK_IMAGE_TYPE_3D)
694 goto fail;
695
696 /* all layers are bound */
697 if (iview->base_layer > 0)
698 goto fail;
699 if (iview->image->info.array_size != iview->layer_count)
700 goto fail;
701
702 if (!radv_image_extent_compare(iview->image, &iview->extent))
703 goto fail;
704
705 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
706 clear_rect->rect.extent.width != iview->image->info.width ||
707 clear_rect->rect.extent.height != iview->image->info.height)
708 goto fail;
709
710 if (clear_rect->baseArrayLayer != 0)
711 goto fail;
712 if (clear_rect->layerCount != iview->image->info.array_size)
713 goto fail;
714
715 if ((clear_value.depth != 0.0 && clear_value.depth != 1.0) || !(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
716 goto fail;
717
718 if (vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) {
719 if (clear_value.stencil != 0 || !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))
720 goto fail;
721 clear_word = clear_value.depth ? 0xfffc0000 : 0;
722 } else
723 clear_word = clear_value.depth ? 0xfffffff0 : 0;
724
725 if (pre_flush) {
726 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
727 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
728 *pre_flush |= cmd_buffer->state.flush_bits;
729 } else
730 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
731 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
732
733 radv_fill_buffer(cmd_buffer, iview->image->bo,
734 iview->image->offset + iview->image->htile_offset,
735 iview->image->surface.htile_size, clear_word);
736
737
738 radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
739 if (post_flush)
740 *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
741 RADV_CMD_FLAG_INV_VMEM_L1 |
742 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
743 else
744 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
745 RADV_CMD_FLAG_INV_VMEM_L1 |
746 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
747 return true;
748 fail:
749 return false;
750 }
751
752 static VkFormat pipeline_formats[] = {
753 VK_FORMAT_R8G8B8A8_UNORM,
754 VK_FORMAT_R8G8B8A8_UINT,
755 VK_FORMAT_R8G8B8A8_SINT,
756 VK_FORMAT_A2R10G10B10_UINT_PACK32,
757 VK_FORMAT_A2R10G10B10_SINT_PACK32,
758 VK_FORMAT_R16G16B16A16_UNORM,
759 VK_FORMAT_R16G16B16A16_SNORM,
760 VK_FORMAT_R16G16B16A16_UINT,
761 VK_FORMAT_R16G16B16A16_SINT,
762 VK_FORMAT_R32_SFLOAT,
763 VK_FORMAT_R32G32_SFLOAT,
764 VK_FORMAT_R32G32B32A32_SFLOAT
765 };
766
767 VkResult
768 radv_device_init_meta_clear_state(struct radv_device *device)
769 {
770 VkResult res;
771 struct radv_meta_state *state = &device->meta_state;
772
773 VkPipelineLayoutCreateInfo pl_color_create_info = {
774 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
775 .setLayoutCount = 0,
776 .pushConstantRangeCount = 1,
777 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
778 };
779
780 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
781 &pl_color_create_info,
782 &device->meta_state.alloc,
783 &device->meta_state.clear_color_p_layout);
784 if (res != VK_SUCCESS)
785 goto fail;
786
787 VkPipelineLayoutCreateInfo pl_depth_create_info = {
788 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
789 .setLayoutCount = 0,
790 .pushConstantRangeCount = 1,
791 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
792 };
793
794 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
795 &pl_depth_create_info,
796 &device->meta_state.alloc,
797 &device->meta_state.clear_depth_p_layout);
798 if (res != VK_SUCCESS)
799 goto fail;
800
801 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
802 uint32_t samples = 1 << i;
803 for (uint32_t j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
804 VkFormat format = pipeline_formats[j];
805 unsigned fs_key = radv_format_meta_fs_key(format);
806 assert(!state->clear[i].color_pipelines[fs_key]);
807
808 res = create_color_renderpass(device, format, samples,
809 &state->clear[i].render_pass[fs_key]);
810 if (res != VK_SUCCESS)
811 goto fail;
812
813 res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
814 state->clear[i].render_pass[fs_key]);
815 if (res != VK_SUCCESS)
816 goto fail;
817
818 }
819
820 res = create_depthstencil_renderpass(device,
821 samples,
822 &state->clear[i].depthstencil_rp);
823 if (res != VK_SUCCESS)
824 goto fail;
825
826 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
827 res = create_depthstencil_pipeline(device,
828 VK_IMAGE_ASPECT_DEPTH_BIT,
829 samples,
830 j,
831 &state->clear[i].depth_only_pipeline[j],
832 state->clear[i].depthstencil_rp);
833 if (res != VK_SUCCESS)
834 goto fail;
835
836 res = create_depthstencil_pipeline(device,
837 VK_IMAGE_ASPECT_STENCIL_BIT,
838 samples,
839 j,
840 &state->clear[i].stencil_only_pipeline[j],
841 state->clear[i].depthstencil_rp);
842 if (res != VK_SUCCESS)
843 goto fail;
844
845 res = create_depthstencil_pipeline(device,
846 VK_IMAGE_ASPECT_DEPTH_BIT |
847 VK_IMAGE_ASPECT_STENCIL_BIT,
848 samples,
849 j,
850 &state->clear[i].depthstencil_pipeline[j],
851 state->clear[i].depthstencil_rp);
852 if (res != VK_SUCCESS)
853 goto fail;
854 }
855 }
856 return VK_SUCCESS;
857
858 fail:
859 radv_device_finish_meta_clear_state(device);
860 return res;
861 }
862
863 static void vi_get_fast_clear_parameters(VkFormat format,
864 const VkClearColorValue *clear_value,
865 uint32_t* reset_value,
866 bool *can_avoid_fast_clear_elim)
867 {
868 bool values[4] = {};
869 int extra_channel;
870 bool main_value = false;
871 bool extra_value = false;
872 int i;
873 *can_avoid_fast_clear_elim = false;
874
875 *reset_value = 0x20202020U;
876
877 const struct vk_format_description *desc = vk_format_description(format);
878 if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
879 format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
880 format == VK_FORMAT_B5G6R5_UNORM_PACK16)
881 extra_channel = -1;
882 else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
883 if (radv_translate_colorswap(format, false) <= 1)
884 extra_channel = desc->nr_channels - 1;
885 else
886 extra_channel = 0;
887 } else
888 return;
889
890 for (i = 0; i < 4; i++) {
891 int index = desc->swizzle[i] - VK_SWIZZLE_X;
892 if (desc->swizzle[i] < VK_SWIZZLE_X ||
893 desc->swizzle[i] > VK_SWIZZLE_W)
894 continue;
895
896 if (desc->channel[i].pure_integer &&
897 desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
898 /* Use the maximum value for clamping the clear color. */
899 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
900
901 values[i] = clear_value->int32[i] != 0;
902 if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
903 return;
904 } else if (desc->channel[i].pure_integer &&
905 desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
906 /* Use the maximum value for clamping the clear color. */
907 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
908
909 values[i] = clear_value->uint32[i] != 0U;
910 if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
911 return;
912 } else {
913 values[i] = clear_value->float32[i] != 0.0F;
914 if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
915 return;
916 }
917
918 if (index == extra_channel)
919 extra_value = values[i];
920 else
921 main_value = values[i];
922 }
923
924 for (int i = 0; i < 4; ++i)
925 if (values[i] != main_value &&
926 desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
927 desc->swizzle[i] >= VK_SWIZZLE_X &&
928 desc->swizzle[i] <= VK_SWIZZLE_W)
929 return;
930
931 *can_avoid_fast_clear_elim = true;
932 if (main_value)
933 *reset_value |= 0x80808080U;
934
935 if (extra_value)
936 *reset_value |= 0x40404040U;
937 return;
938 }
939
940 static bool
941 emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
942 const VkClearAttachment *clear_att,
943 const VkClearRect *clear_rect,
944 enum radv_cmd_flush_bits *pre_flush,
945 enum radv_cmd_flush_bits *post_flush,
946 uint32_t view_mask)
947 {
948 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
949 const uint32_t subpass_att = clear_att->colorAttachment;
950 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
951 VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
952 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
953 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
954 VkClearColorValue clear_value = clear_att->clearValue.color;
955 uint32_t clear_color[2];
956 bool ret;
957
958 if (!iview->image->cmask.size && !iview->image->surface.dcc_size)
959 return false;
960
961 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
962 return false;
963
964 if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
965 goto fail;
966
967 /* don't fast clear 3D */
968 if (iview->image->type == VK_IMAGE_TYPE_3D)
969 goto fail;
970
971 /* all layers are bound */
972 if (iview->base_layer > 0)
973 goto fail;
974 if (iview->image->info.array_size != iview->layer_count)
975 goto fail;
976
977 if (iview->image->info.levels > 1)
978 goto fail;
979
980 if (iview->image->surface.is_linear)
981 goto fail;
982 if (!radv_image_extent_compare(iview->image, &iview->extent))
983 goto fail;
984
985 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
986 clear_rect->rect.extent.width != iview->image->info.width ||
987 clear_rect->rect.extent.height != iview->image->info.height)
988 goto fail;
989
990 if (view_mask && (iview->image->info.array_size >= 32 ||
991 (1u << iview->image->info.array_size) - 1u != view_mask))
992 goto fail;
993 if (!view_mask && clear_rect->baseArrayLayer != 0)
994 goto fail;
995 if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
996 goto fail;
997
998 /* RB+ doesn't work with CMASK fast clear on Stoney. */
999 if (!iview->image->surface.dcc_size &&
1000 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY)
1001 goto fail;
1002
1003 /* DCC */
1004 ret = radv_format_pack_clear_color(iview->image->vk_format,
1005 clear_color, &clear_value);
1006 if (ret == false)
1007 goto fail;
1008
1009 if (pre_flush) {
1010 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1011 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
1012 *pre_flush |= cmd_buffer->state.flush_bits;
1013 } else
1014 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1015 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1016 /* clear cmask buffer */
1017 if (iview->image->surface.dcc_size) {
1018 uint32_t reset_value;
1019 bool can_avoid_fast_clear_elim;
1020 vi_get_fast_clear_parameters(iview->image->vk_format,
1021 &clear_value, &reset_value,
1022 &can_avoid_fast_clear_elim);
1023
1024 radv_fill_buffer(cmd_buffer, iview->image->bo,
1025 iview->image->offset + iview->image->dcc_offset,
1026 iview->image->surface.dcc_size, reset_value);
1027 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
1028 !can_avoid_fast_clear_elim);
1029 } else {
1030 radv_fill_buffer(cmd_buffer, iview->image->bo,
1031 iview->image->offset + iview->image->cmask.offset,
1032 iview->image->cmask.size, 0);
1033 }
1034
1035 if (post_flush)
1036 *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1037 RADV_CMD_FLAG_INV_VMEM_L1 |
1038 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1039 else
1040 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1041 RADV_CMD_FLAG_INV_VMEM_L1 |
1042 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1043
1044 radv_set_color_clear_regs(cmd_buffer, iview->image, subpass_att, clear_color);
1045
1046 return true;
1047 fail:
1048 return false;
1049 }
1050
1051 /**
1052 * The parameters mean that same as those in vkCmdClearAttachments.
1053 */
1054 static void
1055 emit_clear(struct radv_cmd_buffer *cmd_buffer,
1056 const VkClearAttachment *clear_att,
1057 const VkClearRect *clear_rect,
1058 enum radv_cmd_flush_bits *pre_flush,
1059 enum radv_cmd_flush_bits *post_flush,
1060 uint32_t view_mask)
1061 {
1062 if (clear_att->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1063 if (!emit_fast_color_clear(cmd_buffer, clear_att, clear_rect,
1064 pre_flush, post_flush, view_mask))
1065 emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask);
1066 } else {
1067 assert(clear_att->aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT |
1068 VK_IMAGE_ASPECT_STENCIL_BIT));
1069 if (!emit_fast_htile_clear(cmd_buffer, clear_att, clear_rect,
1070 pre_flush, post_flush))
1071 emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
1072 }
1073 }
1074
1075 static inline bool
1076 radv_attachment_needs_clear(struct radv_cmd_state *cmd_state, uint32_t a)
1077 {
1078 uint32_t view_mask = cmd_state->subpass->view_mask;
1079 return (a != VK_ATTACHMENT_UNUSED &&
1080 cmd_state->attachments[a].pending_clear_aspects &&
1081 (!view_mask || (view_mask & ~cmd_state->attachments[a].cleared_views)));
1082 }
1083
1084 static bool
1085 radv_subpass_needs_clear(struct radv_cmd_buffer *cmd_buffer)
1086 {
1087 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1088 uint32_t a;
1089
1090 if (!cmd_state->subpass)
1091 return false;
1092
1093 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1094 a = cmd_state->subpass->color_attachments[i].attachment;
1095 if (radv_attachment_needs_clear(cmd_state, a))
1096 return true;
1097 }
1098
1099 a = cmd_state->subpass->depth_stencil_attachment.attachment;
1100 return radv_attachment_needs_clear(cmd_state, a);
1101 }
1102
1103 static void
1104 radv_subpass_clear_attachment(struct radv_cmd_buffer *cmd_buffer,
1105 struct radv_attachment_state *attachment,
1106 const VkClearAttachment *clear_att,
1107 enum radv_cmd_flush_bits *pre_flush,
1108 enum radv_cmd_flush_bits *post_flush)
1109 {
1110 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1111 uint32_t view_mask = cmd_state->subpass->view_mask;
1112
1113 VkClearRect clear_rect = {
1114 .rect = cmd_state->render_area,
1115 .baseArrayLayer = 0,
1116 .layerCount = cmd_state->framebuffer->layers,
1117 };
1118
1119 emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush,
1120 view_mask & ~attachment->cleared_views);
1121 if (view_mask)
1122 attachment->cleared_views |= view_mask;
1123 else
1124 attachment->pending_clear_aspects = 0;
1125 }
1126
1127 /**
1128 * Emit any pending attachment clears for the current subpass.
1129 *
1130 * @see radv_attachment_state::pending_clear_aspects
1131 */
1132 void
1133 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1134 {
1135 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1136 struct radv_meta_saved_state saved_state;
1137 enum radv_cmd_flush_bits pre_flush = 0;
1138 enum radv_cmd_flush_bits post_flush = 0;
1139
1140 if (!radv_subpass_needs_clear(cmd_buffer))
1141 return;
1142
1143 radv_meta_save(&saved_state, cmd_buffer,
1144 RADV_META_SAVE_GRAPHICS_PIPELINE |
1145 RADV_META_SAVE_CONSTANTS);
1146
1147 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1148 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1149
1150 if (!radv_attachment_needs_clear(cmd_state, a))
1151 continue;
1152
1153 assert(cmd_state->attachments[a].pending_clear_aspects ==
1154 VK_IMAGE_ASPECT_COLOR_BIT);
1155
1156 VkClearAttachment clear_att = {
1157 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1158 .colorAttachment = i, /* Use attachment index relative to subpass */
1159 .clearValue = cmd_state->attachments[a].clear_value,
1160 };
1161
1162 radv_subpass_clear_attachment(cmd_buffer,
1163 &cmd_state->attachments[a],
1164 &clear_att, &pre_flush,
1165 &post_flush);
1166 }
1167
1168 uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1169 if (radv_attachment_needs_clear(cmd_state, ds)) {
1170 VkClearAttachment clear_att = {
1171 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1172 .clearValue = cmd_state->attachments[ds].clear_value,
1173 };
1174
1175 radv_subpass_clear_attachment(cmd_buffer,
1176 &cmd_state->attachments[ds],
1177 &clear_att, &pre_flush,
1178 &post_flush);
1179 }
1180
1181 radv_meta_restore(&saved_state, cmd_buffer);
1182 cmd_buffer->state.flush_bits |= post_flush;
1183 }
1184
1185 static void
1186 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1187 struct radv_image *image,
1188 VkImageLayout image_layout,
1189 const VkImageSubresourceRange *range,
1190 VkFormat format, int level, int layer,
1191 const VkClearValue *clear_val)
1192 {
1193 VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1194 struct radv_image_view iview;
1195 uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level);
1196 uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level);
1197
1198 radv_image_view_init(&iview, cmd_buffer->device,
1199 &(VkImageViewCreateInfo) {
1200 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1201 .image = radv_image_to_handle(image),
1202 .viewType = radv_meta_get_view_type(image),
1203 .format = format,
1204 .subresourceRange = {
1205 .aspectMask = range->aspectMask,
1206 .baseMipLevel = range->baseMipLevel + level,
1207 .levelCount = 1,
1208 .baseArrayLayer = range->baseArrayLayer + layer,
1209 .layerCount = 1
1210 },
1211 });
1212
1213 VkFramebuffer fb;
1214 radv_CreateFramebuffer(device_h,
1215 &(VkFramebufferCreateInfo) {
1216 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1217 .attachmentCount = 1,
1218 .pAttachments = (VkImageView[]) {
1219 radv_image_view_to_handle(&iview),
1220 },
1221 .width = width,
1222 .height = height,
1223 .layers = 1
1224 },
1225 &cmd_buffer->pool->alloc,
1226 &fb);
1227
1228 VkAttachmentDescription att_desc = {
1229 .format = iview.vk_format,
1230 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1231 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1232 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1233 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1234 .initialLayout = image_layout,
1235 .finalLayout = image_layout,
1236 };
1237
1238 VkSubpassDescription subpass_desc = {
1239 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1240 .inputAttachmentCount = 0,
1241 .colorAttachmentCount = 0,
1242 .pColorAttachments = NULL,
1243 .pResolveAttachments = NULL,
1244 .pDepthStencilAttachment = NULL,
1245 .preserveAttachmentCount = 0,
1246 .pPreserveAttachments = NULL,
1247 };
1248
1249 const VkAttachmentReference att_ref = {
1250 .attachment = 0,
1251 .layout = image_layout,
1252 };
1253
1254 if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1255 subpass_desc.colorAttachmentCount = 1;
1256 subpass_desc.pColorAttachments = &att_ref;
1257 } else {
1258 subpass_desc.pDepthStencilAttachment = &att_ref;
1259 }
1260
1261 VkRenderPass pass;
1262 radv_CreateRenderPass(device_h,
1263 &(VkRenderPassCreateInfo) {
1264 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1265 .attachmentCount = 1,
1266 .pAttachments = &att_desc,
1267 .subpassCount = 1,
1268 .pSubpasses = &subpass_desc,
1269 },
1270 &cmd_buffer->pool->alloc,
1271 &pass);
1272
1273 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1274 &(VkRenderPassBeginInfo) {
1275 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1276 .renderArea = {
1277 .offset = { 0, 0, },
1278 .extent = {
1279 .width = width,
1280 .height = height,
1281 },
1282 },
1283 .renderPass = pass,
1284 .framebuffer = fb,
1285 .clearValueCount = 0,
1286 .pClearValues = NULL,
1287 },
1288 VK_SUBPASS_CONTENTS_INLINE);
1289
1290 VkClearAttachment clear_att = {
1291 .aspectMask = range->aspectMask,
1292 .colorAttachment = 0,
1293 .clearValue = *clear_val,
1294 };
1295
1296 VkClearRect clear_rect = {
1297 .rect = {
1298 .offset = { 0, 0 },
1299 .extent = { width, height },
1300 },
1301 .baseArrayLayer = range->baseArrayLayer,
1302 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1303 };
1304
1305 emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0);
1306
1307 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1308 radv_DestroyRenderPass(device_h, pass,
1309 &cmd_buffer->pool->alloc);
1310 radv_DestroyFramebuffer(device_h, fb,
1311 &cmd_buffer->pool->alloc);
1312 }
1313 static void
1314 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
1315 struct radv_image *image,
1316 VkImageLayout image_layout,
1317 const VkClearValue *clear_value,
1318 uint32_t range_count,
1319 const VkImageSubresourceRange *ranges,
1320 bool cs)
1321 {
1322 VkFormat format = image->vk_format;
1323 VkClearValue internal_clear_value = *clear_value;
1324
1325 if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
1326 uint32_t value;
1327 format = VK_FORMAT_R32_UINT;
1328 value = float3_to_rgb9e5(clear_value->color.float32);
1329 internal_clear_value.color.uint32[0] = value;
1330 }
1331
1332 if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
1333 uint8_t r, g;
1334 format = VK_FORMAT_R8_UINT;
1335 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
1336 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
1337 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
1338 }
1339
1340 for (uint32_t r = 0; r < range_count; r++) {
1341 const VkImageSubresourceRange *range = &ranges[r];
1342 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
1343 const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
1344 radv_minify(image->info.depth, range->baseMipLevel + l) :
1345 radv_get_layerCount(image, range);
1346 for (uint32_t s = 0; s < layer_count; ++s) {
1347
1348 if (cs) {
1349 struct radv_meta_blit2d_surf surf;
1350 surf.format = format;
1351 surf.image = image;
1352 surf.level = range->baseMipLevel + l;
1353 surf.layer = range->baseArrayLayer + s;
1354 surf.aspect_mask = range->aspectMask;
1355 radv_meta_clear_image_cs(cmd_buffer, &surf,
1356 &internal_clear_value.color);
1357 } else {
1358 radv_clear_image_layer(cmd_buffer, image, image_layout,
1359 range, format, l, s, &internal_clear_value);
1360 }
1361 }
1362 }
1363 }
1364 }
1365
1366 void radv_CmdClearColorImage(
1367 VkCommandBuffer commandBuffer,
1368 VkImage image_h,
1369 VkImageLayout imageLayout,
1370 const VkClearColorValue* pColor,
1371 uint32_t rangeCount,
1372 const VkImageSubresourceRange* pRanges)
1373 {
1374 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1375 RADV_FROM_HANDLE(radv_image, image, image_h);
1376 struct radv_meta_saved_state saved_state;
1377 bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1378
1379 if (cs) {
1380 radv_meta_save(&saved_state, cmd_buffer,
1381 RADV_META_SAVE_COMPUTE_PIPELINE |
1382 RADV_META_SAVE_CONSTANTS |
1383 RADV_META_SAVE_DESCRIPTORS);
1384 } else {
1385 radv_meta_save(&saved_state, cmd_buffer,
1386 RADV_META_SAVE_GRAPHICS_PIPELINE |
1387 RADV_META_SAVE_CONSTANTS);
1388 }
1389
1390 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1391 (const VkClearValue *) pColor,
1392 rangeCount, pRanges, cs);
1393
1394 radv_meta_restore(&saved_state, cmd_buffer);
1395 }
1396
1397 void radv_CmdClearDepthStencilImage(
1398 VkCommandBuffer commandBuffer,
1399 VkImage image_h,
1400 VkImageLayout imageLayout,
1401 const VkClearDepthStencilValue* pDepthStencil,
1402 uint32_t rangeCount,
1403 const VkImageSubresourceRange* pRanges)
1404 {
1405 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1406 RADV_FROM_HANDLE(radv_image, image, image_h);
1407 struct radv_meta_saved_state saved_state;
1408
1409 radv_meta_save(&saved_state, cmd_buffer,
1410 RADV_META_SAVE_GRAPHICS_PIPELINE |
1411 RADV_META_SAVE_CONSTANTS);
1412
1413 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1414 (const VkClearValue *) pDepthStencil,
1415 rangeCount, pRanges, false);
1416
1417 radv_meta_restore(&saved_state, cmd_buffer);
1418 }
1419
1420 void radv_CmdClearAttachments(
1421 VkCommandBuffer commandBuffer,
1422 uint32_t attachmentCount,
1423 const VkClearAttachment* pAttachments,
1424 uint32_t rectCount,
1425 const VkClearRect* pRects)
1426 {
1427 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1428 struct radv_meta_saved_state saved_state;
1429 enum radv_cmd_flush_bits pre_flush = 0;
1430 enum radv_cmd_flush_bits post_flush = 0;
1431
1432 if (!cmd_buffer->state.subpass)
1433 return;
1434
1435 radv_meta_save(&saved_state, cmd_buffer,
1436 RADV_META_SAVE_GRAPHICS_PIPELINE |
1437 RADV_META_SAVE_CONSTANTS);
1438
1439 /* FINISHME: We can do better than this dumb loop. It thrashes too much
1440 * state.
1441 */
1442 for (uint32_t a = 0; a < attachmentCount; ++a) {
1443 for (uint32_t r = 0; r < rectCount; ++r) {
1444 emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush,
1445 cmd_buffer->state.subpass->view_mask);
1446 }
1447 }
1448
1449 radv_meta_restore(&saved_state, cmd_buffer);
1450 cmd_buffer->state.flush_bits |= post_flush;
1451 }