2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "radv_debug.h"
25 #include "radv_meta.h"
26 #include "radv_private.h"
27 #include "nir/nir_builder.h"
29 #include "util/format_rgb9e5.h"
30 #include "vk_format.h"
34 DEPTH_CLEAR_FAST_EXPCLEAR
,
35 DEPTH_CLEAR_FAST_NO_EXPCLEAR
39 build_color_shaders(struct nir_shader
**out_vs
,
40 struct nir_shader
**out_fs
,
46 nir_builder_init_simple_shader(&vs_b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
47 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
49 vs_b
.shader
->info
.name
= ralloc_strdup(vs_b
.shader
, "meta_clear_color_vs");
50 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "meta_clear_color_fs");
52 const struct glsl_type
*position_type
= glsl_vec4_type();
53 const struct glsl_type
*color_type
= glsl_vec4_type();
55 nir_variable
*vs_out_pos
=
56 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, position_type
,
58 vs_out_pos
->data
.location
= VARYING_SLOT_POS
;
60 nir_intrinsic_instr
*in_color_load
= nir_intrinsic_instr_create(fs_b
.shader
, nir_intrinsic_load_push_constant
);
61 nir_intrinsic_set_base(in_color_load
, 0);
62 nir_intrinsic_set_range(in_color_load
, 16);
63 in_color_load
->src
[0] = nir_src_for_ssa(nir_imm_int(&fs_b
, 0));
64 in_color_load
->num_components
= 4;
65 nir_ssa_dest_init(&in_color_load
->instr
, &in_color_load
->dest
, 4, 32, "clear color");
66 nir_builder_instr_insert(&fs_b
, &in_color_load
->instr
);
68 nir_variable
*fs_out_color
=
69 nir_variable_create(fs_b
.shader
, nir_var_shader_out
, color_type
,
71 fs_out_color
->data
.location
= FRAG_RESULT_DATA0
+ frag_output
;
73 nir_store_var(&fs_b
, fs_out_color
, &in_color_load
->dest
.ssa
, 0xf);
75 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices(&vs_b
);
76 nir_store_var(&vs_b
, vs_out_pos
, outvec
, 0xf);
78 const struct glsl_type
*layer_type
= glsl_int_type();
79 nir_variable
*vs_out_layer
=
80 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, layer_type
,
82 vs_out_layer
->data
.location
= VARYING_SLOT_LAYER
;
83 vs_out_layer
->data
.interpolation
= INTERP_MODE_FLAT
;
84 nir_ssa_def
*inst_id
= nir_load_instance_id(&vs_b
);
85 nir_ssa_def
*base_instance
= nir_load_base_instance(&vs_b
);
87 nir_ssa_def
*layer_id
= nir_iadd(&vs_b
, inst_id
, base_instance
);
88 nir_store_var(&vs_b
, vs_out_layer
, layer_id
, 0x1);
90 *out_vs
= vs_b
.shader
;
91 *out_fs
= fs_b
.shader
;
95 create_pipeline(struct radv_device
*device
,
96 struct radv_render_pass
*render_pass
,
98 struct nir_shader
*vs_nir
,
99 struct nir_shader
*fs_nir
,
100 const VkPipelineVertexInputStateCreateInfo
*vi_state
,
101 const VkPipelineDepthStencilStateCreateInfo
*ds_state
,
102 const VkPipelineColorBlendStateCreateInfo
*cb_state
,
103 const VkPipelineLayout layout
,
104 const struct radv_graphics_pipeline_create_info
*extra
,
105 const VkAllocationCallbacks
*alloc
,
106 VkPipeline
*pipeline
)
108 VkDevice device_h
= radv_device_to_handle(device
);
111 struct radv_shader_module vs_m
= { .nir
= vs_nir
};
112 struct radv_shader_module fs_m
= { .nir
= fs_nir
};
114 result
= radv_graphics_pipeline_create(device_h
,
115 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
116 &(VkGraphicsPipelineCreateInfo
) {
117 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
118 .stageCount
= fs_nir
? 2 : 1,
119 .pStages
= (VkPipelineShaderStageCreateInfo
[]) {
121 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
122 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
123 .module
= radv_shader_module_to_handle(&vs_m
),
127 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
128 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
129 .module
= radv_shader_module_to_handle(&fs_m
),
133 .pVertexInputState
= vi_state
,
134 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
135 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
136 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
137 .primitiveRestartEnable
= false,
139 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
140 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
144 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
145 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
146 .rasterizerDiscardEnable
= false,
147 .polygonMode
= VK_POLYGON_MODE_FILL
,
148 .cullMode
= VK_CULL_MODE_NONE
,
149 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
,
150 .depthBiasEnable
= false,
152 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
153 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
154 .rasterizationSamples
= samples
,
155 .sampleShadingEnable
= false,
157 .alphaToCoverageEnable
= false,
158 .alphaToOneEnable
= false,
160 .pDepthStencilState
= ds_state
,
161 .pColorBlendState
= cb_state
,
162 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
163 /* The meta clear pipeline declares all state as dynamic.
164 * As a consequence, vkCmdBindPipeline writes no dynamic state
165 * to the cmd buffer. Therefore, at the end of the meta clear,
166 * we need only restore dynamic state was vkCmdSet.
168 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
169 .dynamicStateCount
= 8,
170 .pDynamicStates
= (VkDynamicState
[]) {
171 /* Everything except stencil write mask */
172 VK_DYNAMIC_STATE_VIEWPORT
,
173 VK_DYNAMIC_STATE_SCISSOR
,
174 VK_DYNAMIC_STATE_LINE_WIDTH
,
175 VK_DYNAMIC_STATE_DEPTH_BIAS
,
176 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
177 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
178 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
179 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
184 .renderPass
= radv_render_pass_to_handle(render_pass
),
198 create_color_renderpass(struct radv_device
*device
,
203 mtx_lock(&device
->meta_state
.mtx
);
205 mtx_unlock (&device
->meta_state
.mtx
);
209 VkResult result
= radv_CreateRenderPass(radv_device_to_handle(device
),
210 &(VkRenderPassCreateInfo
) {
211 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
212 .attachmentCount
= 1,
213 .pAttachments
= &(VkAttachmentDescription
) {
216 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
217 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
218 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
219 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
222 .pSubpasses
= &(VkSubpassDescription
) {
223 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
224 .inputAttachmentCount
= 0,
225 .colorAttachmentCount
= 1,
226 .pColorAttachments
= &(VkAttachmentReference
) {
228 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
230 .pResolveAttachments
= NULL
,
231 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
232 .attachment
= VK_ATTACHMENT_UNUSED
,
233 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
235 .preserveAttachmentCount
= 0,
236 .pPreserveAttachments
= NULL
,
238 .dependencyCount
= 0,
239 }, &device
->meta_state
.alloc
, pass
);
240 mtx_unlock(&device
->meta_state
.mtx
);
245 create_color_pipeline(struct radv_device
*device
,
247 uint32_t frag_output
,
248 VkPipeline
*pipeline
,
251 struct nir_shader
*vs_nir
;
252 struct nir_shader
*fs_nir
;
255 mtx_lock(&device
->meta_state
.mtx
);
257 mtx_unlock(&device
->meta_state
.mtx
);
261 build_color_shaders(&vs_nir
, &fs_nir
, frag_output
);
263 const VkPipelineVertexInputStateCreateInfo vi_state
= {
264 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
265 .vertexBindingDescriptionCount
= 0,
266 .vertexAttributeDescriptionCount
= 0,
269 const VkPipelineDepthStencilStateCreateInfo ds_state
= {
270 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
271 .depthTestEnable
= false,
272 .depthWriteEnable
= false,
273 .depthBoundsTestEnable
= false,
274 .stencilTestEnable
= false,
277 VkPipelineColorBlendAttachmentState blend_attachment_state
[MAX_RTS
] = { 0 };
278 blend_attachment_state
[frag_output
] = (VkPipelineColorBlendAttachmentState
) {
279 .blendEnable
= false,
280 .colorWriteMask
= VK_COLOR_COMPONENT_A_BIT
|
281 VK_COLOR_COMPONENT_R_BIT
|
282 VK_COLOR_COMPONENT_G_BIT
|
283 VK_COLOR_COMPONENT_B_BIT
,
286 const VkPipelineColorBlendStateCreateInfo cb_state
= {
287 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
288 .logicOpEnable
= false,
289 .attachmentCount
= MAX_RTS
,
290 .pAttachments
= blend_attachment_state
294 struct radv_graphics_pipeline_create_info extra
= {
295 .use_rectlist
= true,
297 result
= create_pipeline(device
, radv_render_pass_from_handle(pass
),
298 samples
, vs_nir
, fs_nir
, &vi_state
, &ds_state
, &cb_state
,
299 device
->meta_state
.clear_color_p_layout
,
300 &extra
, &device
->meta_state
.alloc
, pipeline
);
302 mtx_unlock(&device
->meta_state
.mtx
);
307 finish_meta_clear_htile_mask_state(struct radv_device
*device
)
309 struct radv_meta_state
*state
= &device
->meta_state
;
311 radv_DestroyPipeline(radv_device_to_handle(device
),
312 state
->clear_htile_mask_pipeline
,
314 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
315 state
->clear_htile_mask_p_layout
,
317 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
318 state
->clear_htile_mask_ds_layout
,
323 radv_device_finish_meta_clear_state(struct radv_device
*device
)
325 struct radv_meta_state
*state
= &device
->meta_state
;
327 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->clear
); ++i
) {
328 for (uint32_t j
= 0; j
< ARRAY_SIZE(state
->clear
[i
].color_pipelines
); ++j
) {
329 radv_DestroyPipeline(radv_device_to_handle(device
),
330 state
->clear
[i
].color_pipelines
[j
],
332 radv_DestroyRenderPass(radv_device_to_handle(device
),
333 state
->clear
[i
].render_pass
[j
],
337 for (uint32_t j
= 0; j
< NUM_DEPTH_CLEAR_PIPELINES
; j
++) {
338 radv_DestroyPipeline(radv_device_to_handle(device
),
339 state
->clear
[i
].depth_only_pipeline
[j
],
341 radv_DestroyPipeline(radv_device_to_handle(device
),
342 state
->clear
[i
].stencil_only_pipeline
[j
],
344 radv_DestroyPipeline(radv_device_to_handle(device
),
345 state
->clear
[i
].depthstencil_pipeline
[j
],
348 radv_DestroyPipeline(radv_device_to_handle(device
),
349 state
->clear
[i
].depth_only_unrestricted_pipeline
[j
],
351 radv_DestroyPipeline(radv_device_to_handle(device
),
352 state
->clear
[i
].stencil_only_unrestricted_pipeline
[j
],
354 radv_DestroyPipeline(radv_device_to_handle(device
),
355 state
->clear
[i
].depthstencil_unrestricted_pipeline
[j
],
358 radv_DestroyRenderPass(radv_device_to_handle(device
),
359 state
->clear
[i
].depthstencil_rp
,
362 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
363 state
->clear_color_p_layout
,
365 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
366 state
->clear_depth_p_layout
,
368 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
369 state
->clear_depth_unrestricted_p_layout
,
372 finish_meta_clear_htile_mask_state(device
);
376 emit_color_clear(struct radv_cmd_buffer
*cmd_buffer
,
377 const VkClearAttachment
*clear_att
,
378 const VkClearRect
*clear_rect
,
381 struct radv_device
*device
= cmd_buffer
->device
;
382 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
383 const uint32_t subpass_att
= clear_att
->colorAttachment
;
384 const uint32_t pass_att
= subpass
->color_attachments
[subpass_att
].attachment
;
385 const struct radv_image_view
*iview
= cmd_buffer
->state
.attachments
?
386 cmd_buffer
->state
.attachments
[pass_att
].iview
: NULL
;
387 uint32_t samples
, samples_log2
;
390 VkClearColorValue clear_value
= clear_att
->clearValue
.color
;
391 VkCommandBuffer cmd_buffer_h
= radv_cmd_buffer_to_handle(cmd_buffer
);
394 /* When a framebuffer is bound to the current command buffer, get the
395 * number of samples from it. Otherwise, get the number of samples from
396 * the render pass because it's likely a secondary command buffer.
399 samples
= iview
->image
->info
.samples
;
400 format
= iview
->vk_format
;
402 samples
= cmd_buffer
->state
.pass
->attachments
[pass_att
].samples
;
403 format
= cmd_buffer
->state
.pass
->attachments
[pass_att
].format
;
406 samples_log2
= ffs(samples
) - 1;
407 fs_key
= radv_format_meta_fs_key(format
);
410 radv_finishme("color clears incomplete");
414 if (device
->meta_state
.clear
[samples_log2
].render_pass
[fs_key
] == VK_NULL_HANDLE
) {
415 VkResult ret
= create_color_renderpass(device
, radv_fs_key_format_exemplars
[fs_key
],
417 &device
->meta_state
.clear
[samples_log2
].render_pass
[fs_key
]);
418 if (ret
!= VK_SUCCESS
) {
419 cmd_buffer
->record_result
= ret
;
424 if (device
->meta_state
.clear
[samples_log2
].color_pipelines
[fs_key
] == VK_NULL_HANDLE
) {
425 VkResult ret
= create_color_pipeline(device
, samples
, 0,
426 &device
->meta_state
.clear
[samples_log2
].color_pipelines
[fs_key
],
427 device
->meta_state
.clear
[samples_log2
].render_pass
[fs_key
]);
428 if (ret
!= VK_SUCCESS
) {
429 cmd_buffer
->record_result
= ret
;
434 pipeline
= device
->meta_state
.clear
[samples_log2
].color_pipelines
[fs_key
];
436 radv_finishme("color clears incomplete");
439 assert(samples_log2
< ARRAY_SIZE(device
->meta_state
.clear
));
441 assert(clear_att
->aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
);
442 assert(clear_att
->colorAttachment
< subpass
->color_count
);
444 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
445 device
->meta_state
.clear_color_p_layout
,
446 VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 16,
449 struct radv_subpass clear_subpass
= {
451 .color_attachments
= (struct radv_subpass_attachment
[]) {
452 subpass
->color_attachments
[clear_att
->colorAttachment
]
454 .depth_stencil_attachment
= NULL
,
457 radv_cmd_buffer_set_subpass(cmd_buffer
, &clear_subpass
);
459 radv_CmdBindPipeline(cmd_buffer_h
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
462 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
463 .x
= clear_rect
->rect
.offset
.x
,
464 .y
= clear_rect
->rect
.offset
.y
,
465 .width
= clear_rect
->rect
.extent
.width
,
466 .height
= clear_rect
->rect
.extent
.height
,
471 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &clear_rect
->rect
);
475 for_each_bit(i
, view_mask
)
476 radv_CmdDraw(cmd_buffer_h
, 3, 1, 0, i
);
478 radv_CmdDraw(cmd_buffer_h
, 3, clear_rect
->layerCount
, 0, clear_rect
->baseArrayLayer
);
481 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
486 build_depthstencil_shader(struct nir_shader
**out_vs
,
487 struct nir_shader
**out_fs
,
490 nir_builder vs_b
, fs_b
;
492 nir_builder_init_simple_shader(&vs_b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
493 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
495 vs_b
.shader
->info
.name
= ralloc_strdup(vs_b
.shader
, "meta_clear_depthstencil_vs");
496 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "meta_clear_depthstencil_fs");
497 const struct glsl_type
*position_out_type
= glsl_vec4_type();
499 nir_variable
*vs_out_pos
=
500 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, position_out_type
,
502 vs_out_pos
->data
.location
= VARYING_SLOT_POS
;
506 nir_intrinsic_instr
*in_color_load
= nir_intrinsic_instr_create(fs_b
.shader
, nir_intrinsic_load_push_constant
);
507 nir_intrinsic_set_base(in_color_load
, 0);
508 nir_intrinsic_set_range(in_color_load
, 4);
509 in_color_load
->src
[0] = nir_src_for_ssa(nir_imm_int(&fs_b
, 0));
510 in_color_load
->num_components
= 1;
511 nir_ssa_dest_init(&in_color_load
->instr
, &in_color_load
->dest
, 1, 32, "depth value");
512 nir_builder_instr_insert(&fs_b
, &in_color_load
->instr
);
514 nir_variable
*fs_out_depth
=
515 nir_variable_create(fs_b
.shader
, nir_var_shader_out
,
516 glsl_int_type(), "f_depth");
517 fs_out_depth
->data
.location
= FRAG_RESULT_DEPTH
;
518 nir_store_var(&fs_b
, fs_out_depth
, &in_color_load
->dest
.ssa
, 0x1);
520 z
= nir_imm_float(&vs_b
, 0.0);
522 nir_intrinsic_instr
*in_color_load
= nir_intrinsic_instr_create(vs_b
.shader
, nir_intrinsic_load_push_constant
);
523 nir_intrinsic_set_base(in_color_load
, 0);
524 nir_intrinsic_set_range(in_color_load
, 4);
525 in_color_load
->src
[0] = nir_src_for_ssa(nir_imm_int(&vs_b
, 0));
526 in_color_load
->num_components
= 1;
527 nir_ssa_dest_init(&in_color_load
->instr
, &in_color_load
->dest
, 1, 32, "depth value");
528 nir_builder_instr_insert(&vs_b
, &in_color_load
->instr
);
530 z
= &in_color_load
->dest
.ssa
;
533 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices_comp2(&vs_b
, z
);
534 nir_store_var(&vs_b
, vs_out_pos
, outvec
, 0xf);
536 const struct glsl_type
*layer_type
= glsl_int_type();
537 nir_variable
*vs_out_layer
=
538 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, layer_type
,
540 vs_out_layer
->data
.location
= VARYING_SLOT_LAYER
;
541 vs_out_layer
->data
.interpolation
= INTERP_MODE_FLAT
;
542 nir_ssa_def
*inst_id
= nir_load_instance_id(&vs_b
);
543 nir_ssa_def
*base_instance
= nir_load_base_instance(&vs_b
);
545 nir_ssa_def
*layer_id
= nir_iadd(&vs_b
, inst_id
, base_instance
);
546 nir_store_var(&vs_b
, vs_out_layer
, layer_id
, 0x1);
548 *out_vs
= vs_b
.shader
;
549 *out_fs
= fs_b
.shader
;
553 create_depthstencil_renderpass(struct radv_device
*device
,
555 VkRenderPass
*render_pass
)
557 mtx_lock(&device
->meta_state
.mtx
);
559 mtx_unlock(&device
->meta_state
.mtx
);
563 VkResult result
= radv_CreateRenderPass(radv_device_to_handle(device
),
564 &(VkRenderPassCreateInfo
) {
565 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
566 .attachmentCount
= 1,
567 .pAttachments
= &(VkAttachmentDescription
) {
568 .format
= VK_FORMAT_D32_SFLOAT_S8_UINT
,
570 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
571 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
572 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
573 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
576 .pSubpasses
= &(VkSubpassDescription
) {
577 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
578 .inputAttachmentCount
= 0,
579 .colorAttachmentCount
= 0,
580 .pColorAttachments
= NULL
,
581 .pResolveAttachments
= NULL
,
582 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
584 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
586 .preserveAttachmentCount
= 0,
587 .pPreserveAttachments
= NULL
,
589 .dependencyCount
= 0,
590 }, &device
->meta_state
.alloc
, render_pass
);
591 mtx_unlock(&device
->meta_state
.mtx
);
596 create_depthstencil_pipeline(struct radv_device
*device
,
597 VkImageAspectFlags aspects
,
601 VkPipeline
*pipeline
,
602 VkRenderPass render_pass
)
604 struct nir_shader
*vs_nir
, *fs_nir
;
607 mtx_lock(&device
->meta_state
.mtx
);
609 mtx_unlock(&device
->meta_state
.mtx
);
613 build_depthstencil_shader(&vs_nir
, &fs_nir
, unrestricted
);
615 const VkPipelineVertexInputStateCreateInfo vi_state
= {
616 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
617 .vertexBindingDescriptionCount
= 0,
618 .vertexAttributeDescriptionCount
= 0,
621 const VkPipelineDepthStencilStateCreateInfo ds_state
= {
622 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
623 .depthTestEnable
= (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
),
624 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
625 .depthWriteEnable
= (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
),
626 .depthBoundsTestEnable
= false,
627 .stencilTestEnable
= (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
),
629 .passOp
= VK_STENCIL_OP_REPLACE
,
630 .compareOp
= VK_COMPARE_OP_ALWAYS
,
631 .writeMask
= UINT32_MAX
,
632 .reference
= 0, /* dynamic */
634 .back
= { 0 /* dont care */ },
637 const VkPipelineColorBlendStateCreateInfo cb_state
= {
638 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
639 .logicOpEnable
= false,
640 .attachmentCount
= 0,
641 .pAttachments
= NULL
,
644 struct radv_graphics_pipeline_create_info extra
= {
645 .use_rectlist
= true,
648 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
649 extra
.db_depth_clear
= index
== DEPTH_CLEAR_SLOW
? false : true;
650 extra
.db_depth_disable_expclear
= index
== DEPTH_CLEAR_FAST_NO_EXPCLEAR
? true : false;
652 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
653 extra
.db_stencil_clear
= index
== DEPTH_CLEAR_SLOW
? false : true;
654 extra
.db_stencil_disable_expclear
= index
== DEPTH_CLEAR_FAST_NO_EXPCLEAR
? true : false;
656 result
= create_pipeline(device
, radv_render_pass_from_handle(render_pass
),
657 samples
, vs_nir
, fs_nir
, &vi_state
, &ds_state
, &cb_state
,
658 device
->meta_state
.clear_depth_p_layout
,
659 &extra
, &device
->meta_state
.alloc
, pipeline
);
661 mtx_unlock(&device
->meta_state
.mtx
);
665 static bool depth_view_can_fast_clear(struct radv_cmd_buffer
*cmd_buffer
,
666 const struct radv_image_view
*iview
,
667 VkImageAspectFlags aspects
,
668 VkImageLayout layout
,
670 const VkClearRect
*clear_rect
,
671 VkClearDepthStencilValue clear_value
)
676 uint32_t queue_mask
= radv_image_queue_family_mask(iview
->image
,
677 cmd_buffer
->queue_family_index
,
678 cmd_buffer
->queue_family_index
);
679 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
680 clear_rect
->rect
.extent
.width
!= iview
->extent
.width
||
681 clear_rect
->rect
.extent
.height
!= iview
->extent
.height
)
683 if (radv_image_is_tc_compat_htile(iview
->image
) &&
684 (((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) && clear_value
.depth
!= 0.0 &&
685 clear_value
.depth
!= 1.0) ||
686 ((aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) && clear_value
.stencil
!= 0)))
688 if (radv_image_has_htile(iview
->image
) &&
689 iview
->base_mip
== 0 &&
690 iview
->base_layer
== 0 &&
691 iview
->layer_count
== iview
->image
->info
.array_size
&&
692 radv_layout_is_htile_compressed(iview
->image
, layout
, in_render_loop
, queue_mask
) &&
693 radv_image_extent_compare(iview
->image
, &iview
->extent
))
699 pick_depthstencil_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
700 struct radv_meta_state
*meta_state
,
701 const struct radv_image_view
*iview
,
703 VkImageAspectFlags aspects
,
704 VkImageLayout layout
,
706 const VkClearRect
*clear_rect
,
707 VkClearDepthStencilValue clear_value
)
709 bool fast
= depth_view_can_fast_clear(cmd_buffer
, iview
, aspects
, layout
,
710 in_render_loop
, clear_rect
, clear_value
);
711 bool unrestricted
= cmd_buffer
->device
->enabled_extensions
.EXT_depth_range_unrestricted
;
712 int index
= DEPTH_CLEAR_SLOW
;
713 VkPipeline
*pipeline
;
716 /* we don't know the previous clear values, so we always have
717 * the NO_EXPCLEAR path */
718 index
= DEPTH_CLEAR_FAST_NO_EXPCLEAR
;
722 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
723 pipeline
= unrestricted
?
724 &meta_state
->clear
[samples_log2
].depthstencil_unrestricted_pipeline
[index
] :
725 &meta_state
->clear
[samples_log2
].depthstencil_pipeline
[index
];
727 case VK_IMAGE_ASPECT_DEPTH_BIT
:
728 pipeline
= unrestricted
?
729 &meta_state
->clear
[samples_log2
].depth_only_unrestricted_pipeline
[index
] :
730 &meta_state
->clear
[samples_log2
].depth_only_pipeline
[index
];
732 case VK_IMAGE_ASPECT_STENCIL_BIT
:
733 pipeline
= unrestricted
?
734 &meta_state
->clear
[samples_log2
].stencil_only_unrestricted_pipeline
[index
] :
735 &meta_state
->clear
[samples_log2
].stencil_only_pipeline
[index
];
738 unreachable("expected depth or stencil aspect");
741 if (cmd_buffer
->device
->meta_state
.clear
[samples_log2
].depthstencil_rp
== VK_NULL_HANDLE
) {
742 VkResult ret
= create_depthstencil_renderpass(cmd_buffer
->device
, 1u << samples_log2
,
743 &cmd_buffer
->device
->meta_state
.clear
[samples_log2
].depthstencil_rp
);
744 if (ret
!= VK_SUCCESS
) {
745 cmd_buffer
->record_result
= ret
;
746 return VK_NULL_HANDLE
;
750 if (*pipeline
== VK_NULL_HANDLE
) {
751 VkResult ret
= create_depthstencil_pipeline(cmd_buffer
->device
, aspects
, 1u << samples_log2
, index
, unrestricted
,
752 pipeline
, cmd_buffer
->device
->meta_state
.clear
[samples_log2
].depthstencil_rp
);
753 if (ret
!= VK_SUCCESS
) {
754 cmd_buffer
->record_result
= ret
;
755 return VK_NULL_HANDLE
;
762 emit_depthstencil_clear(struct radv_cmd_buffer
*cmd_buffer
,
763 const VkClearAttachment
*clear_att
,
764 const VkClearRect
*clear_rect
,
765 struct radv_subpass_attachment
*ds_att
,
768 struct radv_device
*device
= cmd_buffer
->device
;
769 struct radv_meta_state
*meta_state
= &device
->meta_state
;
770 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
771 const uint32_t pass_att
= ds_att
->attachment
;
772 VkClearDepthStencilValue clear_value
= clear_att
->clearValue
.depthStencil
;
773 VkImageAspectFlags aspects
= clear_att
->aspectMask
;
774 const struct radv_image_view
*iview
= cmd_buffer
->state
.attachments
?
775 cmd_buffer
->state
.attachments
[pass_att
].iview
: NULL
;
776 uint32_t samples
, samples_log2
;
777 VkCommandBuffer cmd_buffer_h
= radv_cmd_buffer_to_handle(cmd_buffer
);
779 /* When a framebuffer is bound to the current command buffer, get the
780 * number of samples from it. Otherwise, get the number of samples from
781 * the render pass because it's likely a secondary command buffer.
784 samples
= iview
->image
->info
.samples
;
786 samples
= cmd_buffer
->state
.pass
->attachments
[pass_att
].samples
;
789 samples_log2
= ffs(samples
) - 1;
791 assert(pass_att
!= VK_ATTACHMENT_UNUSED
);
793 if (!(aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
794 clear_value
.depth
= 1.0f
;
796 if (cmd_buffer
->device
->enabled_extensions
.EXT_depth_range_unrestricted
) {
797 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
798 device
->meta_state
.clear_depth_unrestricted_p_layout
,
799 VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 4,
802 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
803 device
->meta_state
.clear_depth_p_layout
,
804 VK_SHADER_STAGE_VERTEX_BIT
, 0, 4,
808 uint32_t prev_reference
= cmd_buffer
->state
.dynamic
.stencil_reference
.front
;
809 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
810 radv_CmdSetStencilReference(cmd_buffer_h
, VK_STENCIL_FACE_FRONT_BIT
,
811 clear_value
.stencil
);
814 VkPipeline pipeline
= pick_depthstencil_pipeline(cmd_buffer
,
820 ds_att
->in_render_loop
,
826 struct radv_subpass clear_subpass
= {
828 .color_attachments
= NULL
,
829 .depth_stencil_attachment
= ds_att
,
832 radv_cmd_buffer_set_subpass(cmd_buffer
, &clear_subpass
);
834 radv_CmdBindPipeline(cmd_buffer_h
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
837 if (depth_view_can_fast_clear(cmd_buffer
, iview
, aspects
,
838 ds_att
->layout
, ds_att
->in_render_loop
,
839 clear_rect
, clear_value
))
840 radv_update_ds_clear_metadata(cmd_buffer
, iview
,
841 clear_value
, aspects
);
843 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
844 .x
= clear_rect
->rect
.offset
.x
,
845 .y
= clear_rect
->rect
.offset
.y
,
846 .width
= clear_rect
->rect
.extent
.width
,
847 .height
= clear_rect
->rect
.extent
.height
,
852 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &clear_rect
->rect
);
856 for_each_bit(i
, view_mask
)
857 radv_CmdDraw(cmd_buffer_h
, 3, 1, 0, i
);
859 radv_CmdDraw(cmd_buffer_h
, 3, clear_rect
->layerCount
, 0, clear_rect
->baseArrayLayer
);
862 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
863 radv_CmdSetStencilReference(cmd_buffer_h
, VK_STENCIL_FACE_FRONT_BIT
,
867 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
871 clear_htile_mask(struct radv_cmd_buffer
*cmd_buffer
,
872 struct radeon_winsys_bo
*bo
, uint64_t offset
, uint64_t size
,
873 uint32_t htile_value
, uint32_t htile_mask
)
875 struct radv_device
*device
= cmd_buffer
->device
;
876 struct radv_meta_state
*state
= &device
->meta_state
;
877 uint64_t block_count
= round_up_u64(size
, 1024);
878 struct radv_meta_saved_state saved_state
;
880 radv_meta_save(&saved_state
, cmd_buffer
,
881 RADV_META_SAVE_COMPUTE_PIPELINE
|
882 RADV_META_SAVE_CONSTANTS
|
883 RADV_META_SAVE_DESCRIPTORS
);
885 struct radv_buffer dst_buffer
= {
891 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
892 VK_PIPELINE_BIND_POINT_COMPUTE
,
893 state
->clear_htile_mask_pipeline
);
895 radv_meta_push_descriptor_set(cmd_buffer
, VK_PIPELINE_BIND_POINT_COMPUTE
,
896 state
->clear_htile_mask_p_layout
,
898 1, /* descriptorWriteCount */
899 (VkWriteDescriptorSet
[]) {
901 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
903 .dstArrayElement
= 0,
904 .descriptorCount
= 1,
905 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
,
906 .pBufferInfo
= &(VkDescriptorBufferInfo
) {
907 .buffer
= radv_buffer_to_handle(&dst_buffer
),
914 const unsigned constants
[2] = {
915 htile_value
& htile_mask
,
919 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
920 state
->clear_htile_mask_p_layout
,
921 VK_SHADER_STAGE_COMPUTE_BIT
, 0, 8,
924 radv_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer
), block_count
, 1, 1);
926 radv_meta_restore(&saved_state
, cmd_buffer
);
928 return RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
929 RADV_CMD_FLAG_INV_VCACHE
|
934 radv_get_htile_fast_clear_value(const struct radv_image
*image
,
935 VkClearDepthStencilValue value
)
937 uint32_t clear_value
;
939 if (!image
->planes
[0].surface
.has_stencil
) {
940 clear_value
= value
.depth
? 0xfffffff0 : 0;
942 clear_value
= value
.depth
? 0xfffc0000 : 0;
949 radv_get_htile_mask(const struct radv_image
*image
, VkImageAspectFlags aspects
)
953 if (!image
->planes
[0].surface
.has_stencil
) {
954 /* All the HTILE buffer is used when there is no stencil. */
957 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
959 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
967 radv_is_fast_clear_depth_allowed(VkClearDepthStencilValue value
)
969 return value
.depth
== 1.0f
|| value
.depth
== 0.0f
;
973 radv_is_fast_clear_stencil_allowed(VkClearDepthStencilValue value
)
975 return value
.stencil
== 0;
979 * Determine if the given image can be fast cleared.
982 radv_image_can_fast_clear(struct radv_device
*device
, struct radv_image
*image
)
984 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
)
987 if (vk_format_is_color(image
->vk_format
)) {
988 if (!radv_image_has_cmask(image
) && !radv_image_has_dcc(image
))
991 /* RB+ doesn't work with CMASK fast clear on Stoney. */
992 if (!radv_image_has_dcc(image
) &&
993 device
->physical_device
->rad_info
.family
== CHIP_STONEY
)
996 if (!radv_image_has_htile(image
))
1000 /* Do not fast clears 3D images. */
1001 if (image
->type
== VK_IMAGE_TYPE_3D
)
1008 * Determine if the given image view can be fast cleared.
1011 radv_image_view_can_fast_clear(struct radv_device
*device
,
1012 const struct radv_image_view
*iview
)
1014 struct radv_image
*image
;
1018 image
= iview
->image
;
1020 /* Only fast clear if the image itself can be fast cleared. */
1021 if (!radv_image_can_fast_clear(device
, image
))
1024 /* Only fast clear if all layers are bound. */
1025 if (iview
->base_layer
> 0 ||
1026 iview
->layer_count
!= image
->info
.array_size
)
1029 /* Only fast clear if the view covers the whole image. */
1030 if (!radv_image_extent_compare(image
, &iview
->extent
))
1037 radv_can_fast_clear_depth(struct radv_cmd_buffer
*cmd_buffer
,
1038 const struct radv_image_view
*iview
,
1039 VkImageLayout image_layout
,
1040 bool in_render_loop
,
1041 VkImageAspectFlags aspects
,
1042 const VkClearRect
*clear_rect
,
1043 const VkClearDepthStencilValue clear_value
,
1046 if (!radv_image_view_can_fast_clear(cmd_buffer
->device
, iview
))
1049 if (!radv_layout_is_htile_compressed(iview
->image
, image_layout
, in_render_loop
,
1050 radv_image_queue_family_mask(iview
->image
,
1051 cmd_buffer
->queue_family_index
,
1052 cmd_buffer
->queue_family_index
)))
1055 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
1056 clear_rect
->rect
.extent
.width
!= iview
->image
->info
.width
||
1057 clear_rect
->rect
.extent
.height
!= iview
->image
->info
.height
)
1060 if (view_mask
&& (iview
->image
->info
.array_size
>= 32 ||
1061 (1u << iview
->image
->info
.array_size
) - 1u != view_mask
))
1063 if (!view_mask
&& clear_rect
->baseArrayLayer
!= 0)
1065 if (!view_mask
&& clear_rect
->layerCount
!= iview
->image
->info
.array_size
)
1068 if (((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1069 !radv_is_fast_clear_depth_allowed(clear_value
)) ||
1070 ((aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
1071 !radv_is_fast_clear_stencil_allowed(clear_value
)))
1078 radv_fast_clear_depth(struct radv_cmd_buffer
*cmd_buffer
,
1079 const struct radv_image_view
*iview
,
1080 const VkClearAttachment
*clear_att
,
1081 enum radv_cmd_flush_bits
*pre_flush
,
1082 enum radv_cmd_flush_bits
*post_flush
)
1084 VkClearDepthStencilValue clear_value
= clear_att
->clearValue
.depthStencil
;
1085 VkImageAspectFlags aspects
= clear_att
->aspectMask
;
1086 uint32_t clear_word
, flush_bits
;
1088 clear_word
= radv_get_htile_fast_clear_value(iview
->image
, clear_value
);
1091 cmd_buffer
->state
.flush_bits
|= (RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1092 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
) & ~ *pre_flush
;
1093 *pre_flush
|= cmd_buffer
->state
.flush_bits
;
1096 struct VkImageSubresourceRange range
= {
1097 .aspectMask
= aspects
,
1099 .levelCount
= VK_REMAINING_MIP_LEVELS
,
1100 .baseArrayLayer
= 0,
1101 .layerCount
= VK_REMAINING_ARRAY_LAYERS
,
1104 flush_bits
= radv_clear_htile(cmd_buffer
, iview
->image
, &range
, clear_word
);
1106 if (iview
->image
->planes
[0].surface
.has_stencil
&&
1107 !(aspects
== (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
))) {
1108 /* Synchronize after performing a depth-only or a stencil-only
1109 * fast clear because the driver uses an optimized path which
1110 * performs a read-modify-write operation, and the two separate
1111 * aspects might use the same HTILE memory.
1113 cmd_buffer
->state
.flush_bits
|= flush_bits
;
1116 radv_update_ds_clear_metadata(cmd_buffer
, iview
, clear_value
, aspects
);
1118 *post_flush
|= flush_bits
;
1123 build_clear_htile_mask_shader()
1127 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_COMPUTE
, NULL
);
1128 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "meta_clear_htile_mask");
1129 b
.shader
->info
.cs
.local_size
[0] = 64;
1130 b
.shader
->info
.cs
.local_size
[1] = 1;
1131 b
.shader
->info
.cs
.local_size
[2] = 1;
1133 nir_ssa_def
*invoc_id
= nir_load_local_invocation_id(&b
);
1134 nir_ssa_def
*wg_id
= nir_load_work_group_id(&b
);
1135 nir_ssa_def
*block_size
= nir_imm_ivec4(&b
,
1136 b
.shader
->info
.cs
.local_size
[0],
1137 b
.shader
->info
.cs
.local_size
[1],
1138 b
.shader
->info
.cs
.local_size
[2], 0);
1140 nir_ssa_def
*global_id
= nir_iadd(&b
, nir_imul(&b
, wg_id
, block_size
), invoc_id
);
1142 nir_ssa_def
*offset
= nir_imul(&b
, global_id
, nir_imm_int(&b
, 16));
1143 offset
= nir_channel(&b
, offset
, 0);
1145 nir_intrinsic_instr
*buf
=
1146 nir_intrinsic_instr_create(b
.shader
,
1147 nir_intrinsic_vulkan_resource_index
);
1149 buf
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
1150 buf
->num_components
= 1;
1151 nir_intrinsic_set_desc_set(buf
, 0);
1152 nir_intrinsic_set_binding(buf
, 0);
1153 nir_ssa_dest_init(&buf
->instr
, &buf
->dest
, buf
->num_components
, 32, NULL
);
1154 nir_builder_instr_insert(&b
, &buf
->instr
);
1156 nir_intrinsic_instr
*constants
=
1157 nir_intrinsic_instr_create(b
.shader
,
1158 nir_intrinsic_load_push_constant
);
1159 nir_intrinsic_set_base(constants
, 0);
1160 nir_intrinsic_set_range(constants
, 8);
1161 constants
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
1162 constants
->num_components
= 2;
1163 nir_ssa_dest_init(&constants
->instr
, &constants
->dest
, 2, 32, "constants");
1164 nir_builder_instr_insert(&b
, &constants
->instr
);
1166 nir_intrinsic_instr
*load
=
1167 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ssbo
);
1168 load
->src
[0] = nir_src_for_ssa(&buf
->dest
.ssa
);
1169 load
->src
[1] = nir_src_for_ssa(offset
);
1170 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
1171 load
->num_components
= 4;
1172 nir_intrinsic_set_align(load
, 16, 0);
1173 nir_builder_instr_insert(&b
, &load
->instr
);
1175 /* data = (data & ~htile_mask) | (htile_value & htile_mask) */
1177 nir_iand(&b
, &load
->dest
.ssa
,
1178 nir_channel(&b
, &constants
->dest
.ssa
, 1));
1179 data
= nir_ior(&b
, data
, nir_channel(&b
, &constants
->dest
.ssa
, 0));
1181 nir_intrinsic_instr
*store
=
1182 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
1183 store
->src
[0] = nir_src_for_ssa(data
);
1184 store
->src
[1] = nir_src_for_ssa(&buf
->dest
.ssa
);
1185 store
->src
[2] = nir_src_for_ssa(offset
);
1186 nir_intrinsic_set_write_mask(store
, 0xf);
1187 nir_intrinsic_set_access(store
, ACCESS_NON_READABLE
);
1188 nir_intrinsic_set_align(store
, 16, 0);
1189 store
->num_components
= 4;
1190 nir_builder_instr_insert(&b
, &store
->instr
);
1196 init_meta_clear_htile_mask_state(struct radv_device
*device
)
1198 struct radv_meta_state
*state
= &device
->meta_state
;
1199 struct radv_shader_module cs
= { .nir
= NULL
};
1202 cs
.nir
= build_clear_htile_mask_shader();
1204 VkDescriptorSetLayoutCreateInfo ds_layout_info
= {
1205 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
1206 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
1208 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
1211 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
,
1212 .descriptorCount
= 1,
1213 .stageFlags
= VK_SHADER_STAGE_COMPUTE_BIT
,
1214 .pImmutableSamplers
= NULL
1219 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
1220 &ds_layout_info
, &state
->alloc
,
1221 &state
->clear_htile_mask_ds_layout
);
1222 if (result
!= VK_SUCCESS
)
1225 VkPipelineLayoutCreateInfo p_layout_info
= {
1226 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1227 .setLayoutCount
= 1,
1228 .pSetLayouts
= &state
->clear_htile_mask_ds_layout
,
1229 .pushConstantRangeCount
= 1,
1230 .pPushConstantRanges
= &(VkPushConstantRange
){
1231 VK_SHADER_STAGE_COMPUTE_BIT
, 0, 8,
1235 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1236 &p_layout_info
, &state
->alloc
,
1237 &state
->clear_htile_mask_p_layout
);
1238 if (result
!= VK_SUCCESS
)
1241 VkPipelineShaderStageCreateInfo shader_stage
= {
1242 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1243 .stage
= VK_SHADER_STAGE_COMPUTE_BIT
,
1244 .module
= radv_shader_module_to_handle(&cs
),
1246 .pSpecializationInfo
= NULL
,
1249 VkComputePipelineCreateInfo pipeline_info
= {
1250 .sType
= VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
,
1251 .stage
= shader_stage
,
1253 .layout
= state
->clear_htile_mask_p_layout
,
1256 result
= radv_CreateComputePipelines(radv_device_to_handle(device
),
1257 radv_pipeline_cache_to_handle(&state
->cache
),
1258 1, &pipeline_info
, NULL
,
1259 &state
->clear_htile_mask_pipeline
);
1261 ralloc_free(cs
.nir
);
1264 ralloc_free(cs
.nir
);
1269 radv_device_init_meta_clear_state(struct radv_device
*device
, bool on_demand
)
1272 struct radv_meta_state
*state
= &device
->meta_state
;
1274 VkPipelineLayoutCreateInfo pl_color_create_info
= {
1275 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1276 .setLayoutCount
= 0,
1277 .pushConstantRangeCount
= 1,
1278 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 16},
1281 res
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1282 &pl_color_create_info
,
1283 &device
->meta_state
.alloc
,
1284 &device
->meta_state
.clear_color_p_layout
);
1285 if (res
!= VK_SUCCESS
)
1288 VkPipelineLayoutCreateInfo pl_depth_create_info
= {
1289 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1290 .setLayoutCount
= 0,
1291 .pushConstantRangeCount
= 1,
1292 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_VERTEX_BIT
, 0, 4},
1295 res
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1296 &pl_depth_create_info
,
1297 &device
->meta_state
.alloc
,
1298 &device
->meta_state
.clear_depth_p_layout
);
1299 if (res
!= VK_SUCCESS
)
1302 VkPipelineLayoutCreateInfo pl_depth_unrestricted_create_info
= {
1303 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1304 .setLayoutCount
= 0,
1305 .pushConstantRangeCount
= 1,
1306 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 4},
1309 res
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1310 &pl_depth_unrestricted_create_info
,
1311 &device
->meta_state
.alloc
,
1312 &device
->meta_state
.clear_depth_unrestricted_p_layout
);
1313 if (res
!= VK_SUCCESS
)
1316 res
= init_meta_clear_htile_mask_state(device
);
1317 if (res
!= VK_SUCCESS
)
1323 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->clear
); ++i
) {
1324 uint32_t samples
= 1 << i
;
1325 for (uint32_t j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
1326 VkFormat format
= radv_fs_key_format_exemplars
[j
];
1327 unsigned fs_key
= radv_format_meta_fs_key(format
);
1328 assert(!state
->clear
[i
].color_pipelines
[fs_key
]);
1330 res
= create_color_renderpass(device
, format
, samples
,
1331 &state
->clear
[i
].render_pass
[fs_key
]);
1332 if (res
!= VK_SUCCESS
)
1335 res
= create_color_pipeline(device
, samples
, 0, &state
->clear
[i
].color_pipelines
[fs_key
],
1336 state
->clear
[i
].render_pass
[fs_key
]);
1337 if (res
!= VK_SUCCESS
)
1342 res
= create_depthstencil_renderpass(device
,
1344 &state
->clear
[i
].depthstencil_rp
);
1345 if (res
!= VK_SUCCESS
)
1348 for (uint32_t j
= 0; j
< NUM_DEPTH_CLEAR_PIPELINES
; j
++) {
1349 res
= create_depthstencil_pipeline(device
,
1350 VK_IMAGE_ASPECT_DEPTH_BIT
,
1354 &state
->clear
[i
].depth_only_pipeline
[j
],
1355 state
->clear
[i
].depthstencil_rp
);
1356 if (res
!= VK_SUCCESS
)
1359 res
= create_depthstencil_pipeline(device
,
1360 VK_IMAGE_ASPECT_STENCIL_BIT
,
1364 &state
->clear
[i
].stencil_only_pipeline
[j
],
1365 state
->clear
[i
].depthstencil_rp
);
1366 if (res
!= VK_SUCCESS
)
1369 res
= create_depthstencil_pipeline(device
,
1370 VK_IMAGE_ASPECT_DEPTH_BIT
|
1371 VK_IMAGE_ASPECT_STENCIL_BIT
,
1375 &state
->clear
[i
].depthstencil_pipeline
[j
],
1376 state
->clear
[i
].depthstencil_rp
);
1377 if (res
!= VK_SUCCESS
)
1380 res
= create_depthstencil_pipeline(device
,
1381 VK_IMAGE_ASPECT_DEPTH_BIT
,
1385 &state
->clear
[i
].depth_only_unrestricted_pipeline
[j
],
1386 state
->clear
[i
].depthstencil_rp
);
1387 if (res
!= VK_SUCCESS
)
1390 res
= create_depthstencil_pipeline(device
,
1391 VK_IMAGE_ASPECT_STENCIL_BIT
,
1395 &state
->clear
[i
].stencil_only_unrestricted_pipeline
[j
],
1396 state
->clear
[i
].depthstencil_rp
);
1397 if (res
!= VK_SUCCESS
)
1400 res
= create_depthstencil_pipeline(device
,
1401 VK_IMAGE_ASPECT_DEPTH_BIT
|
1402 VK_IMAGE_ASPECT_STENCIL_BIT
,
1406 &state
->clear
[i
].depthstencil_unrestricted_pipeline
[j
],
1407 state
->clear
[i
].depthstencil_rp
);
1408 if (res
!= VK_SUCCESS
)
1415 radv_device_finish_meta_clear_state(device
);
1420 radv_get_cmask_fast_clear_value(const struct radv_image
*image
)
1422 uint32_t value
= 0; /* Default value when no DCC. */
1424 /* The fast-clear value is different for images that have both DCC and
1427 if (radv_image_has_dcc(image
)) {
1428 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
1429 return image
->info
.samples
> 1 ? 0xcccccccc : 0xffffffff;
1436 radv_clear_cmask(struct radv_cmd_buffer
*cmd_buffer
,
1437 struct radv_image
*image
,
1438 const VkImageSubresourceRange
*range
, uint32_t value
)
1440 uint64_t offset
= image
->offset
+ image
->cmask_offset
;
1443 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1444 /* TODO: clear layers. */
1445 size
= image
->planes
[0].surface
.cmask_size
;
1447 unsigned cmask_slice_size
=
1448 image
->planes
[0].surface
.cmask_slice_size
;
1450 offset
+= cmask_slice_size
* range
->baseArrayLayer
;
1451 size
= cmask_slice_size
* radv_get_layerCount(image
, range
);
1454 return radv_fill_buffer(cmd_buffer
, image
->bo
, offset
, size
, value
);
1459 radv_clear_fmask(struct radv_cmd_buffer
*cmd_buffer
,
1460 struct radv_image
*image
,
1461 const VkImageSubresourceRange
*range
, uint32_t value
)
1463 uint64_t offset
= image
->offset
+ image
->fmask_offset
;
1466 /* MSAA images do not support mipmap levels. */
1467 assert(range
->baseMipLevel
== 0 &&
1468 radv_get_levelCount(image
, range
) == 1);
1470 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1471 /* TODO: clear layers. */
1472 size
= image
->planes
[0].surface
.fmask_size
;
1474 unsigned fmask_slice_size
=
1475 image
->planes
[0].surface
.u
.legacy
.fmask
.slice_size
;
1478 offset
+= fmask_slice_size
* range
->baseArrayLayer
;
1479 size
= fmask_slice_size
* radv_get_layerCount(image
, range
);
1482 return radv_fill_buffer(cmd_buffer
, image
->bo
, offset
, size
, value
);
1486 radv_clear_dcc(struct radv_cmd_buffer
*cmd_buffer
,
1487 struct radv_image
*image
,
1488 const VkImageSubresourceRange
*range
, uint32_t value
)
1490 uint32_t level_count
= radv_get_levelCount(image
, range
);
1491 uint32_t flush_bits
= 0;
1493 /* Mark the image as being compressed. */
1494 radv_update_dcc_metadata(cmd_buffer
, image
, range
, true);
1496 for (uint32_t l
= 0; l
< level_count
; l
++) {
1497 uint64_t offset
= image
->offset
+ image
->dcc_offset
;
1498 uint32_t level
= range
->baseMipLevel
+ l
;
1501 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1502 /* Mipmap levels aren't implemented. */
1504 size
= image
->planes
[0].surface
.dcc_size
;
1506 const struct legacy_surf_level
*surf_level
=
1507 &image
->planes
[0].surface
.u
.legacy
.level
[level
];
1509 /* If dcc_fast_clear_size is 0 (which might happens for
1510 * mipmaps) the fill buffer operation below is a no-op.
1511 * This can only happen during initialization as the
1512 * fast clear path fallbacks to slow clears if one
1513 * level can't be fast cleared.
1515 offset
+= surf_level
->dcc_offset
+
1516 surf_level
->dcc_slice_fast_clear_size
* range
->baseArrayLayer
;
1517 size
= surf_level
->dcc_slice_fast_clear_size
* radv_get_layerCount(image
, range
);
1520 flush_bits
|= radv_fill_buffer(cmd_buffer
, image
->bo
, offset
,
1528 radv_clear_htile(struct radv_cmd_buffer
*cmd_buffer
,
1529 const struct radv_image
*image
,
1530 const VkImageSubresourceRange
*range
,
1533 unsigned layer_count
= radv_get_layerCount(image
, range
);
1534 uint64_t size
= image
->planes
[0].surface
.htile_slice_size
* layer_count
;
1535 uint64_t offset
= image
->offset
+ image
->htile_offset
+
1536 image
->planes
[0].surface
.htile_slice_size
* range
->baseArrayLayer
;
1537 uint32_t htile_mask
, flush_bits
;
1539 htile_mask
= radv_get_htile_mask(image
, range
->aspectMask
);
1541 if (htile_mask
== UINT_MAX
) {
1542 /* Clear the whole HTILE buffer. */
1543 flush_bits
= radv_fill_buffer(cmd_buffer
, image
->bo
, offset
,
1546 /* Only clear depth or stencil bytes in the HTILE buffer. */
1547 flush_bits
= clear_htile_mask(cmd_buffer
, image
->bo
, offset
,
1548 size
, value
, htile_mask
);
1555 RADV_DCC_CLEAR_REG
= 0x20202020U
,
1556 RADV_DCC_CLEAR_MAIN_1
= 0x80808080U
,
1557 RADV_DCC_CLEAR_SECONDARY_1
= 0x40404040U
1560 static void vi_get_fast_clear_parameters(struct radv_device
*device
,
1561 VkFormat image_format
,
1562 VkFormat view_format
,
1563 const VkClearColorValue
*clear_value
,
1564 uint32_t* reset_value
,
1565 bool *can_avoid_fast_clear_elim
)
1567 bool values
[4] = {};
1569 bool main_value
= false;
1570 bool extra_value
= false;
1571 bool has_color
= false;
1572 bool has_alpha
= false;
1574 *can_avoid_fast_clear_elim
= false;
1576 *reset_value
= RADV_DCC_CLEAR_REG
;
1578 const struct vk_format_description
*desc
= vk_format_description(view_format
);
1579 if (view_format
== VK_FORMAT_B10G11R11_UFLOAT_PACK32
||
1580 view_format
== VK_FORMAT_R5G6B5_UNORM_PACK16
||
1581 view_format
== VK_FORMAT_B5G6R5_UNORM_PACK16
)
1583 else if (desc
->layout
== VK_FORMAT_LAYOUT_PLAIN
) {
1584 if (vi_alpha_is_on_msb(device
, view_format
))
1585 extra_channel
= desc
->nr_channels
- 1;
1591 for (i
= 0; i
< 4; i
++) {
1592 int index
= desc
->swizzle
[i
] - VK_SWIZZLE_X
;
1593 if (desc
->swizzle
[i
] < VK_SWIZZLE_X
||
1594 desc
->swizzle
[i
] > VK_SWIZZLE_W
)
1597 if (desc
->channel
[i
].pure_integer
&&
1598 desc
->channel
[i
].type
== VK_FORMAT_TYPE_SIGNED
) {
1599 /* Use the maximum value for clamping the clear color. */
1600 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
1602 values
[i
] = clear_value
->int32
[i
] != 0;
1603 if (clear_value
->int32
[i
] != 0 && MIN2(clear_value
->int32
[i
], max
) != max
)
1605 } else if (desc
->channel
[i
].pure_integer
&&
1606 desc
->channel
[i
].type
== VK_FORMAT_TYPE_UNSIGNED
) {
1607 /* Use the maximum value for clamping the clear color. */
1608 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
1610 values
[i
] = clear_value
->uint32
[i
] != 0U;
1611 if (clear_value
->uint32
[i
] != 0U && MIN2(clear_value
->uint32
[i
], max
) != max
)
1614 values
[i
] = clear_value
->float32
[i
] != 0.0F
;
1615 if (clear_value
->float32
[i
] != 0.0F
&& clear_value
->float32
[i
] != 1.0F
)
1619 if (index
== extra_channel
) {
1620 extra_value
= values
[i
];
1623 main_value
= values
[i
];
1628 /* If alpha isn't present, make it the same as color, and vice versa. */
1630 extra_value
= main_value
;
1631 else if (!has_color
)
1632 main_value
= extra_value
;
1634 for (int i
= 0; i
< 4; ++i
)
1635 if (values
[i
] != main_value
&&
1636 desc
->swizzle
[i
] - VK_SWIZZLE_X
!= extra_channel
&&
1637 desc
->swizzle
[i
] >= VK_SWIZZLE_X
&&
1638 desc
->swizzle
[i
] <= VK_SWIZZLE_W
)
1641 *can_avoid_fast_clear_elim
= true;
1644 *reset_value
|= RADV_DCC_CLEAR_MAIN_1
;
1647 *reset_value
|= RADV_DCC_CLEAR_SECONDARY_1
;
1652 radv_can_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1653 const struct radv_image_view
*iview
,
1654 VkImageLayout image_layout
,
1655 bool in_render_loop
,
1656 const VkClearRect
*clear_rect
,
1657 VkClearColorValue clear_value
,
1660 uint32_t clear_color
[2];
1662 if (!radv_image_view_can_fast_clear(cmd_buffer
->device
, iview
))
1665 if (!radv_layout_can_fast_clear(iview
->image
, image_layout
, in_render_loop
,
1666 radv_image_queue_family_mask(iview
->image
,
1667 cmd_buffer
->queue_family_index
,
1668 cmd_buffer
->queue_family_index
)))
1671 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
1672 clear_rect
->rect
.extent
.width
!= iview
->image
->info
.width
||
1673 clear_rect
->rect
.extent
.height
!= iview
->image
->info
.height
)
1676 if (view_mask
&& (iview
->image
->info
.array_size
>= 32 ||
1677 (1u << iview
->image
->info
.array_size
) - 1u != view_mask
))
1679 if (!view_mask
&& clear_rect
->baseArrayLayer
!= 0)
1681 if (!view_mask
&& clear_rect
->layerCount
!= iview
->image
->info
.array_size
)
1685 if (!radv_format_pack_clear_color(iview
->vk_format
,
1686 clear_color
, &clear_value
))
1689 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
)) {
1690 bool can_avoid_fast_clear_elim
;
1691 uint32_t reset_value
;
1693 vi_get_fast_clear_parameters(cmd_buffer
->device
,
1694 iview
->image
->vk_format
,
1696 &clear_value
, &reset_value
,
1697 &can_avoid_fast_clear_elim
);
1699 if (iview
->image
->info
.samples
> 1) {
1700 /* DCC fast clear with MSAA should clear CMASK. */
1701 /* FIXME: This doesn't work for now. There is a
1702 * hardware bug with fast clears and DCC for MSAA
1703 * textures. AMDVLK has a workaround but it doesn't
1704 * seem to work here. Note that we might emit useless
1705 * CB flushes but that shouldn't matter.
1707 if (!can_avoid_fast_clear_elim
)
1711 if (iview
->image
->info
.levels
> 1 &&
1712 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX8
) {
1713 for (uint32_t l
= 0; l
< iview
->level_count
; l
++) {
1714 uint32_t level
= iview
->base_mip
+ l
;
1715 struct legacy_surf_level
*surf_level
=
1716 &iview
->image
->planes
[0].surface
.u
.legacy
.level
[level
];
1718 /* Do not fast clears if one level can't be
1721 if (!surf_level
->dcc_fast_clear_size
)
1732 radv_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1733 const struct radv_image_view
*iview
,
1734 const VkClearAttachment
*clear_att
,
1735 uint32_t subpass_att
,
1736 enum radv_cmd_flush_bits
*pre_flush
,
1737 enum radv_cmd_flush_bits
*post_flush
)
1739 VkClearColorValue clear_value
= clear_att
->clearValue
.color
;
1740 uint32_t clear_color
[2], flush_bits
= 0;
1741 uint32_t cmask_clear_value
;
1742 VkImageSubresourceRange range
= {
1743 .aspectMask
= iview
->aspect_mask
,
1744 .baseMipLevel
= iview
->base_mip
,
1745 .levelCount
= iview
->level_count
,
1746 .baseArrayLayer
= iview
->base_layer
,
1747 .layerCount
= iview
->layer_count
,
1751 cmd_buffer
->state
.flush_bits
|= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1752 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
) & ~ *pre_flush
;
1753 *pre_flush
|= cmd_buffer
->state
.flush_bits
;
1757 radv_format_pack_clear_color(iview
->vk_format
, clear_color
, &clear_value
);
1759 cmask_clear_value
= radv_get_cmask_fast_clear_value(iview
->image
);
1761 /* clear cmask buffer */
1762 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
)) {
1763 uint32_t reset_value
;
1764 bool can_avoid_fast_clear_elim
;
1765 bool need_decompress_pass
= false;
1767 vi_get_fast_clear_parameters(cmd_buffer
->device
,
1768 iview
->image
->vk_format
,
1770 &clear_value
, &reset_value
,
1771 &can_avoid_fast_clear_elim
);
1773 if (radv_image_has_cmask(iview
->image
)) {
1774 flush_bits
= radv_clear_cmask(cmd_buffer
, iview
->image
,
1775 &range
, cmask_clear_value
);
1777 need_decompress_pass
= true;
1780 if (!can_avoid_fast_clear_elim
)
1781 need_decompress_pass
= true;
1783 flush_bits
|= radv_clear_dcc(cmd_buffer
, iview
->image
, &range
,
1786 radv_update_fce_metadata(cmd_buffer
, iview
->image
, &range
,
1787 need_decompress_pass
);
1789 flush_bits
= radv_clear_cmask(cmd_buffer
, iview
->image
,
1790 &range
, cmask_clear_value
);
1794 *post_flush
|= flush_bits
;
1797 radv_update_color_clear_metadata(cmd_buffer
, iview
, subpass_att
,
1802 * The parameters mean that same as those in vkCmdClearAttachments.
1805 emit_clear(struct radv_cmd_buffer
*cmd_buffer
,
1806 const VkClearAttachment
*clear_att
,
1807 const VkClearRect
*clear_rect
,
1808 enum radv_cmd_flush_bits
*pre_flush
,
1809 enum radv_cmd_flush_bits
*post_flush
,
1811 bool ds_resolve_clear
)
1813 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1814 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1815 VkImageAspectFlags aspects
= clear_att
->aspectMask
;
1817 if (aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
1818 const uint32_t subpass_att
= clear_att
->colorAttachment
;
1819 assert(subpass_att
< subpass
->color_count
);
1820 const uint32_t pass_att
= subpass
->color_attachments
[subpass_att
].attachment
;
1821 if (pass_att
== VK_ATTACHMENT_UNUSED
)
1824 VkImageLayout image_layout
= subpass
->color_attachments
[subpass_att
].layout
;
1825 bool in_render_loop
= subpass
->color_attachments
[subpass_att
].in_render_loop
;
1826 const struct radv_image_view
*iview
= fb
? cmd_buffer
->state
.attachments
[pass_att
].iview
: NULL
;
1827 VkClearColorValue clear_value
= clear_att
->clearValue
.color
;
1829 if (radv_can_fast_clear_color(cmd_buffer
, iview
, image_layout
, in_render_loop
,
1830 clear_rect
, clear_value
, view_mask
)) {
1831 radv_fast_clear_color(cmd_buffer
, iview
, clear_att
,
1832 subpass_att
, pre_flush
,
1835 emit_color_clear(cmd_buffer
, clear_att
, clear_rect
, view_mask
);
1838 struct radv_subpass_attachment
*ds_att
= subpass
->depth_stencil_attachment
;
1840 if (ds_resolve_clear
)
1841 ds_att
= subpass
->ds_resolve_attachment
;
1843 if (!ds_att
|| ds_att
->attachment
== VK_ATTACHMENT_UNUSED
)
1846 VkImageLayout image_layout
= ds_att
->layout
;
1847 bool in_render_loop
= ds_att
->in_render_loop
;
1848 const struct radv_image_view
*iview
= fb
? cmd_buffer
->state
.attachments
[ds_att
->attachment
].iview
: NULL
;
1849 VkClearDepthStencilValue clear_value
= clear_att
->clearValue
.depthStencil
;
1851 assert(aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
1852 VK_IMAGE_ASPECT_STENCIL_BIT
));
1854 if (radv_can_fast_clear_depth(cmd_buffer
, iview
, image_layout
,
1855 in_render_loop
, aspects
, clear_rect
,
1856 clear_value
, view_mask
)) {
1857 radv_fast_clear_depth(cmd_buffer
, iview
, clear_att
,
1858 pre_flush
, post_flush
);
1860 emit_depthstencil_clear(cmd_buffer
, clear_att
, clear_rect
,
1867 radv_attachment_needs_clear(struct radv_cmd_state
*cmd_state
, uint32_t a
)
1869 uint32_t view_mask
= cmd_state
->subpass
->view_mask
;
1870 return (a
!= VK_ATTACHMENT_UNUSED
&&
1871 cmd_state
->attachments
[a
].pending_clear_aspects
&&
1872 (!view_mask
|| (view_mask
& ~cmd_state
->attachments
[a
].cleared_views
)));
1876 radv_subpass_needs_clear(struct radv_cmd_buffer
*cmd_buffer
)
1878 struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1881 if (!cmd_state
->subpass
)
1884 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
1885 a
= cmd_state
->subpass
->color_attachments
[i
].attachment
;
1886 if (radv_attachment_needs_clear(cmd_state
, a
))
1890 if (cmd_state
->subpass
->depth_stencil_attachment
) {
1891 a
= cmd_state
->subpass
->depth_stencil_attachment
->attachment
;
1892 if (radv_attachment_needs_clear(cmd_state
, a
))
1896 if (!cmd_state
->subpass
->ds_resolve_attachment
)
1899 a
= cmd_state
->subpass
->ds_resolve_attachment
->attachment
;
1900 return radv_attachment_needs_clear(cmd_state
, a
);
1904 radv_subpass_clear_attachment(struct radv_cmd_buffer
*cmd_buffer
,
1905 struct radv_attachment_state
*attachment
,
1906 const VkClearAttachment
*clear_att
,
1907 enum radv_cmd_flush_bits
*pre_flush
,
1908 enum radv_cmd_flush_bits
*post_flush
,
1909 bool ds_resolve_clear
)
1911 struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1912 uint32_t view_mask
= cmd_state
->subpass
->view_mask
;
1914 VkClearRect clear_rect
= {
1915 .rect
= cmd_state
->render_area
,
1916 .baseArrayLayer
= 0,
1917 .layerCount
= cmd_state
->framebuffer
->layers
,
1920 emit_clear(cmd_buffer
, clear_att
, &clear_rect
, pre_flush
, post_flush
,
1921 view_mask
& ~attachment
->cleared_views
, ds_resolve_clear
);
1923 attachment
->cleared_views
|= view_mask
;
1925 attachment
->pending_clear_aspects
= 0;
1929 * Emit any pending attachment clears for the current subpass.
1931 * @see radv_attachment_state::pending_clear_aspects
1934 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
)
1936 struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1937 struct radv_meta_saved_state saved_state
;
1938 enum radv_cmd_flush_bits pre_flush
= 0;
1939 enum radv_cmd_flush_bits post_flush
= 0;
1941 if (!radv_subpass_needs_clear(cmd_buffer
))
1944 radv_meta_save(&saved_state
, cmd_buffer
,
1945 RADV_META_SAVE_GRAPHICS_PIPELINE
|
1946 RADV_META_SAVE_CONSTANTS
);
1948 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
1949 uint32_t a
= cmd_state
->subpass
->color_attachments
[i
].attachment
;
1951 if (!radv_attachment_needs_clear(cmd_state
, a
))
1954 assert(cmd_state
->attachments
[a
].pending_clear_aspects
==
1955 VK_IMAGE_ASPECT_COLOR_BIT
);
1957 VkClearAttachment clear_att
= {
1958 .aspectMask
= VK_IMAGE_ASPECT_COLOR_BIT
,
1959 .colorAttachment
= i
, /* Use attachment index relative to subpass */
1960 .clearValue
= cmd_state
->attachments
[a
].clear_value
,
1963 radv_subpass_clear_attachment(cmd_buffer
,
1964 &cmd_state
->attachments
[a
],
1965 &clear_att
, &pre_flush
,
1966 &post_flush
, false);
1969 if (cmd_state
->subpass
->depth_stencil_attachment
) {
1970 uint32_t ds
= cmd_state
->subpass
->depth_stencil_attachment
->attachment
;
1971 if (radv_attachment_needs_clear(cmd_state
, ds
)) {
1972 VkClearAttachment clear_att
= {
1973 .aspectMask
= cmd_state
->attachments
[ds
].pending_clear_aspects
,
1974 .clearValue
= cmd_state
->attachments
[ds
].clear_value
,
1977 radv_subpass_clear_attachment(cmd_buffer
,
1978 &cmd_state
->attachments
[ds
],
1979 &clear_att
, &pre_flush
,
1980 &post_flush
, false);
1984 if (cmd_state
->subpass
->ds_resolve_attachment
) {
1985 uint32_t ds_resolve
= cmd_state
->subpass
->ds_resolve_attachment
->attachment
;
1986 if (radv_attachment_needs_clear(cmd_state
, ds_resolve
)) {
1987 VkClearAttachment clear_att
= {
1988 .aspectMask
= cmd_state
->attachments
[ds_resolve
].pending_clear_aspects
,
1989 .clearValue
= cmd_state
->attachments
[ds_resolve
].clear_value
,
1992 radv_subpass_clear_attachment(cmd_buffer
,
1993 &cmd_state
->attachments
[ds_resolve
],
1994 &clear_att
, &pre_flush
,
1999 radv_meta_restore(&saved_state
, cmd_buffer
);
2000 cmd_buffer
->state
.flush_bits
|= post_flush
;
2004 radv_clear_image_layer(struct radv_cmd_buffer
*cmd_buffer
,
2005 struct radv_image
*image
,
2006 VkImageLayout image_layout
,
2007 const VkImageSubresourceRange
*range
,
2008 VkFormat format
, int level
, int layer
,
2009 const VkClearValue
*clear_val
)
2011 VkDevice device_h
= radv_device_to_handle(cmd_buffer
->device
);
2012 struct radv_image_view iview
;
2013 uint32_t width
= radv_minify(image
->info
.width
, range
->baseMipLevel
+ level
);
2014 uint32_t height
= radv_minify(image
->info
.height
, range
->baseMipLevel
+ level
);
2016 radv_image_view_init(&iview
, cmd_buffer
->device
,
2017 &(VkImageViewCreateInfo
) {
2018 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
2019 .image
= radv_image_to_handle(image
),
2020 .viewType
= radv_meta_get_view_type(image
),
2022 .subresourceRange
= {
2023 .aspectMask
= range
->aspectMask
,
2024 .baseMipLevel
= range
->baseMipLevel
+ level
,
2026 .baseArrayLayer
= range
->baseArrayLayer
+ layer
,
2032 radv_CreateFramebuffer(device_h
,
2033 &(VkFramebufferCreateInfo
) {
2034 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
2035 .attachmentCount
= 1,
2036 .pAttachments
= (VkImageView
[]) {
2037 radv_image_view_to_handle(&iview
),
2043 &cmd_buffer
->pool
->alloc
,
2046 VkAttachmentDescription att_desc
= {
2047 .format
= iview
.vk_format
,
2048 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
2049 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
2050 .stencilLoadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
2051 .stencilStoreOp
= VK_ATTACHMENT_STORE_OP_STORE
,
2052 .initialLayout
= image_layout
,
2053 .finalLayout
= image_layout
,
2056 VkSubpassDescription subpass_desc
= {
2057 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
2058 .inputAttachmentCount
= 0,
2059 .colorAttachmentCount
= 0,
2060 .pColorAttachments
= NULL
,
2061 .pResolveAttachments
= NULL
,
2062 .pDepthStencilAttachment
= NULL
,
2063 .preserveAttachmentCount
= 0,
2064 .pPreserveAttachments
= NULL
,
2067 const VkAttachmentReference att_ref
= {
2069 .layout
= image_layout
,
2072 if (range
->aspectMask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
2073 subpass_desc
.colorAttachmentCount
= 1;
2074 subpass_desc
.pColorAttachments
= &att_ref
;
2076 subpass_desc
.pDepthStencilAttachment
= &att_ref
;
2080 radv_CreateRenderPass(device_h
,
2081 &(VkRenderPassCreateInfo
) {
2082 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
2083 .attachmentCount
= 1,
2084 .pAttachments
= &att_desc
,
2086 .pSubpasses
= &subpass_desc
,
2088 &cmd_buffer
->pool
->alloc
,
2091 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
2092 &(VkRenderPassBeginInfo
) {
2093 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
2095 .offset
= { 0, 0, },
2103 .clearValueCount
= 0,
2104 .pClearValues
= NULL
,
2106 VK_SUBPASS_CONTENTS_INLINE
);
2108 VkClearAttachment clear_att
= {
2109 .aspectMask
= range
->aspectMask
,
2110 .colorAttachment
= 0,
2111 .clearValue
= *clear_val
,
2114 VkClearRect clear_rect
= {
2117 .extent
= { width
, height
},
2119 .baseArrayLayer
= range
->baseArrayLayer
,
2120 .layerCount
= 1, /* FINISHME: clear multi-layer framebuffer */
2123 emit_clear(cmd_buffer
, &clear_att
, &clear_rect
, NULL
, NULL
, 0, false);
2125 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
));
2126 radv_DestroyRenderPass(device_h
, pass
,
2127 &cmd_buffer
->pool
->alloc
);
2128 radv_DestroyFramebuffer(device_h
, fb
,
2129 &cmd_buffer
->pool
->alloc
);
2133 * Return TRUE if a fast color or depth clear has been performed.
2136 radv_fast_clear_range(struct radv_cmd_buffer
*cmd_buffer
,
2137 struct radv_image
*image
,
2139 VkImageLayout image_layout
,
2140 bool in_render_loop
,
2141 const VkImageSubresourceRange
*range
,
2142 const VkClearValue
*clear_val
)
2144 struct radv_image_view iview
;
2146 radv_image_view_init(&iview
, cmd_buffer
->device
,
2147 &(VkImageViewCreateInfo
) {
2148 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
2149 .image
= radv_image_to_handle(image
),
2150 .viewType
= radv_meta_get_view_type(image
),
2151 .format
= image
->vk_format
,
2152 .subresourceRange
= {
2153 .aspectMask
= range
->aspectMask
,
2154 .baseMipLevel
= range
->baseMipLevel
,
2155 .levelCount
= range
->levelCount
,
2156 .baseArrayLayer
= range
->baseArrayLayer
,
2157 .layerCount
= range
->layerCount
,
2161 VkClearRect clear_rect
= {
2165 radv_minify(image
->info
.width
, range
->baseMipLevel
),
2166 radv_minify(image
->info
.height
, range
->baseMipLevel
),
2169 .baseArrayLayer
= range
->baseArrayLayer
,
2170 .layerCount
= range
->layerCount
,
2173 VkClearAttachment clear_att
= {
2174 .aspectMask
= range
->aspectMask
,
2175 .colorAttachment
= 0,
2176 .clearValue
= *clear_val
,
2179 if (vk_format_is_color(format
)) {
2180 if (radv_can_fast_clear_color(cmd_buffer
, &iview
, image_layout
,
2181 in_render_loop
, &clear_rect
,
2182 clear_att
.clearValue
.color
, 0)) {
2183 radv_fast_clear_color(cmd_buffer
, &iview
, &clear_att
,
2184 clear_att
.colorAttachment
,
2189 if (radv_can_fast_clear_depth(cmd_buffer
, &iview
, image_layout
,
2190 in_render_loop
,range
->aspectMask
,
2191 &clear_rect
, clear_att
.clearValue
.depthStencil
,
2193 radv_fast_clear_depth(cmd_buffer
, &iview
, &clear_att
,
2203 radv_cmd_clear_image(struct radv_cmd_buffer
*cmd_buffer
,
2204 struct radv_image
*image
,
2205 VkImageLayout image_layout
,
2206 const VkClearValue
*clear_value
,
2207 uint32_t range_count
,
2208 const VkImageSubresourceRange
*ranges
,
2211 VkFormat format
= image
->vk_format
;
2212 VkClearValue internal_clear_value
= *clear_value
;
2214 if (format
== VK_FORMAT_E5B9G9R9_UFLOAT_PACK32
) {
2216 format
= VK_FORMAT_R32_UINT
;
2217 value
= float3_to_rgb9e5(clear_value
->color
.float32
);
2218 internal_clear_value
.color
.uint32
[0] = value
;
2221 if (format
== VK_FORMAT_R4G4_UNORM_PACK8
) {
2223 format
= VK_FORMAT_R8_UINT
;
2224 r
= float_to_ubyte(clear_value
->color
.float32
[0]) >> 4;
2225 g
= float_to_ubyte(clear_value
->color
.float32
[1]) >> 4;
2226 internal_clear_value
.color
.uint32
[0] = (r
<< 4) | (g
& 0xf);
2229 if (format
== VK_FORMAT_R32G32B32_UINT
||
2230 format
== VK_FORMAT_R32G32B32_SINT
||
2231 format
== VK_FORMAT_R32G32B32_SFLOAT
)
2234 for (uint32_t r
= 0; r
< range_count
; r
++) {
2235 const VkImageSubresourceRange
*range
= &ranges
[r
];
2237 /* Try to perform a fast clear first, otherwise fallback to
2241 radv_fast_clear_range(cmd_buffer
, image
, format
,
2242 image_layout
, false, range
,
2243 &internal_clear_value
)) {
2247 for (uint32_t l
= 0; l
< radv_get_levelCount(image
, range
); ++l
) {
2248 const uint32_t layer_count
= image
->type
== VK_IMAGE_TYPE_3D
?
2249 radv_minify(image
->info
.depth
, range
->baseMipLevel
+ l
) :
2250 radv_get_layerCount(image
, range
);
2251 for (uint32_t s
= 0; s
< layer_count
; ++s
) {
2254 struct radv_meta_blit2d_surf surf
;
2255 surf
.format
= format
;
2257 surf
.level
= range
->baseMipLevel
+ l
;
2258 surf
.layer
= range
->baseArrayLayer
+ s
;
2259 surf
.aspect_mask
= range
->aspectMask
;
2260 radv_meta_clear_image_cs(cmd_buffer
, &surf
,
2261 &internal_clear_value
.color
);
2263 radv_clear_image_layer(cmd_buffer
, image
, image_layout
,
2264 range
, format
, l
, s
, &internal_clear_value
);
2271 void radv_CmdClearColorImage(
2272 VkCommandBuffer commandBuffer
,
2274 VkImageLayout imageLayout
,
2275 const VkClearColorValue
* pColor
,
2276 uint32_t rangeCount
,
2277 const VkImageSubresourceRange
* pRanges
)
2279 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2280 RADV_FROM_HANDLE(radv_image
, image
, image_h
);
2281 struct radv_meta_saved_state saved_state
;
2282 bool cs
= cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
;
2285 radv_meta_save(&saved_state
, cmd_buffer
,
2286 RADV_META_SAVE_COMPUTE_PIPELINE
|
2287 RADV_META_SAVE_CONSTANTS
|
2288 RADV_META_SAVE_DESCRIPTORS
);
2290 radv_meta_save(&saved_state
, cmd_buffer
,
2291 RADV_META_SAVE_GRAPHICS_PIPELINE
|
2292 RADV_META_SAVE_CONSTANTS
);
2295 radv_cmd_clear_image(cmd_buffer
, image
, imageLayout
,
2296 (const VkClearValue
*) pColor
,
2297 rangeCount
, pRanges
, cs
);
2299 radv_meta_restore(&saved_state
, cmd_buffer
);
2302 void radv_CmdClearDepthStencilImage(
2303 VkCommandBuffer commandBuffer
,
2305 VkImageLayout imageLayout
,
2306 const VkClearDepthStencilValue
* pDepthStencil
,
2307 uint32_t rangeCount
,
2308 const VkImageSubresourceRange
* pRanges
)
2310 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2311 RADV_FROM_HANDLE(radv_image
, image
, image_h
);
2312 struct radv_meta_saved_state saved_state
;
2314 radv_meta_save(&saved_state
, cmd_buffer
,
2315 RADV_META_SAVE_GRAPHICS_PIPELINE
|
2316 RADV_META_SAVE_CONSTANTS
);
2318 radv_cmd_clear_image(cmd_buffer
, image
, imageLayout
,
2319 (const VkClearValue
*) pDepthStencil
,
2320 rangeCount
, pRanges
, false);
2322 radv_meta_restore(&saved_state
, cmd_buffer
);
2325 void radv_CmdClearAttachments(
2326 VkCommandBuffer commandBuffer
,
2327 uint32_t attachmentCount
,
2328 const VkClearAttachment
* pAttachments
,
2330 const VkClearRect
* pRects
)
2332 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2333 struct radv_meta_saved_state saved_state
;
2334 enum radv_cmd_flush_bits pre_flush
= 0;
2335 enum radv_cmd_flush_bits post_flush
= 0;
2337 if (!cmd_buffer
->state
.subpass
)
2340 radv_meta_save(&saved_state
, cmd_buffer
,
2341 RADV_META_SAVE_GRAPHICS_PIPELINE
|
2342 RADV_META_SAVE_CONSTANTS
);
2344 /* FINISHME: We can do better than this dumb loop. It thrashes too much
2347 for (uint32_t a
= 0; a
< attachmentCount
; ++a
) {
2348 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
2349 emit_clear(cmd_buffer
, &pAttachments
[a
], &pRects
[r
], &pre_flush
, &post_flush
,
2350 cmd_buffer
->state
.subpass
->view_mask
, false);
2354 radv_meta_restore(&saved_state
, cmd_buffer
);
2355 cmd_buffer
->state
.flush_bits
|= post_flush
;