src/amd/vulkan/radv_meta_clear.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "radv_debug.h"
  25 #include "radv_meta.h"
  26 #include "radv_private.h"
  27 #include "nir/nir_builder.h"
  28
  29 #include "util/format_rgb9e5.h"
  30 #include "vk_format.h"
  31
  32 enum {
  33         DEPTH_CLEAR_SLOW,
  34         DEPTH_CLEAR_FAST_EXPCLEAR,
  35         DEPTH_CLEAR_FAST_NO_EXPCLEAR
  36 };
  37
  38 static void
  39 build_color_shaders(struct nir_shader **out_vs,
  40                     struct nir_shader **out_fs,
  41                     uint32_t frag_output)
  42 {
  43         nir_builder vs_b;
  44         nir_builder fs_b;
  45
  46         nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
  47         nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
  48
  49         vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
  50         fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
  51
  52         const struct glsl_type *position_type = glsl_vec4_type();
  53         const struct glsl_type *color_type = glsl_vec4_type();
  54
  55         nir_variable *vs_out_pos =
  56                 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
  57                                     "gl_Position");
  58         vs_out_pos->data.location = VARYING_SLOT_POS;
  59
  60         nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
  61         nir_intrinsic_set_base(in_color_load, 0);
  62         nir_intrinsic_set_range(in_color_load, 16);
  63         in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
  64         in_color_load->num_components = 4;
  65         nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
  66         nir_builder_instr_insert(&fs_b, &in_color_load->instr);
  67
  68         nir_variable *fs_out_color =
  69                 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
  70                                     "f_color");
  71         fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
  72
  73         nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
  74
  75         nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
  76         nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
  77
  78         const struct glsl_type *layer_type = glsl_int_type();
  79         nir_variable *vs_out_layer =
  80                 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
  81                                     "v_layer");
  82         vs_out_layer->data.location = VARYING_SLOT_LAYER;
  83         vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
  84         nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
  85         nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
  86
  87         nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
  88         nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
  89
  90         *out_vs = vs_b.shader;
  91         *out_fs = fs_b.shader;
  92 }
  93
  94 static VkResult
  95 create_pipeline(struct radv_device *device,
  96                 struct radv_render_pass *render_pass,
  97                 uint32_t samples,
  98                 struct nir_shader *vs_nir,
  99                 struct nir_shader *fs_nir,
 100                 const VkPipelineVertexInputStateCreateInfo *vi_state,
 101                 const VkPipelineDepthStencilStateCreateInfo *ds_state,
 102                 const VkPipelineColorBlendStateCreateInfo *cb_state,
 103                 const VkPipelineLayout layout,
 104                 const struct radv_graphics_pipeline_create_info *extra,
 105                 const VkAllocationCallbacks *alloc,
 106                 VkPipeline *pipeline)
 107 {
 108         VkDevice device_h = radv_device_to_handle(device);
 109         VkResult result;
 110
 111         struct radv_shader_module vs_m = { .nir = vs_nir };
 112         struct radv_shader_module fs_m = { .nir = fs_nir };
 113
 114         result = radv_graphics_pipeline_create(device_h,
 115                                                radv_pipeline_cache_to_handle(&device->meta_state.cache),
 116                                                &(VkGraphicsPipelineCreateInfo) {
 117                                                        .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
 118                                                                .stageCount = fs_nir ? 2 : 1,
 119                                                                .pStages = (VkPipelineShaderStageCreateInfo[]) {
 120                                                                {
 121                                                                        .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
 122                                                                        .stage = VK_SHADER_STAGE_VERTEX_BIT,
 123                                                                        .module = radv_shader_module_to_handle(&vs_m),
 124                                                                        .pName = "main",
 125                                                                },
 126                                                                {
 127                                                                        .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
 128                                                                        .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
 129                                                                        .module = radv_shader_module_to_handle(&fs_m),
 130                                                                        .pName = "main",
 131                                                                },
 132                                                        },
 133                                                                .pVertexInputState = vi_state,
 134                                                                         .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
 135                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
 136                                                                .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
 137                                                                .primitiveRestartEnable = false,
 138                                                        },
 139                                                                         .pViewportState = &(VkPipelineViewportStateCreateInfo) {
 140                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
 141                                                                .viewportCount = 1,
 142                                                                .scissorCount = 1,
 143                                                        },
 144                                                                                  .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
 145                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
 146                                                                .rasterizerDiscardEnable = false,
 147                                                                .polygonMode = VK_POLYGON_MODE_FILL,
 148                                                                .cullMode = VK_CULL_MODE_NONE,
 149                                                                .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
 150                                                                .depthBiasEnable = false,
 151                                                        },
 152                                                                                           .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
 153                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
 154                                                                .rasterizationSamples = samples,
 155                                                                .sampleShadingEnable = false,
 156                                                                .pSampleMask = NULL,
 157                                                                .alphaToCoverageEnable = false,
 158                                                                .alphaToOneEnable = false,
 159                                                        },
 160                                                                                                    .pDepthStencilState = ds_state,
 161                                                                                                             .pColorBlendState = cb_state,
 162                                                                                                             .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
 163                                                                /* The meta clear pipeline declares all state as dynamic.
 164                                                                 * As a consequence, vkCmdBindPipeline writes no dynamic state
 165                                                                 * to the cmd buffer. Therefore, at the end of the meta clear,
 166                                                                 * we need only restore dynamic state was vkCmdSet.
 167                                                                 */
 168                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
 169                                                                .dynamicStateCount = 8,
 170                                                                .pDynamicStates = (VkDynamicState[]) {
 171                                                                        /* Everything except stencil write mask */
 172                                                                        VK_DYNAMIC_STATE_VIEWPORT,
 173                                                                        VK_DYNAMIC_STATE_SCISSOR,
 174                                                                        VK_DYNAMIC_STATE_LINE_WIDTH,
 175                                                                        VK_DYNAMIC_STATE_DEPTH_BIAS,
 176                                                                        VK_DYNAMIC_STATE_BLEND_CONSTANTS,
 177                                                                        VK_DYNAMIC_STATE_DEPTH_BOUNDS,
 178                                                                        VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
 179                                                                        VK_DYNAMIC_STATE_STENCIL_REFERENCE,
 180                                                                },
 181                                                        },
 182                                                     .layout = layout,
 183                                                     .flags = 0,
 184                                                     .renderPass = radv_render_pass_to_handle(render_pass),
 185                                                     .subpass = 0,
 186                                                 },
 187                                                extra,
 188                                                alloc,
 189                                                pipeline);
 190
 191         ralloc_free(vs_nir);
 192         ralloc_free(fs_nir);
 193
 194         return result;
 195 }
 196
 197 static VkResult
 198 create_color_renderpass(struct radv_device *device,
 199                         VkFormat vk_format,
 200                         uint32_t samples,
 201                         VkRenderPass *pass)
 202 {
 203         mtx_lock(&device->meta_state.mtx);
 204         if (*pass) {
 205                 mtx_unlock (&device->meta_state.mtx);
 206                 return VK_SUCCESS;
 207         }
 208
 209         VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
 210                                        &(VkRenderPassCreateInfo) {
 211                                                .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
 212                                                        .attachmentCount = 1,
 213                                                        .pAttachments = &(VkAttachmentDescription) {
 214                                                        .format = vk_format,
 215                                                        .samples = samples,
 216                                                        .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
 217                                                        .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
 218                                                        .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
 219                                                        .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
 220                                                },
 221                                                        .subpassCount = 1,
 222                                                                 .pSubpasses = &(VkSubpassDescription) {
 223                                                        .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
 224                                                        .inputAttachmentCount = 0,
 225                                                        .colorAttachmentCount = 1,
 226                                                        .pColorAttachments = &(VkAttachmentReference) {
 227                                                                .attachment = 0,
 228                                                                .layout = VK_IMAGE_LAYOUT_GENERAL,
 229                                                        },
 230                                                        .pResolveAttachments = NULL,
 231                                                        .pDepthStencilAttachment = &(VkAttachmentReference) {
 232                                                                .attachment = VK_ATTACHMENT_UNUSED,
 233                                                                .layout = VK_IMAGE_LAYOUT_GENERAL,
 234                                                        },
 235                                                        .preserveAttachmentCount = 0,
 236                                                        .pPreserveAttachments = NULL,
 237                                                },
 238                                                                 .dependencyCount = 0,
 239                                                                          }, &device->meta_state.alloc, pass);
 240         mtx_unlock(&device->meta_state.mtx);
 241         return result;
 242 }
 243
 244 static VkResult
 245 create_color_pipeline(struct radv_device *device,
 246                       uint32_t samples,
 247                       uint32_t frag_output,
 248                       VkPipeline *pipeline,
 249                       VkRenderPass pass)
 250 {
 251         struct nir_shader *vs_nir;
 252         struct nir_shader *fs_nir;
 253         VkResult result;
 254
 255         mtx_lock(&device->meta_state.mtx);
 256         if (*pipeline) {
 257                 mtx_unlock(&device->meta_state.mtx);
 258                 return VK_SUCCESS;
 259         }
 260
 261         build_color_shaders(&vs_nir, &fs_nir, frag_output);
 262
 263         const VkPipelineVertexInputStateCreateInfo vi_state = {
 264                 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
 265                 .vertexBindingDescriptionCount = 0,
 266                 .vertexAttributeDescriptionCount = 0,
 267         };
 268
 269         const VkPipelineDepthStencilStateCreateInfo ds_state = {
 270                 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
 271                 .depthTestEnable = false,
 272                 .depthWriteEnable = false,
 273                 .depthBoundsTestEnable = false,
 274                 .stencilTestEnable = false,
 275         };
 276
 277         VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
 278         blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
 279                 .blendEnable = false,
 280                 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
 281                 VK_COLOR_COMPONENT_R_BIT |
 282                 VK_COLOR_COMPONENT_G_BIT |
 283                 VK_COLOR_COMPONENT_B_BIT,
 284         };
 285
 286         const VkPipelineColorBlendStateCreateInfo cb_state = {
 287                 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
 288                 .logicOpEnable = false,
 289                 .attachmentCount = MAX_RTS,
 290                 .pAttachments = blend_attachment_state
 291         };
 292
 293
 294         struct radv_graphics_pipeline_create_info extra = {
 295                 .use_rectlist = true,
 296         };
 297         result = create_pipeline(device, radv_render_pass_from_handle(pass),
 298                                  samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
 299                                  device->meta_state.clear_color_p_layout,
 300                                  &extra, &device->meta_state.alloc, pipeline);
 301
 302         mtx_unlock(&device->meta_state.mtx);
 303         return result;
 304 }
 305
 306 static void
 307 finish_meta_clear_htile_mask_state(struct radv_device *device)
 308 {
 309         struct radv_meta_state *state = &device->meta_state;
 310
 311         radv_DestroyPipeline(radv_device_to_handle(device),
 312                              state->clear_htile_mask_pipeline,
 313                              &state->alloc);
 314         radv_DestroyPipelineLayout(radv_device_to_handle(device),
 315                                    state->clear_htile_mask_p_layout,
 316                                    &state->alloc);
 317         radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
 318                                         state->clear_htile_mask_ds_layout,
 319                                         &state->alloc);
 320 }
 321
 322 void
 323 radv_device_finish_meta_clear_state(struct radv_device *device)
 324 {
 325         struct radv_meta_state *state = &device->meta_state;
 326
 327         for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
 328                 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
 329                         radv_DestroyPipeline(radv_device_to_handle(device),
 330                                              state->clear[i].color_pipelines[j],
 331                                              &state->alloc);
 332                         radv_DestroyRenderPass(radv_device_to_handle(device),
 333                                                state->clear[i].render_pass[j],
 334                                                &state->alloc);
 335                 }
 336
 337                 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
 338                         radv_DestroyPipeline(radv_device_to_handle(device),
 339                                              state->clear[i].depth_only_pipeline[j],
 340                                              &state->alloc);
 341                         radv_DestroyPipeline(radv_device_to_handle(device),
 342                                              state->clear[i].stencil_only_pipeline[j],
 343                                              &state->alloc);
 344                         radv_DestroyPipeline(radv_device_to_handle(device),
 345                                              state->clear[i].depthstencil_pipeline[j],
 346                                              &state->alloc);
 347                 }
 348                 radv_DestroyRenderPass(radv_device_to_handle(device),
 349                                       state->clear[i].depthstencil_rp,
 350                                       &state->alloc);
 351         }
 352         radv_DestroyPipelineLayout(radv_device_to_handle(device),
 353                                    state->clear_color_p_layout,
 354                                    &state->alloc);
 355         radv_DestroyPipelineLayout(radv_device_to_handle(device),
 356                                    state->clear_depth_p_layout,
 357                                    &state->alloc);
 358
 359         finish_meta_clear_htile_mask_state(device);
 360 }
 361
 362 static void
 363 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
 364                  const VkClearAttachment *clear_att,
 365                  const VkClearRect *clear_rect,
 366                  uint32_t view_mask)
 367 {
 368         struct radv_device *device = cmd_buffer->device;
 369         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 370         const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
 371         const uint32_t subpass_att = clear_att->colorAttachment;
 372         const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
 373         const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
 374         uint32_t samples, samples_log2;
 375         VkFormat format;
 376         unsigned fs_key;
 377         VkClearColorValue clear_value = clear_att->clearValue.color;
 378         VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
 379         VkPipeline pipeline;
 380
 381         /* When a framebuffer is bound to the current command buffer, get the
 382          * number of samples from it. Otherwise, get the number of samples from
 383          * the render pass because it's likely a secondary command buffer.
 384          */
 385         if (iview) {
 386                 samples = iview->image->info.samples;
 387                 format = iview->vk_format;
 388         } else {
 389                 samples = cmd_buffer->state.pass->attachments[pass_att].samples;
 390                 format = cmd_buffer->state.pass->attachments[pass_att].format;
 391         }
 392
 393         samples_log2 = ffs(samples) - 1;
 394         fs_key = radv_format_meta_fs_key(format);
 395
 396         if (fs_key == -1) {
 397                 radv_finishme("color clears incomplete");
 398                 return;
 399         }
 400
 401         if (device->meta_state.clear[samples_log2].render_pass[fs_key] == VK_NULL_HANDLE) {
 402                 VkResult ret = create_color_renderpass(device, radv_fs_key_format_exemplars[fs_key],
 403                                                        samples,
 404                                                        &device->meta_state.clear[samples_log2].render_pass[fs_key]);
 405                 if (ret != VK_SUCCESS) {
 406                         cmd_buffer->record_result = ret;
 407                         return;
 408                 }
 409         }
 410
 411         if (device->meta_state.clear[samples_log2].color_pipelines[fs_key] == VK_NULL_HANDLE) {
 412                 VkResult ret = create_color_pipeline(device, samples, 0,
 413                                                      &device->meta_state.clear[samples_log2].color_pipelines[fs_key],
 414                                                      device->meta_state.clear[samples_log2].render_pass[fs_key]);
 415                 if (ret != VK_SUCCESS) {
 416                         cmd_buffer->record_result = ret;
 417                         return;
 418                 }
 419         }
 420
 421         pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
 422         if (!pipeline) {
 423                 radv_finishme("color clears incomplete");
 424                 return;
 425         }
 426         assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
 427         assert(pipeline);
 428         assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
 429         assert(clear_att->colorAttachment < subpass->color_count);
 430
 431         radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
 432                               device->meta_state.clear_color_p_layout,
 433                               VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
 434                               &clear_value);
 435
 436         struct radv_subpass clear_subpass = {
 437                 .color_count = 1,
 438                 .color_attachments = (struct radv_subpass_attachment[]) {
 439                         subpass->color_attachments[clear_att->colorAttachment]
 440                 },
 441                 .depth_stencil_attachment = NULL,
 442         };
 443
 444         radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass);
 445
 446         radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
 447                              pipeline);
 448
 449         radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
 450                         .x = clear_rect->rect.offset.x,
 451                         .y = clear_rect->rect.offset.y,
 452                         .width = clear_rect->rect.extent.width,
 453                         .height = clear_rect->rect.extent.height,
 454                         .minDepth = 0.0f,
 455                         .maxDepth = 1.0f
 456                 });
 457
 458         radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
 459
 460         if (view_mask) {
 461                 unsigned i;
 462                 for_each_bit(i, view_mask)
 463                         radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
 464         } else {
 465                 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
 466         }
 467
 468         radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
 469 }
 470
 471
 472 static void
 473 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
 474 {
 475         nir_builder vs_b, fs_b;
 476
 477         nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
 478         nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
 479
 480         vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
 481         fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
 482         const struct glsl_type *position_out_type = glsl_vec4_type();
 483
 484         nir_variable *vs_out_pos =
 485                 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
 486                                     "gl_Position");
 487         vs_out_pos->data.location = VARYING_SLOT_POS;
 488
 489         nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
 490         nir_intrinsic_set_base(in_color_load, 0);
 491         nir_intrinsic_set_range(in_color_load, 4);
 492         in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
 493         in_color_load->num_components = 1;
 494         nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
 495         nir_builder_instr_insert(&vs_b, &in_color_load->instr);
 496
 497         nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
 498         nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
 499
 500         const struct glsl_type *layer_type = glsl_int_type();
 501         nir_variable *vs_out_layer =
 502                 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
 503                                     "v_layer");
 504         vs_out_layer->data.location = VARYING_SLOT_LAYER;
 505         vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
 506         nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
 507         nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
 508
 509         nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
 510         nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
 511
 512         *out_vs = vs_b.shader;
 513         *out_fs = fs_b.shader;
 514 }
 515
 516 static VkResult
 517 create_depthstencil_renderpass(struct radv_device *device,
 518                                uint32_t samples,
 519                                VkRenderPass *render_pass)
 520 {
 521         mtx_lock(&device->meta_state.mtx);
 522         if (*render_pass) {
 523                 mtx_unlock(&device->meta_state.mtx);
 524                 return VK_SUCCESS;
 525         }
 526
 527         VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
 528                                        &(VkRenderPassCreateInfo) {
 529                                                .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
 530                                                        .attachmentCount = 1,
 531                                                        .pAttachments = &(VkAttachmentDescription) {
 532                                                        .format = VK_FORMAT_D32_SFLOAT_S8_UINT,
 533                                                        .samples = samples,
 534                                                        .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
 535                                                        .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
 536                                                        .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
 537                                                        .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
 538                                                },
 539                                                        .subpassCount = 1,
 540                                                                 .pSubpasses = &(VkSubpassDescription) {
 541                                                        .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
 542                                                        .inputAttachmentCount = 0,
 543                                                        .colorAttachmentCount = 0,
 544                                                        .pColorAttachments = NULL,
 545                                                        .pResolveAttachments = NULL,
 546                                                        .pDepthStencilAttachment = &(VkAttachmentReference) {
 547                                                                .attachment = 0,
 548                                                                .layout = VK_IMAGE_LAYOUT_GENERAL,
 549                                                        },
 550                                                        .preserveAttachmentCount = 0,
 551                                                        .pPreserveAttachments = NULL,
 552                                                },
 553                                                                 .dependencyCount = 0,
 554                                                                          }, &device->meta_state.alloc, render_pass);
 555         mtx_unlock(&device->meta_state.mtx);
 556         return result;
 557 }
 558
 559 static VkResult
 560 create_depthstencil_pipeline(struct radv_device *device,
 561                              VkImageAspectFlags aspects,
 562                              uint32_t samples,
 563                              int index,
 564                              VkPipeline *pipeline,
 565                              VkRenderPass render_pass)
 566 {
 567         struct nir_shader *vs_nir, *fs_nir;
 568         VkResult result;
 569
 570         mtx_lock(&device->meta_state.mtx);
 571         if (*pipeline) {
 572                 mtx_unlock(&device->meta_state.mtx);
 573                 return VK_SUCCESS;
 574         }
 575
 576         build_depthstencil_shader(&vs_nir, &fs_nir);
 577
 578         const VkPipelineVertexInputStateCreateInfo vi_state = {
 579                 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
 580                 .vertexBindingDescriptionCount = 0,
 581                 .vertexAttributeDescriptionCount = 0,
 582         };
 583
 584         const VkPipelineDepthStencilStateCreateInfo ds_state = {
 585                 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
 586                 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
 587                 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
 588                 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
 589                 .depthBoundsTestEnable = false,
 590                 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
 591                 .front = {
 592                         .passOp = VK_STENCIL_OP_REPLACE,
 593                         .compareOp = VK_COMPARE_OP_ALWAYS,
 594                         .writeMask = UINT32_MAX,
 595                         .reference = 0, /* dynamic */
 596                 },
 597                 .back = { 0 /* dont care */ },
 598         };
 599
 600         const VkPipelineColorBlendStateCreateInfo cb_state = {
 601                 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
 602                 .logicOpEnable = false,
 603                 .attachmentCount = 0,
 604                 .pAttachments = NULL,
 605         };
 606
 607         struct radv_graphics_pipeline_create_info extra = {
 608                 .use_rectlist = true,
 609         };
 610
 611         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
 612                 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
 613                 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
 614         }
 615         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
 616                 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
 617                 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
 618         }
 619         result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
 620                                  samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
 621                                  device->meta_state.clear_depth_p_layout,
 622                                  &extra, &device->meta_state.alloc, pipeline);
 623
 624         mtx_unlock(&device->meta_state.mtx);
 625         return result;
 626 }
 627
 628 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
 629                                       const struct radv_image_view *iview,
 630                                       VkImageAspectFlags aspects,
 631                                       VkImageLayout layout,
 632                                       const VkClearRect *clear_rect,
 633                                       VkClearDepthStencilValue clear_value)
 634 {
 635         if (!iview)
 636                 return false;
 637
 638         uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
 639                                                            cmd_buffer->queue_family_index,
 640                                                            cmd_buffer->queue_family_index);
 641         if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
 642             clear_rect->rect.extent.width != iview->extent.width ||
 643             clear_rect->rect.extent.height != iview->extent.height)
 644                 return false;
 645         if (radv_image_is_tc_compat_htile(iview->image) &&
 646             (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && clear_value.depth != 0.0 &&
 647               clear_value.depth != 1.0) ||
 648              ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0)))
 649                 return false;
 650         if (radv_image_has_htile(iview->image) &&
 651             iview->base_mip == 0 &&
 652             iview->base_layer == 0 &&
 653             iview->layer_count == iview->image->info.array_size &&
 654             radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
 655             radv_image_extent_compare(iview->image, &iview->extent))
 656                 return true;
 657         return false;
 658 }
 659
 660 static VkPipeline
 661 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
 662                            struct radv_meta_state *meta_state,
 663                            const struct radv_image_view *iview,
 664                            int samples_log2,
 665                            VkImageAspectFlags aspects,
 666                            VkImageLayout layout,
 667                            const VkClearRect *clear_rect,
 668                            VkClearDepthStencilValue clear_value)
 669 {
 670         bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, clear_rect, clear_value);
 671         int index = DEPTH_CLEAR_SLOW;
 672         VkPipeline *pipeline;
 673
 674         if (fast) {
 675                 /* we don't know the previous clear values, so we always have
 676                  * the NO_EXPCLEAR path */
 677                 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
 678         }
 679
 680         switch (aspects) {
 681         case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
 682                 pipeline = &meta_state->clear[samples_log2].depthstencil_pipeline[index];
 683                 break;
 684         case VK_IMAGE_ASPECT_DEPTH_BIT:
 685                 pipeline = &meta_state->clear[samples_log2].depth_only_pipeline[index];
 686                 break;
 687         case VK_IMAGE_ASPECT_STENCIL_BIT:
 688                 pipeline = &meta_state->clear[samples_log2].stencil_only_pipeline[index];
 689                 break;
 690         default:
 691                 unreachable("expected depth or stencil aspect");
 692         }
 693
 694         if (cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp == VK_NULL_HANDLE) {
 695                 VkResult ret = create_depthstencil_renderpass(cmd_buffer->device, 1u << samples_log2,
 696                                                               &cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
 697                 if (ret != VK_SUCCESS) {
 698                         cmd_buffer->record_result = ret;
 699                         return VK_NULL_HANDLE;
 700                 }
 701         }
 702
 703         if (*pipeline == VK_NULL_HANDLE) {
 704                 VkResult ret = create_depthstencil_pipeline(cmd_buffer->device, aspects, 1u << samples_log2, index,
 705                                                             pipeline, cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
 706                 if (ret != VK_SUCCESS) {
 707                         cmd_buffer->record_result = ret;
 708                         return VK_NULL_HANDLE;
 709                 }
 710         }
 711         return *pipeline;
 712 }
 713
 714 static void
 715 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
 716                         const VkClearAttachment *clear_att,
 717                         const VkClearRect *clear_rect,
 718                         struct radv_subpass_attachment *ds_att,
 719                         uint32_t view_mask)
 720 {
 721         struct radv_device *device = cmd_buffer->device;
 722         struct radv_meta_state *meta_state = &device->meta_state;
 723         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 724         const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
 725         const uint32_t pass_att = ds_att->attachment;
 726         VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
 727         VkImageAspectFlags aspects = clear_att->aspectMask;
 728         const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
 729         uint32_t samples, samples_log2;
 730         VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
 731
 732         /* When a framebuffer is bound to the current command buffer, get the
 733          * number of samples from it. Otherwise, get the number of samples from
 734          * the render pass because it's likely a secondary command buffer.
 735          */
 736         if (iview) {
 737                 samples = iview->image->info.samples;
 738         } else {
 739                 samples = cmd_buffer->state.pass->attachments[pass_att].samples;
 740         }
 741
 742         samples_log2 = ffs(samples) - 1;
 743
 744         assert(pass_att != VK_ATTACHMENT_UNUSED);
 745
 746         if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
 747                 clear_value.depth = 1.0f;
 748
 749         radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
 750                               device->meta_state.clear_depth_p_layout,
 751                               VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
 752                               &clear_value.depth);
 753
 754         uint32_t prev_reference = cmd_buffer->state.dynamic.stencil_reference.front;
 755         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
 756                 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
 757                                                   clear_value.stencil);
 758         }
 759
 760         VkPipeline pipeline = pick_depthstencil_pipeline(cmd_buffer,
 761                                                          meta_state,
 762                                                          iview,
 763                                                          samples_log2,
 764                                                          aspects,
 765                                                          ds_att->layout,
 766                                                          clear_rect,
 767                                                          clear_value);
 768         if (!pipeline)
 769                 return;
 770
 771         struct radv_subpass clear_subpass = {
 772                 .color_count = 0,
 773                 .color_attachments = NULL,
 774                 .depth_stencil_attachment = ds_att,
 775         };
 776
 777         radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass);
 778
 779         radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
 780                              pipeline);
 781
 782         if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
 783                                       ds_att->layout, clear_rect, clear_value))
 784                 radv_update_ds_clear_metadata(cmd_buffer, iview->image,
 785                                               clear_value, aspects);
 786
 787         radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
 788                         .x = clear_rect->rect.offset.x,
 789                         .y = clear_rect->rect.offset.y,
 790                         .width = clear_rect->rect.extent.width,
 791                         .height = clear_rect->rect.extent.height,
 792                         .minDepth = 0.0f,
 793                         .maxDepth = 1.0f
 794                 });
 795
 796         radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
 797
 798         if (view_mask) {
 799                 unsigned i;
 800                 for_each_bit(i, view_mask)
 801                         radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
 802         } else {
 803                 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
 804         }
 805
 806         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
 807                 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
 808                                                   prev_reference);
 809         }
 810
 811         radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
 812 }
 813
 814 static uint32_t
 815 clear_htile_mask(struct radv_cmd_buffer *cmd_buffer,
 816                  struct radeon_winsys_bo *bo, uint64_t offset, uint64_t size,
 817                  uint32_t htile_value, uint32_t htile_mask)
 818 {
 819         struct radv_device *device = cmd_buffer->device;
 820         struct radv_meta_state *state = &device->meta_state;
 821         uint64_t block_count = round_up_u64(size, 1024);
 822         struct radv_meta_saved_state saved_state;
 823
 824         radv_meta_save(&saved_state, cmd_buffer,
 825                        RADV_META_SAVE_COMPUTE_PIPELINE |
 826                        RADV_META_SAVE_CONSTANTS |
 827                        RADV_META_SAVE_DESCRIPTORS);
 828
 829         struct radv_buffer dst_buffer = {
 830                 .bo = bo,
 831                 .offset = offset,
 832                 .size = size
 833         };
 834
 835         radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
 836                              VK_PIPELINE_BIND_POINT_COMPUTE,
 837                              state->clear_htile_mask_pipeline);
 838
 839         radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
 840                                       state->clear_htile_mask_p_layout,
 841                                       0, /* set */
 842                                       1, /* descriptorWriteCount */
 843                                       (VkWriteDescriptorSet[]) {
 844                                               {
 845                                                       .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
 846                                                       .dstBinding = 0,
 847                                                       .dstArrayElement = 0,
 848                                                       .descriptorCount = 1,
 849                                                       .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
 850                                                       .pBufferInfo = &(VkDescriptorBufferInfo) {
 851                                                               .buffer = radv_buffer_to_handle(&dst_buffer),
 852                                                               .offset = 0,
 853                                                               .range = size
 854                                                       }
 855                                               }
 856                                       });
 857
 858         const unsigned constants[2] = {
 859                 htile_value & htile_mask,
 860                 ~htile_mask,
 861         };
 862
 863         radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
 864                               state->clear_htile_mask_p_layout,
 865                               VK_SHADER_STAGE_COMPUTE_BIT, 0, 8,
 866                               constants);
 867
 868         radv_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer), block_count, 1, 1);
 869
 870         radv_meta_restore(&saved_state, cmd_buffer);
 871
 872         return RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
 873                RADV_CMD_FLAG_INV_VMEM_L1 |
 874                RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
 875 }
 876
 877 static uint32_t
 878 radv_get_htile_fast_clear_value(const struct radv_image *image,
 879                                 VkClearDepthStencilValue value)
 880 {
 881         uint32_t clear_value;
 882
 883         if (!image->planes[0].surface.has_stencil) {
 884                 clear_value = value.depth ? 0xfffffff0 : 0;
 885         } else {
 886                 clear_value = value.depth ? 0xfffc0000 : 0;
 887         }
 888
 889         return clear_value;
 890 }
 891
 892 static uint32_t
 893 radv_get_htile_mask(const struct radv_image *image, VkImageAspectFlags aspects)
 894 {
 895         uint32_t mask = 0;
 896
 897         if (!image->planes[0].surface.has_stencil) {
 898                 /* All the HTILE buffer is used when there is no stencil. */
 899                 mask = UINT32_MAX;
 900         } else {
 901                 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
 902                         mask |= 0xfffffc0f;
 903                 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
 904                         mask |= 0x000003f0;
 905         }
 906
 907         return mask;
 908 }
 909
 910 static bool
 911 radv_is_fast_clear_depth_allowed(VkClearDepthStencilValue value)
 912 {
 913         return value.depth == 1.0f || value.depth == 0.0f;
 914 }
 915
 916 static bool
 917 radv_is_fast_clear_stencil_allowed(VkClearDepthStencilValue value)
 918 {
 919         return value.stencil == 0;
 920 }
 921
 922 /**
 923  * Determine if the given image can be fast cleared.
 924  */
 925 static bool
 926 radv_image_can_fast_clear(struct radv_device *device,  struct radv_image *image)
 927 {
 928         if (device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
 929                 return false;
 930
 931         if (vk_format_is_color(image->vk_format)) {
 932                 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
 933                         return false;
 934
 935                 /* RB+ doesn't work with CMASK fast clear on Stoney. */
 936                 if (!radv_image_has_dcc(image) &&
 937                     device->physical_device->rad_info.family == CHIP_STONEY)
 938                         return false;
 939         } else {
 940                 if (!radv_image_has_htile(image))
 941                         return false;
 942         }
 943
 944         /* Do not fast clears 3D images. */
 945         if (image->type == VK_IMAGE_TYPE_3D)
 946                 return false;
 947
 948         return true;
 949 }
 950
 951 /**
 952  * Determine if the given image view can be fast cleared.
 953  */
 954 static bool
 955 radv_image_view_can_fast_clear(struct radv_device *device,
 956                                const struct radv_image_view *iview)
 957 {
 958         struct radv_image *image;
 959
 960         if (!iview)
 961                 return false;
 962         image = iview->image;
 963
 964         /* Only fast clear if the image itself can be fast cleared. */
 965         if (!radv_image_can_fast_clear(device, image))
 966                 return false;
 967
 968         /* Only fast clear if all layers are bound. */
 969         if (iview->base_layer > 0 ||
 970             iview->layer_count != image->info.array_size)
 971                 return false;
 972
 973         /* Only fast clear if the view covers the whole image. */
 974         if (!radv_image_extent_compare(image, &iview->extent))
 975                 return false;
 976
 977         return true;
 978 }
 979
 980 static bool
 981 radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer,
 982                           const struct radv_image_view *iview,
 983                           VkImageLayout image_layout,
 984                           VkImageAspectFlags aspects,
 985                           const VkClearRect *clear_rect,
 986                           const VkClearDepthStencilValue clear_value,
 987                           uint32_t view_mask)
 988 {
 989         if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview))
 990                 return false;
 991
 992         if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
 993                 return false;
 994
 995         if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
 996             clear_rect->rect.extent.width != iview->image->info.width ||
 997             clear_rect->rect.extent.height != iview->image->info.height)
 998                 return false;
 999
1000         if (view_mask && (iview->image->info.array_size >= 32 ||
1001                          (1u << iview->image->info.array_size) - 1u != view_mask))
1002                 return false;
1003         if (!view_mask && clear_rect->baseArrayLayer != 0)
1004                 return false;
1005         if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
1006                 return false;
1007
1008         if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 &&
1009             (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT) ||
1010             ((vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1011              !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))))
1012                 return false;
1013
1014         if (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1015             !radv_is_fast_clear_depth_allowed(clear_value)) ||
1016             ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1017              !radv_is_fast_clear_stencil_allowed(clear_value)))
1018                 return false;
1019
1020         return true;
1021 }
1022
1023 static void
1024 radv_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer,
1025                       const struct radv_image_view *iview,
1026                       const VkClearAttachment *clear_att,
1027                       enum radv_cmd_flush_bits *pre_flush,
1028                       enum radv_cmd_flush_bits *post_flush)
1029 {
1030         VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
1031         VkImageAspectFlags aspects = clear_att->aspectMask;
1032         uint32_t clear_word, flush_bits;
1033         uint32_t htile_mask;
1034
1035         clear_word = radv_get_htile_fast_clear_value(iview->image, clear_value);
1036         htile_mask = radv_get_htile_mask(iview->image, aspects);
1037
1038         if (pre_flush) {
1039                 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1040                                                  RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
1041                 *pre_flush |= cmd_buffer->state.flush_bits;
1042         }
1043
1044         if (htile_mask == UINT_MAX) {
1045                 /* Clear the whole HTILE buffer. */
1046                 flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
1047                                               iview->image->offset + iview->image->htile_offset,
1048                                               iview->image->planes[0].surface.htile_size, clear_word);
1049         } else {
1050                 /* Only clear depth or stencil bytes in the HTILE buffer. */
1051                 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9);
1052                 flush_bits = clear_htile_mask(cmd_buffer, iview->image->bo,
1053                                               iview->image->offset + iview->image->htile_offset,
1054                                               iview->image->planes[0].surface.htile_size, clear_word,
1055                                               htile_mask);
1056         }
1057
1058         radv_update_ds_clear_metadata(cmd_buffer, iview->image, clear_value, aspects);
1059         if (post_flush) {
1060                 *post_flush |= flush_bits;
1061         }
1062 }
1063
1064 static nir_shader *
1065 build_clear_htile_mask_shader()
1066 {
1067         nir_builder b;
1068
1069         nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
1070         b.shader->info.name = ralloc_strdup(b.shader, "meta_clear_htile_mask");
1071         b.shader->info.cs.local_size[0] = 64;
1072         b.shader->info.cs.local_size[1] = 1;
1073         b.shader->info.cs.local_size[2] = 1;
1074
1075         nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
1076         nir_ssa_def *wg_id = nir_load_work_group_id(&b);
1077         nir_ssa_def *block_size = nir_imm_ivec4(&b,
1078                                                 b.shader->info.cs.local_size[0],
1079                                                 b.shader->info.cs.local_size[1],
1080                                                 b.shader->info.cs.local_size[2], 0);
1081
1082         nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
1083
1084         nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16));
1085         offset = nir_channel(&b, offset, 0);
1086
1087         nir_intrinsic_instr *buf =
1088                 nir_intrinsic_instr_create(b.shader,
1089                                            nir_intrinsic_vulkan_resource_index);
1090
1091         buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
1092         buf->num_components = 1;
1093         nir_intrinsic_set_desc_set(buf, 0);
1094         nir_intrinsic_set_binding(buf, 0);
1095         nir_ssa_dest_init(&buf->instr, &buf->dest, buf->num_components, 32, NULL);
1096         nir_builder_instr_insert(&b, &buf->instr);
1097
1098         nir_intrinsic_instr *constants =
1099                 nir_intrinsic_instr_create(b.shader,
1100                                            nir_intrinsic_load_push_constant);
1101         nir_intrinsic_set_base(constants, 0);
1102         nir_intrinsic_set_range(constants, 8);
1103         constants->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
1104         constants->num_components = 2;
1105         nir_ssa_dest_init(&constants->instr, &constants->dest, 2, 32, "constants");
1106         nir_builder_instr_insert(&b, &constants->instr);
1107
1108         nir_intrinsic_instr *load =
1109                 nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
1110         load->src[0] = nir_src_for_ssa(&buf->dest.ssa);
1111         load->src[1] = nir_src_for_ssa(offset);
1112         nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
1113         load->num_components = 4;
1114         nir_builder_instr_insert(&b, &load->instr);
1115
1116         /* data = (data & ~htile_mask) | (htile_value & htile_mask) */
1117         nir_ssa_def *data =
1118                 nir_iand(&b, &load->dest.ssa,
1119                          nir_channel(&b, &constants->dest.ssa, 1));
1120         data = nir_ior(&b, data, nir_channel(&b, &constants->dest.ssa, 0));
1121
1122         nir_intrinsic_instr *store =
1123                 nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
1124         store->src[0] = nir_src_for_ssa(data);
1125         store->src[1] = nir_src_for_ssa(&buf->dest.ssa);
1126         store->src[2] = nir_src_for_ssa(offset);
1127         nir_intrinsic_set_write_mask(store, 0xf);
1128         nir_intrinsic_set_access(store, ACCESS_NON_READABLE);
1129         store->num_components = 4;
1130         nir_builder_instr_insert(&b, &store->instr);
1131
1132         return b.shader;
1133 }
1134
1135 static VkResult
1136 init_meta_clear_htile_mask_state(struct radv_device *device)
1137 {
1138         struct radv_meta_state *state = &device->meta_state;
1139         struct radv_shader_module cs = { .nir = NULL };
1140         VkResult result;
1141
1142         cs.nir = build_clear_htile_mask_shader();
1143
1144         VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1145                 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1146                 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1147                 .bindingCount = 1,
1148                 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1149                         {
1150                                 .binding = 0,
1151                                 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
1152                                 .descriptorCount = 1,
1153                                 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
1154                                 .pImmutableSamplers = NULL
1155                         },
1156                 }
1157         };
1158
1159         result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1160                                                 &ds_layout_info, &state->alloc,
1161                                                 &state->clear_htile_mask_ds_layout);
1162         if (result != VK_SUCCESS)
1163                 goto fail;
1164
1165         VkPipelineLayoutCreateInfo p_layout_info = {
1166                 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1167                 .setLayoutCount = 1,
1168                 .pSetLayouts = &state->clear_htile_mask_ds_layout,
1169                 .pushConstantRangeCount = 1,
1170                 .pPushConstantRanges = &(VkPushConstantRange){
1171                         VK_SHADER_STAGE_COMPUTE_BIT, 0, 8,
1172                 },
1173         };
1174
1175         result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1176                                           &p_layout_info, &state->alloc,
1177                                           &state->clear_htile_mask_p_layout);
1178         if (result != VK_SUCCESS)
1179                 goto fail;
1180
1181         VkPipelineShaderStageCreateInfo shader_stage = {
1182                 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1183                 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
1184                 .module = radv_shader_module_to_handle(&cs),
1185                 .pName = "main",
1186                 .pSpecializationInfo = NULL,
1187         };
1188
1189         VkComputePipelineCreateInfo pipeline_info = {
1190                 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
1191                 .stage = shader_stage,
1192                 .flags = 0,
1193                 .layout = state->clear_htile_mask_p_layout,
1194         };
1195
1196         result = radv_CreateComputePipelines(radv_device_to_handle(device),
1197                                              radv_pipeline_cache_to_handle(&state->cache),
1198                                              1, &pipeline_info, NULL,
1199                                              &state->clear_htile_mask_pipeline);
1200
1201         ralloc_free(cs.nir);
1202         return result;
1203 fail:
1204         ralloc_free(cs.nir);
1205         return result;
1206 }
1207
1208 VkResult
1209 radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand)
1210 {
1211         VkResult res;
1212         struct radv_meta_state *state = &device->meta_state;
1213
1214         VkPipelineLayoutCreateInfo pl_color_create_info = {
1215                 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1216                 .setLayoutCount = 0,
1217                 .pushConstantRangeCount = 1,
1218                 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
1219         };
1220
1221         res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1222                                         &pl_color_create_info,
1223                                         &device->meta_state.alloc,
1224                                         &device->meta_state.clear_color_p_layout);
1225         if (res != VK_SUCCESS)
1226                 goto fail;
1227
1228         VkPipelineLayoutCreateInfo pl_depth_create_info = {
1229                 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1230                 .setLayoutCount = 0,
1231                 .pushConstantRangeCount = 1,
1232                 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
1233         };
1234
1235         res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1236                                         &pl_depth_create_info,
1237                                         &device->meta_state.alloc,
1238                                         &device->meta_state.clear_depth_p_layout);
1239         if (res != VK_SUCCESS)
1240                 goto fail;
1241
1242         res = init_meta_clear_htile_mask_state(device);
1243         if (res != VK_SUCCESS)
1244                 goto fail;
1245
1246         if (on_demand)
1247                 return VK_SUCCESS;
1248
1249         for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
1250                 uint32_t samples = 1 << i;
1251                 for (uint32_t j = 0; j < NUM_META_FS_KEYS; ++j) {
1252                         VkFormat format = radv_fs_key_format_exemplars[j];
1253                         unsigned fs_key = radv_format_meta_fs_key(format);
1254                         assert(!state->clear[i].color_pipelines[fs_key]);
1255
1256                         res = create_color_renderpass(device, format, samples,
1257                                                       &state->clear[i].render_pass[fs_key]);
1258                         if (res != VK_SUCCESS)
1259                                 goto fail;
1260
1261                         res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
1262                                                     state->clear[i].render_pass[fs_key]);
1263                         if (res != VK_SUCCESS)
1264                                 goto fail;
1265
1266                 }
1267
1268                 res = create_depthstencil_renderpass(device,
1269                                                      samples,
1270                                                      &state->clear[i].depthstencil_rp);
1271                 if (res != VK_SUCCESS)
1272                         goto fail;
1273
1274                 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
1275                         res = create_depthstencil_pipeline(device,
1276                                                            VK_IMAGE_ASPECT_DEPTH_BIT,
1277                                                            samples,
1278                                                            j,
1279                                                            &state->clear[i].depth_only_pipeline[j],
1280                                                            state->clear[i].depthstencil_rp);
1281                         if (res != VK_SUCCESS)
1282                                 goto fail;
1283
1284                         res = create_depthstencil_pipeline(device,
1285                                                            VK_IMAGE_ASPECT_STENCIL_BIT,
1286                                                            samples,
1287                                                            j,
1288                                                            &state->clear[i].stencil_only_pipeline[j],
1289                                                            state->clear[i].depthstencil_rp);
1290                         if (res != VK_SUCCESS)
1291                                 goto fail;
1292
1293                         res = create_depthstencil_pipeline(device,
1294                                                            VK_IMAGE_ASPECT_DEPTH_BIT |
1295                                                            VK_IMAGE_ASPECT_STENCIL_BIT,
1296                                                            samples,
1297                                                            j,
1298                                                            &state->clear[i].depthstencil_pipeline[j],
1299                                                            state->clear[i].depthstencil_rp);
1300                         if (res != VK_SUCCESS)
1301                                 goto fail;
1302                 }
1303         }
1304         return VK_SUCCESS;
1305
1306 fail:
1307         radv_device_finish_meta_clear_state(device);
1308         return res;
1309 }
1310
1311 static uint32_t
1312 radv_get_cmask_fast_clear_value(const struct radv_image *image)
1313 {
1314         uint32_t value = 0; /* Default value when no DCC. */
1315
1316         /* The fast-clear value is different for images that have both DCC and
1317          * CMASK metadata.
1318          */
1319         if (radv_image_has_dcc(image)) {
1320                 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
1321                 return image->info.samples > 1 ? 0xcccccccc : 0xffffffff;
1322         }
1323
1324         return value;
1325 }
1326
1327 uint32_t
1328 radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
1329                  struct radv_image *image,
1330                  const VkImageSubresourceRange *range, uint32_t value)
1331 {
1332         uint64_t offset = image->offset + image->cmask.offset;
1333         uint64_t size;
1334
1335         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1336                 /* TODO: clear layers. */
1337                 size = image->cmask.size;
1338         } else {
1339                 offset += image->cmask.slice_size * range->baseArrayLayer;
1340                 size = image->cmask.slice_size * radv_get_layerCount(image, range);
1341         }
1342
1343         return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
1344 }
1345
1346
1347 uint32_t
1348 radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
1349                  struct radv_image *image,
1350                  const VkImageSubresourceRange *range, uint32_t value)
1351 {
1352         uint64_t offset = image->offset + image->fmask.offset;
1353         uint64_t size;
1354
1355         /* MSAA images do not support mipmap levels. */
1356         assert(range->baseMipLevel == 0 &&
1357                radv_get_levelCount(image, range) == 1);
1358
1359         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1360                 /* TODO: clear layers. */
1361                 size = image->fmask.size;
1362         } else {
1363                 offset += image->fmask.slice_size * range->baseArrayLayer;
1364                 size = image->fmask.slice_size * radv_get_layerCount(image, range);
1365         }
1366
1367         return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
1368 }
1369
1370 uint32_t
1371 radv_dcc_clear_level(struct radv_cmd_buffer *cmd_buffer,
1372                      const struct radv_image *image,
1373                      uint32_t level, uint32_t value)
1374 {
1375         uint64_t offset = image->offset + image->dcc_offset;
1376         uint32_t size;
1377
1378         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1379                 /* Mipmap levels aren't implemented. */
1380                 assert(level == 0);
1381                 size = image->planes[0].surface.dcc_size;
1382         } else {
1383                 const struct legacy_surf_level *surf_level =
1384                         &image->planes[0].surface.u.legacy.level[level];
1385
1386                 /* If this is 0, fast clear isn't possible. */
1387                 assert(surf_level->dcc_fast_clear_size);
1388
1389                 offset += surf_level->dcc_offset;
1390                 size = surf_level->dcc_fast_clear_size;
1391         }
1392
1393         return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
1394 }
1395
1396 uint32_t
1397 radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
1398                struct radv_image *image,
1399                const VkImageSubresourceRange *range, uint32_t value)
1400 {
1401         uint32_t level_count = radv_get_levelCount(image, range);
1402         uint32_t flush_bits = 0;
1403
1404         /* Mark the image as being compressed. */
1405         radv_update_dcc_metadata(cmd_buffer, image, range, true);
1406
1407         for (uint32_t l = 0; l < level_count; l++) {
1408                 uint32_t level = range->baseMipLevel + l;
1409
1410                 flush_bits |= radv_dcc_clear_level(cmd_buffer, image,
1411                                                    level, value);
1412         }
1413
1414         return flush_bits;
1415 }
1416
1417 uint32_t
1418 radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
1419                  const VkImageSubresourceRange *range, uint32_t value)
1420 {
1421         unsigned layer_count = radv_get_layerCount(image, range);
1422         uint64_t size = image->planes[0].surface.htile_slice_size * layer_count;
1423         uint64_t offset = image->offset + image->htile_offset +
1424                           image->planes[0].surface.htile_slice_size * range->baseArrayLayer;
1425
1426         return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
1427 }
1428
1429 static void vi_get_fast_clear_parameters(VkFormat format,
1430                                          const VkClearColorValue *clear_value,
1431                                          uint32_t* reset_value,
1432                                          bool *can_avoid_fast_clear_elim)
1433 {
1434         bool values[4] = {};
1435         int extra_channel;
1436         bool main_value = false;
1437         bool extra_value = false;
1438         int i;
1439         *can_avoid_fast_clear_elim = false;
1440
1441         *reset_value = 0x20202020U;
1442
1443         const struct vk_format_description *desc = vk_format_description(format);
1444         if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
1445             format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
1446             format == VK_FORMAT_B5G6R5_UNORM_PACK16)
1447                 extra_channel = -1;
1448         else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
1449                 if (radv_translate_colorswap(format, false) <= 1)
1450                         extra_channel = desc->nr_channels - 1;
1451                 else
1452                         extra_channel = 0;
1453         } else
1454                 return;
1455
1456         for (i = 0; i < 4; i++) {
1457                 int index = desc->swizzle[i] - VK_SWIZZLE_X;
1458                 if (desc->swizzle[i] < VK_SWIZZLE_X ||
1459                     desc->swizzle[i] > VK_SWIZZLE_W)
1460                         continue;
1461
1462                 if (desc->channel[i].pure_integer &&
1463                     desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
1464                         /* Use the maximum value for clamping the clear color. */
1465                         int max = u_bit_consecutive(0, desc->channel[i].size - 1);
1466
1467                         values[i] = clear_value->int32[i] != 0;
1468                         if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
1469                                 return;
1470                 } else if (desc->channel[i].pure_integer &&
1471                            desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
1472                         /* Use the maximum value for clamping the clear color. */
1473                         unsigned max = u_bit_consecutive(0, desc->channel[i].size);
1474
1475                         values[i] = clear_value->uint32[i] != 0U;
1476                         if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
1477                                 return;
1478                 } else {
1479                         values[i] = clear_value->float32[i] != 0.0F;
1480                         if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
1481                                 return;
1482                 }
1483
1484                 if (index == extra_channel)
1485                         extra_value = values[i];
1486                 else
1487                         main_value = values[i];
1488         }
1489
1490         for (int i = 0; i < 4; ++i)
1491                 if (values[i] != main_value &&
1492                     desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
1493                     desc->swizzle[i] >= VK_SWIZZLE_X &&
1494                     desc->swizzle[i] <= VK_SWIZZLE_W)
1495                         return;
1496
1497         *can_avoid_fast_clear_elim = true;
1498         if (main_value)
1499                 *reset_value |= 0x80808080U;
1500
1501         if (extra_value)
1502                 *reset_value |= 0x40404040U;
1503         return;
1504 }
1505
1506 static bool
1507 radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1508                           const struct radv_image_view *iview,
1509                           VkImageLayout image_layout,
1510                           const VkClearRect *clear_rect,
1511                           VkClearColorValue clear_value,
1512                           uint32_t view_mask)
1513 {
1514         uint32_t clear_color[2];
1515
1516         if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview))
1517                 return false;
1518
1519         if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
1520                 return false;
1521
1522         if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
1523             clear_rect->rect.extent.width != iview->image->info.width ||
1524             clear_rect->rect.extent.height != iview->image->info.height)
1525                 return false;
1526
1527         if (view_mask && (iview->image->info.array_size >= 32 ||
1528                          (1u << iview->image->info.array_size) - 1u != view_mask))
1529                 return false;
1530         if (!view_mask && clear_rect->baseArrayLayer != 0)
1531                 return false;
1532         if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
1533                 return false;
1534
1535         /* DCC */
1536         if (!radv_format_pack_clear_color(iview->vk_format,
1537                                           clear_color, &clear_value))
1538                 return false;
1539
1540         if (radv_dcc_enabled(iview->image, iview->base_mip)) {
1541                 bool can_avoid_fast_clear_elim;
1542                 uint32_t reset_value;
1543
1544                 vi_get_fast_clear_parameters(iview->vk_format,
1545                                              &clear_value, &reset_value,
1546                                              &can_avoid_fast_clear_elim);
1547
1548                 if (iview->image->info.samples > 1) {
1549                         /* DCC fast clear with MSAA should clear CMASK. */
1550                         /* FIXME: This doesn't work for now. There is a
1551                          * hardware bug with fast clears and DCC for MSAA
1552                          * textures. AMDVLK has a workaround but it doesn't
1553                          * seem to work here. Note that we might emit useless
1554                          * CB flushes but that shouldn't matter.
1555                          */
1556                         if (!can_avoid_fast_clear_elim)
1557                                 return false;
1558                 }
1559
1560                 if (iview->image->info.levels > 1 &&
1561                     cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
1562                         for (uint32_t l = 0; l < iview->level_count; l++) {
1563                                 uint32_t level = iview->base_mip + l;
1564                                 struct legacy_surf_level *surf_level =
1565                                         &iview->image->planes[0].surface.u.legacy.level[level];
1566
1567                                 /* Do not fast clears if one level can't be
1568                                  * fast cleared.
1569                                  */
1570                                 if (!surf_level->dcc_fast_clear_size)
1571                                         return false;
1572                         }
1573                 }
1574         }
1575
1576         return true;
1577 }
1578
1579
1580 static void
1581 radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1582                       const struct radv_image_view *iview,
1583                       const VkClearAttachment *clear_att,
1584                       uint32_t subpass_att,
1585                       enum radv_cmd_flush_bits *pre_flush,
1586                       enum radv_cmd_flush_bits *post_flush)
1587 {
1588         VkClearColorValue clear_value = clear_att->clearValue.color;
1589         uint32_t clear_color[2], flush_bits = 0;
1590         uint32_t cmask_clear_value;
1591         VkImageSubresourceRange range = {
1592                 .aspectMask = iview->aspect_mask,
1593                 .baseMipLevel = iview->base_mip,
1594                 .levelCount = iview->level_count,
1595                 .baseArrayLayer = iview->base_layer,
1596                 .layerCount = iview->layer_count,
1597         };
1598
1599         if (pre_flush) {
1600                 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1601                                                  RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
1602                 *pre_flush |= cmd_buffer->state.flush_bits;
1603         }
1604
1605         /* DCC */
1606         radv_format_pack_clear_color(iview->vk_format, clear_color, &clear_value);
1607
1608         cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
1609
1610         /* clear cmask buffer */
1611         if (radv_dcc_enabled(iview->image, iview->base_mip)) {
1612                 uint32_t reset_value;
1613                 bool can_avoid_fast_clear_elim;
1614                 bool need_decompress_pass = false;
1615
1616                 vi_get_fast_clear_parameters(iview->vk_format,
1617                                              &clear_value, &reset_value,
1618                                              &can_avoid_fast_clear_elim);
1619
1620                 if (radv_image_has_cmask(iview->image)) {
1621                         flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1622                                                       &range, cmask_clear_value);
1623
1624                         need_decompress_pass = true;
1625                 }
1626
1627                 if (!can_avoid_fast_clear_elim)
1628                         need_decompress_pass = true;
1629
1630                 flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, &range,
1631                                              reset_value);
1632
1633                 radv_update_fce_metadata(cmd_buffer, iview->image, &range,
1634                                          need_decompress_pass);
1635         } else {
1636                 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1637                                               &range, cmask_clear_value);
1638         }
1639
1640         if (post_flush) {
1641                 *post_flush |= flush_bits;
1642         }
1643
1644         radv_update_color_clear_metadata(cmd_buffer, iview, subpass_att,
1645                                          clear_color);
1646 }
1647
1648 /**
1649  * The parameters mean that same as those in vkCmdClearAttachments.
1650  */
1651 static void
1652 emit_clear(struct radv_cmd_buffer *cmd_buffer,
1653            const VkClearAttachment *clear_att,
1654            const VkClearRect *clear_rect,
1655            enum radv_cmd_flush_bits *pre_flush,
1656            enum radv_cmd_flush_bits *post_flush,
1657            uint32_t view_mask,
1658            bool ds_resolve_clear)
1659 {
1660         const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
1661         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1662         VkImageAspectFlags aspects = clear_att->aspectMask;
1663
1664         if (aspects & VK_IMAGE_ASPECT_COLOR_BIT) {
1665                 const uint32_t subpass_att = clear_att->colorAttachment;
1666                 assert(subpass_att < subpass->color_count);
1667                 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
1668                 if (pass_att == VK_ATTACHMENT_UNUSED)
1669                         return;
1670
1671                 VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
1672                 const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
1673                 VkClearColorValue clear_value = clear_att->clearValue.color;
1674
1675                 if (radv_can_fast_clear_color(cmd_buffer, iview, image_layout,
1676                                               clear_rect, clear_value, view_mask)) {
1677                         radv_fast_clear_color(cmd_buffer, iview, clear_att,
1678                                               subpass_att, pre_flush,
1679                                               post_flush);
1680                 } else {
1681                         emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask);
1682                 }
1683         } else {
1684                 struct radv_subpass_attachment *ds_att = subpass->depth_stencil_attachment;
1685
1686                 if (ds_resolve_clear)
1687                         ds_att = subpass->ds_resolve_attachment;
1688
1689                 if (ds_att->attachment == VK_ATTACHMENT_UNUSED)
1690                         return;
1691
1692                 VkImageLayout image_layout = ds_att->layout;
1693                 const struct radv_image_view *iview = fb ? fb->attachments[ds_att->attachment].attachment : NULL;
1694                 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
1695
1696                 assert(aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
1697                                   VK_IMAGE_ASPECT_STENCIL_BIT));
1698
1699                 if (radv_can_fast_clear_depth(cmd_buffer, iview, image_layout,
1700                                               aspects, clear_rect, clear_value,
1701                                               view_mask)) {
1702                         radv_fast_clear_depth(cmd_buffer, iview, clear_att,
1703                                               pre_flush, post_flush);
1704                 } else {
1705                         emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect,
1706                                                 ds_att, view_mask);
1707                 }
1708         }
1709 }
1710
1711 static inline bool
1712 radv_attachment_needs_clear(struct radv_cmd_state *cmd_state, uint32_t a)
1713 {
1714         uint32_t view_mask = cmd_state->subpass->view_mask;
1715         return (a != VK_ATTACHMENT_UNUSED &&
1716                 cmd_state->attachments[a].pending_clear_aspects &&
1717                 (!view_mask || (view_mask & ~cmd_state->attachments[a].cleared_views)));
1718 }
1719
1720 static bool
1721 radv_subpass_needs_clear(struct radv_cmd_buffer *cmd_buffer)
1722 {
1723         struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1724         uint32_t a;
1725
1726         if (!cmd_state->subpass)
1727                 return false;
1728
1729         for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1730                 a = cmd_state->subpass->color_attachments[i].attachment;
1731                 if (radv_attachment_needs_clear(cmd_state, a))
1732                         return true;
1733         }
1734
1735         if (cmd_state->subpass->depth_stencil_attachment) {
1736                 a = cmd_state->subpass->depth_stencil_attachment->attachment;
1737                 if (radv_attachment_needs_clear(cmd_state, a))
1738                         return true;
1739         }
1740
1741         if (!cmd_state->subpass->ds_resolve_attachment)
1742                 return false;
1743
1744         a = cmd_state->subpass->ds_resolve_attachment->attachment;
1745         return radv_attachment_needs_clear(cmd_state, a);
1746 }
1747
1748 static void
1749 radv_subpass_clear_attachment(struct radv_cmd_buffer *cmd_buffer,
1750                               struct radv_attachment_state *attachment,
1751                               const VkClearAttachment *clear_att,
1752                               enum radv_cmd_flush_bits *pre_flush,
1753                               enum radv_cmd_flush_bits *post_flush,
1754                               bool ds_resolve_clear)
1755 {
1756         struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1757         uint32_t view_mask = cmd_state->subpass->view_mask;
1758
1759         VkClearRect clear_rect = {
1760                 .rect = cmd_state->render_area,
1761                 .baseArrayLayer = 0,
1762                 .layerCount = cmd_state->framebuffer->layers,
1763         };
1764
1765         emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush,
1766                    view_mask & ~attachment->cleared_views, ds_resolve_clear);
1767         if (view_mask)
1768                 attachment->cleared_views |= view_mask;
1769         else
1770                 attachment->pending_clear_aspects = 0;
1771 }
1772
1773 /**
1774  * Emit any pending attachment clears for the current subpass.
1775  *
1776  * @see radv_attachment_state::pending_clear_aspects
1777  */
1778 void
1779 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1780 {
1781         struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1782         struct radv_meta_saved_state saved_state;
1783         enum radv_cmd_flush_bits pre_flush = 0;
1784         enum radv_cmd_flush_bits post_flush = 0;
1785
1786         if (!radv_subpass_needs_clear(cmd_buffer))
1787                 return;
1788
1789         radv_meta_save(&saved_state, cmd_buffer,
1790                        RADV_META_SAVE_GRAPHICS_PIPELINE |
1791                        RADV_META_SAVE_CONSTANTS);
1792
1793         for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1794                 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1795
1796                 if (!radv_attachment_needs_clear(cmd_state, a))
1797                         continue;
1798
1799                 assert(cmd_state->attachments[a].pending_clear_aspects ==
1800                        VK_IMAGE_ASPECT_COLOR_BIT);
1801
1802                 VkClearAttachment clear_att = {
1803                         .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1804                         .colorAttachment = i, /* Use attachment index relative to subpass */
1805                         .clearValue = cmd_state->attachments[a].clear_value,
1806                 };
1807
1808                 radv_subpass_clear_attachment(cmd_buffer,
1809                                               &cmd_state->attachments[a],
1810                                               &clear_att, &pre_flush,
1811                                               &post_flush, false);
1812         }
1813
1814         if (cmd_state->subpass->depth_stencil_attachment) {
1815                 uint32_t ds = cmd_state->subpass->depth_stencil_attachment->attachment;
1816                 if (radv_attachment_needs_clear(cmd_state, ds)) {
1817                         VkClearAttachment clear_att = {
1818                                 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1819                                 .clearValue = cmd_state->attachments[ds].clear_value,
1820                         };
1821
1822                         radv_subpass_clear_attachment(cmd_buffer,
1823                                                       &cmd_state->attachments[ds],
1824                                                       &clear_att, &pre_flush,
1825                                                       &post_flush, false);
1826                 }
1827         }
1828
1829         if (cmd_state->subpass->ds_resolve_attachment) {
1830                 uint32_t ds_resolve = cmd_state->subpass->ds_resolve_attachment->attachment;
1831                 if (radv_attachment_needs_clear(cmd_state, ds_resolve)) {
1832                         VkClearAttachment clear_att = {
1833                                 .aspectMask = cmd_state->attachments[ds_resolve].pending_clear_aspects,
1834                                 .clearValue = cmd_state->attachments[ds_resolve].clear_value,
1835                         };
1836
1837                         radv_subpass_clear_attachment(cmd_buffer,
1838                                                       &cmd_state->attachments[ds_resolve],
1839                                                       &clear_att, &pre_flush,
1840                                                       &post_flush, true);
1841                 }
1842         }
1843
1844         radv_meta_restore(&saved_state, cmd_buffer);
1845         cmd_buffer->state.flush_bits |= post_flush;
1846 }
1847
1848 static void
1849 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1850                        struct radv_image *image,
1851                        VkImageLayout image_layout,
1852                        const VkImageSubresourceRange *range,
1853                        VkFormat format, int level, int layer,
1854                        const VkClearValue *clear_val)
1855 {
1856         VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1857         struct radv_image_view iview;
1858         uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level);
1859         uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level);
1860
1861         radv_image_view_init(&iview, cmd_buffer->device,
1862                              &(VkImageViewCreateInfo) {
1863                                      .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1864                                              .image = radv_image_to_handle(image),
1865                                              .viewType = radv_meta_get_view_type(image),
1866                                              .format = format,
1867                                              .subresourceRange = {
1868                                              .aspectMask = range->aspectMask,
1869                                              .baseMipLevel = range->baseMipLevel + level,
1870                                              .levelCount = 1,
1871                                              .baseArrayLayer = range->baseArrayLayer + layer,
1872                                              .layerCount = 1
1873                                      },
1874                              });
1875
1876         VkFramebuffer fb;
1877         radv_CreateFramebuffer(device_h,
1878                                &(VkFramebufferCreateInfo) {
1879                                        .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1880                                                .attachmentCount = 1,
1881                                                .pAttachments = (VkImageView[]) {
1882                                                radv_image_view_to_handle(&iview),
1883                                        },
1884                                                .width = width,
1885                                                .height = height,
1886                                                .layers = 1
1887                                },
1888                                &cmd_buffer->pool->alloc,
1889                                &fb);
1890
1891         VkAttachmentDescription att_desc = {
1892                 .format = iview.vk_format,
1893                 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1894                 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1895                 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1896                 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1897                 .initialLayout = image_layout,
1898                 .finalLayout = image_layout,
1899         };
1900
1901         VkSubpassDescription subpass_desc = {
1902                 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1903                 .inputAttachmentCount = 0,
1904                 .colorAttachmentCount = 0,
1905                 .pColorAttachments = NULL,
1906                 .pResolveAttachments = NULL,
1907                 .pDepthStencilAttachment = NULL,
1908                 .preserveAttachmentCount = 0,
1909                 .pPreserveAttachments = NULL,
1910         };
1911
1912         const VkAttachmentReference att_ref = {
1913                 .attachment = 0,
1914                 .layout = image_layout,
1915         };
1916
1917         if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1918                 subpass_desc.colorAttachmentCount = 1;
1919                 subpass_desc.pColorAttachments = &att_ref;
1920         } else {
1921                 subpass_desc.pDepthStencilAttachment = &att_ref;
1922         }
1923
1924         VkRenderPass pass;
1925         radv_CreateRenderPass(device_h,
1926                               &(VkRenderPassCreateInfo) {
1927                                       .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1928                                               .attachmentCount = 1,
1929                                               .pAttachments = &att_desc,
1930                                               .subpassCount = 1,
1931                                               .pSubpasses = &subpass_desc,
1932                                               },
1933                               &cmd_buffer->pool->alloc,
1934                               &pass);
1935
1936         radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1937                                 &(VkRenderPassBeginInfo) {
1938                                         .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1939                                                 .renderArea = {
1940                                                 .offset = { 0, 0, },
1941                                                 .extent = {
1942                                                         .width = width,
1943                                                         .height = height,
1944                                                 },
1945                                         },
1946                                                 .renderPass = pass,
1947                                                 .framebuffer = fb,
1948                                                 .clearValueCount = 0,
1949                                                 .pClearValues = NULL,
1950                                                 },
1951                                 VK_SUBPASS_CONTENTS_INLINE);
1952
1953         VkClearAttachment clear_att = {
1954                 .aspectMask = range->aspectMask,
1955                 .colorAttachment = 0,
1956                 .clearValue = *clear_val,
1957         };
1958
1959         VkClearRect clear_rect = {
1960                 .rect = {
1961                         .offset = { 0, 0 },
1962                         .extent = { width, height },
1963                 },
1964                 .baseArrayLayer = range->baseArrayLayer,
1965                 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1966         };
1967
1968         emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0, false);
1969
1970         radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1971         radv_DestroyRenderPass(device_h, pass,
1972                                &cmd_buffer->pool->alloc);
1973         radv_DestroyFramebuffer(device_h, fb,
1974                                 &cmd_buffer->pool->alloc);
1975 }
1976
1977 /**
1978  * Return TRUE if a fast color or depth clear has been performed.
1979  */
1980 static bool
1981 radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer,
1982                       struct radv_image *image,
1983                       VkFormat format,
1984                       VkImageLayout image_layout,
1985                       const VkImageSubresourceRange *range,
1986                       const VkClearValue *clear_val)
1987 {
1988         struct radv_image_view iview;
1989
1990         radv_image_view_init(&iview, cmd_buffer->device,
1991                              &(VkImageViewCreateInfo) {
1992                                         .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1993                                         .image = radv_image_to_handle(image),
1994                                         .viewType = radv_meta_get_view_type(image),
1995                                         .format = image->vk_format,
1996                                         .subresourceRange = {
1997                                         .aspectMask = range->aspectMask,
1998                                         .baseMipLevel = range->baseMipLevel,
1999                                         .levelCount = range->levelCount,
2000                                         .baseArrayLayer = range->baseArrayLayer,
2001                                         .layerCount = range->layerCount,
2002                                    },
2003                              });
2004
2005         VkClearRect clear_rect = {
2006                 .rect = {
2007                         .offset = { 0, 0 },
2008                         .extent = {
2009                                 radv_minify(image->info.width, range->baseMipLevel),
2010                                 radv_minify(image->info.height, range->baseMipLevel),
2011                         },
2012                 },
2013                 .baseArrayLayer = range->baseArrayLayer,
2014                 .layerCount = range->layerCount,
2015         };
2016
2017         VkClearAttachment clear_att = {
2018                 .aspectMask = range->aspectMask,
2019                 .colorAttachment = 0,
2020                 .clearValue = *clear_val,
2021         };
2022
2023         if (vk_format_is_color(format)) {
2024                 if (radv_can_fast_clear_color(cmd_buffer, &iview,
2025                                               image_layout, &clear_rect,
2026                                               clear_att.clearValue.color, 0)) {
2027                         radv_fast_clear_color(cmd_buffer, &iview, &clear_att,
2028                                               clear_att.colorAttachment,
2029                                               NULL, NULL);
2030                         return true;
2031                 }
2032         } else {
2033                 if (radv_can_fast_clear_depth(cmd_buffer, &iview, image_layout,
2034                                               range->aspectMask, &clear_rect,
2035                                               clear_att.clearValue.depthStencil, 0)) {
2036                         radv_fast_clear_depth(cmd_buffer, &iview, &clear_att,
2037                                               NULL, NULL);
2038                         return true;
2039                 }
2040         }
2041
2042         return false;
2043 }
2044
2045 static void
2046 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
2047                      struct radv_image *image,
2048                      VkImageLayout image_layout,
2049                      const VkClearValue *clear_value,
2050                      uint32_t range_count,
2051                      const VkImageSubresourceRange *ranges,
2052                      bool cs)
2053 {
2054         VkFormat format = image->vk_format;
2055         VkClearValue internal_clear_value = *clear_value;
2056
2057         if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
2058                 uint32_t value;
2059                 format = VK_FORMAT_R32_UINT;
2060                 value = float3_to_rgb9e5(clear_value->color.float32);
2061                 internal_clear_value.color.uint32[0] = value;
2062         }
2063
2064         if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
2065                 uint8_t r, g;
2066                 format = VK_FORMAT_R8_UINT;
2067                 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
2068                 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
2069                 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
2070         }
2071
2072         if (format == VK_FORMAT_R32G32B32_UINT ||
2073             format == VK_FORMAT_R32G32B32_SINT ||
2074             format == VK_FORMAT_R32G32B32_SFLOAT)
2075                 cs = true;
2076
2077         for (uint32_t r = 0; r < range_count; r++) {
2078                 const VkImageSubresourceRange *range = &ranges[r];
2079
2080                 /* Try to perform a fast clear first, otherwise fallback to
2081                  * the legacy path.
2082                  */
2083                 if (!cs &&
2084                     radv_fast_clear_range(cmd_buffer, image, format,
2085                                           image_layout, range,
2086                                           &internal_clear_value)) {
2087                         continue;
2088                 }
2089
2090                 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
2091                         const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
2092                                 radv_minify(image->info.depth, range->baseMipLevel + l) :
2093                                 radv_get_layerCount(image, range);
2094                         for (uint32_t s = 0; s < layer_count; ++s) {
2095
2096                                 if (cs) {
2097                                         struct radv_meta_blit2d_surf surf;
2098                                         surf.format = format;
2099                                         surf.image = image;
2100                                         surf.level = range->baseMipLevel + l;
2101                                         surf.layer = range->baseArrayLayer + s;
2102                                         surf.aspect_mask = range->aspectMask;
2103                                         radv_meta_clear_image_cs(cmd_buffer, &surf,
2104                                                                  &internal_clear_value.color);
2105                                 } else {
2106                                         radv_clear_image_layer(cmd_buffer, image, image_layout,
2107                                                                range, format, l, s, &internal_clear_value);
2108                                 }
2109                         }
2110                 }
2111         }
2112 }
2113
2114 void radv_CmdClearColorImage(
2115         VkCommandBuffer                             commandBuffer,
2116         VkImage                                     image_h,
2117         VkImageLayout                               imageLayout,
2118         const VkClearColorValue*                    pColor,
2119         uint32_t                                    rangeCount,
2120         const VkImageSubresourceRange*              pRanges)
2121 {
2122         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2123         RADV_FROM_HANDLE(radv_image, image, image_h);
2124         struct radv_meta_saved_state saved_state;
2125         bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
2126
2127         if (cs) {
2128                 radv_meta_save(&saved_state, cmd_buffer,
2129                                RADV_META_SAVE_COMPUTE_PIPELINE |
2130                                RADV_META_SAVE_CONSTANTS |
2131                                RADV_META_SAVE_DESCRIPTORS);
2132         } else {
2133                 radv_meta_save(&saved_state, cmd_buffer,
2134                                RADV_META_SAVE_GRAPHICS_PIPELINE |
2135                                RADV_META_SAVE_CONSTANTS);
2136         }
2137
2138         radv_cmd_clear_image(cmd_buffer, image, imageLayout,
2139                              (const VkClearValue *) pColor,
2140                              rangeCount, pRanges, cs);
2141
2142         radv_meta_restore(&saved_state, cmd_buffer);
2143 }
2144
2145 void radv_CmdClearDepthStencilImage(
2146         VkCommandBuffer                             commandBuffer,
2147         VkImage                                     image_h,
2148         VkImageLayout                               imageLayout,
2149         const VkClearDepthStencilValue*             pDepthStencil,
2150         uint32_t                                    rangeCount,
2151         const VkImageSubresourceRange*              pRanges)
2152 {
2153         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2154         RADV_FROM_HANDLE(radv_image, image, image_h);
2155         struct radv_meta_saved_state saved_state;
2156
2157         radv_meta_save(&saved_state, cmd_buffer,
2158                        RADV_META_SAVE_GRAPHICS_PIPELINE |
2159                        RADV_META_SAVE_CONSTANTS);
2160
2161         radv_cmd_clear_image(cmd_buffer, image, imageLayout,
2162                              (const VkClearValue *) pDepthStencil,
2163                              rangeCount, pRanges, false);
2164
2165         radv_meta_restore(&saved_state, cmd_buffer);
2166 }
2167
2168 void radv_CmdClearAttachments(
2169         VkCommandBuffer                             commandBuffer,
2170         uint32_t                                    attachmentCount,
2171         const VkClearAttachment*                    pAttachments,
2172         uint32_t                                    rectCount,
2173         const VkClearRect*                          pRects)
2174 {
2175         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2176         struct radv_meta_saved_state saved_state;
2177         enum radv_cmd_flush_bits pre_flush = 0;
2178         enum radv_cmd_flush_bits post_flush = 0;
2179
2180         if (!cmd_buffer->state.subpass)
2181                 return;
2182
2183         radv_meta_save(&saved_state, cmd_buffer,
2184                        RADV_META_SAVE_GRAPHICS_PIPELINE |
2185                        RADV_META_SAVE_CONSTANTS);
2186
2187         /* FINISHME: We can do better than this dumb loop. It thrashes too much
2188          * state.
2189          */
2190         for (uint32_t a = 0; a < attachmentCount; ++a) {
2191                 for (uint32_t r = 0; r < rectCount; ++r) {
2192                         emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush,
2193                                    cmd_buffer->state.subpass->view_mask, false);
2194                 }
2195         }
2196
2197         radv_meta_restore(&saved_state, cmd_buffer);
2198         cmd_buffer->state.flush_bits |= post_flush;
2199 }