projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: implement fast HTILE clears for depth or stencil only on GFX9
[mesa.git] / src / amd / vulkan / radv_meta_clear.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_debug.h"
25 #include "radv_meta.h"
26 #include "radv_private.h"
27 #include "nir/nir_builder.h"
28
29 #include "util/format_rgb9e5.h"
30 #include "vk_format.h"
31
32 enum {
33 DEPTH_CLEAR_SLOW,
34 DEPTH_CLEAR_FAST_EXPCLEAR,
35 DEPTH_CLEAR_FAST_NO_EXPCLEAR
36 };
37
38 static void
39 build_color_shaders(struct nir_shader **out_vs,
40 struct nir_shader **out_fs,
41 uint32_t frag_output)
42 {
43 nir_builder vs_b;
44 nir_builder fs_b;
45
46 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
47 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
48
49 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
50 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
51
52 const struct glsl_type *position_type = glsl_vec4_type();
53 const struct glsl_type *color_type = glsl_vec4_type();
54
55 nir_variable *vs_out_pos =
56 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
57 "gl_Position");
58 vs_out_pos->data.location = VARYING_SLOT_POS;
59
60 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
61 nir_intrinsic_set_base(in_color_load, 0);
62 nir_intrinsic_set_range(in_color_load, 16);
63 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
64 in_color_load->num_components = 4;
65 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
66 nir_builder_instr_insert(&fs_b, &in_color_load->instr);
67
68 nir_variable *fs_out_color =
69 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
70 "f_color");
71 fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
72
73 nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
74
75 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
76 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
77
78 const struct glsl_type *layer_type = glsl_int_type();
79 nir_variable *vs_out_layer =
80 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
81 "v_layer");
82 vs_out_layer->data.location = VARYING_SLOT_LAYER;
83 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
84 nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
85 nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
86
87 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
88 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
89
90 *out_vs = vs_b.shader;
91 *out_fs = fs_b.shader;
92 }
93
94 static VkResult
95 create_pipeline(struct radv_device *device,
96 struct radv_render_pass *render_pass,
97 uint32_t samples,
98 struct nir_shader *vs_nir,
99 struct nir_shader *fs_nir,
100 const VkPipelineVertexInputStateCreateInfo *vi_state,
101 const VkPipelineDepthStencilStateCreateInfo *ds_state,
102 const VkPipelineColorBlendStateCreateInfo *cb_state,
103 const VkPipelineLayout layout,
104 const struct radv_graphics_pipeline_create_info *extra,
105 const VkAllocationCallbacks *alloc,
106 VkPipeline *pipeline)
107 {
108 VkDevice device_h = radv_device_to_handle(device);
109 VkResult result;
110
111 struct radv_shader_module vs_m = { .nir = vs_nir };
112 struct radv_shader_module fs_m = { .nir = fs_nir };
113
114 result = radv_graphics_pipeline_create(device_h,
115 radv_pipeline_cache_to_handle(&device->meta_state.cache),
116 &(VkGraphicsPipelineCreateInfo) {
117 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
118 .stageCount = fs_nir ? 2 : 1,
119 .pStages = (VkPipelineShaderStageCreateInfo[]) {
120 {
121 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
122 .stage = VK_SHADER_STAGE_VERTEX_BIT,
123 .module = radv_shader_module_to_handle(&vs_m),
124 .pName = "main",
125 },
126 {
127 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
128 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
129 .module = radv_shader_module_to_handle(&fs_m),
130 .pName = "main",
131 },
132 },
133 .pVertexInputState = vi_state,
134 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
135 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
136 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
137 .primitiveRestartEnable = false,
138 },
139 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
140 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
141 .viewportCount = 1,
142 .scissorCount = 1,
143 },
144 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
145 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
146 .rasterizerDiscardEnable = false,
147 .polygonMode = VK_POLYGON_MODE_FILL,
148 .cullMode = VK_CULL_MODE_NONE,
149 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
150 .depthBiasEnable = false,
151 },
152 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
153 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
154 .rasterizationSamples = samples,
155 .sampleShadingEnable = false,
156 .pSampleMask = NULL,
157 .alphaToCoverageEnable = false,
158 .alphaToOneEnable = false,
159 },
160 .pDepthStencilState = ds_state,
161 .pColorBlendState = cb_state,
162 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
163 /* The meta clear pipeline declares all state as dynamic.
164 * As a consequence, vkCmdBindPipeline writes no dynamic state
165 * to the cmd buffer. Therefore, at the end of the meta clear,
166 * we need only restore dynamic state was vkCmdSet.
167 */
168 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
169 .dynamicStateCount = 8,
170 .pDynamicStates = (VkDynamicState[]) {
171 /* Everything except stencil write mask */
172 VK_DYNAMIC_STATE_VIEWPORT,
173 VK_DYNAMIC_STATE_SCISSOR,
174 VK_DYNAMIC_STATE_LINE_WIDTH,
175 VK_DYNAMIC_STATE_DEPTH_BIAS,
176 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
177 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
178 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
179 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
180 },
181 },
182 .layout = layout,
183 .flags = 0,
184 .renderPass = radv_render_pass_to_handle(render_pass),
185 .subpass = 0,
186 },
187 extra,
188 alloc,
189 pipeline);
190
191 ralloc_free(vs_nir);
192 ralloc_free(fs_nir);
193
194 return result;
195 }
196
197 static VkResult
198 create_color_renderpass(struct radv_device *device,
199 VkFormat vk_format,
200 uint32_t samples,
201 VkRenderPass *pass)
202 {
203 mtx_lock(&device->meta_state.mtx);
204 if (*pass) {
205 mtx_unlock (&device->meta_state.mtx);
206 return VK_SUCCESS;
207 }
208
209 VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
210 &(VkRenderPassCreateInfo) {
211 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
212 .attachmentCount = 1,
213 .pAttachments = &(VkAttachmentDescription) {
214 .format = vk_format,
215 .samples = samples,
216 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
217 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
218 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
219 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
220 },
221 .subpassCount = 1,
222 .pSubpasses = &(VkSubpassDescription) {
223 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
224 .inputAttachmentCount = 0,
225 .colorAttachmentCount = 1,
226 .pColorAttachments = &(VkAttachmentReference) {
227 .attachment = 0,
228 .layout = VK_IMAGE_LAYOUT_GENERAL,
229 },
230 .pResolveAttachments = NULL,
231 .pDepthStencilAttachment = &(VkAttachmentReference) {
232 .attachment = VK_ATTACHMENT_UNUSED,
233 .layout = VK_IMAGE_LAYOUT_GENERAL,
234 },
235 .preserveAttachmentCount = 1,
236 .pPreserveAttachments = (uint32_t[]) { 0 },
237 },
238 .dependencyCount = 0,
239 }, &device->meta_state.alloc, pass);
240 mtx_unlock(&device->meta_state.mtx);
241 return result;
242 }
243
244 static VkResult
245 create_color_pipeline(struct radv_device *device,
246 uint32_t samples,
247 uint32_t frag_output,
248 VkPipeline *pipeline,
249 VkRenderPass pass)
250 {
251 struct nir_shader *vs_nir;
252 struct nir_shader *fs_nir;
253 VkResult result;
254
255 mtx_lock(&device->meta_state.mtx);
256 if (*pipeline) {
257 mtx_unlock(&device->meta_state.mtx);
258 return VK_SUCCESS;
259 }
260
261 build_color_shaders(&vs_nir, &fs_nir, frag_output);
262
263 const VkPipelineVertexInputStateCreateInfo vi_state = {
264 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
265 .vertexBindingDescriptionCount = 0,
266 .vertexAttributeDescriptionCount = 0,
267 };
268
269 const VkPipelineDepthStencilStateCreateInfo ds_state = {
270 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
271 .depthTestEnable = false,
272 .depthWriteEnable = false,
273 .depthBoundsTestEnable = false,
274 .stencilTestEnable = false,
275 };
276
277 VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
278 blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
279 .blendEnable = false,
280 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
281 VK_COLOR_COMPONENT_R_BIT |
282 VK_COLOR_COMPONENT_G_BIT |
283 VK_COLOR_COMPONENT_B_BIT,
284 };
285
286 const VkPipelineColorBlendStateCreateInfo cb_state = {
287 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
288 .logicOpEnable = false,
289 .attachmentCount = MAX_RTS,
290 .pAttachments = blend_attachment_state
291 };
292
293
294 struct radv_graphics_pipeline_create_info extra = {
295 .use_rectlist = true,
296 };
297 result = create_pipeline(device, radv_render_pass_from_handle(pass),
298 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
299 device->meta_state.clear_color_p_layout,
300 &extra, &device->meta_state.alloc, pipeline);
301
302 mtx_unlock(&device->meta_state.mtx);
303 return result;
304 }
305
306 static void
307 finish_meta_clear_htile_mask_state(struct radv_device *device)
308 {
309 struct radv_meta_state *state = &device->meta_state;
310
311 radv_DestroyPipeline(radv_device_to_handle(device),
312 state->clear_htile_mask_pipeline,
313 &state->alloc);
314 radv_DestroyPipelineLayout(radv_device_to_handle(device),
315 state->clear_htile_mask_p_layout,
316 &state->alloc);
317 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
318 state->clear_htile_mask_ds_layout,
319 &state->alloc);
320 }
321
322 void
323 radv_device_finish_meta_clear_state(struct radv_device *device)
324 {
325 struct radv_meta_state *state = &device->meta_state;
326
327 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
328 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
329 radv_DestroyPipeline(radv_device_to_handle(device),
330 state->clear[i].color_pipelines[j],
331 &state->alloc);
332 radv_DestroyRenderPass(radv_device_to_handle(device),
333 state->clear[i].render_pass[j],
334 &state->alloc);
335 }
336
337 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
338 radv_DestroyPipeline(radv_device_to_handle(device),
339 state->clear[i].depth_only_pipeline[j],
340 &state->alloc);
341 radv_DestroyPipeline(radv_device_to_handle(device),
342 state->clear[i].stencil_only_pipeline[j],
343 &state->alloc);
344 radv_DestroyPipeline(radv_device_to_handle(device),
345 state->clear[i].depthstencil_pipeline[j],
346 &state->alloc);
347 }
348 radv_DestroyRenderPass(radv_device_to_handle(device),
349 state->clear[i].depthstencil_rp,
350 &state->alloc);
351 }
352 radv_DestroyPipelineLayout(radv_device_to_handle(device),
353 state->clear_color_p_layout,
354 &state->alloc);
355 radv_DestroyPipelineLayout(radv_device_to_handle(device),
356 state->clear_depth_p_layout,
357 &state->alloc);
358
359 finish_meta_clear_htile_mask_state(device);
360 }
361
362 static void
363 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
364 const VkClearAttachment *clear_att,
365 const VkClearRect *clear_rect,
366 uint32_t view_mask)
367 {
368 struct radv_device *device = cmd_buffer->device;
369 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
370 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
371 const uint32_t subpass_att = clear_att->colorAttachment;
372 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
373 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
374 const uint32_t samples = iview->image->info.samples;
375 const uint32_t samples_log2 = ffs(samples) - 1;
376 unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
377 VkClearColorValue clear_value = clear_att->clearValue.color;
378 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
379 VkPipeline pipeline;
380
381 if (fs_key == -1) {
382 radv_finishme("color clears incomplete");
383 return;
384 }
385
386 if (device->meta_state.clear[samples_log2].render_pass[fs_key] == VK_NULL_HANDLE) {
387 VkResult ret = create_color_renderpass(device, radv_fs_key_format_exemplars[fs_key],
388 samples,
389 &device->meta_state.clear[samples_log2].render_pass[fs_key]);
390 if (ret != VK_SUCCESS) {
391 cmd_buffer->record_result = ret;
392 return;
393 }
394 }
395
396 if (device->meta_state.clear[samples_log2].color_pipelines[fs_key] == VK_NULL_HANDLE) {
397 VkResult ret = create_color_pipeline(device, samples, 0,
398 &device->meta_state.clear[samples_log2].color_pipelines[fs_key],
399 device->meta_state.clear[samples_log2].render_pass[fs_key]);
400 if (ret != VK_SUCCESS) {
401 cmd_buffer->record_result = ret;
402 return;
403 }
404 }
405
406 pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
407 if (!pipeline) {
408 radv_finishme("color clears incomplete");
409 return;
410 }
411 assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
412 assert(pipeline);
413 assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
414 assert(clear_att->colorAttachment < subpass->color_count);
415
416 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
417 device->meta_state.clear_color_p_layout,
418 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
419 &clear_value);
420
421 struct radv_subpass clear_subpass = {
422 .color_count = 1,
423 .color_attachments = (struct radv_subpass_attachment[]) {
424 subpass->color_attachments[clear_att->colorAttachment]
425 },
426 .depth_stencil_attachment = (struct radv_subpass_attachment) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
427 };
428
429 radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
430
431 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
432 pipeline);
433
434 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
435 .x = clear_rect->rect.offset.x,
436 .y = clear_rect->rect.offset.y,
437 .width = clear_rect->rect.extent.width,
438 .height = clear_rect->rect.extent.height,
439 .minDepth = 0.0f,
440 .maxDepth = 1.0f
441 });
442
443 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
444
445 if (view_mask) {
446 unsigned i;
447 for_each_bit(i, view_mask)
448 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
449 } else {
450 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
451 }
452
453 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
454 }
455
456
457 static void
458 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
459 {
460 nir_builder vs_b, fs_b;
461
462 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
463 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
464
465 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
466 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
467 const struct glsl_type *position_out_type = glsl_vec4_type();
468
469 nir_variable *vs_out_pos =
470 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
471 "gl_Position");
472 vs_out_pos->data.location = VARYING_SLOT_POS;
473
474 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
475 nir_intrinsic_set_base(in_color_load, 0);
476 nir_intrinsic_set_range(in_color_load, 4);
477 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
478 in_color_load->num_components = 1;
479 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
480 nir_builder_instr_insert(&vs_b, &in_color_load->instr);
481
482 nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
483 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
484
485 const struct glsl_type *layer_type = glsl_int_type();
486 nir_variable *vs_out_layer =
487 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
488 "v_layer");
489 vs_out_layer->data.location = VARYING_SLOT_LAYER;
490 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
491 nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
492 nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
493
494 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
495 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
496
497 *out_vs = vs_b.shader;
498 *out_fs = fs_b.shader;
499 }
500
501 static VkResult
502 create_depthstencil_renderpass(struct radv_device *device,
503 uint32_t samples,
504 VkRenderPass *render_pass)
505 {
506 mtx_lock(&device->meta_state.mtx);
507 if (*render_pass) {
508 mtx_unlock(&device->meta_state.mtx);
509 return VK_SUCCESS;
510 }
511
512 VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
513 &(VkRenderPassCreateInfo) {
514 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
515 .attachmentCount = 1,
516 .pAttachments = &(VkAttachmentDescription) {
517 .format = VK_FORMAT_D32_SFLOAT_S8_UINT,
518 .samples = samples,
519 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
520 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
521 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
522 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
523 },
524 .subpassCount = 1,
525 .pSubpasses = &(VkSubpassDescription) {
526 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
527 .inputAttachmentCount = 0,
528 .colorAttachmentCount = 0,
529 .pColorAttachments = NULL,
530 .pResolveAttachments = NULL,
531 .pDepthStencilAttachment = &(VkAttachmentReference) {
532 .attachment = 0,
533 .layout = VK_IMAGE_LAYOUT_GENERAL,
534 },
535 .preserveAttachmentCount = 1,
536 .pPreserveAttachments = (uint32_t[]) { 0 },
537 },
538 .dependencyCount = 0,
539 }, &device->meta_state.alloc, render_pass);
540 mtx_unlock(&device->meta_state.mtx);
541 return result;
542 }
543
544 static VkResult
545 create_depthstencil_pipeline(struct radv_device *device,
546 VkImageAspectFlags aspects,
547 uint32_t samples,
548 int index,
549 VkPipeline *pipeline,
550 VkRenderPass render_pass)
551 {
552 struct nir_shader *vs_nir, *fs_nir;
553 VkResult result;
554
555 mtx_lock(&device->meta_state.mtx);
556 if (*pipeline) {
557 mtx_unlock(&device->meta_state.mtx);
558 return VK_SUCCESS;
559 }
560
561 build_depthstencil_shader(&vs_nir, &fs_nir);
562
563 const VkPipelineVertexInputStateCreateInfo vi_state = {
564 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
565 .vertexBindingDescriptionCount = 0,
566 .vertexAttributeDescriptionCount = 0,
567 };
568
569 const VkPipelineDepthStencilStateCreateInfo ds_state = {
570 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
571 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
572 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
573 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
574 .depthBoundsTestEnable = false,
575 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
576 .front = {
577 .passOp = VK_STENCIL_OP_REPLACE,
578 .compareOp = VK_COMPARE_OP_ALWAYS,
579 .writeMask = UINT32_MAX,
580 .reference = 0, /* dynamic */
581 },
582 .back = { 0 /* dont care */ },
583 };
584
585 const VkPipelineColorBlendStateCreateInfo cb_state = {
586 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
587 .logicOpEnable = false,
588 .attachmentCount = 0,
589 .pAttachments = NULL,
590 };
591
592 struct radv_graphics_pipeline_create_info extra = {
593 .use_rectlist = true,
594 };
595
596 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
597 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
598 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
599 }
600 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
601 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
602 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
603 }
604 result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
605 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
606 device->meta_state.clear_depth_p_layout,
607 &extra, &device->meta_state.alloc, pipeline);
608
609 mtx_unlock(&device->meta_state.mtx);
610 return result;
611 }
612
613 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
614 const struct radv_image_view *iview,
615 VkImageAspectFlags aspects,
616 VkImageLayout layout,
617 const VkClearRect *clear_rect,
618 VkClearDepthStencilValue clear_value)
619 {
620 uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
621 cmd_buffer->queue_family_index,
622 cmd_buffer->queue_family_index);
623 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
624 clear_rect->rect.extent.width != iview->extent.width ||
625 clear_rect->rect.extent.height != iview->extent.height)
626 return false;
627 if (radv_image_is_tc_compat_htile(iview->image) &&
628 (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && clear_value.depth != 0.0 &&
629 clear_value.depth != 1.0) ||
630 ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0)))
631 return false;
632 if (radv_image_has_htile(iview->image) &&
633 iview->base_mip == 0 &&
634 iview->base_layer == 0 &&
635 radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
636 !radv_image_extent_compare(iview->image, &iview->extent))
637 return true;
638 return false;
639 }
640
641 static VkPipeline
642 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
643 struct radv_meta_state *meta_state,
644 const struct radv_image_view *iview,
645 int samples_log2,
646 VkImageAspectFlags aspects,
647 VkImageLayout layout,
648 const VkClearRect *clear_rect,
649 VkClearDepthStencilValue clear_value)
650 {
651 bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, clear_rect, clear_value);
652 int index = DEPTH_CLEAR_SLOW;
653 VkPipeline *pipeline;
654
655 if (fast) {
656 /* we don't know the previous clear values, so we always have
657 * the NO_EXPCLEAR path */
658 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
659 }
660
661 switch (aspects) {
662 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
663 pipeline = &meta_state->clear[samples_log2].depthstencil_pipeline[index];
664 break;
665 case VK_IMAGE_ASPECT_DEPTH_BIT:
666 pipeline = &meta_state->clear[samples_log2].depth_only_pipeline[index];
667 break;
668 case VK_IMAGE_ASPECT_STENCIL_BIT:
669 pipeline = &meta_state->clear[samples_log2].stencil_only_pipeline[index];
670 break;
671 default:
672 unreachable("expected depth or stencil aspect");
673 }
674
675 if (cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp == VK_NULL_HANDLE) {
676 VkResult ret = create_depthstencil_renderpass(cmd_buffer->device, 1u << samples_log2,
677 &cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
678 if (ret != VK_SUCCESS) {
679 cmd_buffer->record_result = ret;
680 return VK_NULL_HANDLE;
681 }
682 }
683
684 if (*pipeline == VK_NULL_HANDLE) {
685 VkResult ret = create_depthstencil_pipeline(cmd_buffer->device, aspects, 1u << samples_log2, index,
686 pipeline, cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
687 if (ret != VK_SUCCESS) {
688 cmd_buffer->record_result = ret;
689 return VK_NULL_HANDLE;
690 }
691 }
692 return *pipeline;
693 }
694
695 static void
696 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
697 const VkClearAttachment *clear_att,
698 const VkClearRect *clear_rect)
699 {
700 struct radv_device *device = cmd_buffer->device;
701 struct radv_meta_state *meta_state = &device->meta_state;
702 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
703 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
704 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
705 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
706 VkImageAspectFlags aspects = clear_att->aspectMask;
707 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
708 const uint32_t samples = iview->image->info.samples;
709 const uint32_t samples_log2 = ffs(samples) - 1;
710 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
711
712 assert(pass_att != VK_ATTACHMENT_UNUSED);
713
714 if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
715 clear_value.depth = 1.0f;
716
717 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
718 device->meta_state.clear_depth_p_layout,
719 VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
720 &clear_value.depth);
721
722 uint32_t prev_reference = cmd_buffer->state.dynamic.stencil_reference.front;
723 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
724 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
725 clear_value.stencil);
726 }
727
728 VkPipeline pipeline = pick_depthstencil_pipeline(cmd_buffer,
729 meta_state,
730 iview,
731 samples_log2,
732 aspects,
733 subpass->depth_stencil_attachment.layout,
734 clear_rect,
735 clear_value);
736 if (!pipeline)
737 return;
738
739 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
740 pipeline);
741
742 if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
743 subpass->depth_stencil_attachment.layout,
744 clear_rect, clear_value))
745 radv_update_ds_clear_metadata(cmd_buffer, iview->image,
746 clear_value, aspects);
747
748 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
749 .x = clear_rect->rect.offset.x,
750 .y = clear_rect->rect.offset.y,
751 .width = clear_rect->rect.extent.width,
752 .height = clear_rect->rect.extent.height,
753 .minDepth = 0.0f,
754 .maxDepth = 1.0f
755 });
756
757 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
758
759 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
760
761 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
762 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
763 prev_reference);
764 }
765 }
766
767 static uint32_t
768 clear_htile_mask(struct radv_cmd_buffer *cmd_buffer,
769 struct radeon_winsys_bo *bo, uint64_t offset, uint64_t size,
770 uint32_t htile_value, uint32_t htile_mask)
771 {
772 struct radv_device *device = cmd_buffer->device;
773 struct radv_meta_state *state = &device->meta_state;
774 uint64_t block_count = round_up_u64(size, 1024);
775 struct radv_meta_saved_state saved_state;
776
777 radv_meta_save(&saved_state, cmd_buffer,
778 RADV_META_SAVE_COMPUTE_PIPELINE |
779 RADV_META_SAVE_CONSTANTS |
780 RADV_META_SAVE_DESCRIPTORS);
781
782 struct radv_buffer dst_buffer = {
783 .bo = bo,
784 .offset = offset,
785 .size = size
786 };
787
788 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
789 VK_PIPELINE_BIND_POINT_COMPUTE,
790 state->clear_htile_mask_pipeline);
791
792 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
793 state->clear_htile_mask_p_layout,
794 0, /* set */
795 1, /* descriptorWriteCount */
796 (VkWriteDescriptorSet[]) {
797 {
798 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
799 .dstBinding = 0,
800 .dstArrayElement = 0,
801 .descriptorCount = 1,
802 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
803 .pBufferInfo = &(VkDescriptorBufferInfo) {
804 .buffer = radv_buffer_to_handle(&dst_buffer),
805 .offset = 0,
806 .range = size
807 }
808 }
809 });
810
811 const unsigned constants[2] = {
812 htile_value & htile_mask,
813 ~htile_mask,
814 };
815
816 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
817 state->clear_htile_mask_p_layout,
818 VK_SHADER_STAGE_COMPUTE_BIT, 0, 8,
819 constants);
820
821 radv_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer), block_count, 1, 1);
822
823 radv_meta_restore(&saved_state, cmd_buffer);
824
825 return RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
826 RADV_CMD_FLAG_INV_VMEM_L1 |
827 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
828 }
829
830 static uint32_t
831 radv_get_htile_fast_clear_value(const struct radv_image *image,
832 VkClearDepthStencilValue value)
833 {
834 uint32_t clear_value;
835
836 if (!image->surface.has_stencil) {
837 clear_value = value.depth ? 0xfffffff0 : 0;
838 } else {
839 clear_value = value.depth ? 0xfffc0000 : 0;
840 }
841
842 return clear_value;
843 }
844
845 static uint32_t
846 radv_get_htile_mask(const struct radv_image *image, VkImageAspectFlags aspects)
847 {
848 uint32_t mask = 0;
849
850 if (!image->surface.has_stencil) {
851 /* All the HTILE buffer is used when there is no stencil. */
852 mask = UINT32_MAX;
853 } else {
854 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
855 mask |= 0xfffffc0f;
856 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
857 mask |= 0x000003f0;
858 }
859
860 return mask;
861 }
862
863 static bool
864 radv_is_fast_clear_depth_allowed(VkClearDepthStencilValue value)
865 {
866 return value.depth == 1.0f || value.depth == 0.0f;
867 }
868
869 static bool
870 radv_is_fast_clear_stencil_allowed(VkClearDepthStencilValue value)
871 {
872 return value.stencil == 0;
873 }
874
875 static bool
876 emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
877 const VkClearAttachment *clear_att,
878 const VkClearRect *clear_rect,
879 enum radv_cmd_flush_bits *pre_flush,
880 enum radv_cmd_flush_bits *post_flush)
881 {
882 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
883 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
884 VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
885 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
886 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
887 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
888 VkImageAspectFlags aspects = clear_att->aspectMask;
889 uint32_t clear_word, flush_bits;
890 uint32_t htile_mask;
891
892 if (!radv_image_has_htile(iview->image))
893 return false;
894
895 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
896 return false;
897
898 if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
899 return false;
900
901 /* don't fast clear 3D */
902 if (iview->image->type == VK_IMAGE_TYPE_3D)
903 return false;
904
905 /* all layers are bound */
906 if (iview->base_layer > 0)
907 return false;
908 if (iview->image->info.array_size != iview->layer_count)
909 return false;
910
911 if (!radv_image_extent_compare(iview->image, &iview->extent))
912 return false;
913
914 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
915 clear_rect->rect.extent.width != iview->image->info.width ||
916 clear_rect->rect.extent.height != iview->image->info.height)
917 return false;
918
919 if (clear_rect->baseArrayLayer != 0)
920 return false;
921 if (clear_rect->layerCount != iview->image->info.array_size)
922 return false;
923
924 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 &&
925 (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT) ||
926 ((vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) &&
927 !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))))
928 return false;
929
930 if (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
931 !radv_is_fast_clear_depth_allowed(clear_value)) ||
932 ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
933 !radv_is_fast_clear_stencil_allowed(clear_value)))
934 return false;
935
936 /* GFX8 only supports 32-bit depth surfaces but we can enable TC-compat
937 * HTILE for 16-bit surfaces if no Z planes are compressed. Though,
938 * fast HTILE clears don't seem to work.
939 */
940 if (cmd_buffer->device->physical_device->rad_info.chip_class == VI &&
941 iview->image->vk_format == VK_FORMAT_D16_UNORM)
942 return false;
943
944 clear_word = radv_get_htile_fast_clear_value(iview->image, clear_value);
945 htile_mask = radv_get_htile_mask(iview->image, aspects);
946
947 if (pre_flush) {
948 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
949 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
950 *pre_flush |= cmd_buffer->state.flush_bits;
951 } else
952 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
953 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
954
955 if (htile_mask == UINT_MAX) {
956 /* Clear the whole HTILE buffer. */
957 flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
958 iview->image->offset + iview->image->htile_offset,
959 iview->image->surface.htile_size, clear_word);
960 } else {
961 /* Only clear depth or stencil bytes in the HTILE buffer. */
962 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9);
963 flush_bits = clear_htile_mask(cmd_buffer, iview->image->bo,
964 iview->image->offset + iview->image->htile_offset,
965 iview->image->surface.htile_size, clear_word,
966 htile_mask);
967 }
968
969 radv_update_ds_clear_metadata(cmd_buffer, iview->image, clear_value, aspects);
970 if (post_flush) {
971 *post_flush |= flush_bits;
972 } else {
973 cmd_buffer->state.flush_bits |= flush_bits;
974 }
975
976 return true;
977 }
978
979 static nir_shader *
980 build_clear_htile_mask_shader()
981 {
982 nir_builder b;
983
984 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
985 b.shader->info.name = ralloc_strdup(b.shader, "meta_clear_htile_mask");
986 b.shader->info.cs.local_size[0] = 64;
987 b.shader->info.cs.local_size[1] = 1;
988 b.shader->info.cs.local_size[2] = 1;
989
990 nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
991 nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
992 nir_ssa_def *block_size = nir_imm_ivec4(&b,
993 b.shader->info.cs.local_size[0],
994 b.shader->info.cs.local_size[1],
995 b.shader->info.cs.local_size[2], 0);
996
997 nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
998
999 nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16));
1000 offset = nir_channel(&b, offset, 0);
1001
1002 nir_intrinsic_instr *buf =
1003 nir_intrinsic_instr_create(b.shader,
1004 nir_intrinsic_vulkan_resource_index);
1005
1006 buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
1007 nir_intrinsic_set_desc_set(buf, 0);
1008 nir_intrinsic_set_binding(buf, 0);
1009 nir_ssa_dest_init(&buf->instr, &buf->dest, 1, 32, NULL);
1010 nir_builder_instr_insert(&b, &buf->instr);
1011
1012 nir_intrinsic_instr *constants =
1013 nir_intrinsic_instr_create(b.shader,
1014 nir_intrinsic_load_push_constant);
1015 nir_intrinsic_set_base(constants, 0);
1016 nir_intrinsic_set_range(constants, 8);
1017 constants->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
1018 constants->num_components = 2;
1019 nir_ssa_dest_init(&constants->instr, &constants->dest, 2, 32, "constants");
1020 nir_builder_instr_insert(&b, &constants->instr);
1021
1022 nir_intrinsic_instr *load =
1023 nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
1024 load->src[0] = nir_src_for_ssa(&buf->dest.ssa);
1025 load->src[1] = nir_src_for_ssa(offset);
1026 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
1027 load->num_components = 4;
1028 nir_builder_instr_insert(&b, &load->instr);
1029
1030 /* data = (data & ~htile_mask) | (htile_value & htile_mask) */
1031 nir_ssa_def *data =
1032 nir_iand(&b, &load->dest.ssa,
1033 nir_channel(&b, &constants->dest.ssa, 1));
1034 data = nir_ior(&b, data, nir_channel(&b, &constants->dest.ssa, 0));
1035
1036 nir_intrinsic_instr *store =
1037 nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
1038 store->src[0] = nir_src_for_ssa(data);
1039 store->src[1] = nir_src_for_ssa(&buf->dest.ssa);
1040 store->src[2] = nir_src_for_ssa(offset);
1041 nir_intrinsic_set_write_mask(store, 0xf);
1042 store->num_components = 4;
1043 nir_builder_instr_insert(&b, &store->instr);
1044
1045 return b.shader;
1046 }
1047
1048 static VkResult
1049 init_meta_clear_htile_mask_state(struct radv_device *device)
1050 {
1051 struct radv_meta_state *state = &device->meta_state;
1052 struct radv_shader_module cs = { .nir = NULL };
1053 VkResult result;
1054
1055 cs.nir = build_clear_htile_mask_shader();
1056
1057 VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1058 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1059 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1060 .bindingCount = 1,
1061 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1062 {
1063 .binding = 0,
1064 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
1065 .descriptorCount = 1,
1066 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
1067 .pImmutableSamplers = NULL
1068 },
1069 }
1070 };
1071
1072 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1073 &ds_layout_info, &state->alloc,
1074 &state->clear_htile_mask_ds_layout);
1075 if (result != VK_SUCCESS)
1076 goto fail;
1077
1078 VkPipelineLayoutCreateInfo p_layout_info = {
1079 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1080 .setLayoutCount = 1,
1081 .pSetLayouts = &state->clear_htile_mask_ds_layout,
1082 .pushConstantRangeCount = 1,
1083 .pPushConstantRanges = &(VkPushConstantRange){
1084 VK_SHADER_STAGE_COMPUTE_BIT, 0, 8,
1085 },
1086 };
1087
1088 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1089 &p_layout_info, &state->alloc,
1090 &state->clear_htile_mask_p_layout);
1091 if (result != VK_SUCCESS)
1092 goto fail;
1093
1094 VkPipelineShaderStageCreateInfo shader_stage = {
1095 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1096 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
1097 .module = radv_shader_module_to_handle(&cs),
1098 .pName = "main",
1099 .pSpecializationInfo = NULL,
1100 };
1101
1102 VkComputePipelineCreateInfo pipeline_info = {
1103 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
1104 .stage = shader_stage,
1105 .flags = 0,
1106 .layout = state->clear_htile_mask_p_layout,
1107 };
1108
1109 result = radv_CreateComputePipelines(radv_device_to_handle(device),
1110 radv_pipeline_cache_to_handle(&state->cache),
1111 1, &pipeline_info, NULL,
1112 &state->clear_htile_mask_pipeline);
1113
1114 ralloc_free(cs.nir);
1115 return result;
1116 fail:
1117 ralloc_free(cs.nir);
1118 return result;
1119 }
1120
1121 VkResult
1122 radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand)
1123 {
1124 VkResult res;
1125 struct radv_meta_state *state = &device->meta_state;
1126
1127 VkPipelineLayoutCreateInfo pl_color_create_info = {
1128 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1129 .setLayoutCount = 0,
1130 .pushConstantRangeCount = 1,
1131 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
1132 };
1133
1134 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1135 &pl_color_create_info,
1136 &device->meta_state.alloc,
1137 &device->meta_state.clear_color_p_layout);
1138 if (res != VK_SUCCESS)
1139 goto fail;
1140
1141 VkPipelineLayoutCreateInfo pl_depth_create_info = {
1142 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1143 .setLayoutCount = 0,
1144 .pushConstantRangeCount = 1,
1145 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
1146 };
1147
1148 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1149 &pl_depth_create_info,
1150 &device->meta_state.alloc,
1151 &device->meta_state.clear_depth_p_layout);
1152 if (res != VK_SUCCESS)
1153 goto fail;
1154
1155 res = init_meta_clear_htile_mask_state(device);
1156 if (res != VK_SUCCESS)
1157 goto fail;
1158
1159 if (on_demand)
1160 return VK_SUCCESS;
1161
1162 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
1163 uint32_t samples = 1 << i;
1164 for (uint32_t j = 0; j < NUM_META_FS_KEYS; ++j) {
1165 VkFormat format = radv_fs_key_format_exemplars[j];
1166 unsigned fs_key = radv_format_meta_fs_key(format);
1167 assert(!state->clear[i].color_pipelines[fs_key]);
1168
1169 res = create_color_renderpass(device, format, samples,
1170 &state->clear[i].render_pass[fs_key]);
1171 if (res != VK_SUCCESS)
1172 goto fail;
1173
1174 res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
1175 state->clear[i].render_pass[fs_key]);
1176 if (res != VK_SUCCESS)
1177 goto fail;
1178
1179 }
1180
1181 res = create_depthstencil_renderpass(device,
1182 samples,
1183 &state->clear[i].depthstencil_rp);
1184 if (res != VK_SUCCESS)
1185 goto fail;
1186
1187 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
1188 res = create_depthstencil_pipeline(device,
1189 VK_IMAGE_ASPECT_DEPTH_BIT,
1190 samples,
1191 j,
1192 &state->clear[i].depth_only_pipeline[j],
1193 state->clear[i].depthstencil_rp);
1194 if (res != VK_SUCCESS)
1195 goto fail;
1196
1197 res = create_depthstencil_pipeline(device,
1198 VK_IMAGE_ASPECT_STENCIL_BIT,
1199 samples,
1200 j,
1201 &state->clear[i].stencil_only_pipeline[j],
1202 state->clear[i].depthstencil_rp);
1203 if (res != VK_SUCCESS)
1204 goto fail;
1205
1206 res = create_depthstencil_pipeline(device,
1207 VK_IMAGE_ASPECT_DEPTH_BIT |
1208 VK_IMAGE_ASPECT_STENCIL_BIT,
1209 samples,
1210 j,
1211 &state->clear[i].depthstencil_pipeline[j],
1212 state->clear[i].depthstencil_rp);
1213 if (res != VK_SUCCESS)
1214 goto fail;
1215 }
1216 }
1217 return VK_SUCCESS;
1218
1219 fail:
1220 radv_device_finish_meta_clear_state(device);
1221 return res;
1222 }
1223
1224 static uint32_t
1225 radv_get_cmask_fast_clear_value(const struct radv_image *image)
1226 {
1227 uint32_t value = 0; /* Default value when no DCC. */
1228
1229 /* The fast-clear value is different for images that have both DCC and
1230 * CMASK metadata.
1231 */
1232 if (radv_image_has_dcc(image)) {
1233 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
1234 return image->info.samples > 1 ? 0xcccccccc : 0xffffffff;
1235 }
1236
1237 return value;
1238 }
1239
1240 uint32_t
1241 radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
1242 struct radv_image *image, uint32_t value)
1243 {
1244 return radv_fill_buffer(cmd_buffer, image->bo,
1245 image->offset + image->cmask.offset,
1246 image->cmask.size, value);
1247 }
1248
1249 uint32_t
1250 radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
1251 struct radv_image *image, uint32_t value)
1252 {
1253 return radv_fill_buffer(cmd_buffer, image->bo,
1254 image->offset + image->dcc_offset,
1255 image->surface.dcc_size, value);
1256 }
1257
1258 static void vi_get_fast_clear_parameters(VkFormat format,
1259 const VkClearColorValue *clear_value,
1260 uint32_t* reset_value,
1261 bool *can_avoid_fast_clear_elim)
1262 {
1263 bool values[4] = {};
1264 int extra_channel;
1265 bool main_value = false;
1266 bool extra_value = false;
1267 int i;
1268 *can_avoid_fast_clear_elim = false;
1269
1270 *reset_value = 0x20202020U;
1271
1272 const struct vk_format_description *desc = vk_format_description(format);
1273 if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
1274 format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
1275 format == VK_FORMAT_B5G6R5_UNORM_PACK16)
1276 extra_channel = -1;
1277 else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
1278 if (radv_translate_colorswap(format, false) <= 1)
1279 extra_channel = desc->nr_channels - 1;
1280 else
1281 extra_channel = 0;
1282 } else
1283 return;
1284
1285 for (i = 0; i < 4; i++) {
1286 int index = desc->swizzle[i] - VK_SWIZZLE_X;
1287 if (desc->swizzle[i] < VK_SWIZZLE_X ||
1288 desc->swizzle[i] > VK_SWIZZLE_W)
1289 continue;
1290
1291 if (desc->channel[i].pure_integer &&
1292 desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
1293 /* Use the maximum value for clamping the clear color. */
1294 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
1295
1296 values[i] = clear_value->int32[i] != 0;
1297 if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
1298 return;
1299 } else if (desc->channel[i].pure_integer &&
1300 desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
1301 /* Use the maximum value for clamping the clear color. */
1302 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
1303
1304 values[i] = clear_value->uint32[i] != 0U;
1305 if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
1306 return;
1307 } else {
1308 values[i] = clear_value->float32[i] != 0.0F;
1309 if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
1310 return;
1311 }
1312
1313 if (index == extra_channel)
1314 extra_value = values[i];
1315 else
1316 main_value = values[i];
1317 }
1318
1319 for (int i = 0; i < 4; ++i)
1320 if (values[i] != main_value &&
1321 desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
1322 desc->swizzle[i] >= VK_SWIZZLE_X &&
1323 desc->swizzle[i] <= VK_SWIZZLE_W)
1324 return;
1325
1326 *can_avoid_fast_clear_elim = true;
1327 if (main_value)
1328 *reset_value |= 0x80808080U;
1329
1330 if (extra_value)
1331 *reset_value |= 0x40404040U;
1332 return;
1333 }
1334
1335 static bool
1336 emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
1337 const VkClearAttachment *clear_att,
1338 const VkClearRect *clear_rect,
1339 enum radv_cmd_flush_bits *pre_flush,
1340 enum radv_cmd_flush_bits *post_flush,
1341 uint32_t view_mask)
1342 {
1343 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1344 const uint32_t subpass_att = clear_att->colorAttachment;
1345 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
1346 VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
1347 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
1348 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
1349 VkClearColorValue clear_value = clear_att->clearValue.color;
1350 uint32_t clear_color[2], flush_bits = 0;
1351 uint32_t cmask_clear_value;
1352 bool ret;
1353
1354 if (!radv_image_has_cmask(iview->image) && !radv_image_has_dcc(iview->image))
1355 return false;
1356
1357 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
1358 return false;
1359
1360 if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
1361 return false;
1362
1363 /* don't fast clear 3D */
1364 if (iview->image->type == VK_IMAGE_TYPE_3D)
1365 return false;
1366
1367 /* all layers are bound */
1368 if (iview->base_layer > 0)
1369 return false;
1370 if (iview->image->info.array_size != iview->layer_count)
1371 return false;
1372
1373 if (iview->image->info.levels > 1)
1374 return false;
1375
1376 if (!radv_image_extent_compare(iview->image, &iview->extent))
1377 return false;
1378
1379 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
1380 clear_rect->rect.extent.width != iview->image->info.width ||
1381 clear_rect->rect.extent.height != iview->image->info.height)
1382 return false;
1383
1384 if (view_mask && (iview->image->info.array_size >= 32 ||
1385 (1u << iview->image->info.array_size) - 1u != view_mask))
1386 return false;
1387 if (!view_mask && clear_rect->baseArrayLayer != 0)
1388 return false;
1389 if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
1390 return false;
1391
1392 /* RB+ doesn't work with CMASK fast clear on Stoney. */
1393 if (!radv_image_has_dcc(iview->image) &&
1394 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY)
1395 return false;
1396
1397 /* DCC */
1398 ret = radv_format_pack_clear_color(iview->vk_format,
1399 clear_color, &clear_value);
1400 if (ret == false)
1401 return false;
1402
1403 if (pre_flush) {
1404 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1405 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
1406 *pre_flush |= cmd_buffer->state.flush_bits;
1407 } else
1408 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1409 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1410
1411 cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
1412
1413 /* clear cmask buffer */
1414 if (radv_image_has_dcc(iview->image)) {
1415 uint32_t reset_value;
1416 bool can_avoid_fast_clear_elim;
1417 bool need_decompress_pass = false;
1418
1419 vi_get_fast_clear_parameters(iview->vk_format,
1420 &clear_value, &reset_value,
1421 &can_avoid_fast_clear_elim);
1422
1423 if (iview->image->info.samples > 1) {
1424 /* DCC fast clear with MSAA should clear CMASK. */
1425 /* FIXME: This doesn't work for now. There is a
1426 * hardware bug with fast clears and DCC for MSAA
1427 * textures. AMDVLK has a workaround but it doesn't
1428 * seem to work here. Note that we might emit useless
1429 * CB flushes but that shouldn't matter.
1430 */
1431 if (!can_avoid_fast_clear_elim)
1432 return false;
1433
1434 assert(radv_image_has_cmask(iview->image));
1435
1436 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1437 cmask_clear_value);
1438
1439 need_decompress_pass = true;
1440 }
1441
1442 if (!can_avoid_fast_clear_elim)
1443 need_decompress_pass = true;
1444
1445 flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, reset_value);
1446
1447 radv_update_fce_metadata(cmd_buffer, iview->image,
1448 need_decompress_pass);
1449 } else {
1450 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1451 cmask_clear_value);
1452 }
1453
1454 if (post_flush) {
1455 *post_flush |= flush_bits;
1456 } else {
1457 cmd_buffer->state.flush_bits |= flush_bits;
1458 }
1459
1460 radv_update_color_clear_metadata(cmd_buffer, iview->image, subpass_att,
1461 clear_color);
1462
1463 return true;
1464 }
1465
1466 /**
1467 * The parameters mean that same as those in vkCmdClearAttachments.
1468 */
1469 static void
1470 emit_clear(struct radv_cmd_buffer *cmd_buffer,
1471 const VkClearAttachment *clear_att,
1472 const VkClearRect *clear_rect,
1473 enum radv_cmd_flush_bits *pre_flush,
1474 enum radv_cmd_flush_bits *post_flush,
1475 uint32_t view_mask)
1476 {
1477 if (clear_att->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1478 if (!emit_fast_color_clear(cmd_buffer, clear_att, clear_rect,
1479 pre_flush, post_flush, view_mask))
1480 emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask);
1481 } else {
1482 assert(clear_att->aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT |
1483 VK_IMAGE_ASPECT_STENCIL_BIT));
1484 if (!emit_fast_htile_clear(cmd_buffer, clear_att, clear_rect,
1485 pre_flush, post_flush))
1486 emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
1487 }
1488 }
1489
1490 static inline bool
1491 radv_attachment_needs_clear(struct radv_cmd_state *cmd_state, uint32_t a)
1492 {
1493 uint32_t view_mask = cmd_state->subpass->view_mask;
1494 return (a != VK_ATTACHMENT_UNUSED &&
1495 cmd_state->attachments[a].pending_clear_aspects &&
1496 (!view_mask || (view_mask & ~cmd_state->attachments[a].cleared_views)));
1497 }
1498
1499 static bool
1500 radv_subpass_needs_clear(struct radv_cmd_buffer *cmd_buffer)
1501 {
1502 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1503 uint32_t a;
1504
1505 if (!cmd_state->subpass)
1506 return false;
1507
1508 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1509 a = cmd_state->subpass->color_attachments[i].attachment;
1510 if (radv_attachment_needs_clear(cmd_state, a))
1511 return true;
1512 }
1513
1514 a = cmd_state->subpass->depth_stencil_attachment.attachment;
1515 return radv_attachment_needs_clear(cmd_state, a);
1516 }
1517
1518 static void
1519 radv_subpass_clear_attachment(struct radv_cmd_buffer *cmd_buffer,
1520 struct radv_attachment_state *attachment,
1521 const VkClearAttachment *clear_att,
1522 enum radv_cmd_flush_bits *pre_flush,
1523 enum radv_cmd_flush_bits *post_flush)
1524 {
1525 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1526 uint32_t view_mask = cmd_state->subpass->view_mask;
1527
1528 VkClearRect clear_rect = {
1529 .rect = cmd_state->render_area,
1530 .baseArrayLayer = 0,
1531 .layerCount = cmd_state->framebuffer->layers,
1532 };
1533
1534 emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush,
1535 view_mask & ~attachment->cleared_views);
1536 if (view_mask)
1537 attachment->cleared_views |= view_mask;
1538 else
1539 attachment->pending_clear_aspects = 0;
1540 }
1541
1542 /**
1543 * Emit any pending attachment clears for the current subpass.
1544 *
1545 * @see radv_attachment_state::pending_clear_aspects
1546 */
1547 void
1548 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1549 {
1550 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1551 struct radv_meta_saved_state saved_state;
1552 enum radv_cmd_flush_bits pre_flush = 0;
1553 enum radv_cmd_flush_bits post_flush = 0;
1554
1555 if (!radv_subpass_needs_clear(cmd_buffer))
1556 return;
1557
1558 radv_meta_save(&saved_state, cmd_buffer,
1559 RADV_META_SAVE_GRAPHICS_PIPELINE |
1560 RADV_META_SAVE_CONSTANTS);
1561
1562 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1563 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1564
1565 if (!radv_attachment_needs_clear(cmd_state, a))
1566 continue;
1567
1568 assert(cmd_state->attachments[a].pending_clear_aspects ==
1569 VK_IMAGE_ASPECT_COLOR_BIT);
1570
1571 VkClearAttachment clear_att = {
1572 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1573 .colorAttachment = i, /* Use attachment index relative to subpass */
1574 .clearValue = cmd_state->attachments[a].clear_value,
1575 };
1576
1577 radv_subpass_clear_attachment(cmd_buffer,
1578 &cmd_state->attachments[a],
1579 &clear_att, &pre_flush,
1580 &post_flush);
1581 }
1582
1583 uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1584 if (radv_attachment_needs_clear(cmd_state, ds)) {
1585 VkClearAttachment clear_att = {
1586 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1587 .clearValue = cmd_state->attachments[ds].clear_value,
1588 };
1589
1590 radv_subpass_clear_attachment(cmd_buffer,
1591 &cmd_state->attachments[ds],
1592 &clear_att, &pre_flush,
1593 &post_flush);
1594 }
1595
1596 radv_meta_restore(&saved_state, cmd_buffer);
1597 cmd_buffer->state.flush_bits |= post_flush;
1598 }
1599
1600 static void
1601 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1602 struct radv_image *image,
1603 VkImageLayout image_layout,
1604 const VkImageSubresourceRange *range,
1605 VkFormat format, int level, int layer,
1606 const VkClearValue *clear_val)
1607 {
1608 VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1609 struct radv_image_view iview;
1610 uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level);
1611 uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level);
1612
1613 radv_image_view_init(&iview, cmd_buffer->device,
1614 &(VkImageViewCreateInfo) {
1615 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1616 .image = radv_image_to_handle(image),
1617 .viewType = radv_meta_get_view_type(image),
1618 .format = format,
1619 .subresourceRange = {
1620 .aspectMask = range->aspectMask,
1621 .baseMipLevel = range->baseMipLevel + level,
1622 .levelCount = 1,
1623 .baseArrayLayer = range->baseArrayLayer + layer,
1624 .layerCount = 1
1625 },
1626 });
1627
1628 VkFramebuffer fb;
1629 radv_CreateFramebuffer(device_h,
1630 &(VkFramebufferCreateInfo) {
1631 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1632 .attachmentCount = 1,
1633 .pAttachments = (VkImageView[]) {
1634 radv_image_view_to_handle(&iview),
1635 },
1636 .width = width,
1637 .height = height,
1638 .layers = 1
1639 },
1640 &cmd_buffer->pool->alloc,
1641 &fb);
1642
1643 VkAttachmentDescription att_desc = {
1644 .format = iview.vk_format,
1645 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1646 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1647 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1648 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1649 .initialLayout = image_layout,
1650 .finalLayout = image_layout,
1651 };
1652
1653 VkSubpassDescription subpass_desc = {
1654 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1655 .inputAttachmentCount = 0,
1656 .colorAttachmentCount = 0,
1657 .pColorAttachments = NULL,
1658 .pResolveAttachments = NULL,
1659 .pDepthStencilAttachment = NULL,
1660 .preserveAttachmentCount = 0,
1661 .pPreserveAttachments = NULL,
1662 };
1663
1664 const VkAttachmentReference att_ref = {
1665 .attachment = 0,
1666 .layout = image_layout,
1667 };
1668
1669 if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1670 subpass_desc.colorAttachmentCount = 1;
1671 subpass_desc.pColorAttachments = &att_ref;
1672 } else {
1673 subpass_desc.pDepthStencilAttachment = &att_ref;
1674 }
1675
1676 VkRenderPass pass;
1677 radv_CreateRenderPass(device_h,
1678 &(VkRenderPassCreateInfo) {
1679 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1680 .attachmentCount = 1,
1681 .pAttachments = &att_desc,
1682 .subpassCount = 1,
1683 .pSubpasses = &subpass_desc,
1684 },
1685 &cmd_buffer->pool->alloc,
1686 &pass);
1687
1688 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1689 &(VkRenderPassBeginInfo) {
1690 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1691 .renderArea = {
1692 .offset = { 0, 0, },
1693 .extent = {
1694 .width = width,
1695 .height = height,
1696 },
1697 },
1698 .renderPass = pass,
1699 .framebuffer = fb,
1700 .clearValueCount = 0,
1701 .pClearValues = NULL,
1702 },
1703 VK_SUBPASS_CONTENTS_INLINE);
1704
1705 VkClearAttachment clear_att = {
1706 .aspectMask = range->aspectMask,
1707 .colorAttachment = 0,
1708 .clearValue = *clear_val,
1709 };
1710
1711 VkClearRect clear_rect = {
1712 .rect = {
1713 .offset = { 0, 0 },
1714 .extent = { width, height },
1715 },
1716 .baseArrayLayer = range->baseArrayLayer,
1717 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1718 };
1719
1720 emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0);
1721
1722 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1723 radv_DestroyRenderPass(device_h, pass,
1724 &cmd_buffer->pool->alloc);
1725 radv_DestroyFramebuffer(device_h, fb,
1726 &cmd_buffer->pool->alloc);
1727 }
1728 static void
1729 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
1730 struct radv_image *image,
1731 VkImageLayout image_layout,
1732 const VkClearValue *clear_value,
1733 uint32_t range_count,
1734 const VkImageSubresourceRange *ranges,
1735 bool cs)
1736 {
1737 VkFormat format = image->vk_format;
1738 VkClearValue internal_clear_value = *clear_value;
1739
1740 if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
1741 uint32_t value;
1742 format = VK_FORMAT_R32_UINT;
1743 value = float3_to_rgb9e5(clear_value->color.float32);
1744 internal_clear_value.color.uint32[0] = value;
1745 }
1746
1747 if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
1748 uint8_t r, g;
1749 format = VK_FORMAT_R8_UINT;
1750 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
1751 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
1752 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
1753 }
1754
1755 for (uint32_t r = 0; r < range_count; r++) {
1756 const VkImageSubresourceRange *range = &ranges[r];
1757 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
1758 const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
1759 radv_minify(image->info.depth, range->baseMipLevel + l) :
1760 radv_get_layerCount(image, range);
1761 for (uint32_t s = 0; s < layer_count; ++s) {
1762
1763 if (cs ||
1764 (format == VK_FORMAT_R32G32B32_UINT ||
1765 format == VK_FORMAT_R32G32B32_SINT ||
1766 format == VK_FORMAT_R32G32B32_SFLOAT)) {
1767 struct radv_meta_blit2d_surf surf;
1768 surf.format = format;
1769 surf.image = image;
1770 surf.level = range->baseMipLevel + l;
1771 surf.layer = range->baseArrayLayer + s;
1772 surf.aspect_mask = range->aspectMask;
1773 radv_meta_clear_image_cs(cmd_buffer, &surf,
1774 &internal_clear_value.color);
1775 } else {
1776 radv_clear_image_layer(cmd_buffer, image, image_layout,
1777 range, format, l, s, &internal_clear_value);
1778 }
1779 }
1780 }
1781 }
1782 }
1783
1784 void radv_CmdClearColorImage(
1785 VkCommandBuffer commandBuffer,
1786 VkImage image_h,
1787 VkImageLayout imageLayout,
1788 const VkClearColorValue* pColor,
1789 uint32_t rangeCount,
1790 const VkImageSubresourceRange* pRanges)
1791 {
1792 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1793 RADV_FROM_HANDLE(radv_image, image, image_h);
1794 struct radv_meta_saved_state saved_state;
1795 bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1796
1797 if (cs) {
1798 radv_meta_save(&saved_state, cmd_buffer,
1799 RADV_META_SAVE_COMPUTE_PIPELINE |
1800 RADV_META_SAVE_CONSTANTS |
1801 RADV_META_SAVE_DESCRIPTORS);
1802 } else {
1803 radv_meta_save(&saved_state, cmd_buffer,
1804 RADV_META_SAVE_GRAPHICS_PIPELINE |
1805 RADV_META_SAVE_CONSTANTS);
1806 }
1807
1808 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1809 (const VkClearValue *) pColor,
1810 rangeCount, pRanges, cs);
1811
1812 radv_meta_restore(&saved_state, cmd_buffer);
1813 }
1814
1815 void radv_CmdClearDepthStencilImage(
1816 VkCommandBuffer commandBuffer,
1817 VkImage image_h,
1818 VkImageLayout imageLayout,
1819 const VkClearDepthStencilValue* pDepthStencil,
1820 uint32_t rangeCount,
1821 const VkImageSubresourceRange* pRanges)
1822 {
1823 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1824 RADV_FROM_HANDLE(radv_image, image, image_h);
1825 struct radv_meta_saved_state saved_state;
1826
1827 radv_meta_save(&saved_state, cmd_buffer,
1828 RADV_META_SAVE_GRAPHICS_PIPELINE |
1829 RADV_META_SAVE_CONSTANTS);
1830
1831 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1832 (const VkClearValue *) pDepthStencil,
1833 rangeCount, pRanges, false);
1834
1835 radv_meta_restore(&saved_state, cmd_buffer);
1836 }
1837
1838 void radv_CmdClearAttachments(
1839 VkCommandBuffer commandBuffer,
1840 uint32_t attachmentCount,
1841 const VkClearAttachment* pAttachments,
1842 uint32_t rectCount,
1843 const VkClearRect* pRects)
1844 {
1845 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1846 struct radv_meta_saved_state saved_state;
1847 enum radv_cmd_flush_bits pre_flush = 0;
1848 enum radv_cmd_flush_bits post_flush = 0;
1849
1850 if (!cmd_buffer->state.subpass)
1851 return;
1852
1853 radv_meta_save(&saved_state, cmd_buffer,
1854 RADV_META_SAVE_GRAPHICS_PIPELINE |
1855 RADV_META_SAVE_CONSTANTS);
1856
1857 /* FINISHME: We can do better than this dumb loop. It thrashes too much
1858 * state.
1859 */
1860 for (uint32_t a = 0; a < attachmentCount; ++a) {
1861 for (uint32_t r = 0; r < rectCount; ++r) {
1862 emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush,
1863 cmd_buffer->state.subpass->view_mask);
1864 }
1865 }
1866
1867 radv_meta_restore(&saved_state, cmd_buffer);
1868 cmd_buffer->state.flush_bits |= post_flush;
1869 }