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nir: Embed the shader_info in the nir_shader again
[mesa.git] / src / amd / vulkan / radv_meta_clear.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_meta.h"
25 #include "radv_private.h"
26 #include "nir/nir_builder.h"
27
28 #include "util/format_rgb9e5.h"
29 #include "vk_format.h"
30
31 enum {
32 DEPTH_CLEAR_SLOW,
33 DEPTH_CLEAR_FAST_EXPCLEAR,
34 DEPTH_CLEAR_FAST_NO_EXPCLEAR
35 };
36
37 static void
38 build_color_shaders(struct nir_shader **out_vs,
39 struct nir_shader **out_fs,
40 uint32_t frag_output)
41 {
42 nir_builder vs_b;
43 nir_builder fs_b;
44
45 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
46 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
47
48 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
49 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
50
51 const struct glsl_type *position_type = glsl_vec4_type();
52 const struct glsl_type *color_type = glsl_vec4_type();
53
54 nir_variable *vs_out_pos =
55 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
56 "gl_Position");
57 vs_out_pos->data.location = VARYING_SLOT_POS;
58
59 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
60 nir_intrinsic_set_base(in_color_load, 0);
61 nir_intrinsic_set_range(in_color_load, 16);
62 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
63 in_color_load->num_components = 4;
64 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
65 nir_builder_instr_insert(&fs_b, &in_color_load->instr);
66
67 nir_variable *fs_out_color =
68 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
69 "f_color");
70 fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
71
72 nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
73
74 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
75 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
76
77 const struct glsl_type *layer_type = glsl_int_type();
78 nir_variable *vs_out_layer =
79 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
80 "v_layer");
81 vs_out_layer->data.location = VARYING_SLOT_LAYER;
82 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
83 nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
84
85 nir_store_var(&vs_b, vs_out_layer, inst_id, 0x1);
86
87 *out_vs = vs_b.shader;
88 *out_fs = fs_b.shader;
89 }
90
91 static VkResult
92 create_pipeline(struct radv_device *device,
93 struct radv_render_pass *render_pass,
94 uint32_t samples,
95 struct nir_shader *vs_nir,
96 struct nir_shader *fs_nir,
97 const VkPipelineVertexInputStateCreateInfo *vi_state,
98 const VkPipelineDepthStencilStateCreateInfo *ds_state,
99 const VkPipelineColorBlendStateCreateInfo *cb_state,
100 const VkPipelineLayout layout,
101 const struct radv_graphics_pipeline_create_info *extra,
102 const VkAllocationCallbacks *alloc,
103 struct radv_pipeline **pipeline)
104 {
105 VkDevice device_h = radv_device_to_handle(device);
106 VkResult result;
107
108 struct radv_shader_module vs_m = { .nir = vs_nir };
109 struct radv_shader_module fs_m = { .nir = fs_nir };
110
111 VkPipeline pipeline_h = VK_NULL_HANDLE;
112 result = radv_graphics_pipeline_create(device_h,
113 radv_pipeline_cache_to_handle(&device->meta_state.cache),
114 &(VkGraphicsPipelineCreateInfo) {
115 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
116 .stageCount = fs_nir ? 2 : 1,
117 .pStages = (VkPipelineShaderStageCreateInfo[]) {
118 {
119 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
120 .stage = VK_SHADER_STAGE_VERTEX_BIT,
121 .module = radv_shader_module_to_handle(&vs_m),
122 .pName = "main",
123 },
124 {
125 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
126 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
127 .module = radv_shader_module_to_handle(&fs_m),
128 .pName = "main",
129 },
130 },
131 .pVertexInputState = vi_state,
132 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
133 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
134 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
135 .primitiveRestartEnable = false,
136 },
137 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
138 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
139 .viewportCount = 1,
140 .scissorCount = 1,
141 },
142 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
143 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
144 .rasterizerDiscardEnable = false,
145 .polygonMode = VK_POLYGON_MODE_FILL,
146 .cullMode = VK_CULL_MODE_NONE,
147 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
148 .depthBiasEnable = false,
149 },
150 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
151 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
152 .rasterizationSamples = samples,
153 .sampleShadingEnable = false,
154 .pSampleMask = NULL,
155 .alphaToCoverageEnable = false,
156 .alphaToOneEnable = false,
157 },
158 .pDepthStencilState = ds_state,
159 .pColorBlendState = cb_state,
160 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
161 /* The meta clear pipeline declares all state as dynamic.
162 * As a consequence, vkCmdBindPipeline writes no dynamic state
163 * to the cmd buffer. Therefore, at the end of the meta clear,
164 * we need only restore dynamic state was vkCmdSet.
165 */
166 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
167 .dynamicStateCount = 8,
168 .pDynamicStates = (VkDynamicState[]) {
169 /* Everything except stencil write mask */
170 VK_DYNAMIC_STATE_VIEWPORT,
171 VK_DYNAMIC_STATE_SCISSOR,
172 VK_DYNAMIC_STATE_LINE_WIDTH,
173 VK_DYNAMIC_STATE_DEPTH_BIAS,
174 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
175 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
176 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
177 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
178 },
179 },
180 .layout = layout,
181 .flags = 0,
182 .renderPass = radv_render_pass_to_handle(render_pass),
183 .subpass = 0,
184 },
185 extra,
186 alloc,
187 &pipeline_h);
188
189 ralloc_free(vs_nir);
190 ralloc_free(fs_nir);
191
192 *pipeline = radv_pipeline_from_handle(pipeline_h);
193
194 return result;
195 }
196
197 static VkResult
198 create_color_renderpass(struct radv_device *device,
199 VkFormat vk_format,
200 uint32_t samples,
201 VkRenderPass *pass)
202 {
203 return radv_CreateRenderPass(radv_device_to_handle(device),
204 &(VkRenderPassCreateInfo) {
205 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
206 .attachmentCount = 1,
207 .pAttachments = &(VkAttachmentDescription) {
208 .format = vk_format,
209 .samples = samples,
210 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
211 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
212 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
213 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
214 },
215 .subpassCount = 1,
216 .pSubpasses = &(VkSubpassDescription) {
217 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
218 .inputAttachmentCount = 0,
219 .colorAttachmentCount = 1,
220 .pColorAttachments = &(VkAttachmentReference) {
221 .attachment = 0,
222 .layout = VK_IMAGE_LAYOUT_GENERAL,
223 },
224 .pResolveAttachments = NULL,
225 .pDepthStencilAttachment = &(VkAttachmentReference) {
226 .attachment = VK_ATTACHMENT_UNUSED,
227 .layout = VK_IMAGE_LAYOUT_GENERAL,
228 },
229 .preserveAttachmentCount = 1,
230 .pPreserveAttachments = (uint32_t[]) { 0 },
231 },
232 .dependencyCount = 0,
233 }, &device->meta_state.alloc, pass);
234 }
235
236 static VkResult
237 create_color_pipeline(struct radv_device *device,
238 uint32_t samples,
239 uint32_t frag_output,
240 struct radv_pipeline **pipeline,
241 VkRenderPass pass)
242 {
243 struct nir_shader *vs_nir;
244 struct nir_shader *fs_nir;
245 VkResult result;
246 build_color_shaders(&vs_nir, &fs_nir, frag_output);
247
248 const VkPipelineVertexInputStateCreateInfo vi_state = {
249 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
250 .vertexBindingDescriptionCount = 0,
251 .vertexAttributeDescriptionCount = 0,
252 };
253
254 const VkPipelineDepthStencilStateCreateInfo ds_state = {
255 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
256 .depthTestEnable = false,
257 .depthWriteEnable = false,
258 .depthBoundsTestEnable = false,
259 .stencilTestEnable = false,
260 };
261
262 VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
263 blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
264 .blendEnable = false,
265 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
266 VK_COLOR_COMPONENT_R_BIT |
267 VK_COLOR_COMPONENT_G_BIT |
268 VK_COLOR_COMPONENT_B_BIT,
269 };
270
271 const VkPipelineColorBlendStateCreateInfo cb_state = {
272 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
273 .logicOpEnable = false,
274 .attachmentCount = MAX_RTS,
275 .pAttachments = blend_attachment_state
276 };
277
278
279 struct radv_graphics_pipeline_create_info extra = {
280 .use_rectlist = true,
281 };
282 result = create_pipeline(device, radv_render_pass_from_handle(pass),
283 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
284 device->meta_state.clear_color_p_layout,
285 &extra, &device->meta_state.alloc, pipeline);
286
287 return result;
288 }
289
290 static void
291 destroy_pipeline(struct radv_device *device, struct radv_pipeline *pipeline)
292 {
293 if (!pipeline)
294 return;
295
296 radv_DestroyPipeline(radv_device_to_handle(device),
297 radv_pipeline_to_handle(pipeline),
298 &device->meta_state.alloc);
299
300 }
301
302 static void
303 destroy_render_pass(struct radv_device *device, VkRenderPass renderpass)
304 {
305 radv_DestroyRenderPass(radv_device_to_handle(device), renderpass,
306 &device->meta_state.alloc);
307 }
308
309 void
310 radv_device_finish_meta_clear_state(struct radv_device *device)
311 {
312 struct radv_meta_state *state = &device->meta_state;
313
314 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
315 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
316 destroy_pipeline(device, state->clear[i].color_pipelines[j]);
317 destroy_render_pass(device, state->clear[i].render_pass[j]);
318 }
319
320 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
321 destroy_pipeline(device, state->clear[i].depth_only_pipeline[j]);
322 destroy_pipeline(device, state->clear[i].stencil_only_pipeline[j]);
323 destroy_pipeline(device, state->clear[i].depthstencil_pipeline[j]);
324 }
325 destroy_render_pass(device, state->clear[i].depthstencil_rp);
326 }
327 radv_DestroyPipelineLayout(radv_device_to_handle(device),
328 state->clear_color_p_layout,
329 &state->alloc);
330 radv_DestroyPipelineLayout(radv_device_to_handle(device),
331 state->clear_depth_p_layout,
332 &state->alloc);
333 }
334
335 static void
336 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
337 const VkClearAttachment *clear_att,
338 const VkClearRect *clear_rect)
339 {
340 struct radv_device *device = cmd_buffer->device;
341 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
342 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
343 const uint32_t subpass_att = clear_att->colorAttachment;
344 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
345 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
346 const uint32_t samples = iview->image->info.samples;
347 const uint32_t samples_log2 = ffs(samples) - 1;
348 unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
349 struct radv_pipeline *pipeline;
350 VkClearColorValue clear_value = clear_att->clearValue.color;
351 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
352 VkPipeline pipeline_h;
353
354 if (fs_key == -1) {
355 radv_finishme("color clears incomplete");
356 return;
357 }
358 pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
359 pipeline_h = radv_pipeline_to_handle(pipeline);
360
361 if (!pipeline) {
362 radv_finishme("color clears incomplete");
363 return;
364 }
365 assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
366 assert(pipeline);
367 assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
368 assert(clear_att->colorAttachment < subpass->color_count);
369
370 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
371 device->meta_state.clear_color_p_layout,
372 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
373 &clear_value);
374
375 struct radv_subpass clear_subpass = {
376 .color_count = 1,
377 .color_attachments = (VkAttachmentReference[]) {
378 subpass->color_attachments[clear_att->colorAttachment]
379 },
380 .depth_stencil_attachment = (VkAttachmentReference) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
381 };
382
383 radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
384
385 if (cmd_buffer->state.pipeline != pipeline) {
386 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
387 pipeline_h);
388 }
389
390 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
391 .x = clear_rect->rect.offset.x,
392 .y = clear_rect->rect.offset.y,
393 .width = clear_rect->rect.extent.width,
394 .height = clear_rect->rect.extent.height,
395 .minDepth = 0.0f,
396 .maxDepth = 1.0f
397 });
398
399 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
400
401 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, 0);
402
403 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
404 }
405
406
407 static void
408 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
409 {
410 nir_builder vs_b, fs_b;
411
412 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
413 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
414
415 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
416 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
417 const struct glsl_type *position_out_type = glsl_vec4_type();
418
419 nir_variable *vs_out_pos =
420 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
421 "gl_Position");
422 vs_out_pos->data.location = VARYING_SLOT_POS;
423
424 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
425 nir_intrinsic_set_base(in_color_load, 0);
426 nir_intrinsic_set_range(in_color_load, 4);
427 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
428 in_color_load->num_components = 1;
429 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
430 nir_builder_instr_insert(&vs_b, &in_color_load->instr);
431
432 nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
433 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
434
435 const struct glsl_type *layer_type = glsl_int_type();
436 nir_variable *vs_out_layer =
437 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
438 "v_layer");
439 vs_out_layer->data.location = VARYING_SLOT_LAYER;
440 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
441 nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
442 nir_store_var(&vs_b, vs_out_layer, inst_id, 0x1);
443
444 *out_vs = vs_b.shader;
445 *out_fs = fs_b.shader;
446 }
447
448 static VkResult
449 create_depthstencil_renderpass(struct radv_device *device,
450 uint32_t samples,
451 VkRenderPass *render_pass)
452 {
453 return radv_CreateRenderPass(radv_device_to_handle(device),
454 &(VkRenderPassCreateInfo) {
455 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
456 .attachmentCount = 1,
457 .pAttachments = &(VkAttachmentDescription) {
458 .format = VK_FORMAT_UNDEFINED,
459 .samples = samples,
460 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
461 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
462 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
463 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
464 },
465 .subpassCount = 1,
466 .pSubpasses = &(VkSubpassDescription) {
467 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
468 .inputAttachmentCount = 0,
469 .colorAttachmentCount = 0,
470 .pColorAttachments = NULL,
471 .pResolveAttachments = NULL,
472 .pDepthStencilAttachment = &(VkAttachmentReference) {
473 .attachment = 0,
474 .layout = VK_IMAGE_LAYOUT_GENERAL,
475 },
476 .preserveAttachmentCount = 1,
477 .pPreserveAttachments = (uint32_t[]) { 0 },
478 },
479 .dependencyCount = 0,
480 }, &device->meta_state.alloc, render_pass);
481 }
482
483 static VkResult
484 create_depthstencil_pipeline(struct radv_device *device,
485 VkImageAspectFlags aspects,
486 uint32_t samples,
487 int index,
488 struct radv_pipeline **pipeline,
489 VkRenderPass render_pass)
490 {
491 struct nir_shader *vs_nir, *fs_nir;
492 VkResult result;
493 build_depthstencil_shader(&vs_nir, &fs_nir);
494
495 const VkPipelineVertexInputStateCreateInfo vi_state = {
496 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
497 .vertexBindingDescriptionCount = 0,
498 .vertexAttributeDescriptionCount = 0,
499 };
500
501 const VkPipelineDepthStencilStateCreateInfo ds_state = {
502 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
503 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
504 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
505 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
506 .depthBoundsTestEnable = false,
507 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
508 .front = {
509 .passOp = VK_STENCIL_OP_REPLACE,
510 .compareOp = VK_COMPARE_OP_ALWAYS,
511 .writeMask = UINT32_MAX,
512 .reference = 0, /* dynamic */
513 },
514 .back = { 0 /* dont care */ },
515 };
516
517 const VkPipelineColorBlendStateCreateInfo cb_state = {
518 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
519 .logicOpEnable = false,
520 .attachmentCount = 0,
521 .pAttachments = NULL,
522 };
523
524 struct radv_graphics_pipeline_create_info extra = {
525 .use_rectlist = true,
526 };
527
528 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
529 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
530 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
531 }
532 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
533 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
534 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
535 }
536 result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
537 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
538 device->meta_state.clear_depth_p_layout,
539 &extra, &device->meta_state.alloc, pipeline);
540 return result;
541 }
542
543 static bool depth_view_can_fast_clear(const struct radv_image_view *iview,
544 VkImageLayout layout,
545 const VkClearRect *clear_rect)
546 {
547 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
548 clear_rect->rect.extent.width != iview->extent.width ||
549 clear_rect->rect.extent.height != iview->extent.height)
550 return false;
551 if (iview->image->surface.htile_size &&
552 iview->base_mip == 0 &&
553 iview->base_layer == 0 &&
554 radv_layout_can_expclear(iview->image, layout) &&
555 !radv_image_extent_compare(iview->image, &iview->extent))
556 return true;
557 return false;
558 }
559
560 static struct radv_pipeline *
561 pick_depthstencil_pipeline(struct radv_meta_state *meta_state,
562 const struct radv_image_view *iview,
563 int samples_log2,
564 VkImageAspectFlags aspects,
565 VkImageLayout layout,
566 const VkClearRect *clear_rect,
567 VkClearDepthStencilValue clear_value)
568 {
569 bool fast = depth_view_can_fast_clear(iview, layout, clear_rect);
570 int index = DEPTH_CLEAR_SLOW;
571
572 if (fast) {
573 /* we don't know the previous clear values, so we always have
574 * the NO_EXPCLEAR path */
575 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
576 }
577
578 switch (aspects) {
579 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
580 return meta_state->clear[samples_log2].depthstencil_pipeline[index];
581 case VK_IMAGE_ASPECT_DEPTH_BIT:
582 return meta_state->clear[samples_log2].depth_only_pipeline[index];
583 case VK_IMAGE_ASPECT_STENCIL_BIT:
584 return meta_state->clear[samples_log2].stencil_only_pipeline[index];
585 }
586 unreachable("expected depth or stencil aspect");
587 }
588
589 static void
590 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
591 const VkClearAttachment *clear_att,
592 const VkClearRect *clear_rect)
593 {
594 struct radv_device *device = cmd_buffer->device;
595 struct radv_meta_state *meta_state = &device->meta_state;
596 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
597 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
598 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
599 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
600 VkImageAspectFlags aspects = clear_att->aspectMask;
601 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
602 const uint32_t samples = iview->image->info.samples;
603 const uint32_t samples_log2 = ffs(samples) - 1;
604 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
605
606 assert(aspects == VK_IMAGE_ASPECT_DEPTH_BIT ||
607 aspects == VK_IMAGE_ASPECT_STENCIL_BIT ||
608 aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
609 VK_IMAGE_ASPECT_STENCIL_BIT));
610 assert(pass_att != VK_ATTACHMENT_UNUSED);
611
612 if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
613 clear_value.depth = 1.0f;
614
615 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
616 device->meta_state.clear_depth_p_layout,
617 VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
618 &clear_value.depth);
619
620 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
621 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
622 clear_value.stencil);
623 }
624
625 struct radv_pipeline *pipeline = pick_depthstencil_pipeline(meta_state,
626 iview,
627 samples_log2,
628 aspects,
629 subpass->depth_stencil_attachment.layout,
630 clear_rect,
631 clear_value);
632 if (cmd_buffer->state.pipeline != pipeline) {
633 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
634 radv_pipeline_to_handle(pipeline));
635 }
636
637 if (depth_view_can_fast_clear(iview, subpass->depth_stencil_attachment.layout, clear_rect))
638 radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
639
640 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
641 .x = clear_rect->rect.offset.x,
642 .y = clear_rect->rect.offset.y,
643 .width = clear_rect->rect.extent.width,
644 .height = clear_rect->rect.extent.height,
645 .minDepth = 0.0f,
646 .maxDepth = 1.0f
647 });
648
649 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
650
651 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, 0);
652 }
653
654
655 static VkFormat pipeline_formats[] = {
656 VK_FORMAT_R8G8B8A8_UNORM,
657 VK_FORMAT_R8G8B8A8_UINT,
658 VK_FORMAT_R8G8B8A8_SINT,
659 VK_FORMAT_R16G16B16A16_UNORM,
660 VK_FORMAT_R16G16B16A16_SNORM,
661 VK_FORMAT_R16G16B16A16_UINT,
662 VK_FORMAT_R16G16B16A16_SINT,
663 VK_FORMAT_R32_SFLOAT,
664 VK_FORMAT_R32G32_SFLOAT,
665 VK_FORMAT_R32G32B32A32_SFLOAT
666 };
667
668 VkResult
669 radv_device_init_meta_clear_state(struct radv_device *device)
670 {
671 VkResult res;
672 struct radv_meta_state *state = &device->meta_state;
673
674 memset(&device->meta_state.clear, 0, sizeof(device->meta_state.clear));
675
676 VkPipelineLayoutCreateInfo pl_color_create_info = {
677 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
678 .setLayoutCount = 0,
679 .pushConstantRangeCount = 1,
680 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
681 };
682
683 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
684 &pl_color_create_info,
685 &device->meta_state.alloc,
686 &device->meta_state.clear_color_p_layout);
687 if (res != VK_SUCCESS)
688 goto fail;
689
690 VkPipelineLayoutCreateInfo pl_depth_create_info = {
691 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
692 .setLayoutCount = 0,
693 .pushConstantRangeCount = 1,
694 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
695 };
696
697 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
698 &pl_depth_create_info,
699 &device->meta_state.alloc,
700 &device->meta_state.clear_depth_p_layout);
701 if (res != VK_SUCCESS)
702 goto fail;
703
704 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
705 uint32_t samples = 1 << i;
706 for (uint32_t j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
707 VkFormat format = pipeline_formats[j];
708 unsigned fs_key = radv_format_meta_fs_key(format);
709 assert(!state->clear[i].color_pipelines[fs_key]);
710
711 res = create_color_renderpass(device, format, samples,
712 &state->clear[i].render_pass[fs_key]);
713 if (res != VK_SUCCESS)
714 goto fail;
715
716 res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
717 state->clear[i].render_pass[fs_key]);
718 if (res != VK_SUCCESS)
719 goto fail;
720
721 }
722
723 res = create_depthstencil_renderpass(device,
724 samples,
725 &state->clear[i].depthstencil_rp);
726 if (res != VK_SUCCESS)
727 goto fail;
728
729 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
730 res = create_depthstencil_pipeline(device,
731 VK_IMAGE_ASPECT_DEPTH_BIT,
732 samples,
733 j,
734 &state->clear[i].depth_only_pipeline[j],
735 state->clear[i].depthstencil_rp);
736 if (res != VK_SUCCESS)
737 goto fail;
738
739 res = create_depthstencil_pipeline(device,
740 VK_IMAGE_ASPECT_STENCIL_BIT,
741 samples,
742 j,
743 &state->clear[i].stencil_only_pipeline[j],
744 state->clear[i].depthstencil_rp);
745 if (res != VK_SUCCESS)
746 goto fail;
747
748 res = create_depthstencil_pipeline(device,
749 VK_IMAGE_ASPECT_DEPTH_BIT |
750 VK_IMAGE_ASPECT_STENCIL_BIT,
751 samples,
752 j,
753 &state->clear[i].depthstencil_pipeline[j],
754 state->clear[i].depthstencil_rp);
755 if (res != VK_SUCCESS)
756 goto fail;
757 }
758 }
759 return VK_SUCCESS;
760
761 fail:
762 radv_device_finish_meta_clear_state(device);
763 return res;
764 }
765
766 static bool
767 emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
768 const VkClearAttachment *clear_att,
769 const VkClearRect *clear_rect,
770 enum radv_cmd_flush_bits *pre_flush,
771 enum radv_cmd_flush_bits *post_flush)
772 {
773 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
774 const uint32_t subpass_att = clear_att->colorAttachment;
775 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
776 VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
777 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
778 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
779 VkClearColorValue clear_value = clear_att->clearValue.color;
780 uint32_t clear_color[2];
781 bool ret;
782
783 if (!iview->image->cmask.size && !iview->image->surface.dcc_size)
784 return false;
785
786 if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
787 return false;
788
789 if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
790 goto fail;
791 if (vk_format_get_blocksizebits(iview->image->vk_format) > 64)
792 goto fail;
793
794 /* don't fast clear 3D */
795 if (iview->image->type == VK_IMAGE_TYPE_3D)
796 goto fail;
797
798 /* all layers are bound */
799 if (iview->base_layer > 0)
800 goto fail;
801 if (iview->image->info.array_size != iview->layer_count)
802 goto fail;
803
804 if (iview->image->info.levels > 1)
805 goto fail;
806
807 if (iview->image->surface.level[0].mode < RADEON_SURF_MODE_1D)
808 goto fail;
809 if (!radv_image_extent_compare(iview->image, &iview->extent))
810 goto fail;
811
812 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
813 clear_rect->rect.extent.width != iview->image->info.width ||
814 clear_rect->rect.extent.height != iview->image->info.height)
815 goto fail;
816
817 if (clear_rect->baseArrayLayer != 0)
818 goto fail;
819 if (clear_rect->layerCount != iview->image->info.array_size)
820 goto fail;
821
822 /* DCC */
823 ret = radv_format_pack_clear_color(iview->image->vk_format,
824 clear_color, &clear_value);
825 if (ret == false)
826 goto fail;
827
828 if (pre_flush) {
829 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
830 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
831 *pre_flush |= cmd_buffer->state.flush_bits;
832 } else
833 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
834 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
835 /* clear cmask buffer */
836 if (iview->image->surface.dcc_size) {
837 radv_fill_buffer(cmd_buffer, iview->image->bo,
838 iview->image->offset + iview->image->dcc_offset,
839 iview->image->surface.dcc_size, 0x20202020);
840 } else {
841 radv_fill_buffer(cmd_buffer, iview->image->bo,
842 iview->image->offset + iview->image->cmask.offset,
843 iview->image->cmask.size, 0);
844 }
845
846 if (post_flush)
847 *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
848 RADV_CMD_FLAG_INV_VMEM_L1 |
849 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
850 else
851 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
852 RADV_CMD_FLAG_INV_VMEM_L1 |
853 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
854
855 radv_set_color_clear_regs(cmd_buffer, iview->image, subpass_att, clear_color);
856
857 return true;
858 fail:
859 return false;
860 }
861
862 /**
863 * The parameters mean that same as those in vkCmdClearAttachments.
864 */
865 static void
866 emit_clear(struct radv_cmd_buffer *cmd_buffer,
867 const VkClearAttachment *clear_att,
868 const VkClearRect *clear_rect,
869 enum radv_cmd_flush_bits *pre_flush,
870 enum radv_cmd_flush_bits *post_flush)
871 {
872 if (clear_att->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
873
874 if (!emit_fast_color_clear(cmd_buffer, clear_att, clear_rect,
875 pre_flush, post_flush))
876 emit_color_clear(cmd_buffer, clear_att, clear_rect);
877 } else {
878 assert(clear_att->aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT |
879 VK_IMAGE_ASPECT_STENCIL_BIT));
880 emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
881 }
882 }
883
884 static bool
885 subpass_needs_clear(const struct radv_cmd_buffer *cmd_buffer)
886 {
887 const struct radv_cmd_state *cmd_state = &cmd_buffer->state;
888 uint32_t ds;
889
890 if (!cmd_state->subpass)
891 return false;
892 ds = cmd_state->subpass->depth_stencil_attachment.attachment;
893 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
894 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
895 if (cmd_state->attachments[a].pending_clear_aspects) {
896 return true;
897 }
898 }
899
900 if (ds != VK_ATTACHMENT_UNUSED &&
901 cmd_state->attachments[ds].pending_clear_aspects) {
902 return true;
903 }
904
905 return false;
906 }
907
908 /**
909 * Emit any pending attachment clears for the current subpass.
910 *
911 * @see radv_attachment_state::pending_clear_aspects
912 */
913 void
914 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
915 {
916 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
917 struct radv_meta_saved_state saved_state;
918 enum radv_cmd_flush_bits pre_flush = 0;
919 enum radv_cmd_flush_bits post_flush = 0;
920
921 if (!subpass_needs_clear(cmd_buffer))
922 return;
923
924 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
925
926 VkClearRect clear_rect = {
927 .rect = cmd_state->render_area,
928 .baseArrayLayer = 0,
929 .layerCount = cmd_state->framebuffer->layers,
930 };
931
932 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
933 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
934
935 if (!cmd_state->attachments[a].pending_clear_aspects)
936 continue;
937
938 assert(cmd_state->attachments[a].pending_clear_aspects ==
939 VK_IMAGE_ASPECT_COLOR_BIT);
940
941 VkClearAttachment clear_att = {
942 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
943 .colorAttachment = i, /* Use attachment index relative to subpass */
944 .clearValue = cmd_state->attachments[a].clear_value,
945 };
946
947 emit_clear(cmd_buffer, &clear_att, &clear_rect, &pre_flush, &post_flush);
948 cmd_state->attachments[a].pending_clear_aspects = 0;
949 }
950
951 uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
952
953 if (ds != VK_ATTACHMENT_UNUSED) {
954
955 if (cmd_state->attachments[ds].pending_clear_aspects) {
956
957 VkClearAttachment clear_att = {
958 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
959 .clearValue = cmd_state->attachments[ds].clear_value,
960 };
961
962 emit_clear(cmd_buffer, &clear_att, &clear_rect,
963 &pre_flush, &post_flush);
964 cmd_state->attachments[ds].pending_clear_aspects = 0;
965 }
966 }
967
968 radv_meta_restore(&saved_state, cmd_buffer);
969 cmd_buffer->state.flush_bits |= post_flush;
970 }
971
972 static void
973 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
974 struct radv_image *image,
975 VkImageLayout image_layout,
976 const VkImageSubresourceRange *range,
977 VkFormat format, int level, int layer,
978 const VkClearValue *clear_val)
979 {
980 VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
981 struct radv_image_view iview;
982 radv_image_view_init(&iview, cmd_buffer->device,
983 &(VkImageViewCreateInfo) {
984 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
985 .image = radv_image_to_handle(image),
986 .viewType = radv_meta_get_view_type(image),
987 .format = format,
988 .subresourceRange = {
989 .aspectMask = range->aspectMask,
990 .baseMipLevel = range->baseMipLevel + level,
991 .levelCount = 1,
992 .baseArrayLayer = range->baseArrayLayer + layer,
993 .layerCount = 1
994 },
995 },
996 cmd_buffer, VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT);
997
998 VkFramebuffer fb;
999 radv_CreateFramebuffer(device_h,
1000 &(VkFramebufferCreateInfo) {
1001 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1002 .attachmentCount = 1,
1003 .pAttachments = (VkImageView[]) {
1004 radv_image_view_to_handle(&iview),
1005 },
1006 .width = iview.extent.width,
1007 .height = iview.extent.height,
1008 .layers = 1
1009 },
1010 &cmd_buffer->pool->alloc,
1011 &fb);
1012
1013 VkAttachmentDescription att_desc = {
1014 .format = iview.vk_format,
1015 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1016 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1017 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1018 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1019 .initialLayout = image_layout,
1020 .finalLayout = image_layout,
1021 };
1022
1023 VkSubpassDescription subpass_desc = {
1024 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1025 .inputAttachmentCount = 0,
1026 .colorAttachmentCount = 0,
1027 .pColorAttachments = NULL,
1028 .pResolveAttachments = NULL,
1029 .pDepthStencilAttachment = NULL,
1030 .preserveAttachmentCount = 0,
1031 .pPreserveAttachments = NULL,
1032 };
1033
1034 const VkAttachmentReference att_ref = {
1035 .attachment = 0,
1036 .layout = image_layout,
1037 };
1038
1039 if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1040 subpass_desc.colorAttachmentCount = 1;
1041 subpass_desc.pColorAttachments = &att_ref;
1042 } else {
1043 subpass_desc.pDepthStencilAttachment = &att_ref;
1044 }
1045
1046 VkRenderPass pass;
1047 radv_CreateRenderPass(device_h,
1048 &(VkRenderPassCreateInfo) {
1049 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1050 .attachmentCount = 1,
1051 .pAttachments = &att_desc,
1052 .subpassCount = 1,
1053 .pSubpasses = &subpass_desc,
1054 },
1055 &cmd_buffer->pool->alloc,
1056 &pass);
1057
1058 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1059 &(VkRenderPassBeginInfo) {
1060 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1061 .renderArea = {
1062 .offset = { 0, 0, },
1063 .extent = {
1064 .width = iview.extent.width,
1065 .height = iview.extent.height,
1066 },
1067 },
1068 .renderPass = pass,
1069 .framebuffer = fb,
1070 .clearValueCount = 0,
1071 .pClearValues = NULL,
1072 },
1073 VK_SUBPASS_CONTENTS_INLINE);
1074
1075 VkClearAttachment clear_att = {
1076 .aspectMask = range->aspectMask,
1077 .colorAttachment = 0,
1078 .clearValue = *clear_val,
1079 };
1080
1081 VkClearRect clear_rect = {
1082 .rect = {
1083 .offset = { 0, 0 },
1084 .extent = { iview.extent.width, iview.extent.height },
1085 },
1086 .baseArrayLayer = range->baseArrayLayer,
1087 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1088 };
1089
1090 emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL);
1091
1092 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1093 radv_DestroyRenderPass(device_h, pass,
1094 &cmd_buffer->pool->alloc);
1095 radv_DestroyFramebuffer(device_h, fb,
1096 &cmd_buffer->pool->alloc);
1097 }
1098 static void
1099 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
1100 struct radv_image *image,
1101 VkImageLayout image_layout,
1102 const VkClearValue *clear_value,
1103 uint32_t range_count,
1104 const VkImageSubresourceRange *ranges,
1105 bool cs)
1106 {
1107 VkFormat format = image->vk_format;
1108 VkClearValue internal_clear_value = *clear_value;
1109
1110 if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
1111 uint32_t value;
1112 format = VK_FORMAT_R32_UINT;
1113 value = float3_to_rgb9e5(clear_value->color.float32);
1114 internal_clear_value.color.uint32[0] = value;
1115 }
1116
1117 if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
1118 uint8_t r, g;
1119 format = VK_FORMAT_R8_UINT;
1120 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
1121 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
1122 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
1123 }
1124
1125 for (uint32_t r = 0; r < range_count; r++) {
1126 const VkImageSubresourceRange *range = &ranges[r];
1127 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
1128 const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
1129 radv_minify(image->info.depth, range->baseMipLevel + l) :
1130 radv_get_layerCount(image, range);
1131 for (uint32_t s = 0; s < layer_count; ++s) {
1132
1133 if (cs) {
1134 struct radv_meta_blit2d_surf surf;
1135 surf.format = format;
1136 surf.image = image;
1137 surf.level = range->baseMipLevel + l;
1138 surf.layer = range->baseArrayLayer + s;
1139 surf.aspect_mask = range->aspectMask;
1140 radv_meta_clear_image_cs(cmd_buffer, &surf,
1141 &internal_clear_value.color);
1142 } else {
1143 radv_clear_image_layer(cmd_buffer, image, image_layout,
1144 range, format, l, s, &internal_clear_value);
1145 }
1146 }
1147 }
1148 }
1149 }
1150
1151 union meta_saved_state {
1152 struct radv_meta_saved_state gfx;
1153 struct radv_meta_saved_compute_state compute;
1154 };
1155
1156 void radv_CmdClearColorImage(
1157 VkCommandBuffer commandBuffer,
1158 VkImage image_h,
1159 VkImageLayout imageLayout,
1160 const VkClearColorValue* pColor,
1161 uint32_t rangeCount,
1162 const VkImageSubresourceRange* pRanges)
1163 {
1164 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1165 RADV_FROM_HANDLE(radv_image, image, image_h);
1166 union meta_saved_state saved_state;
1167 bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1168
1169 if (cs)
1170 radv_meta_begin_cleari(cmd_buffer, &saved_state.compute);
1171 else
1172 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state.gfx, cmd_buffer);
1173
1174 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1175 (const VkClearValue *) pColor,
1176 rangeCount, pRanges, cs);
1177
1178 if (cs)
1179 radv_meta_end_cleari(cmd_buffer, &saved_state.compute);
1180 else
1181 radv_meta_restore(&saved_state.gfx, cmd_buffer);
1182 }
1183
1184 void radv_CmdClearDepthStencilImage(
1185 VkCommandBuffer commandBuffer,
1186 VkImage image_h,
1187 VkImageLayout imageLayout,
1188 const VkClearDepthStencilValue* pDepthStencil,
1189 uint32_t rangeCount,
1190 const VkImageSubresourceRange* pRanges)
1191 {
1192 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1193 RADV_FROM_HANDLE(radv_image, image, image_h);
1194 struct radv_meta_saved_state saved_state;
1195
1196 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
1197
1198 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1199 (const VkClearValue *) pDepthStencil,
1200 rangeCount, pRanges, false);
1201
1202 radv_meta_restore(&saved_state, cmd_buffer);
1203 }
1204
1205 void radv_CmdClearAttachments(
1206 VkCommandBuffer commandBuffer,
1207 uint32_t attachmentCount,
1208 const VkClearAttachment* pAttachments,
1209 uint32_t rectCount,
1210 const VkClearRect* pRects)
1211 {
1212 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1213 struct radv_meta_saved_state saved_state;
1214 enum radv_cmd_flush_bits pre_flush = 0;
1215 enum radv_cmd_flush_bits post_flush = 0;
1216
1217 if (!cmd_buffer->state.subpass)
1218 return;
1219
1220 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
1221
1222 /* FINISHME: We can do better than this dumb loop. It thrashes too much
1223 * state.
1224 */
1225 for (uint32_t a = 0; a < attachmentCount; ++a) {
1226 for (uint32_t r = 0; r < rectCount; ++r) {
1227 emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush);
1228 }
1229 }
1230
1231 radv_meta_restore(&saved_state, cmd_buffer);
1232 cmd_buffer->state.flush_bits |= post_flush;
1233 }