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radv: use ac_surface data structures
[mesa.git] / src / amd / vulkan / radv_meta_clear.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_meta.h"
25 #include "radv_private.h"
26 #include "nir/nir_builder.h"
27
28 #include "util/format_rgb9e5.h"
29 #include "vk_format.h"
30
31 enum {
32 DEPTH_CLEAR_SLOW,
33 DEPTH_CLEAR_FAST_EXPCLEAR,
34 DEPTH_CLEAR_FAST_NO_EXPCLEAR
35 };
36
37 static void
38 build_color_shaders(struct nir_shader **out_vs,
39 struct nir_shader **out_fs,
40 uint32_t frag_output)
41 {
42 nir_builder vs_b;
43 nir_builder fs_b;
44
45 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
46 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
47
48 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
49 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
50
51 const struct glsl_type *position_type = glsl_vec4_type();
52 const struct glsl_type *color_type = glsl_vec4_type();
53
54 nir_variable *vs_out_pos =
55 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
56 "gl_Position");
57 vs_out_pos->data.location = VARYING_SLOT_POS;
58
59 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
60 nir_intrinsic_set_base(in_color_load, 0);
61 nir_intrinsic_set_range(in_color_load, 16);
62 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
63 in_color_load->num_components = 4;
64 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
65 nir_builder_instr_insert(&fs_b, &in_color_load->instr);
66
67 nir_variable *fs_out_color =
68 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
69 "f_color");
70 fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
71
72 nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
73
74 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
75 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
76
77 const struct glsl_type *layer_type = glsl_int_type();
78 nir_variable *vs_out_layer =
79 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
80 "v_layer");
81 vs_out_layer->data.location = VARYING_SLOT_LAYER;
82 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
83 nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
84
85 nir_store_var(&vs_b, vs_out_layer, inst_id, 0x1);
86
87 *out_vs = vs_b.shader;
88 *out_fs = fs_b.shader;
89 }
90
91 static VkResult
92 create_pipeline(struct radv_device *device,
93 struct radv_render_pass *render_pass,
94 uint32_t samples,
95 struct nir_shader *vs_nir,
96 struct nir_shader *fs_nir,
97 const VkPipelineVertexInputStateCreateInfo *vi_state,
98 const VkPipelineDepthStencilStateCreateInfo *ds_state,
99 const VkPipelineColorBlendStateCreateInfo *cb_state,
100 const VkPipelineLayout layout,
101 const struct radv_graphics_pipeline_create_info *extra,
102 const VkAllocationCallbacks *alloc,
103 struct radv_pipeline **pipeline)
104 {
105 VkDevice device_h = radv_device_to_handle(device);
106 VkResult result;
107
108 struct radv_shader_module vs_m = { .nir = vs_nir };
109 struct radv_shader_module fs_m = { .nir = fs_nir };
110
111 VkPipeline pipeline_h = VK_NULL_HANDLE;
112 result = radv_graphics_pipeline_create(device_h,
113 radv_pipeline_cache_to_handle(&device->meta_state.cache),
114 &(VkGraphicsPipelineCreateInfo) {
115 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
116 .stageCount = fs_nir ? 2 : 1,
117 .pStages = (VkPipelineShaderStageCreateInfo[]) {
118 {
119 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
120 .stage = VK_SHADER_STAGE_VERTEX_BIT,
121 .module = radv_shader_module_to_handle(&vs_m),
122 .pName = "main",
123 },
124 {
125 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
126 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
127 .module = radv_shader_module_to_handle(&fs_m),
128 .pName = "main",
129 },
130 },
131 .pVertexInputState = vi_state,
132 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
133 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
134 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
135 .primitiveRestartEnable = false,
136 },
137 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
138 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
139 .viewportCount = 1,
140 .scissorCount = 1,
141 },
142 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
143 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
144 .rasterizerDiscardEnable = false,
145 .polygonMode = VK_POLYGON_MODE_FILL,
146 .cullMode = VK_CULL_MODE_NONE,
147 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
148 .depthBiasEnable = false,
149 },
150 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
151 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
152 .rasterizationSamples = samples,
153 .sampleShadingEnable = false,
154 .pSampleMask = NULL,
155 .alphaToCoverageEnable = false,
156 .alphaToOneEnable = false,
157 },
158 .pDepthStencilState = ds_state,
159 .pColorBlendState = cb_state,
160 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
161 /* The meta clear pipeline declares all state as dynamic.
162 * As a consequence, vkCmdBindPipeline writes no dynamic state
163 * to the cmd buffer. Therefore, at the end of the meta clear,
164 * we need only restore dynamic state was vkCmdSet.
165 */
166 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
167 .dynamicStateCount = 8,
168 .pDynamicStates = (VkDynamicState[]) {
169 /* Everything except stencil write mask */
170 VK_DYNAMIC_STATE_VIEWPORT,
171 VK_DYNAMIC_STATE_SCISSOR,
172 VK_DYNAMIC_STATE_LINE_WIDTH,
173 VK_DYNAMIC_STATE_DEPTH_BIAS,
174 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
175 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
176 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
177 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
178 },
179 },
180 .layout = layout,
181 .flags = 0,
182 .renderPass = radv_render_pass_to_handle(render_pass),
183 .subpass = 0,
184 },
185 extra,
186 alloc,
187 &pipeline_h);
188
189 ralloc_free(vs_nir);
190 ralloc_free(fs_nir);
191
192 *pipeline = radv_pipeline_from_handle(pipeline_h);
193
194 return result;
195 }
196
197 static VkResult
198 create_color_renderpass(struct radv_device *device,
199 VkFormat vk_format,
200 uint32_t samples,
201 VkRenderPass *pass)
202 {
203 return radv_CreateRenderPass(radv_device_to_handle(device),
204 &(VkRenderPassCreateInfo) {
205 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
206 .attachmentCount = 1,
207 .pAttachments = &(VkAttachmentDescription) {
208 .format = vk_format,
209 .samples = samples,
210 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
211 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
212 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
213 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
214 },
215 .subpassCount = 1,
216 .pSubpasses = &(VkSubpassDescription) {
217 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
218 .inputAttachmentCount = 0,
219 .colorAttachmentCount = 1,
220 .pColorAttachments = &(VkAttachmentReference) {
221 .attachment = 0,
222 .layout = VK_IMAGE_LAYOUT_GENERAL,
223 },
224 .pResolveAttachments = NULL,
225 .pDepthStencilAttachment = &(VkAttachmentReference) {
226 .attachment = VK_ATTACHMENT_UNUSED,
227 .layout = VK_IMAGE_LAYOUT_GENERAL,
228 },
229 .preserveAttachmentCount = 1,
230 .pPreserveAttachments = (uint32_t[]) { 0 },
231 },
232 .dependencyCount = 0,
233 }, &device->meta_state.alloc, pass);
234 }
235
236 static VkResult
237 create_color_pipeline(struct radv_device *device,
238 uint32_t samples,
239 uint32_t frag_output,
240 struct radv_pipeline **pipeline,
241 VkRenderPass pass)
242 {
243 struct nir_shader *vs_nir;
244 struct nir_shader *fs_nir;
245 VkResult result;
246 build_color_shaders(&vs_nir, &fs_nir, frag_output);
247
248 const VkPipelineVertexInputStateCreateInfo vi_state = {
249 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
250 .vertexBindingDescriptionCount = 0,
251 .vertexAttributeDescriptionCount = 0,
252 };
253
254 const VkPipelineDepthStencilStateCreateInfo ds_state = {
255 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
256 .depthTestEnable = false,
257 .depthWriteEnable = false,
258 .depthBoundsTestEnable = false,
259 .stencilTestEnable = false,
260 };
261
262 VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
263 blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
264 .blendEnable = false,
265 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
266 VK_COLOR_COMPONENT_R_BIT |
267 VK_COLOR_COMPONENT_G_BIT |
268 VK_COLOR_COMPONENT_B_BIT,
269 };
270
271 const VkPipelineColorBlendStateCreateInfo cb_state = {
272 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
273 .logicOpEnable = false,
274 .attachmentCount = MAX_RTS,
275 .pAttachments = blend_attachment_state
276 };
277
278
279 struct radv_graphics_pipeline_create_info extra = {
280 .use_rectlist = true,
281 };
282 result = create_pipeline(device, radv_render_pass_from_handle(pass),
283 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
284 device->meta_state.clear_color_p_layout,
285 &extra, &device->meta_state.alloc, pipeline);
286
287 return result;
288 }
289
290 static void
291 destroy_pipeline(struct radv_device *device, struct radv_pipeline *pipeline)
292 {
293 if (!pipeline)
294 return;
295
296 radv_DestroyPipeline(radv_device_to_handle(device),
297 radv_pipeline_to_handle(pipeline),
298 &device->meta_state.alloc);
299
300 }
301
302 static void
303 destroy_render_pass(struct radv_device *device, VkRenderPass renderpass)
304 {
305 radv_DestroyRenderPass(radv_device_to_handle(device), renderpass,
306 &device->meta_state.alloc);
307 }
308
309 void
310 radv_device_finish_meta_clear_state(struct radv_device *device)
311 {
312 struct radv_meta_state *state = &device->meta_state;
313
314 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
315 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
316 destroy_pipeline(device, state->clear[i].color_pipelines[j]);
317 destroy_render_pass(device, state->clear[i].render_pass[j]);
318 }
319
320 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
321 destroy_pipeline(device, state->clear[i].depth_only_pipeline[j]);
322 destroy_pipeline(device, state->clear[i].stencil_only_pipeline[j]);
323 destroy_pipeline(device, state->clear[i].depthstencil_pipeline[j]);
324 }
325 destroy_render_pass(device, state->clear[i].depthstencil_rp);
326 }
327 radv_DestroyPipelineLayout(radv_device_to_handle(device),
328 state->clear_color_p_layout,
329 &state->alloc);
330 radv_DestroyPipelineLayout(radv_device_to_handle(device),
331 state->clear_depth_p_layout,
332 &state->alloc);
333 }
334
335 static void
336 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
337 const VkClearAttachment *clear_att,
338 const VkClearRect *clear_rect)
339 {
340 struct radv_device *device = cmd_buffer->device;
341 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
342 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
343 const uint32_t subpass_att = clear_att->colorAttachment;
344 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
345 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
346 const uint32_t samples = iview->image->info.samples;
347 const uint32_t samples_log2 = ffs(samples) - 1;
348 unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
349 struct radv_pipeline *pipeline;
350 VkClearColorValue clear_value = clear_att->clearValue.color;
351 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
352 VkPipeline pipeline_h;
353
354 if (fs_key == -1) {
355 radv_finishme("color clears incomplete");
356 return;
357 }
358 pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
359 pipeline_h = radv_pipeline_to_handle(pipeline);
360
361 if (!pipeline) {
362 radv_finishme("color clears incomplete");
363 return;
364 }
365 assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
366 assert(pipeline);
367 assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
368 assert(clear_att->colorAttachment < subpass->color_count);
369
370 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
371 device->meta_state.clear_color_p_layout,
372 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
373 &clear_value);
374
375 struct radv_subpass clear_subpass = {
376 .color_count = 1,
377 .color_attachments = (VkAttachmentReference[]) {
378 subpass->color_attachments[clear_att->colorAttachment]
379 },
380 .depth_stencil_attachment = (VkAttachmentReference) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
381 };
382
383 radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
384
385 if (cmd_buffer->state.pipeline != pipeline) {
386 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
387 pipeline_h);
388 }
389
390 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
391 .x = clear_rect->rect.offset.x,
392 .y = clear_rect->rect.offset.y,
393 .width = clear_rect->rect.extent.width,
394 .height = clear_rect->rect.extent.height,
395 .minDepth = 0.0f,
396 .maxDepth = 1.0f
397 });
398
399 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
400
401 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, 0);
402
403 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
404 }
405
406
407 static void
408 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
409 {
410 nir_builder vs_b, fs_b;
411
412 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
413 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
414
415 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
416 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
417 const struct glsl_type *position_out_type = glsl_vec4_type();
418
419 nir_variable *vs_out_pos =
420 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
421 "gl_Position");
422 vs_out_pos->data.location = VARYING_SLOT_POS;
423
424 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
425 nir_intrinsic_set_base(in_color_load, 0);
426 nir_intrinsic_set_range(in_color_load, 4);
427 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
428 in_color_load->num_components = 1;
429 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
430 nir_builder_instr_insert(&vs_b, &in_color_load->instr);
431
432 nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
433 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
434
435 const struct glsl_type *layer_type = glsl_int_type();
436 nir_variable *vs_out_layer =
437 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
438 "v_layer");
439 vs_out_layer->data.location = VARYING_SLOT_LAYER;
440 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
441 nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
442 nir_store_var(&vs_b, vs_out_layer, inst_id, 0x1);
443
444 *out_vs = vs_b.shader;
445 *out_fs = fs_b.shader;
446 }
447
448 static VkResult
449 create_depthstencil_renderpass(struct radv_device *device,
450 uint32_t samples,
451 VkRenderPass *render_pass)
452 {
453 return radv_CreateRenderPass(radv_device_to_handle(device),
454 &(VkRenderPassCreateInfo) {
455 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
456 .attachmentCount = 1,
457 .pAttachments = &(VkAttachmentDescription) {
458 .format = VK_FORMAT_UNDEFINED,
459 .samples = samples,
460 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
461 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
462 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
463 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
464 },
465 .subpassCount = 1,
466 .pSubpasses = &(VkSubpassDescription) {
467 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
468 .inputAttachmentCount = 0,
469 .colorAttachmentCount = 0,
470 .pColorAttachments = NULL,
471 .pResolveAttachments = NULL,
472 .pDepthStencilAttachment = &(VkAttachmentReference) {
473 .attachment = 0,
474 .layout = VK_IMAGE_LAYOUT_GENERAL,
475 },
476 .preserveAttachmentCount = 1,
477 .pPreserveAttachments = (uint32_t[]) { 0 },
478 },
479 .dependencyCount = 0,
480 }, &device->meta_state.alloc, render_pass);
481 }
482
483 static VkResult
484 create_depthstencil_pipeline(struct radv_device *device,
485 VkImageAspectFlags aspects,
486 uint32_t samples,
487 int index,
488 struct radv_pipeline **pipeline,
489 VkRenderPass render_pass)
490 {
491 struct nir_shader *vs_nir, *fs_nir;
492 VkResult result;
493 build_depthstencil_shader(&vs_nir, &fs_nir);
494
495 const VkPipelineVertexInputStateCreateInfo vi_state = {
496 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
497 .vertexBindingDescriptionCount = 0,
498 .vertexAttributeDescriptionCount = 0,
499 };
500
501 const VkPipelineDepthStencilStateCreateInfo ds_state = {
502 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
503 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
504 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
505 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
506 .depthBoundsTestEnable = false,
507 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
508 .front = {
509 .passOp = VK_STENCIL_OP_REPLACE,
510 .compareOp = VK_COMPARE_OP_ALWAYS,
511 .writeMask = UINT32_MAX,
512 .reference = 0, /* dynamic */
513 },
514 .back = { 0 /* dont care */ },
515 };
516
517 const VkPipelineColorBlendStateCreateInfo cb_state = {
518 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
519 .logicOpEnable = false,
520 .attachmentCount = 0,
521 .pAttachments = NULL,
522 };
523
524 struct radv_graphics_pipeline_create_info extra = {
525 .use_rectlist = true,
526 };
527
528 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
529 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
530 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
531 }
532 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
533 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
534 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
535 }
536 result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
537 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
538 device->meta_state.clear_depth_p_layout,
539 &extra, &device->meta_state.alloc, pipeline);
540 return result;
541 }
542
543 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
544 const struct radv_image_view *iview,
545 VkImageLayout layout,
546 const VkClearRect *clear_rect)
547 {
548 uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
549 cmd_buffer->queue_family_index,
550 cmd_buffer->queue_family_index);
551 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
552 clear_rect->rect.extent.width != iview->extent.width ||
553 clear_rect->rect.extent.height != iview->extent.height)
554 return false;
555 if (iview->image->surface.htile_size &&
556 iview->base_mip == 0 &&
557 iview->base_layer == 0 &&
558 radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
559 !radv_image_extent_compare(iview->image, &iview->extent))
560 return true;
561 return false;
562 }
563
564 static struct radv_pipeline *
565 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
566 struct radv_meta_state *meta_state,
567 const struct radv_image_view *iview,
568 int samples_log2,
569 VkImageAspectFlags aspects,
570 VkImageLayout layout,
571 const VkClearRect *clear_rect,
572 VkClearDepthStencilValue clear_value)
573 {
574 bool fast = depth_view_can_fast_clear(cmd_buffer, iview, layout, clear_rect);
575 int index = DEPTH_CLEAR_SLOW;
576
577 if (fast) {
578 /* we don't know the previous clear values, so we always have
579 * the NO_EXPCLEAR path */
580 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
581 }
582
583 switch (aspects) {
584 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
585 return meta_state->clear[samples_log2].depthstencil_pipeline[index];
586 case VK_IMAGE_ASPECT_DEPTH_BIT:
587 return meta_state->clear[samples_log2].depth_only_pipeline[index];
588 case VK_IMAGE_ASPECT_STENCIL_BIT:
589 return meta_state->clear[samples_log2].stencil_only_pipeline[index];
590 }
591 unreachable("expected depth or stencil aspect");
592 }
593
594 static void
595 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
596 const VkClearAttachment *clear_att,
597 const VkClearRect *clear_rect)
598 {
599 struct radv_device *device = cmd_buffer->device;
600 struct radv_meta_state *meta_state = &device->meta_state;
601 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
602 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
603 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
604 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
605 VkImageAspectFlags aspects = clear_att->aspectMask;
606 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
607 const uint32_t samples = iview->image->info.samples;
608 const uint32_t samples_log2 = ffs(samples) - 1;
609 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
610
611 assert(aspects == VK_IMAGE_ASPECT_DEPTH_BIT ||
612 aspects == VK_IMAGE_ASPECT_STENCIL_BIT ||
613 aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
614 VK_IMAGE_ASPECT_STENCIL_BIT));
615 assert(pass_att != VK_ATTACHMENT_UNUSED);
616
617 if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
618 clear_value.depth = 1.0f;
619
620 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
621 device->meta_state.clear_depth_p_layout,
622 VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
623 &clear_value.depth);
624
625 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
626 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
627 clear_value.stencil);
628 }
629
630 struct radv_pipeline *pipeline = pick_depthstencil_pipeline(cmd_buffer,
631 meta_state,
632 iview,
633 samples_log2,
634 aspects,
635 subpass->depth_stencil_attachment.layout,
636 clear_rect,
637 clear_value);
638 if (cmd_buffer->state.pipeline != pipeline) {
639 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
640 radv_pipeline_to_handle(pipeline));
641 }
642
643 if (depth_view_can_fast_clear(cmd_buffer, iview, subpass->depth_stencil_attachment.layout, clear_rect))
644 radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
645
646 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
647 .x = clear_rect->rect.offset.x,
648 .y = clear_rect->rect.offset.y,
649 .width = clear_rect->rect.extent.width,
650 .height = clear_rect->rect.extent.height,
651 .minDepth = 0.0f,
652 .maxDepth = 1.0f
653 });
654
655 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
656
657 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, 0);
658 }
659
660 static bool
661 emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
662 const VkClearAttachment *clear_att,
663 const VkClearRect *clear_rect,
664 enum radv_cmd_flush_bits *pre_flush,
665 enum radv_cmd_flush_bits *post_flush)
666 {
667 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
668 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
669 VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
670 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
671 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
672 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
673 VkImageAspectFlags aspects = clear_att->aspectMask;
674 uint32_t clear_word;
675 bool ret;
676
677 if (!iview->image->surface.htile_size)
678 return false;
679
680 if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
681 return false;
682
683 if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
684 goto fail;
685
686 /* don't fast clear 3D */
687 if (iview->image->type == VK_IMAGE_TYPE_3D)
688 goto fail;
689
690 /* all layers are bound */
691 if (iview->base_layer > 0)
692 goto fail;
693 if (iview->image->info.array_size != iview->layer_count)
694 goto fail;
695
696 if (iview->image->info.levels > 1)
697 goto fail;
698
699 if (!radv_image_extent_compare(iview->image, &iview->extent))
700 goto fail;
701
702 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
703 clear_rect->rect.extent.width != iview->image->info.width ||
704 clear_rect->rect.extent.height != iview->image->info.height)
705 goto fail;
706
707 if (clear_rect->baseArrayLayer != 0)
708 goto fail;
709 if (clear_rect->layerCount != iview->image->info.array_size)
710 goto fail;
711
712 /* Don't do stencil clears till we have figured out if the clear words are
713 * correct. */
714 if (vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT)
715 goto fail;
716
717 if (clear_value.depth == 1.0)
718 clear_word = 0xfffffff0;
719 else if (clear_value.depth == 0.0)
720 clear_word = 0;
721 else
722 goto fail;
723
724 if (pre_flush) {
725 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
726 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
727 *pre_flush |= cmd_buffer->state.flush_bits;
728 } else
729 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
730 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
731
732 radv_fill_buffer(cmd_buffer, iview->image->bo,
733 iview->image->offset + iview->image->htile_offset,
734 iview->image->surface.htile_size, clear_word);
735
736
737 radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
738 if (post_flush)
739 *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
740 RADV_CMD_FLAG_INV_VMEM_L1 |
741 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
742 else
743 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
744 RADV_CMD_FLAG_INV_VMEM_L1 |
745 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
746 return true;
747 fail:
748 return false;
749 }
750
751 static VkFormat pipeline_formats[] = {
752 VK_FORMAT_R8G8B8A8_UNORM,
753 VK_FORMAT_R8G8B8A8_UINT,
754 VK_FORMAT_R8G8B8A8_SINT,
755 VK_FORMAT_R16G16B16A16_UNORM,
756 VK_FORMAT_R16G16B16A16_SNORM,
757 VK_FORMAT_R16G16B16A16_UINT,
758 VK_FORMAT_R16G16B16A16_SINT,
759 VK_FORMAT_R32_SFLOAT,
760 VK_FORMAT_R32G32_SFLOAT,
761 VK_FORMAT_R32G32B32A32_SFLOAT
762 };
763
764 VkResult
765 radv_device_init_meta_clear_state(struct radv_device *device)
766 {
767 VkResult res;
768 struct radv_meta_state *state = &device->meta_state;
769
770 memset(&device->meta_state.clear, 0, sizeof(device->meta_state.clear));
771
772 VkPipelineLayoutCreateInfo pl_color_create_info = {
773 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
774 .setLayoutCount = 0,
775 .pushConstantRangeCount = 1,
776 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
777 };
778
779 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
780 &pl_color_create_info,
781 &device->meta_state.alloc,
782 &device->meta_state.clear_color_p_layout);
783 if (res != VK_SUCCESS)
784 goto fail;
785
786 VkPipelineLayoutCreateInfo pl_depth_create_info = {
787 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
788 .setLayoutCount = 0,
789 .pushConstantRangeCount = 1,
790 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
791 };
792
793 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
794 &pl_depth_create_info,
795 &device->meta_state.alloc,
796 &device->meta_state.clear_depth_p_layout);
797 if (res != VK_SUCCESS)
798 goto fail;
799
800 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
801 uint32_t samples = 1 << i;
802 for (uint32_t j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
803 VkFormat format = pipeline_formats[j];
804 unsigned fs_key = radv_format_meta_fs_key(format);
805 assert(!state->clear[i].color_pipelines[fs_key]);
806
807 res = create_color_renderpass(device, format, samples,
808 &state->clear[i].render_pass[fs_key]);
809 if (res != VK_SUCCESS)
810 goto fail;
811
812 res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
813 state->clear[i].render_pass[fs_key]);
814 if (res != VK_SUCCESS)
815 goto fail;
816
817 }
818
819 res = create_depthstencil_renderpass(device,
820 samples,
821 &state->clear[i].depthstencil_rp);
822 if (res != VK_SUCCESS)
823 goto fail;
824
825 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
826 res = create_depthstencil_pipeline(device,
827 VK_IMAGE_ASPECT_DEPTH_BIT,
828 samples,
829 j,
830 &state->clear[i].depth_only_pipeline[j],
831 state->clear[i].depthstencil_rp);
832 if (res != VK_SUCCESS)
833 goto fail;
834
835 res = create_depthstencil_pipeline(device,
836 VK_IMAGE_ASPECT_STENCIL_BIT,
837 samples,
838 j,
839 &state->clear[i].stencil_only_pipeline[j],
840 state->clear[i].depthstencil_rp);
841 if (res != VK_SUCCESS)
842 goto fail;
843
844 res = create_depthstencil_pipeline(device,
845 VK_IMAGE_ASPECT_DEPTH_BIT |
846 VK_IMAGE_ASPECT_STENCIL_BIT,
847 samples,
848 j,
849 &state->clear[i].depthstencil_pipeline[j],
850 state->clear[i].depthstencil_rp);
851 if (res != VK_SUCCESS)
852 goto fail;
853 }
854 }
855 return VK_SUCCESS;
856
857 fail:
858 radv_device_finish_meta_clear_state(device);
859 return res;
860 }
861
862 static bool
863 emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
864 const VkClearAttachment *clear_att,
865 const VkClearRect *clear_rect,
866 enum radv_cmd_flush_bits *pre_flush,
867 enum radv_cmd_flush_bits *post_flush)
868 {
869 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
870 const uint32_t subpass_att = clear_att->colorAttachment;
871 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
872 VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
873 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
874 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
875 VkClearColorValue clear_value = clear_att->clearValue.color;
876 uint32_t clear_color[2];
877 bool ret;
878
879 if (!iview->image->cmask.size && !iview->image->surface.dcc_size)
880 return false;
881
882 if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
883 return false;
884
885 if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
886 goto fail;
887 if (vk_format_get_blocksizebits(iview->image->vk_format) > 64)
888 goto fail;
889
890 /* don't fast clear 3D */
891 if (iview->image->type == VK_IMAGE_TYPE_3D)
892 goto fail;
893
894 /* all layers are bound */
895 if (iview->base_layer > 0)
896 goto fail;
897 if (iview->image->info.array_size != iview->layer_count)
898 goto fail;
899
900 if (iview->image->info.levels > 1)
901 goto fail;
902
903 if (iview->image->surface.u.legacy.level[0].mode < RADEON_SURF_MODE_1D)
904 goto fail;
905 if (!radv_image_extent_compare(iview->image, &iview->extent))
906 goto fail;
907
908 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
909 clear_rect->rect.extent.width != iview->image->info.width ||
910 clear_rect->rect.extent.height != iview->image->info.height)
911 goto fail;
912
913 if (clear_rect->baseArrayLayer != 0)
914 goto fail;
915 if (clear_rect->layerCount != iview->image->info.array_size)
916 goto fail;
917
918 /* DCC */
919 ret = radv_format_pack_clear_color(iview->image->vk_format,
920 clear_color, &clear_value);
921 if (ret == false)
922 goto fail;
923
924 if (pre_flush) {
925 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
926 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
927 *pre_flush |= cmd_buffer->state.flush_bits;
928 } else
929 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
930 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
931 /* clear cmask buffer */
932 if (iview->image->surface.dcc_size) {
933 radv_fill_buffer(cmd_buffer, iview->image->bo,
934 iview->image->offset + iview->image->dcc_offset,
935 iview->image->surface.dcc_size, 0x20202020);
936 } else {
937 radv_fill_buffer(cmd_buffer, iview->image->bo,
938 iview->image->offset + iview->image->cmask.offset,
939 iview->image->cmask.size, 0);
940 }
941
942 if (post_flush)
943 *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
944 RADV_CMD_FLAG_INV_VMEM_L1 |
945 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
946 else
947 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
948 RADV_CMD_FLAG_INV_VMEM_L1 |
949 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
950
951 radv_set_color_clear_regs(cmd_buffer, iview->image, subpass_att, clear_color);
952
953 return true;
954 fail:
955 return false;
956 }
957
958 /**
959 * The parameters mean that same as those in vkCmdClearAttachments.
960 */
961 static void
962 emit_clear(struct radv_cmd_buffer *cmd_buffer,
963 const VkClearAttachment *clear_att,
964 const VkClearRect *clear_rect,
965 enum radv_cmd_flush_bits *pre_flush,
966 enum radv_cmd_flush_bits *post_flush)
967 {
968 if (clear_att->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
969
970 if (!emit_fast_color_clear(cmd_buffer, clear_att, clear_rect,
971 pre_flush, post_flush))
972 emit_color_clear(cmd_buffer, clear_att, clear_rect);
973 } else {
974 assert(clear_att->aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT |
975 VK_IMAGE_ASPECT_STENCIL_BIT));
976 if (!emit_fast_htile_clear(cmd_buffer, clear_att, clear_rect,
977 pre_flush, post_flush))
978 emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
979 }
980 }
981
982 static bool
983 subpass_needs_clear(const struct radv_cmd_buffer *cmd_buffer)
984 {
985 const struct radv_cmd_state *cmd_state = &cmd_buffer->state;
986 uint32_t ds;
987
988 if (!cmd_state->subpass)
989 return false;
990 ds = cmd_state->subpass->depth_stencil_attachment.attachment;
991 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
992 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
993 if (cmd_state->attachments[a].pending_clear_aspects) {
994 return true;
995 }
996 }
997
998 if (ds != VK_ATTACHMENT_UNUSED &&
999 cmd_state->attachments[ds].pending_clear_aspects) {
1000 return true;
1001 }
1002
1003 return false;
1004 }
1005
1006 /**
1007 * Emit any pending attachment clears for the current subpass.
1008 *
1009 * @see radv_attachment_state::pending_clear_aspects
1010 */
1011 void
1012 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1013 {
1014 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1015 struct radv_meta_saved_state saved_state;
1016 enum radv_cmd_flush_bits pre_flush = 0;
1017 enum radv_cmd_flush_bits post_flush = 0;
1018
1019 if (!subpass_needs_clear(cmd_buffer))
1020 return;
1021
1022 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
1023
1024 VkClearRect clear_rect = {
1025 .rect = cmd_state->render_area,
1026 .baseArrayLayer = 0,
1027 .layerCount = cmd_state->framebuffer->layers,
1028 };
1029
1030 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1031 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1032
1033 if (!cmd_state->attachments[a].pending_clear_aspects)
1034 continue;
1035
1036 assert(cmd_state->attachments[a].pending_clear_aspects ==
1037 VK_IMAGE_ASPECT_COLOR_BIT);
1038
1039 VkClearAttachment clear_att = {
1040 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1041 .colorAttachment = i, /* Use attachment index relative to subpass */
1042 .clearValue = cmd_state->attachments[a].clear_value,
1043 };
1044
1045 emit_clear(cmd_buffer, &clear_att, &clear_rect, &pre_flush, &post_flush);
1046 cmd_state->attachments[a].pending_clear_aspects = 0;
1047 }
1048
1049 uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1050
1051 if (ds != VK_ATTACHMENT_UNUSED) {
1052
1053 if (cmd_state->attachments[ds].pending_clear_aspects) {
1054
1055 VkClearAttachment clear_att = {
1056 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1057 .clearValue = cmd_state->attachments[ds].clear_value,
1058 };
1059
1060 emit_clear(cmd_buffer, &clear_att, &clear_rect,
1061 &pre_flush, &post_flush);
1062 cmd_state->attachments[ds].pending_clear_aspects = 0;
1063 }
1064 }
1065
1066 radv_meta_restore(&saved_state, cmd_buffer);
1067 cmd_buffer->state.flush_bits |= post_flush;
1068 }
1069
1070 static void
1071 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1072 struct radv_image *image,
1073 VkImageLayout image_layout,
1074 const VkImageSubresourceRange *range,
1075 VkFormat format, int level, int layer,
1076 const VkClearValue *clear_val)
1077 {
1078 VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1079 struct radv_image_view iview;
1080 radv_image_view_init(&iview, cmd_buffer->device,
1081 &(VkImageViewCreateInfo) {
1082 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1083 .image = radv_image_to_handle(image),
1084 .viewType = radv_meta_get_view_type(image),
1085 .format = format,
1086 .subresourceRange = {
1087 .aspectMask = range->aspectMask,
1088 .baseMipLevel = range->baseMipLevel + level,
1089 .levelCount = 1,
1090 .baseArrayLayer = range->baseArrayLayer + layer,
1091 .layerCount = 1
1092 },
1093 },
1094 cmd_buffer, VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT);
1095
1096 VkFramebuffer fb;
1097 radv_CreateFramebuffer(device_h,
1098 &(VkFramebufferCreateInfo) {
1099 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1100 .attachmentCount = 1,
1101 .pAttachments = (VkImageView[]) {
1102 radv_image_view_to_handle(&iview),
1103 },
1104 .width = iview.extent.width,
1105 .height = iview.extent.height,
1106 .layers = 1
1107 },
1108 &cmd_buffer->pool->alloc,
1109 &fb);
1110
1111 VkAttachmentDescription att_desc = {
1112 .format = iview.vk_format,
1113 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1114 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1115 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1116 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1117 .initialLayout = image_layout,
1118 .finalLayout = image_layout,
1119 };
1120
1121 VkSubpassDescription subpass_desc = {
1122 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1123 .inputAttachmentCount = 0,
1124 .colorAttachmentCount = 0,
1125 .pColorAttachments = NULL,
1126 .pResolveAttachments = NULL,
1127 .pDepthStencilAttachment = NULL,
1128 .preserveAttachmentCount = 0,
1129 .pPreserveAttachments = NULL,
1130 };
1131
1132 const VkAttachmentReference att_ref = {
1133 .attachment = 0,
1134 .layout = image_layout,
1135 };
1136
1137 if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1138 subpass_desc.colorAttachmentCount = 1;
1139 subpass_desc.pColorAttachments = &att_ref;
1140 } else {
1141 subpass_desc.pDepthStencilAttachment = &att_ref;
1142 }
1143
1144 VkRenderPass pass;
1145 radv_CreateRenderPass(device_h,
1146 &(VkRenderPassCreateInfo) {
1147 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1148 .attachmentCount = 1,
1149 .pAttachments = &att_desc,
1150 .subpassCount = 1,
1151 .pSubpasses = &subpass_desc,
1152 },
1153 &cmd_buffer->pool->alloc,
1154 &pass);
1155
1156 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1157 &(VkRenderPassBeginInfo) {
1158 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1159 .renderArea = {
1160 .offset = { 0, 0, },
1161 .extent = {
1162 .width = iview.extent.width,
1163 .height = iview.extent.height,
1164 },
1165 },
1166 .renderPass = pass,
1167 .framebuffer = fb,
1168 .clearValueCount = 0,
1169 .pClearValues = NULL,
1170 },
1171 VK_SUBPASS_CONTENTS_INLINE);
1172
1173 VkClearAttachment clear_att = {
1174 .aspectMask = range->aspectMask,
1175 .colorAttachment = 0,
1176 .clearValue = *clear_val,
1177 };
1178
1179 VkClearRect clear_rect = {
1180 .rect = {
1181 .offset = { 0, 0 },
1182 .extent = { iview.extent.width, iview.extent.height },
1183 },
1184 .baseArrayLayer = range->baseArrayLayer,
1185 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1186 };
1187
1188 emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL);
1189
1190 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1191 radv_DestroyRenderPass(device_h, pass,
1192 &cmd_buffer->pool->alloc);
1193 radv_DestroyFramebuffer(device_h, fb,
1194 &cmd_buffer->pool->alloc);
1195 }
1196 static void
1197 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
1198 struct radv_image *image,
1199 VkImageLayout image_layout,
1200 const VkClearValue *clear_value,
1201 uint32_t range_count,
1202 const VkImageSubresourceRange *ranges,
1203 bool cs)
1204 {
1205 VkFormat format = image->vk_format;
1206 VkClearValue internal_clear_value = *clear_value;
1207
1208 if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
1209 uint32_t value;
1210 format = VK_FORMAT_R32_UINT;
1211 value = float3_to_rgb9e5(clear_value->color.float32);
1212 internal_clear_value.color.uint32[0] = value;
1213 }
1214
1215 if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
1216 uint8_t r, g;
1217 format = VK_FORMAT_R8_UINT;
1218 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
1219 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
1220 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
1221 }
1222
1223 for (uint32_t r = 0; r < range_count; r++) {
1224 const VkImageSubresourceRange *range = &ranges[r];
1225 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
1226 const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
1227 radv_minify(image->info.depth, range->baseMipLevel + l) :
1228 radv_get_layerCount(image, range);
1229 for (uint32_t s = 0; s < layer_count; ++s) {
1230
1231 if (cs) {
1232 struct radv_meta_blit2d_surf surf;
1233 surf.format = format;
1234 surf.image = image;
1235 surf.level = range->baseMipLevel + l;
1236 surf.layer = range->baseArrayLayer + s;
1237 surf.aspect_mask = range->aspectMask;
1238 radv_meta_clear_image_cs(cmd_buffer, &surf,
1239 &internal_clear_value.color);
1240 } else {
1241 radv_clear_image_layer(cmd_buffer, image, image_layout,
1242 range, format, l, s, &internal_clear_value);
1243 }
1244 }
1245 }
1246 }
1247 }
1248
1249 union meta_saved_state {
1250 struct radv_meta_saved_state gfx;
1251 struct radv_meta_saved_compute_state compute;
1252 };
1253
1254 void radv_CmdClearColorImage(
1255 VkCommandBuffer commandBuffer,
1256 VkImage image_h,
1257 VkImageLayout imageLayout,
1258 const VkClearColorValue* pColor,
1259 uint32_t rangeCount,
1260 const VkImageSubresourceRange* pRanges)
1261 {
1262 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1263 RADV_FROM_HANDLE(radv_image, image, image_h);
1264 union meta_saved_state saved_state;
1265 bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1266
1267 if (cs)
1268 radv_meta_begin_cleari(cmd_buffer, &saved_state.compute);
1269 else
1270 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state.gfx, cmd_buffer);
1271
1272 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1273 (const VkClearValue *) pColor,
1274 rangeCount, pRanges, cs);
1275
1276 if (cs)
1277 radv_meta_end_cleari(cmd_buffer, &saved_state.compute);
1278 else
1279 radv_meta_restore(&saved_state.gfx, cmd_buffer);
1280 }
1281
1282 void radv_CmdClearDepthStencilImage(
1283 VkCommandBuffer commandBuffer,
1284 VkImage image_h,
1285 VkImageLayout imageLayout,
1286 const VkClearDepthStencilValue* pDepthStencil,
1287 uint32_t rangeCount,
1288 const VkImageSubresourceRange* pRanges)
1289 {
1290 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1291 RADV_FROM_HANDLE(radv_image, image, image_h);
1292 struct radv_meta_saved_state saved_state;
1293
1294 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
1295
1296 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1297 (const VkClearValue *) pDepthStencil,
1298 rangeCount, pRanges, false);
1299
1300 radv_meta_restore(&saved_state, cmd_buffer);
1301 }
1302
1303 void radv_CmdClearAttachments(
1304 VkCommandBuffer commandBuffer,
1305 uint32_t attachmentCount,
1306 const VkClearAttachment* pAttachments,
1307 uint32_t rectCount,
1308 const VkClearRect* pRects)
1309 {
1310 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1311 struct radv_meta_saved_state saved_state;
1312 enum radv_cmd_flush_bits pre_flush = 0;
1313 enum radv_cmd_flush_bits post_flush = 0;
1314
1315 if (!cmd_buffer->state.subpass)
1316 return;
1317
1318 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
1319
1320 /* FINISHME: We can do better than this dumb loop. It thrashes too much
1321 * state.
1322 */
1323 for (uint32_t a = 0; a < attachmentCount; ++a) {
1324 for (uint32_t r = 0; r < rectCount; ++r) {
1325 emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush);
1326 }
1327 }
1328
1329 radv_meta_restore(&saved_state, cmd_buffer);
1330 cmd_buffer->state.flush_bits |= post_flush;
1331 }