2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "radv_meta.h"
25 #include "radv_private.h"
26 #include "nir/nir_builder.h"
28 #include "util/format_rgb9e5.h"
29 #include "vk_format.h"
30 /** Vertex attributes for color clears. */
31 struct color_clear_vattrs
{
33 VkClearColorValue color
;
36 /** Vertex attributes for depthstencil clears. */
37 struct depthstencil_clear_vattrs
{
44 DEPTH_CLEAR_FAST_EXPCLEAR
,
45 DEPTH_CLEAR_FAST_NO_EXPCLEAR
49 build_color_shaders(struct nir_shader
**out_vs
,
50 struct nir_shader
**out_fs
,
56 nir_builder_init_simple_shader(&vs_b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
57 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
59 vs_b
.shader
->info
->name
= ralloc_strdup(vs_b
.shader
, "meta_clear_color_vs");
60 fs_b
.shader
->info
->name
= ralloc_strdup(fs_b
.shader
, "meta_clear_color_fs");
62 const struct glsl_type
*position_type
= glsl_vec4_type();
63 const struct glsl_type
*color_type
= glsl_vec4_type();
65 nir_variable
*vs_in_pos
=
66 nir_variable_create(vs_b
.shader
, nir_var_shader_in
, position_type
,
68 vs_in_pos
->data
.location
= VERT_ATTRIB_GENERIC0
;
70 nir_variable
*vs_out_pos
=
71 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, position_type
,
73 vs_out_pos
->data
.location
= VARYING_SLOT_POS
;
75 nir_variable
*vs_in_color
=
76 nir_variable_create(vs_b
.shader
, nir_var_shader_in
, color_type
,
78 vs_in_color
->data
.location
= VERT_ATTRIB_GENERIC1
;
80 nir_variable
*vs_out_color
=
81 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, color_type
,
83 vs_out_color
->data
.location
= VARYING_SLOT_VAR0
;
84 vs_out_color
->data
.interpolation
= INTERP_MODE_FLAT
;
86 nir_variable
*fs_in_color
=
87 nir_variable_create(fs_b
.shader
, nir_var_shader_in
, color_type
,
89 fs_in_color
->data
.location
= vs_out_color
->data
.location
;
90 fs_in_color
->data
.interpolation
= vs_out_color
->data
.interpolation
;
92 nir_variable
*fs_out_color
=
93 nir_variable_create(fs_b
.shader
, nir_var_shader_out
, color_type
,
95 fs_out_color
->data
.location
= FRAG_RESULT_DATA0
+ frag_output
;
97 nir_copy_var(&vs_b
, vs_out_pos
, vs_in_pos
);
98 nir_copy_var(&vs_b
, vs_out_color
, vs_in_color
);
99 nir_copy_var(&fs_b
, fs_out_color
, fs_in_color
);
101 const struct glsl_type
*layer_type
= glsl_int_type();
102 nir_variable
*vs_out_layer
=
103 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, layer_type
,
105 vs_out_layer
->data
.location
= VARYING_SLOT_LAYER
;
106 vs_out_layer
->data
.interpolation
= INTERP_MODE_FLAT
;
107 nir_ssa_def
*inst_id
= nir_load_system_value(&vs_b
, nir_intrinsic_load_instance_id
, 0);
109 nir_store_var(&vs_b
, vs_out_layer
, inst_id
, 0x1);
111 *out_vs
= vs_b
.shader
;
112 *out_fs
= fs_b
.shader
;
116 create_pipeline(struct radv_device
*device
,
117 struct radv_render_pass
*render_pass
,
119 struct nir_shader
*vs_nir
,
120 struct nir_shader
*fs_nir
,
121 const VkPipelineVertexInputStateCreateInfo
*vi_state
,
122 const VkPipelineDepthStencilStateCreateInfo
*ds_state
,
123 const VkPipelineColorBlendStateCreateInfo
*cb_state
,
124 const struct radv_graphics_pipeline_create_info
*extra
,
125 const VkAllocationCallbacks
*alloc
,
126 struct radv_pipeline
**pipeline
)
128 VkDevice device_h
= radv_device_to_handle(device
);
131 struct radv_shader_module vs_m
= { .nir
= vs_nir
};
132 struct radv_shader_module fs_m
= { .nir
= fs_nir
};
134 VkPipeline pipeline_h
= VK_NULL_HANDLE
;
135 result
= radv_graphics_pipeline_create(device_h
,
136 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
137 &(VkGraphicsPipelineCreateInfo
) {
138 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
139 .stageCount
= fs_nir
? 2 : 1,
140 .pStages
= (VkPipelineShaderStageCreateInfo
[]) {
142 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
143 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
144 .module
= radv_shader_module_to_handle(&vs_m
),
148 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
149 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
150 .module
= radv_shader_module_to_handle(&fs_m
),
154 .pVertexInputState
= vi_state
,
155 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
156 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
157 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
158 .primitiveRestartEnable
= false,
160 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
161 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
165 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
166 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
167 .rasterizerDiscardEnable
= false,
168 .polygonMode
= VK_POLYGON_MODE_FILL
,
169 .cullMode
= VK_CULL_MODE_NONE
,
170 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
,
171 .depthBiasEnable
= false,
173 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
174 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
175 .rasterizationSamples
= samples
,
176 .sampleShadingEnable
= false,
178 .alphaToCoverageEnable
= false,
179 .alphaToOneEnable
= false,
181 .pDepthStencilState
= ds_state
,
182 .pColorBlendState
= cb_state
,
183 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
184 /* The meta clear pipeline declares all state as dynamic.
185 * As a consequence, vkCmdBindPipeline writes no dynamic state
186 * to the cmd buffer. Therefore, at the end of the meta clear,
187 * we need only restore dynamic state was vkCmdSet.
189 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
190 .dynamicStateCount
= 6,
191 .pDynamicStates
= (VkDynamicState
[]) {
192 /* Everything except stencil write mask */
193 VK_DYNAMIC_STATE_LINE_WIDTH
,
194 VK_DYNAMIC_STATE_DEPTH_BIAS
,
195 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
196 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
197 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
198 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
202 .renderPass
= radv_render_pass_to_handle(render_pass
),
212 *pipeline
= radv_pipeline_from_handle(pipeline_h
);
218 create_color_renderpass(struct radv_device
*device
,
223 return radv_CreateRenderPass(radv_device_to_handle(device
),
224 &(VkRenderPassCreateInfo
) {
225 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
226 .attachmentCount
= 1,
227 .pAttachments
= &(VkAttachmentDescription
) {
230 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
231 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
232 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
233 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
236 .pSubpasses
= &(VkSubpassDescription
) {
237 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
238 .inputAttachmentCount
= 0,
239 .colorAttachmentCount
= 1,
240 .pColorAttachments
= &(VkAttachmentReference
) {
242 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
244 .pResolveAttachments
= NULL
,
245 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
246 .attachment
= VK_ATTACHMENT_UNUSED
,
247 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
249 .preserveAttachmentCount
= 1,
250 .pPreserveAttachments
= (uint32_t[]) { 0 },
252 .dependencyCount
= 0,
253 }, &device
->meta_state
.alloc
, pass
);
257 create_color_pipeline(struct radv_device
*device
,
259 uint32_t frag_output
,
260 struct radv_pipeline
**pipeline
,
263 struct nir_shader
*vs_nir
;
264 struct nir_shader
*fs_nir
;
266 build_color_shaders(&vs_nir
, &fs_nir
, frag_output
);
268 const VkPipelineVertexInputStateCreateInfo vi_state
= {
269 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
270 .vertexBindingDescriptionCount
= 1,
271 .pVertexBindingDescriptions
= (VkVertexInputBindingDescription
[]) {
274 .stride
= sizeof(struct color_clear_vattrs
),
275 .inputRate
= VK_VERTEX_INPUT_RATE_VERTEX
278 .vertexAttributeDescriptionCount
= 2,
279 .pVertexAttributeDescriptions
= (VkVertexInputAttributeDescription
[]) {
284 .format
= VK_FORMAT_R32G32_SFLOAT
,
285 .offset
= offsetof(struct color_clear_vattrs
, position
),
291 .format
= VK_FORMAT_R32G32B32A32_SFLOAT
,
292 .offset
= offsetof(struct color_clear_vattrs
, color
),
297 const VkPipelineDepthStencilStateCreateInfo ds_state
= {
298 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
299 .depthTestEnable
= false,
300 .depthWriteEnable
= false,
301 .depthBoundsTestEnable
= false,
302 .stencilTestEnable
= false,
305 VkPipelineColorBlendAttachmentState blend_attachment_state
[MAX_RTS
] = { 0 };
306 blend_attachment_state
[frag_output
] = (VkPipelineColorBlendAttachmentState
) {
307 .blendEnable
= false,
308 .colorWriteMask
= VK_COLOR_COMPONENT_A_BIT
|
309 VK_COLOR_COMPONENT_R_BIT
|
310 VK_COLOR_COMPONENT_G_BIT
|
311 VK_COLOR_COMPONENT_B_BIT
,
314 const VkPipelineColorBlendStateCreateInfo cb_state
= {
315 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
316 .logicOpEnable
= false,
317 .attachmentCount
= MAX_RTS
,
318 .pAttachments
= blend_attachment_state
322 struct radv_graphics_pipeline_create_info extra
= {
323 .use_rectlist
= true,
325 result
= create_pipeline(device
, radv_render_pass_from_handle(pass
),
326 samples
, vs_nir
, fs_nir
, &vi_state
, &ds_state
, &cb_state
,
327 &extra
, &device
->meta_state
.alloc
, pipeline
);
333 destroy_pipeline(struct radv_device
*device
, struct radv_pipeline
*pipeline
)
338 radv_DestroyPipeline(radv_device_to_handle(device
),
339 radv_pipeline_to_handle(pipeline
),
340 &device
->meta_state
.alloc
);
345 destroy_render_pass(struct radv_device
*device
, VkRenderPass renderpass
)
347 radv_DestroyRenderPass(radv_device_to_handle(device
), renderpass
,
348 &device
->meta_state
.alloc
);
352 radv_device_finish_meta_clear_state(struct radv_device
*device
)
354 struct radv_meta_state
*state
= &device
->meta_state
;
356 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->clear
); ++i
) {
357 for (uint32_t j
= 0; j
< ARRAY_SIZE(state
->clear
[i
].color_pipelines
); ++j
) {
358 destroy_pipeline(device
, state
->clear
[i
].color_pipelines
[j
]);
359 destroy_render_pass(device
, state
->clear
[i
].render_pass
[j
]);
362 for (uint32_t j
= 0; j
< NUM_DEPTH_CLEAR_PIPELINES
; j
++) {
363 destroy_pipeline(device
, state
->clear
[i
].depth_only_pipeline
[j
]);
364 destroy_pipeline(device
, state
->clear
[i
].stencil_only_pipeline
[j
]);
365 destroy_pipeline(device
, state
->clear
[i
].depthstencil_pipeline
[j
]);
367 destroy_render_pass(device
, state
->clear
[i
].depthstencil_rp
);
373 emit_color_clear(struct radv_cmd_buffer
*cmd_buffer
,
374 const VkClearAttachment
*clear_att
,
375 const VkClearRect
*clear_rect
)
377 struct radv_device
*device
= cmd_buffer
->device
;
378 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
379 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
380 const uint32_t subpass_att
= clear_att
->colorAttachment
;
381 const uint32_t pass_att
= subpass
->color_attachments
[subpass_att
].attachment
;
382 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
383 const uint32_t samples
= iview
->image
->samples
;
384 const uint32_t samples_log2
= ffs(samples
) - 1;
385 unsigned fs_key
= radv_format_meta_fs_key(iview
->vk_format
);
386 struct radv_pipeline
*pipeline
;
387 VkClearColorValue clear_value
= clear_att
->clearValue
.color
;
388 VkCommandBuffer cmd_buffer_h
= radv_cmd_buffer_to_handle(cmd_buffer
);
389 VkPipeline pipeline_h
;
393 radv_finishme("color clears incomplete");
396 pipeline
= device
->meta_state
.clear
[samples_log2
].color_pipelines
[fs_key
];
397 pipeline_h
= radv_pipeline_to_handle(pipeline
);
400 radv_finishme("color clears incomplete");
403 assert(samples_log2
< ARRAY_SIZE(device
->meta_state
.clear
));
405 assert(clear_att
->aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
);
406 assert(clear_att
->colorAttachment
< subpass
->color_count
);
408 const struct color_clear_vattrs vertex_data
[3] = {
411 clear_rect
->rect
.offset
.x
,
412 clear_rect
->rect
.offset
.y
,
414 .color
= clear_value
,
418 clear_rect
->rect
.offset
.x
,
419 clear_rect
->rect
.offset
.y
+ clear_rect
->rect
.extent
.height
,
421 .color
= clear_value
,
425 clear_rect
->rect
.offset
.x
+ clear_rect
->rect
.extent
.width
,
426 clear_rect
->rect
.offset
.y
,
428 .color
= clear_value
,
432 struct radv_subpass clear_subpass
= {
434 .color_attachments
= (VkAttachmentReference
[]) {
435 subpass
->color_attachments
[clear_att
->colorAttachment
]
437 .depth_stencil_attachment
= (VkAttachmentReference
) { VK_ATTACHMENT_UNUSED
, VK_IMAGE_LAYOUT_UNDEFINED
}
440 radv_cmd_buffer_set_subpass(cmd_buffer
, &clear_subpass
, false);
442 radv_cmd_buffer_upload_data(cmd_buffer
, sizeof(vertex_data
), 16, vertex_data
, &offset
);
443 struct radv_buffer vertex_buffer
= {
445 .size
= sizeof(vertex_data
),
446 .bo
= cmd_buffer
->upload
.upload_bo
,
451 radv_CmdBindVertexBuffers(cmd_buffer_h
, 0, 1,
452 (VkBuffer
[]) { radv_buffer_to_handle(&vertex_buffer
) },
453 (VkDeviceSize
[]) { 0 });
455 if (cmd_buffer
->state
.pipeline
!= pipeline
) {
456 radv_CmdBindPipeline(cmd_buffer_h
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
460 radv_CmdDraw(cmd_buffer_h
, 3, clear_rect
->layerCount
, 0, 0);
462 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
467 build_depthstencil_shader(struct nir_shader
**out_vs
, struct nir_shader
**out_fs
)
469 nir_builder vs_b
, fs_b
;
471 nir_builder_init_simple_shader(&vs_b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
472 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
474 vs_b
.shader
->info
->name
= ralloc_strdup(vs_b
.shader
, "meta_clear_depthstencil_vs");
475 fs_b
.shader
->info
->name
= ralloc_strdup(fs_b
.shader
, "meta_clear_depthstencil_fs");
476 const struct glsl_type
*position_type
= glsl_vec4_type();
478 nir_variable
*vs_in_pos
=
479 nir_variable_create(vs_b
.shader
, nir_var_shader_in
, position_type
,
481 vs_in_pos
->data
.location
= VERT_ATTRIB_GENERIC0
;
483 nir_variable
*vs_out_pos
=
484 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, position_type
,
486 vs_out_pos
->data
.location
= VARYING_SLOT_POS
;
488 nir_copy_var(&vs_b
, vs_out_pos
, vs_in_pos
);
490 const struct glsl_type
*layer_type
= glsl_int_type();
491 nir_variable
*vs_out_layer
=
492 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, layer_type
,
494 vs_out_layer
->data
.location
= VARYING_SLOT_LAYER
;
495 vs_out_layer
->data
.interpolation
= INTERP_MODE_FLAT
;
496 nir_ssa_def
*inst_id
= nir_load_system_value(&vs_b
, nir_intrinsic_load_instance_id
, 0);
497 nir_store_var(&vs_b
, vs_out_layer
, inst_id
, 0x1);
499 *out_vs
= vs_b
.shader
;
500 *out_fs
= fs_b
.shader
;
504 create_depthstencil_renderpass(struct radv_device
*device
,
506 VkRenderPass
*render_pass
)
508 return radv_CreateRenderPass(radv_device_to_handle(device
),
509 &(VkRenderPassCreateInfo
) {
510 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
511 .attachmentCount
= 1,
512 .pAttachments
= &(VkAttachmentDescription
) {
513 .format
= VK_FORMAT_UNDEFINED
,
515 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
516 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
517 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
518 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
521 .pSubpasses
= &(VkSubpassDescription
) {
522 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
523 .inputAttachmentCount
= 0,
524 .colorAttachmentCount
= 0,
525 .pColorAttachments
= NULL
,
526 .pResolveAttachments
= NULL
,
527 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
529 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
531 .preserveAttachmentCount
= 1,
532 .pPreserveAttachments
= (uint32_t[]) { 0 },
534 .dependencyCount
= 0,
535 }, &device
->meta_state
.alloc
, render_pass
);
539 create_depthstencil_pipeline(struct radv_device
*device
,
540 VkImageAspectFlags aspects
,
543 struct radv_pipeline
**pipeline
,
544 VkRenderPass render_pass
)
546 struct nir_shader
*vs_nir
, *fs_nir
;
548 build_depthstencil_shader(&vs_nir
, &fs_nir
);
550 const VkPipelineVertexInputStateCreateInfo vi_state
= {
551 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
552 .vertexBindingDescriptionCount
= 1,
553 .pVertexBindingDescriptions
= (VkVertexInputBindingDescription
[]) {
556 .stride
= sizeof(struct depthstencil_clear_vattrs
),
557 .inputRate
= VK_VERTEX_INPUT_RATE_VERTEX
560 .vertexAttributeDescriptionCount
= 1,
561 .pVertexAttributeDescriptions
= (VkVertexInputAttributeDescription
[]) {
566 .format
= VK_FORMAT_R32G32B32_SFLOAT
,
567 .offset
= offsetof(struct depthstencil_clear_vattrs
, position
),
572 const VkPipelineDepthStencilStateCreateInfo ds_state
= {
573 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
574 .depthTestEnable
= (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
),
575 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
576 .depthWriteEnable
= (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
),
577 .depthBoundsTestEnable
= false,
578 .stencilTestEnable
= (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
),
580 .passOp
= VK_STENCIL_OP_REPLACE
,
581 .compareOp
= VK_COMPARE_OP_ALWAYS
,
582 .writeMask
= UINT32_MAX
,
583 .reference
= 0, /* dynamic */
585 .back
= { 0 /* dont care */ },
588 const VkPipelineColorBlendStateCreateInfo cb_state
= {
589 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
590 .logicOpEnable
= false,
591 .attachmentCount
= 0,
592 .pAttachments
= NULL
,
595 struct radv_graphics_pipeline_create_info extra
= {
596 .use_rectlist
= true,
599 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
600 extra
.db_depth_clear
= index
== DEPTH_CLEAR_SLOW
? false : true;
601 extra
.db_depth_disable_expclear
= index
== DEPTH_CLEAR_FAST_NO_EXPCLEAR
? true : false;
603 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
604 extra
.db_stencil_clear
= index
== DEPTH_CLEAR_SLOW
? false : true;
605 extra
.db_stencil_disable_expclear
= index
== DEPTH_CLEAR_FAST_NO_EXPCLEAR
? true : false;
607 result
= create_pipeline(device
, radv_render_pass_from_handle(render_pass
),
608 samples
, vs_nir
, fs_nir
, &vi_state
, &ds_state
, &cb_state
,
609 &extra
, &device
->meta_state
.alloc
, pipeline
);
613 static bool depth_view_can_fast_clear(const struct radv_image_view
*iview
,
614 VkImageLayout layout
,
615 const VkClearRect
*clear_rect
)
617 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
618 clear_rect
->rect
.extent
.width
!= iview
->extent
.width
||
619 clear_rect
->rect
.extent
.height
!= iview
->extent
.height
)
621 if (iview
->image
->htile
.size
&&
622 iview
->base_mip
== 0 &&
623 iview
->base_layer
== 0 &&
624 radv_layout_can_expclear(iview
->image
, layout
) &&
625 memcmp(&iview
->extent
, &iview
->image
->extent
, sizeof(iview
->extent
)) == 0)
630 static struct radv_pipeline
*
631 pick_depthstencil_pipeline(struct radv_meta_state
*meta_state
,
632 const struct radv_image_view
*iview
,
634 VkImageAspectFlags aspects
,
635 VkImageLayout layout
,
636 const VkClearRect
*clear_rect
,
637 VkClearDepthStencilValue clear_value
)
639 bool fast
= depth_view_can_fast_clear(iview
, layout
, clear_rect
);
640 int index
= DEPTH_CLEAR_SLOW
;
643 /* we don't know the previous clear values, so we always have
644 * the NO_EXPCLEAR path */
645 index
= DEPTH_CLEAR_FAST_NO_EXPCLEAR
;
649 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
650 return meta_state
->clear
[samples_log2
].depthstencil_pipeline
[index
];
651 case VK_IMAGE_ASPECT_DEPTH_BIT
:
652 return meta_state
->clear
[samples_log2
].depth_only_pipeline
[index
];
653 case VK_IMAGE_ASPECT_STENCIL_BIT
:
654 return meta_state
->clear
[samples_log2
].stencil_only_pipeline
[index
];
656 unreachable("expected depth or stencil aspect");
660 emit_depthstencil_clear(struct radv_cmd_buffer
*cmd_buffer
,
661 const VkClearAttachment
*clear_att
,
662 const VkClearRect
*clear_rect
)
664 struct radv_device
*device
= cmd_buffer
->device
;
665 struct radv_meta_state
*meta_state
= &device
->meta_state
;
666 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
667 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
668 const uint32_t pass_att
= subpass
->depth_stencil_attachment
.attachment
;
669 VkClearDepthStencilValue clear_value
= clear_att
->clearValue
.depthStencil
;
670 VkImageAspectFlags aspects
= clear_att
->aspectMask
;
671 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
672 const uint32_t samples
= iview
->image
->samples
;
673 const uint32_t samples_log2
= ffs(samples
) - 1;
674 VkCommandBuffer cmd_buffer_h
= radv_cmd_buffer_to_handle(cmd_buffer
);
677 assert(aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
||
678 aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
||
679 aspects
== (VK_IMAGE_ASPECT_DEPTH_BIT
|
680 VK_IMAGE_ASPECT_STENCIL_BIT
));
681 assert(pass_att
!= VK_ATTACHMENT_UNUSED
);
683 const struct depthstencil_clear_vattrs vertex_data
[3] = {
686 clear_rect
->rect
.offset
.x
,
687 clear_rect
->rect
.offset
.y
,
689 .depth_clear
= clear_value
.depth
,
693 clear_rect
->rect
.offset
.x
,
694 clear_rect
->rect
.offset
.y
+ clear_rect
->rect
.extent
.height
,
696 .depth_clear
= clear_value
.depth
,
700 clear_rect
->rect
.offset
.x
+ clear_rect
->rect
.extent
.width
,
701 clear_rect
->rect
.offset
.y
,
703 .depth_clear
= clear_value
.depth
,
707 radv_cmd_buffer_upload_data(cmd_buffer
, sizeof(vertex_data
), 16, vertex_data
, &offset
);
708 struct radv_buffer vertex_buffer
= {
710 .size
= sizeof(vertex_data
),
711 .bo
= cmd_buffer
->upload
.upload_bo
,
715 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
716 radv_CmdSetStencilReference(cmd_buffer_h
, VK_STENCIL_FACE_FRONT_BIT
,
717 clear_value
.stencil
);
720 radv_CmdBindVertexBuffers(cmd_buffer_h
, 0, 1,
721 (VkBuffer
[]) { radv_buffer_to_handle(&vertex_buffer
) },
722 (VkDeviceSize
[]) { 0 });
724 struct radv_pipeline
*pipeline
= pick_depthstencil_pipeline(meta_state
,
728 subpass
->depth_stencil_attachment
.layout
,
731 if (cmd_buffer
->state
.pipeline
!= pipeline
) {
732 radv_CmdBindPipeline(cmd_buffer_h
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
733 radv_pipeline_to_handle(pipeline
));
736 if (depth_view_can_fast_clear(iview
, subpass
->depth_stencil_attachment
.layout
, clear_rect
))
737 radv_set_depth_clear_regs(cmd_buffer
, iview
->image
, clear_value
, aspects
);
739 radv_CmdDraw(cmd_buffer_h
, 3, clear_rect
->layerCount
, 0, 0);
743 static VkFormat pipeline_formats
[] = {
744 VK_FORMAT_R8G8B8A8_UNORM
,
745 VK_FORMAT_R8G8B8A8_UINT
,
746 VK_FORMAT_R8G8B8A8_SINT
,
747 VK_FORMAT_R16G16B16A16_UNORM
,
748 VK_FORMAT_R16G16B16A16_SNORM
,
749 VK_FORMAT_R16G16B16A16_UINT
,
750 VK_FORMAT_R16G16B16A16_SINT
,
751 VK_FORMAT_R32_SFLOAT
,
752 VK_FORMAT_R32G32_SFLOAT
,
753 VK_FORMAT_R32G32B32A32_SFLOAT
757 radv_device_init_meta_clear_state(struct radv_device
*device
)
760 struct radv_meta_state
*state
= &device
->meta_state
;
762 memset(&device
->meta_state
.clear
, 0, sizeof(device
->meta_state
.clear
));
764 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->clear
); ++i
) {
765 uint32_t samples
= 1 << i
;
766 for (uint32_t j
= 0; j
< ARRAY_SIZE(pipeline_formats
); ++j
) {
767 VkFormat format
= pipeline_formats
[j
];
768 unsigned fs_key
= radv_format_meta_fs_key(format
);
769 assert(!state
->clear
[i
].color_pipelines
[fs_key
]);
771 res
= create_color_renderpass(device
, format
, samples
,
772 &state
->clear
[i
].render_pass
[fs_key
]);
773 if (res
!= VK_SUCCESS
)
776 res
= create_color_pipeline(device
, samples
, 0, &state
->clear
[i
].color_pipelines
[fs_key
],
777 state
->clear
[i
].render_pass
[fs_key
]);
778 if (res
!= VK_SUCCESS
)
783 res
= create_depthstencil_renderpass(device
,
785 &state
->clear
[i
].depthstencil_rp
);
786 if (res
!= VK_SUCCESS
)
789 for (uint32_t j
= 0; j
< NUM_DEPTH_CLEAR_PIPELINES
; j
++) {
790 res
= create_depthstencil_pipeline(device
,
791 VK_IMAGE_ASPECT_DEPTH_BIT
,
794 &state
->clear
[i
].depth_only_pipeline
[j
],
795 state
->clear
[i
].depthstencil_rp
);
796 if (res
!= VK_SUCCESS
)
799 res
= create_depthstencil_pipeline(device
,
800 VK_IMAGE_ASPECT_STENCIL_BIT
,
803 &state
->clear
[i
].stencil_only_pipeline
[j
],
804 state
->clear
[i
].depthstencil_rp
);
805 if (res
!= VK_SUCCESS
)
808 res
= create_depthstencil_pipeline(device
,
809 VK_IMAGE_ASPECT_DEPTH_BIT
|
810 VK_IMAGE_ASPECT_STENCIL_BIT
,
813 &state
->clear
[i
].depthstencil_pipeline
[j
],
814 state
->clear
[i
].depthstencil_rp
);
815 if (res
!= VK_SUCCESS
)
822 radv_device_finish_meta_clear_state(device
);
827 emit_fast_color_clear(struct radv_cmd_buffer
*cmd_buffer
,
828 const VkClearAttachment
*clear_att
,
829 const VkClearRect
*clear_rect
,
830 enum radv_cmd_flush_bits
*pre_flush
,
831 enum radv_cmd_flush_bits
*post_flush
)
833 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
834 const uint32_t subpass_att
= clear_att
->colorAttachment
;
835 const uint32_t pass_att
= subpass
->color_attachments
[subpass_att
].attachment
;
836 VkImageLayout image_layout
= subpass
->color_attachments
[subpass_att
].layout
;
837 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
838 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
839 VkClearColorValue clear_value
= clear_att
->clearValue
.color
;
840 uint32_t clear_color
[2];
843 if (!iview
->image
->cmask
.size
&& !iview
->image
->surface
.dcc_size
)
846 if (cmd_buffer
->device
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
)
849 if (!radv_layout_can_fast_clear(iview
->image
, image_layout
, radv_image_queue_family_mask(iview
->image
, cmd_buffer
->queue_family_index
, cmd_buffer
->queue_family_index
)))
851 if (vk_format_get_blocksizebits(iview
->image
->vk_format
) > 64)
854 /* don't fast clear 3D */
855 if (iview
->image
->type
== VK_IMAGE_TYPE_3D
)
858 /* all layers are bound */
859 if (iview
->base_layer
> 0)
861 if (iview
->image
->array_size
!= iview
->layer_count
)
864 if (iview
->image
->levels
> 1)
867 if (iview
->image
->surface
.level
[0].mode
< RADEON_SURF_MODE_1D
)
870 if (memcmp(&iview
->extent
, &iview
->image
->extent
, sizeof(iview
->extent
)))
873 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
874 clear_rect
->rect
.extent
.width
!= iview
->image
->extent
.width
||
875 clear_rect
->rect
.extent
.height
!= iview
->image
->extent
.height
)
878 if (clear_rect
->baseArrayLayer
!= 0)
880 if (clear_rect
->layerCount
!= iview
->image
->array_size
)
884 ret
= radv_format_pack_clear_color(iview
->image
->vk_format
,
885 clear_color
, &clear_value
);
890 cmd_buffer
->state
.flush_bits
|= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
891 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
) & ~ *pre_flush
;
892 *pre_flush
|= cmd_buffer
->state
.flush_bits
;
894 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
895 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
896 /* clear cmask buffer */
897 if (iview
->image
->surface
.dcc_size
) {
898 radv_fill_buffer(cmd_buffer
, iview
->image
->bo
,
899 iview
->image
->offset
+ iview
->image
->dcc_offset
,
900 iview
->image
->surface
.dcc_size
, 0x20202020);
902 radv_fill_buffer(cmd_buffer
, iview
->image
->bo
,
903 iview
->image
->offset
+ iview
->image
->cmask
.offset
,
904 iview
->image
->cmask
.size
, 0);
908 *post_flush
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
909 RADV_CMD_FLAG_INV_VMEM_L1
|
910 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
912 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
913 RADV_CMD_FLAG_INV_VMEM_L1
|
914 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
916 radv_set_color_clear_regs(cmd_buffer
, iview
->image
, subpass_att
, clear_color
);
924 * The parameters mean that same as those in vkCmdClearAttachments.
927 emit_clear(struct radv_cmd_buffer
*cmd_buffer
,
928 const VkClearAttachment
*clear_att
,
929 const VkClearRect
*clear_rect
,
930 enum radv_cmd_flush_bits
*pre_flush
,
931 enum radv_cmd_flush_bits
*post_flush
)
933 if (clear_att
->aspectMask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
935 if (!emit_fast_color_clear(cmd_buffer
, clear_att
, clear_rect
,
936 pre_flush
, post_flush
))
937 emit_color_clear(cmd_buffer
, clear_att
, clear_rect
);
939 assert(clear_att
->aspectMask
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
940 VK_IMAGE_ASPECT_STENCIL_BIT
));
941 emit_depthstencil_clear(cmd_buffer
, clear_att
, clear_rect
);
946 subpass_needs_clear(const struct radv_cmd_buffer
*cmd_buffer
)
948 const struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
951 if (!cmd_state
->subpass
)
953 ds
= cmd_state
->subpass
->depth_stencil_attachment
.attachment
;
954 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
955 uint32_t a
= cmd_state
->subpass
->color_attachments
[i
].attachment
;
956 if (cmd_state
->attachments
[a
].pending_clear_aspects
) {
961 if (ds
!= VK_ATTACHMENT_UNUSED
&&
962 cmd_state
->attachments
[ds
].pending_clear_aspects
) {
970 * Emit any pending attachment clears for the current subpass.
972 * @see radv_attachment_state::pending_clear_aspects
975 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
)
977 struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
978 struct radv_meta_saved_state saved_state
;
979 enum radv_cmd_flush_bits pre_flush
= 0;
980 enum radv_cmd_flush_bits post_flush
= 0;
982 if (!subpass_needs_clear(cmd_buffer
))
985 radv_meta_save_graphics_reset_vport_scissor(&saved_state
, cmd_buffer
);
987 VkClearRect clear_rect
= {
988 .rect
= cmd_state
->render_area
,
990 .layerCount
= cmd_state
->framebuffer
->layers
,
993 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
994 uint32_t a
= cmd_state
->subpass
->color_attachments
[i
].attachment
;
996 if (!cmd_state
->attachments
[a
].pending_clear_aspects
)
999 assert(cmd_state
->attachments
[a
].pending_clear_aspects
==
1000 VK_IMAGE_ASPECT_COLOR_BIT
);
1002 VkClearAttachment clear_att
= {
1003 .aspectMask
= VK_IMAGE_ASPECT_COLOR_BIT
,
1004 .colorAttachment
= i
, /* Use attachment index relative to subpass */
1005 .clearValue
= cmd_state
->attachments
[a
].clear_value
,
1008 emit_clear(cmd_buffer
, &clear_att
, &clear_rect
, &pre_flush
, &post_flush
);
1009 cmd_state
->attachments
[a
].pending_clear_aspects
= 0;
1012 uint32_t ds
= cmd_state
->subpass
->depth_stencil_attachment
.attachment
;
1014 if (ds
!= VK_ATTACHMENT_UNUSED
) {
1016 if (cmd_state
->attachments
[ds
].pending_clear_aspects
) {
1018 VkClearAttachment clear_att
= {
1019 .aspectMask
= cmd_state
->attachments
[ds
].pending_clear_aspects
,
1020 .clearValue
= cmd_state
->attachments
[ds
].clear_value
,
1023 emit_clear(cmd_buffer
, &clear_att
, &clear_rect
,
1024 &pre_flush
, &post_flush
);
1025 cmd_state
->attachments
[ds
].pending_clear_aspects
= 0;
1029 radv_meta_restore(&saved_state
, cmd_buffer
);
1030 cmd_buffer
->state
.flush_bits
|= post_flush
;
1034 radv_clear_image_layer(struct radv_cmd_buffer
*cmd_buffer
,
1035 struct radv_image
*image
,
1036 VkImageLayout image_layout
,
1037 const VkImageSubresourceRange
*range
,
1038 VkFormat format
, int level
, int layer
,
1039 const VkClearValue
*clear_val
)
1041 VkDevice device_h
= radv_device_to_handle(cmd_buffer
->device
);
1042 struct radv_image_view iview
;
1043 radv_image_view_init(&iview
, cmd_buffer
->device
,
1044 &(VkImageViewCreateInfo
) {
1045 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
1046 .image
= radv_image_to_handle(image
),
1047 .viewType
= radv_meta_get_view_type(image
),
1049 .subresourceRange
= {
1050 .aspectMask
= range
->aspectMask
,
1051 .baseMipLevel
= range
->baseMipLevel
+ level
,
1053 .baseArrayLayer
= range
->baseArrayLayer
+ layer
,
1057 cmd_buffer
, VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
);
1060 radv_CreateFramebuffer(device_h
,
1061 &(VkFramebufferCreateInfo
) {
1062 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
1063 .attachmentCount
= 1,
1064 .pAttachments
= (VkImageView
[]) {
1065 radv_image_view_to_handle(&iview
),
1067 .width
= iview
.extent
.width
,
1068 .height
= iview
.extent
.height
,
1071 &cmd_buffer
->pool
->alloc
,
1074 VkAttachmentDescription att_desc
= {
1075 .format
= iview
.vk_format
,
1076 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1077 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1078 .stencilLoadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1079 .stencilStoreOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1080 .initialLayout
= image_layout
,
1081 .finalLayout
= image_layout
,
1084 VkSubpassDescription subpass_desc
= {
1085 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
1086 .inputAttachmentCount
= 0,
1087 .colorAttachmentCount
= 0,
1088 .pColorAttachments
= NULL
,
1089 .pResolveAttachments
= NULL
,
1090 .pDepthStencilAttachment
= NULL
,
1091 .preserveAttachmentCount
= 0,
1092 .pPreserveAttachments
= NULL
,
1095 const VkAttachmentReference att_ref
= {
1097 .layout
= image_layout
,
1100 if (range
->aspectMask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
1101 subpass_desc
.colorAttachmentCount
= 1;
1102 subpass_desc
.pColorAttachments
= &att_ref
;
1104 subpass_desc
.pDepthStencilAttachment
= &att_ref
;
1108 radv_CreateRenderPass(device_h
,
1109 &(VkRenderPassCreateInfo
) {
1110 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
1111 .attachmentCount
= 1,
1112 .pAttachments
= &att_desc
,
1114 .pSubpasses
= &subpass_desc
,
1116 &cmd_buffer
->pool
->alloc
,
1119 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
1120 &(VkRenderPassBeginInfo
) {
1121 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
1123 .offset
= { 0, 0, },
1125 .width
= iview
.extent
.width
,
1126 .height
= iview
.extent
.height
,
1131 .clearValueCount
= 0,
1132 .pClearValues
= NULL
,
1134 VK_SUBPASS_CONTENTS_INLINE
);
1136 VkClearAttachment clear_att
= {
1137 .aspectMask
= range
->aspectMask
,
1138 .colorAttachment
= 0,
1139 .clearValue
= *clear_val
,
1142 VkClearRect clear_rect
= {
1145 .extent
= { iview
.extent
.width
, iview
.extent
.height
},
1147 .baseArrayLayer
= range
->baseArrayLayer
,
1148 .layerCount
= 1, /* FINISHME: clear multi-layer framebuffer */
1151 emit_clear(cmd_buffer
, &clear_att
, &clear_rect
, NULL
, NULL
);
1153 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
));
1154 radv_DestroyRenderPass(device_h
, pass
,
1155 &cmd_buffer
->pool
->alloc
);
1156 radv_DestroyFramebuffer(device_h
, fb
,
1157 &cmd_buffer
->pool
->alloc
);
1160 radv_cmd_clear_image(struct radv_cmd_buffer
*cmd_buffer
,
1161 struct radv_image
*image
,
1162 VkImageLayout image_layout
,
1163 const VkClearValue
*clear_value
,
1164 uint32_t range_count
,
1165 const VkImageSubresourceRange
*ranges
,
1168 VkFormat format
= image
->vk_format
;
1169 VkClearValue internal_clear_value
= *clear_value
;
1171 if (format
== VK_FORMAT_E5B9G9R9_UFLOAT_PACK32
) {
1173 format
= VK_FORMAT_R32_UINT
;
1174 value
= float3_to_rgb9e5(clear_value
->color
.float32
);
1175 internal_clear_value
.color
.uint32
[0] = value
;
1178 for (uint32_t r
= 0; r
< range_count
; r
++) {
1179 const VkImageSubresourceRange
*range
= &ranges
[r
];
1180 for (uint32_t l
= 0; l
< radv_get_levelCount(image
, range
); ++l
) {
1181 const uint32_t layer_count
= image
->type
== VK_IMAGE_TYPE_3D
?
1182 radv_minify(image
->extent
.depth
, range
->baseMipLevel
+ l
) :
1183 radv_get_layerCount(image
, range
);
1184 for (uint32_t s
= 0; s
< layer_count
; ++s
) {
1187 struct radv_meta_blit2d_surf surf
;
1188 surf
.format
= format
;
1190 surf
.level
= range
->baseMipLevel
+ l
;
1191 surf
.layer
= range
->baseArrayLayer
+ s
;
1192 surf
.aspect_mask
= range
->aspectMask
;
1193 radv_meta_clear_image_cs(cmd_buffer
, &surf
,
1194 &internal_clear_value
.color
);
1196 radv_clear_image_layer(cmd_buffer
, image
, image_layout
,
1197 range
, format
, l
, s
, &internal_clear_value
);
1204 union meta_saved_state
{
1205 struct radv_meta_saved_state gfx
;
1206 struct radv_meta_saved_compute_state compute
;
1209 void radv_CmdClearColorImage(
1210 VkCommandBuffer commandBuffer
,
1212 VkImageLayout imageLayout
,
1213 const VkClearColorValue
* pColor
,
1214 uint32_t rangeCount
,
1215 const VkImageSubresourceRange
* pRanges
)
1217 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1218 RADV_FROM_HANDLE(radv_image
, image
, image_h
);
1219 union meta_saved_state saved_state
;
1220 bool cs
= cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
;
1223 radv_meta_begin_cleari(cmd_buffer
, &saved_state
.compute
);
1225 radv_meta_save_graphics_reset_vport_scissor(&saved_state
.gfx
, cmd_buffer
);
1227 radv_cmd_clear_image(cmd_buffer
, image
, imageLayout
,
1228 (const VkClearValue
*) pColor
,
1229 rangeCount
, pRanges
, cs
);
1232 radv_meta_end_cleari(cmd_buffer
, &saved_state
.compute
);
1234 radv_meta_restore(&saved_state
.gfx
, cmd_buffer
);
1237 void radv_CmdClearDepthStencilImage(
1238 VkCommandBuffer commandBuffer
,
1240 VkImageLayout imageLayout
,
1241 const VkClearDepthStencilValue
* pDepthStencil
,
1242 uint32_t rangeCount
,
1243 const VkImageSubresourceRange
* pRanges
)
1245 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1246 RADV_FROM_HANDLE(radv_image
, image
, image_h
);
1247 struct radv_meta_saved_state saved_state
;
1249 radv_meta_save_graphics_reset_vport_scissor(&saved_state
, cmd_buffer
);
1251 radv_cmd_clear_image(cmd_buffer
, image
, imageLayout
,
1252 (const VkClearValue
*) pDepthStencil
,
1253 rangeCount
, pRanges
, false);
1255 radv_meta_restore(&saved_state
, cmd_buffer
);
1258 void radv_CmdClearAttachments(
1259 VkCommandBuffer commandBuffer
,
1260 uint32_t attachmentCount
,
1261 const VkClearAttachment
* pAttachments
,
1263 const VkClearRect
* pRects
)
1265 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1266 struct radv_meta_saved_state saved_state
;
1267 enum radv_cmd_flush_bits pre_flush
= 0;
1268 enum radv_cmd_flush_bits post_flush
= 0;
1270 if (!cmd_buffer
->state
.subpass
)
1273 radv_meta_save_graphics_reset_vport_scissor(&saved_state
, cmd_buffer
);
1275 /* FINISHME: We can do better than this dumb loop. It thrashes too much
1278 for (uint32_t a
= 0; a
< attachmentCount
; ++a
) {
1279 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
1280 emit_clear(cmd_buffer
, &pAttachments
[a
], &pRects
[r
], &pre_flush
, &post_flush
);
1284 radv_meta_restore(&saved_state
, cmd_buffer
);
1285 cmd_buffer
->state
.flush_bits
|= post_flush
;