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radv: add radv_clear_{cmask,dcc} helpers
[mesa.git] / src / amd / vulkan / radv_meta_clear.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_debug.h"
25 #include "radv_meta.h"
26 #include "radv_private.h"
27 #include "nir/nir_builder.h"
28
29 #include "util/format_rgb9e5.h"
30 #include "vk_format.h"
31
32 enum {
33 DEPTH_CLEAR_SLOW,
34 DEPTH_CLEAR_FAST_EXPCLEAR,
35 DEPTH_CLEAR_FAST_NO_EXPCLEAR
36 };
37
38 static void
39 build_color_shaders(struct nir_shader **out_vs,
40 struct nir_shader **out_fs,
41 uint32_t frag_output)
42 {
43 nir_builder vs_b;
44 nir_builder fs_b;
45
46 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
47 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
48
49 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
50 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
51
52 const struct glsl_type *position_type = glsl_vec4_type();
53 const struct glsl_type *color_type = glsl_vec4_type();
54
55 nir_variable *vs_out_pos =
56 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
57 "gl_Position");
58 vs_out_pos->data.location = VARYING_SLOT_POS;
59
60 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
61 nir_intrinsic_set_base(in_color_load, 0);
62 nir_intrinsic_set_range(in_color_load, 16);
63 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
64 in_color_load->num_components = 4;
65 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
66 nir_builder_instr_insert(&fs_b, &in_color_load->instr);
67
68 nir_variable *fs_out_color =
69 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
70 "f_color");
71 fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
72
73 nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
74
75 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
76 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
77
78 const struct glsl_type *layer_type = glsl_int_type();
79 nir_variable *vs_out_layer =
80 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
81 "v_layer");
82 vs_out_layer->data.location = VARYING_SLOT_LAYER;
83 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
84 nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
85 nir_ssa_def *base_instance = nir_load_system_value(&vs_b, nir_intrinsic_load_base_instance, 0);
86
87 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
88 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
89
90 *out_vs = vs_b.shader;
91 *out_fs = fs_b.shader;
92 }
93
94 static VkResult
95 create_pipeline(struct radv_device *device,
96 struct radv_render_pass *render_pass,
97 uint32_t samples,
98 struct nir_shader *vs_nir,
99 struct nir_shader *fs_nir,
100 const VkPipelineVertexInputStateCreateInfo *vi_state,
101 const VkPipelineDepthStencilStateCreateInfo *ds_state,
102 const VkPipelineColorBlendStateCreateInfo *cb_state,
103 const VkPipelineLayout layout,
104 const struct radv_graphics_pipeline_create_info *extra,
105 const VkAllocationCallbacks *alloc,
106 VkPipeline *pipeline)
107 {
108 VkDevice device_h = radv_device_to_handle(device);
109 VkResult result;
110
111 struct radv_shader_module vs_m = { .nir = vs_nir };
112 struct radv_shader_module fs_m = { .nir = fs_nir };
113
114 result = radv_graphics_pipeline_create(device_h,
115 radv_pipeline_cache_to_handle(&device->meta_state.cache),
116 &(VkGraphicsPipelineCreateInfo) {
117 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
118 .stageCount = fs_nir ? 2 : 1,
119 .pStages = (VkPipelineShaderStageCreateInfo[]) {
120 {
121 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
122 .stage = VK_SHADER_STAGE_VERTEX_BIT,
123 .module = radv_shader_module_to_handle(&vs_m),
124 .pName = "main",
125 },
126 {
127 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
128 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
129 .module = radv_shader_module_to_handle(&fs_m),
130 .pName = "main",
131 },
132 },
133 .pVertexInputState = vi_state,
134 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
135 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
136 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
137 .primitiveRestartEnable = false,
138 },
139 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
140 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
141 .viewportCount = 1,
142 .scissorCount = 1,
143 },
144 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
145 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
146 .rasterizerDiscardEnable = false,
147 .polygonMode = VK_POLYGON_MODE_FILL,
148 .cullMode = VK_CULL_MODE_NONE,
149 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
150 .depthBiasEnable = false,
151 },
152 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
153 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
154 .rasterizationSamples = samples,
155 .sampleShadingEnable = false,
156 .pSampleMask = NULL,
157 .alphaToCoverageEnable = false,
158 .alphaToOneEnable = false,
159 },
160 .pDepthStencilState = ds_state,
161 .pColorBlendState = cb_state,
162 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
163 /* The meta clear pipeline declares all state as dynamic.
164 * As a consequence, vkCmdBindPipeline writes no dynamic state
165 * to the cmd buffer. Therefore, at the end of the meta clear,
166 * we need only restore dynamic state was vkCmdSet.
167 */
168 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
169 .dynamicStateCount = 8,
170 .pDynamicStates = (VkDynamicState[]) {
171 /* Everything except stencil write mask */
172 VK_DYNAMIC_STATE_VIEWPORT,
173 VK_DYNAMIC_STATE_SCISSOR,
174 VK_DYNAMIC_STATE_LINE_WIDTH,
175 VK_DYNAMIC_STATE_DEPTH_BIAS,
176 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
177 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
178 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
179 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
180 },
181 },
182 .layout = layout,
183 .flags = 0,
184 .renderPass = radv_render_pass_to_handle(render_pass),
185 .subpass = 0,
186 },
187 extra,
188 alloc,
189 pipeline);
190
191 ralloc_free(vs_nir);
192 ralloc_free(fs_nir);
193
194 return result;
195 }
196
197 static VkResult
198 create_color_renderpass(struct radv_device *device,
199 VkFormat vk_format,
200 uint32_t samples,
201 VkRenderPass *pass)
202 {
203 return radv_CreateRenderPass(radv_device_to_handle(device),
204 &(VkRenderPassCreateInfo) {
205 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
206 .attachmentCount = 1,
207 .pAttachments = &(VkAttachmentDescription) {
208 .format = vk_format,
209 .samples = samples,
210 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
211 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
212 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
213 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
214 },
215 .subpassCount = 1,
216 .pSubpasses = &(VkSubpassDescription) {
217 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
218 .inputAttachmentCount = 0,
219 .colorAttachmentCount = 1,
220 .pColorAttachments = &(VkAttachmentReference) {
221 .attachment = 0,
222 .layout = VK_IMAGE_LAYOUT_GENERAL,
223 },
224 .pResolveAttachments = NULL,
225 .pDepthStencilAttachment = &(VkAttachmentReference) {
226 .attachment = VK_ATTACHMENT_UNUSED,
227 .layout = VK_IMAGE_LAYOUT_GENERAL,
228 },
229 .preserveAttachmentCount = 1,
230 .pPreserveAttachments = (uint32_t[]) { 0 },
231 },
232 .dependencyCount = 0,
233 }, &device->meta_state.alloc, pass);
234 }
235
236 static VkResult
237 create_color_pipeline(struct radv_device *device,
238 uint32_t samples,
239 uint32_t frag_output,
240 VkPipeline *pipeline,
241 VkRenderPass pass)
242 {
243 struct nir_shader *vs_nir;
244 struct nir_shader *fs_nir;
245 VkResult result;
246 build_color_shaders(&vs_nir, &fs_nir, frag_output);
247
248 const VkPipelineVertexInputStateCreateInfo vi_state = {
249 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
250 .vertexBindingDescriptionCount = 0,
251 .vertexAttributeDescriptionCount = 0,
252 };
253
254 const VkPipelineDepthStencilStateCreateInfo ds_state = {
255 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
256 .depthTestEnable = false,
257 .depthWriteEnable = false,
258 .depthBoundsTestEnable = false,
259 .stencilTestEnable = false,
260 };
261
262 VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
263 blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
264 .blendEnable = false,
265 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
266 VK_COLOR_COMPONENT_R_BIT |
267 VK_COLOR_COMPONENT_G_BIT |
268 VK_COLOR_COMPONENT_B_BIT,
269 };
270
271 const VkPipelineColorBlendStateCreateInfo cb_state = {
272 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
273 .logicOpEnable = false,
274 .attachmentCount = MAX_RTS,
275 .pAttachments = blend_attachment_state
276 };
277
278
279 struct radv_graphics_pipeline_create_info extra = {
280 .use_rectlist = true,
281 };
282 result = create_pipeline(device, radv_render_pass_from_handle(pass),
283 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
284 device->meta_state.clear_color_p_layout,
285 &extra, &device->meta_state.alloc, pipeline);
286
287 return result;
288 }
289
290 void
291 radv_device_finish_meta_clear_state(struct radv_device *device)
292 {
293 struct radv_meta_state *state = &device->meta_state;
294
295 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
296 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
297 radv_DestroyPipeline(radv_device_to_handle(device),
298 state->clear[i].color_pipelines[j],
299 &state->alloc);
300 radv_DestroyRenderPass(radv_device_to_handle(device),
301 state->clear[i].render_pass[j],
302 &state->alloc);
303 }
304
305 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
306 radv_DestroyPipeline(radv_device_to_handle(device),
307 state->clear[i].depth_only_pipeline[j],
308 &state->alloc);
309 radv_DestroyPipeline(radv_device_to_handle(device),
310 state->clear[i].stencil_only_pipeline[j],
311 &state->alloc);
312 radv_DestroyPipeline(radv_device_to_handle(device),
313 state->clear[i].depthstencil_pipeline[j],
314 &state->alloc);
315 }
316 radv_DestroyRenderPass(radv_device_to_handle(device),
317 state->clear[i].depthstencil_rp,
318 &state->alloc);
319 }
320 radv_DestroyPipelineLayout(radv_device_to_handle(device),
321 state->clear_color_p_layout,
322 &state->alloc);
323 radv_DestroyPipelineLayout(radv_device_to_handle(device),
324 state->clear_depth_p_layout,
325 &state->alloc);
326 }
327
328 static void
329 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
330 const VkClearAttachment *clear_att,
331 const VkClearRect *clear_rect,
332 uint32_t view_mask)
333 {
334 struct radv_device *device = cmd_buffer->device;
335 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
336 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
337 const uint32_t subpass_att = clear_att->colorAttachment;
338 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
339 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
340 const uint32_t samples = iview->image->info.samples;
341 const uint32_t samples_log2 = ffs(samples) - 1;
342 unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
343 VkClearColorValue clear_value = clear_att->clearValue.color;
344 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
345 VkPipeline pipeline;
346
347 if (fs_key == -1) {
348 radv_finishme("color clears incomplete");
349 return;
350 }
351
352 pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
353 if (!pipeline) {
354 radv_finishme("color clears incomplete");
355 return;
356 }
357 assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
358 assert(pipeline);
359 assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
360 assert(clear_att->colorAttachment < subpass->color_count);
361
362 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
363 device->meta_state.clear_color_p_layout,
364 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
365 &clear_value);
366
367 struct radv_subpass clear_subpass = {
368 .color_count = 1,
369 .color_attachments = (VkAttachmentReference[]) {
370 subpass->color_attachments[clear_att->colorAttachment]
371 },
372 .depth_stencil_attachment = (VkAttachmentReference) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
373 };
374
375 radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
376
377 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
378 pipeline);
379
380 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
381 .x = clear_rect->rect.offset.x,
382 .y = clear_rect->rect.offset.y,
383 .width = clear_rect->rect.extent.width,
384 .height = clear_rect->rect.extent.height,
385 .minDepth = 0.0f,
386 .maxDepth = 1.0f
387 });
388
389 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
390
391 if (view_mask) {
392 unsigned i;
393 for_each_bit(i, view_mask)
394 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
395 } else {
396 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
397 }
398
399 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
400 }
401
402
403 static void
404 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
405 {
406 nir_builder vs_b, fs_b;
407
408 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
409 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
410
411 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
412 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
413 const struct glsl_type *position_out_type = glsl_vec4_type();
414
415 nir_variable *vs_out_pos =
416 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
417 "gl_Position");
418 vs_out_pos->data.location = VARYING_SLOT_POS;
419
420 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
421 nir_intrinsic_set_base(in_color_load, 0);
422 nir_intrinsic_set_range(in_color_load, 4);
423 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
424 in_color_load->num_components = 1;
425 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
426 nir_builder_instr_insert(&vs_b, &in_color_load->instr);
427
428 nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
429 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
430
431 const struct glsl_type *layer_type = glsl_int_type();
432 nir_variable *vs_out_layer =
433 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
434 "v_layer");
435 vs_out_layer->data.location = VARYING_SLOT_LAYER;
436 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
437 nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
438 nir_ssa_def *base_instance = nir_load_system_value(&vs_b, nir_intrinsic_load_base_instance, 0);
439
440 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
441 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
442
443 *out_vs = vs_b.shader;
444 *out_fs = fs_b.shader;
445 }
446
447 static VkResult
448 create_depthstencil_renderpass(struct radv_device *device,
449 uint32_t samples,
450 VkRenderPass *render_pass)
451 {
452 return radv_CreateRenderPass(radv_device_to_handle(device),
453 &(VkRenderPassCreateInfo) {
454 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
455 .attachmentCount = 1,
456 .pAttachments = &(VkAttachmentDescription) {
457 .format = VK_FORMAT_D32_SFLOAT_S8_UINT,
458 .samples = samples,
459 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
460 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
461 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
462 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
463 },
464 .subpassCount = 1,
465 .pSubpasses = &(VkSubpassDescription) {
466 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
467 .inputAttachmentCount = 0,
468 .colorAttachmentCount = 0,
469 .pColorAttachments = NULL,
470 .pResolveAttachments = NULL,
471 .pDepthStencilAttachment = &(VkAttachmentReference) {
472 .attachment = 0,
473 .layout = VK_IMAGE_LAYOUT_GENERAL,
474 },
475 .preserveAttachmentCount = 1,
476 .pPreserveAttachments = (uint32_t[]) { 0 },
477 },
478 .dependencyCount = 0,
479 }, &device->meta_state.alloc, render_pass);
480 }
481
482 static VkResult
483 create_depthstencil_pipeline(struct radv_device *device,
484 VkImageAspectFlags aspects,
485 uint32_t samples,
486 int index,
487 VkPipeline *pipeline,
488 VkRenderPass render_pass)
489 {
490 struct nir_shader *vs_nir, *fs_nir;
491 VkResult result;
492 build_depthstencil_shader(&vs_nir, &fs_nir);
493
494 const VkPipelineVertexInputStateCreateInfo vi_state = {
495 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
496 .vertexBindingDescriptionCount = 0,
497 .vertexAttributeDescriptionCount = 0,
498 };
499
500 const VkPipelineDepthStencilStateCreateInfo ds_state = {
501 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
502 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
503 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
504 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
505 .depthBoundsTestEnable = false,
506 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
507 .front = {
508 .passOp = VK_STENCIL_OP_REPLACE,
509 .compareOp = VK_COMPARE_OP_ALWAYS,
510 .writeMask = UINT32_MAX,
511 .reference = 0, /* dynamic */
512 },
513 .back = { 0 /* dont care */ },
514 };
515
516 const VkPipelineColorBlendStateCreateInfo cb_state = {
517 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
518 .logicOpEnable = false,
519 .attachmentCount = 0,
520 .pAttachments = NULL,
521 };
522
523 struct radv_graphics_pipeline_create_info extra = {
524 .use_rectlist = true,
525 };
526
527 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
528 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
529 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
530 }
531 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
532 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
533 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
534 }
535 result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
536 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
537 device->meta_state.clear_depth_p_layout,
538 &extra, &device->meta_state.alloc, pipeline);
539 return result;
540 }
541
542 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
543 const struct radv_image_view *iview,
544 VkImageAspectFlags aspects,
545 VkImageLayout layout,
546 const VkClearRect *clear_rect,
547 VkClearDepthStencilValue clear_value)
548 {
549 uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
550 cmd_buffer->queue_family_index,
551 cmd_buffer->queue_family_index);
552 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
553 clear_rect->rect.extent.width != iview->extent.width ||
554 clear_rect->rect.extent.height != iview->extent.height)
555 return false;
556 if (iview->image->tc_compatible_htile &&
557 (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && clear_value.depth != 0.0 &&
558 clear_value.depth != 1.0) ||
559 ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0)))
560 return false;
561 if (iview->image->surface.htile_size &&
562 iview->base_mip == 0 &&
563 iview->base_layer == 0 &&
564 radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
565 !radv_image_extent_compare(iview->image, &iview->extent))
566 return true;
567 return false;
568 }
569
570 static VkPipeline
571 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
572 struct radv_meta_state *meta_state,
573 const struct radv_image_view *iview,
574 int samples_log2,
575 VkImageAspectFlags aspects,
576 VkImageLayout layout,
577 const VkClearRect *clear_rect,
578 VkClearDepthStencilValue clear_value)
579 {
580 bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, clear_rect, clear_value);
581 int index = DEPTH_CLEAR_SLOW;
582
583 if (fast) {
584 /* we don't know the previous clear values, so we always have
585 * the NO_EXPCLEAR path */
586 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
587 }
588
589 switch (aspects) {
590 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
591 return meta_state->clear[samples_log2].depthstencil_pipeline[index];
592 case VK_IMAGE_ASPECT_DEPTH_BIT:
593 return meta_state->clear[samples_log2].depth_only_pipeline[index];
594 case VK_IMAGE_ASPECT_STENCIL_BIT:
595 return meta_state->clear[samples_log2].stencil_only_pipeline[index];
596 }
597 unreachable("expected depth or stencil aspect");
598 }
599
600 static void
601 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
602 const VkClearAttachment *clear_att,
603 const VkClearRect *clear_rect)
604 {
605 struct radv_device *device = cmd_buffer->device;
606 struct radv_meta_state *meta_state = &device->meta_state;
607 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
608 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
609 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
610 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
611 VkImageAspectFlags aspects = clear_att->aspectMask;
612 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
613 const uint32_t samples = iview->image->info.samples;
614 const uint32_t samples_log2 = ffs(samples) - 1;
615 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
616
617 assert(pass_att != VK_ATTACHMENT_UNUSED);
618
619 if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
620 clear_value.depth = 1.0f;
621
622 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
623 device->meta_state.clear_depth_p_layout,
624 VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
625 &clear_value.depth);
626
627 uint32_t prev_reference = cmd_buffer->state.dynamic.stencil_reference.front;
628 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
629 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
630 clear_value.stencil);
631 }
632
633 VkPipeline pipeline = pick_depthstencil_pipeline(cmd_buffer,
634 meta_state,
635 iview,
636 samples_log2,
637 aspects,
638 subpass->depth_stencil_attachment.layout,
639 clear_rect,
640 clear_value);
641
642 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
643 pipeline);
644
645 if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
646 subpass->depth_stencil_attachment.layout,
647 clear_rect, clear_value))
648 radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
649
650 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
651 .x = clear_rect->rect.offset.x,
652 .y = clear_rect->rect.offset.y,
653 .width = clear_rect->rect.extent.width,
654 .height = clear_rect->rect.extent.height,
655 .minDepth = 0.0f,
656 .maxDepth = 1.0f
657 });
658
659 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
660
661 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
662
663 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
664 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
665 prev_reference);
666 }
667 }
668
669 static bool
670 emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
671 const VkClearAttachment *clear_att,
672 const VkClearRect *clear_rect,
673 enum radv_cmd_flush_bits *pre_flush,
674 enum radv_cmd_flush_bits *post_flush)
675 {
676 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
677 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
678 VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
679 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
680 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
681 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
682 VkImageAspectFlags aspects = clear_att->aspectMask;
683 uint32_t clear_word, flush_bits;
684
685 if (!iview->image->surface.htile_size)
686 return false;
687
688 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
689 return false;
690
691 if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
692 goto fail;
693
694 /* don't fast clear 3D */
695 if (iview->image->type == VK_IMAGE_TYPE_3D)
696 goto fail;
697
698 /* all layers are bound */
699 if (iview->base_layer > 0)
700 goto fail;
701 if (iview->image->info.array_size != iview->layer_count)
702 goto fail;
703
704 if (!radv_image_extent_compare(iview->image, &iview->extent))
705 goto fail;
706
707 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
708 clear_rect->rect.extent.width != iview->image->info.width ||
709 clear_rect->rect.extent.height != iview->image->info.height)
710 goto fail;
711
712 if (clear_rect->baseArrayLayer != 0)
713 goto fail;
714 if (clear_rect->layerCount != iview->image->info.array_size)
715 goto fail;
716
717 if ((clear_value.depth != 0.0 && clear_value.depth != 1.0) || !(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
718 goto fail;
719
720 if (vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) {
721 if (clear_value.stencil != 0 || !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))
722 goto fail;
723 clear_word = clear_value.depth ? 0xfffc0000 : 0;
724 } else
725 clear_word = clear_value.depth ? 0xfffffff0 : 0;
726
727 if (pre_flush) {
728 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
729 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
730 *pre_flush |= cmd_buffer->state.flush_bits;
731 } else
732 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
733 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
734
735 flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
736 iview->image->offset + iview->image->htile_offset,
737 iview->image->surface.htile_size, clear_word);
738
739 radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
740 if (post_flush) {
741 *post_flush |= flush_bits;
742 } else {
743 cmd_buffer->state.flush_bits |= flush_bits;
744 }
745
746 return true;
747 fail:
748 return false;
749 }
750
751 static VkFormat pipeline_formats[] = {
752 VK_FORMAT_R8G8B8A8_UNORM,
753 VK_FORMAT_R8G8B8A8_UINT,
754 VK_FORMAT_R8G8B8A8_SINT,
755 VK_FORMAT_A2R10G10B10_UINT_PACK32,
756 VK_FORMAT_A2R10G10B10_SINT_PACK32,
757 VK_FORMAT_R16G16B16A16_UNORM,
758 VK_FORMAT_R16G16B16A16_SNORM,
759 VK_FORMAT_R16G16B16A16_UINT,
760 VK_FORMAT_R16G16B16A16_SINT,
761 VK_FORMAT_R32_SFLOAT,
762 VK_FORMAT_R32G32_SFLOAT,
763 VK_FORMAT_R32G32B32A32_SFLOAT
764 };
765
766 VkResult
767 radv_device_init_meta_clear_state(struct radv_device *device)
768 {
769 VkResult res;
770 struct radv_meta_state *state = &device->meta_state;
771
772 VkPipelineLayoutCreateInfo pl_color_create_info = {
773 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
774 .setLayoutCount = 0,
775 .pushConstantRangeCount = 1,
776 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
777 };
778
779 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
780 &pl_color_create_info,
781 &device->meta_state.alloc,
782 &device->meta_state.clear_color_p_layout);
783 if (res != VK_SUCCESS)
784 goto fail;
785
786 VkPipelineLayoutCreateInfo pl_depth_create_info = {
787 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
788 .setLayoutCount = 0,
789 .pushConstantRangeCount = 1,
790 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
791 };
792
793 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
794 &pl_depth_create_info,
795 &device->meta_state.alloc,
796 &device->meta_state.clear_depth_p_layout);
797 if (res != VK_SUCCESS)
798 goto fail;
799
800 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
801 uint32_t samples = 1 << i;
802 for (uint32_t j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
803 VkFormat format = pipeline_formats[j];
804 unsigned fs_key = radv_format_meta_fs_key(format);
805 assert(!state->clear[i].color_pipelines[fs_key]);
806
807 res = create_color_renderpass(device, format, samples,
808 &state->clear[i].render_pass[fs_key]);
809 if (res != VK_SUCCESS)
810 goto fail;
811
812 res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
813 state->clear[i].render_pass[fs_key]);
814 if (res != VK_SUCCESS)
815 goto fail;
816
817 }
818
819 res = create_depthstencil_renderpass(device,
820 samples,
821 &state->clear[i].depthstencil_rp);
822 if (res != VK_SUCCESS)
823 goto fail;
824
825 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
826 res = create_depthstencil_pipeline(device,
827 VK_IMAGE_ASPECT_DEPTH_BIT,
828 samples,
829 j,
830 &state->clear[i].depth_only_pipeline[j],
831 state->clear[i].depthstencil_rp);
832 if (res != VK_SUCCESS)
833 goto fail;
834
835 res = create_depthstencil_pipeline(device,
836 VK_IMAGE_ASPECT_STENCIL_BIT,
837 samples,
838 j,
839 &state->clear[i].stencil_only_pipeline[j],
840 state->clear[i].depthstencil_rp);
841 if (res != VK_SUCCESS)
842 goto fail;
843
844 res = create_depthstencil_pipeline(device,
845 VK_IMAGE_ASPECT_DEPTH_BIT |
846 VK_IMAGE_ASPECT_STENCIL_BIT,
847 samples,
848 j,
849 &state->clear[i].depthstencil_pipeline[j],
850 state->clear[i].depthstencil_rp);
851 if (res != VK_SUCCESS)
852 goto fail;
853 }
854 }
855 return VK_SUCCESS;
856
857 fail:
858 radv_device_finish_meta_clear_state(device);
859 return res;
860 }
861
862 uint32_t
863 radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
864 struct radv_image *image, uint32_t value)
865 {
866 return radv_fill_buffer(cmd_buffer, image->bo,
867 image->offset + image->cmask.offset,
868 image->cmask.size, value);
869 }
870
871 uint32_t
872 radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
873 struct radv_image *image, uint32_t value)
874 {
875 return radv_fill_buffer(cmd_buffer, image->bo,
876 image->offset + image->dcc_offset,
877 image->surface.dcc_size, value);
878 }
879
880 static void vi_get_fast_clear_parameters(VkFormat format,
881 const VkClearColorValue *clear_value,
882 uint32_t* reset_value,
883 bool *can_avoid_fast_clear_elim)
884 {
885 bool values[4] = {};
886 int extra_channel;
887 bool main_value = false;
888 bool extra_value = false;
889 int i;
890 *can_avoid_fast_clear_elim = false;
891
892 *reset_value = 0x20202020U;
893
894 const struct vk_format_description *desc = vk_format_description(format);
895 if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
896 format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
897 format == VK_FORMAT_B5G6R5_UNORM_PACK16)
898 extra_channel = -1;
899 else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
900 if (radv_translate_colorswap(format, false) <= 1)
901 extra_channel = desc->nr_channels - 1;
902 else
903 extra_channel = 0;
904 } else
905 return;
906
907 for (i = 0; i < 4; i++) {
908 int index = desc->swizzle[i] - VK_SWIZZLE_X;
909 if (desc->swizzle[i] < VK_SWIZZLE_X ||
910 desc->swizzle[i] > VK_SWIZZLE_W)
911 continue;
912
913 if (desc->channel[i].pure_integer &&
914 desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
915 /* Use the maximum value for clamping the clear color. */
916 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
917
918 values[i] = clear_value->int32[i] != 0;
919 if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
920 return;
921 } else if (desc->channel[i].pure_integer &&
922 desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
923 /* Use the maximum value for clamping the clear color. */
924 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
925
926 values[i] = clear_value->uint32[i] != 0U;
927 if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
928 return;
929 } else {
930 values[i] = clear_value->float32[i] != 0.0F;
931 if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
932 return;
933 }
934
935 if (index == extra_channel)
936 extra_value = values[i];
937 else
938 main_value = values[i];
939 }
940
941 for (int i = 0; i < 4; ++i)
942 if (values[i] != main_value &&
943 desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
944 desc->swizzle[i] >= VK_SWIZZLE_X &&
945 desc->swizzle[i] <= VK_SWIZZLE_W)
946 return;
947
948 *can_avoid_fast_clear_elim = true;
949 if (main_value)
950 *reset_value |= 0x80808080U;
951
952 if (extra_value)
953 *reset_value |= 0x40404040U;
954 return;
955 }
956
957 static bool
958 emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
959 const VkClearAttachment *clear_att,
960 const VkClearRect *clear_rect,
961 enum radv_cmd_flush_bits *pre_flush,
962 enum radv_cmd_flush_bits *post_flush,
963 uint32_t view_mask)
964 {
965 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
966 const uint32_t subpass_att = clear_att->colorAttachment;
967 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
968 VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
969 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
970 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
971 VkClearColorValue clear_value = clear_att->clearValue.color;
972 uint32_t clear_color[2], flush_bits;
973 bool ret;
974
975 if (!iview->image->cmask.size && !iview->image->surface.dcc_size)
976 return false;
977
978 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
979 return false;
980
981 if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
982 goto fail;
983
984 /* don't fast clear 3D */
985 if (iview->image->type == VK_IMAGE_TYPE_3D)
986 goto fail;
987
988 /* all layers are bound */
989 if (iview->base_layer > 0)
990 goto fail;
991 if (iview->image->info.array_size != iview->layer_count)
992 goto fail;
993
994 if (iview->image->info.levels > 1)
995 goto fail;
996
997 if (iview->image->surface.is_linear)
998 goto fail;
999 if (!radv_image_extent_compare(iview->image, &iview->extent))
1000 goto fail;
1001
1002 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
1003 clear_rect->rect.extent.width != iview->image->info.width ||
1004 clear_rect->rect.extent.height != iview->image->info.height)
1005 goto fail;
1006
1007 if (view_mask && (iview->image->info.array_size >= 32 ||
1008 (1u << iview->image->info.array_size) - 1u != view_mask))
1009 goto fail;
1010 if (!view_mask && clear_rect->baseArrayLayer != 0)
1011 goto fail;
1012 if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
1013 goto fail;
1014
1015 /* RB+ doesn't work with CMASK fast clear on Stoney. */
1016 if (!iview->image->surface.dcc_size &&
1017 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY)
1018 goto fail;
1019
1020 /* DCC */
1021 ret = radv_format_pack_clear_color(iview->image->vk_format,
1022 clear_color, &clear_value);
1023 if (ret == false)
1024 goto fail;
1025
1026 if (pre_flush) {
1027 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1028 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
1029 *pre_flush |= cmd_buffer->state.flush_bits;
1030 } else
1031 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1032 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1033 /* clear cmask buffer */
1034 if (iview->image->surface.dcc_size) {
1035 uint32_t reset_value;
1036 bool can_avoid_fast_clear_elim;
1037 vi_get_fast_clear_parameters(iview->image->vk_format,
1038 &clear_value, &reset_value,
1039 &can_avoid_fast_clear_elim);
1040
1041 flush_bits = radv_clear_dcc(cmd_buffer, iview->image, reset_value);
1042
1043 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
1044 !can_avoid_fast_clear_elim);
1045 } else {
1046 flush_bits = radv_clear_cmask(cmd_buffer, iview->image, 0);
1047 }
1048
1049 if (post_flush) {
1050 *post_flush |= flush_bits;
1051 } else {
1052 cmd_buffer->state.flush_bits |= flush_bits;
1053 }
1054
1055 radv_set_color_clear_regs(cmd_buffer, iview->image, subpass_att, clear_color);
1056
1057 return true;
1058 fail:
1059 return false;
1060 }
1061
1062 /**
1063 * The parameters mean that same as those in vkCmdClearAttachments.
1064 */
1065 static void
1066 emit_clear(struct radv_cmd_buffer *cmd_buffer,
1067 const VkClearAttachment *clear_att,
1068 const VkClearRect *clear_rect,
1069 enum radv_cmd_flush_bits *pre_flush,
1070 enum radv_cmd_flush_bits *post_flush,
1071 uint32_t view_mask)
1072 {
1073 if (clear_att->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1074 if (!emit_fast_color_clear(cmd_buffer, clear_att, clear_rect,
1075 pre_flush, post_flush, view_mask))
1076 emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask);
1077 } else {
1078 assert(clear_att->aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT |
1079 VK_IMAGE_ASPECT_STENCIL_BIT));
1080 if (!emit_fast_htile_clear(cmd_buffer, clear_att, clear_rect,
1081 pre_flush, post_flush))
1082 emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
1083 }
1084 }
1085
1086 static inline bool
1087 radv_attachment_needs_clear(struct radv_cmd_state *cmd_state, uint32_t a)
1088 {
1089 uint32_t view_mask = cmd_state->subpass->view_mask;
1090 return (a != VK_ATTACHMENT_UNUSED &&
1091 cmd_state->attachments[a].pending_clear_aspects &&
1092 (!view_mask || (view_mask & ~cmd_state->attachments[a].cleared_views)));
1093 }
1094
1095 static bool
1096 radv_subpass_needs_clear(struct radv_cmd_buffer *cmd_buffer)
1097 {
1098 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1099 uint32_t a;
1100
1101 if (!cmd_state->subpass)
1102 return false;
1103
1104 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1105 a = cmd_state->subpass->color_attachments[i].attachment;
1106 if (radv_attachment_needs_clear(cmd_state, a))
1107 return true;
1108 }
1109
1110 a = cmd_state->subpass->depth_stencil_attachment.attachment;
1111 return radv_attachment_needs_clear(cmd_state, a);
1112 }
1113
1114 static void
1115 radv_subpass_clear_attachment(struct radv_cmd_buffer *cmd_buffer,
1116 struct radv_attachment_state *attachment,
1117 const VkClearAttachment *clear_att,
1118 enum radv_cmd_flush_bits *pre_flush,
1119 enum radv_cmd_flush_bits *post_flush)
1120 {
1121 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1122 uint32_t view_mask = cmd_state->subpass->view_mask;
1123
1124 VkClearRect clear_rect = {
1125 .rect = cmd_state->render_area,
1126 .baseArrayLayer = 0,
1127 .layerCount = cmd_state->framebuffer->layers,
1128 };
1129
1130 emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush,
1131 view_mask & ~attachment->cleared_views);
1132 if (view_mask)
1133 attachment->cleared_views |= view_mask;
1134 else
1135 attachment->pending_clear_aspects = 0;
1136 }
1137
1138 /**
1139 * Emit any pending attachment clears for the current subpass.
1140 *
1141 * @see radv_attachment_state::pending_clear_aspects
1142 */
1143 void
1144 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1145 {
1146 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1147 struct radv_meta_saved_state saved_state;
1148 enum radv_cmd_flush_bits pre_flush = 0;
1149 enum radv_cmd_flush_bits post_flush = 0;
1150
1151 if (!radv_subpass_needs_clear(cmd_buffer))
1152 return;
1153
1154 radv_meta_save(&saved_state, cmd_buffer,
1155 RADV_META_SAVE_GRAPHICS_PIPELINE |
1156 RADV_META_SAVE_CONSTANTS);
1157
1158 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1159 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1160
1161 if (!radv_attachment_needs_clear(cmd_state, a))
1162 continue;
1163
1164 assert(cmd_state->attachments[a].pending_clear_aspects ==
1165 VK_IMAGE_ASPECT_COLOR_BIT);
1166
1167 VkClearAttachment clear_att = {
1168 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1169 .colorAttachment = i, /* Use attachment index relative to subpass */
1170 .clearValue = cmd_state->attachments[a].clear_value,
1171 };
1172
1173 radv_subpass_clear_attachment(cmd_buffer,
1174 &cmd_state->attachments[a],
1175 &clear_att, &pre_flush,
1176 &post_flush);
1177 }
1178
1179 uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1180 if (radv_attachment_needs_clear(cmd_state, ds)) {
1181 VkClearAttachment clear_att = {
1182 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1183 .clearValue = cmd_state->attachments[ds].clear_value,
1184 };
1185
1186 radv_subpass_clear_attachment(cmd_buffer,
1187 &cmd_state->attachments[ds],
1188 &clear_att, &pre_flush,
1189 &post_flush);
1190 }
1191
1192 radv_meta_restore(&saved_state, cmd_buffer);
1193 cmd_buffer->state.flush_bits |= post_flush;
1194 }
1195
1196 static void
1197 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1198 struct radv_image *image,
1199 VkImageLayout image_layout,
1200 const VkImageSubresourceRange *range,
1201 VkFormat format, int level, int layer,
1202 const VkClearValue *clear_val)
1203 {
1204 VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1205 struct radv_image_view iview;
1206 uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level);
1207 uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level);
1208
1209 radv_image_view_init(&iview, cmd_buffer->device,
1210 &(VkImageViewCreateInfo) {
1211 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1212 .image = radv_image_to_handle(image),
1213 .viewType = radv_meta_get_view_type(image),
1214 .format = format,
1215 .subresourceRange = {
1216 .aspectMask = range->aspectMask,
1217 .baseMipLevel = range->baseMipLevel + level,
1218 .levelCount = 1,
1219 .baseArrayLayer = range->baseArrayLayer + layer,
1220 .layerCount = 1
1221 },
1222 });
1223
1224 VkFramebuffer fb;
1225 radv_CreateFramebuffer(device_h,
1226 &(VkFramebufferCreateInfo) {
1227 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1228 .attachmentCount = 1,
1229 .pAttachments = (VkImageView[]) {
1230 radv_image_view_to_handle(&iview),
1231 },
1232 .width = width,
1233 .height = height,
1234 .layers = 1
1235 },
1236 &cmd_buffer->pool->alloc,
1237 &fb);
1238
1239 VkAttachmentDescription att_desc = {
1240 .format = iview.vk_format,
1241 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1242 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1243 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1244 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1245 .initialLayout = image_layout,
1246 .finalLayout = image_layout,
1247 };
1248
1249 VkSubpassDescription subpass_desc = {
1250 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1251 .inputAttachmentCount = 0,
1252 .colorAttachmentCount = 0,
1253 .pColorAttachments = NULL,
1254 .pResolveAttachments = NULL,
1255 .pDepthStencilAttachment = NULL,
1256 .preserveAttachmentCount = 0,
1257 .pPreserveAttachments = NULL,
1258 };
1259
1260 const VkAttachmentReference att_ref = {
1261 .attachment = 0,
1262 .layout = image_layout,
1263 };
1264
1265 if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1266 subpass_desc.colorAttachmentCount = 1;
1267 subpass_desc.pColorAttachments = &att_ref;
1268 } else {
1269 subpass_desc.pDepthStencilAttachment = &att_ref;
1270 }
1271
1272 VkRenderPass pass;
1273 radv_CreateRenderPass(device_h,
1274 &(VkRenderPassCreateInfo) {
1275 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1276 .attachmentCount = 1,
1277 .pAttachments = &att_desc,
1278 .subpassCount = 1,
1279 .pSubpasses = &subpass_desc,
1280 },
1281 &cmd_buffer->pool->alloc,
1282 &pass);
1283
1284 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1285 &(VkRenderPassBeginInfo) {
1286 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1287 .renderArea = {
1288 .offset = { 0, 0, },
1289 .extent = {
1290 .width = width,
1291 .height = height,
1292 },
1293 },
1294 .renderPass = pass,
1295 .framebuffer = fb,
1296 .clearValueCount = 0,
1297 .pClearValues = NULL,
1298 },
1299 VK_SUBPASS_CONTENTS_INLINE);
1300
1301 VkClearAttachment clear_att = {
1302 .aspectMask = range->aspectMask,
1303 .colorAttachment = 0,
1304 .clearValue = *clear_val,
1305 };
1306
1307 VkClearRect clear_rect = {
1308 .rect = {
1309 .offset = { 0, 0 },
1310 .extent = { width, height },
1311 },
1312 .baseArrayLayer = range->baseArrayLayer,
1313 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1314 };
1315
1316 emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0);
1317
1318 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1319 radv_DestroyRenderPass(device_h, pass,
1320 &cmd_buffer->pool->alloc);
1321 radv_DestroyFramebuffer(device_h, fb,
1322 &cmd_buffer->pool->alloc);
1323 }
1324 static void
1325 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
1326 struct radv_image *image,
1327 VkImageLayout image_layout,
1328 const VkClearValue *clear_value,
1329 uint32_t range_count,
1330 const VkImageSubresourceRange *ranges,
1331 bool cs)
1332 {
1333 VkFormat format = image->vk_format;
1334 VkClearValue internal_clear_value = *clear_value;
1335
1336 if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
1337 uint32_t value;
1338 format = VK_FORMAT_R32_UINT;
1339 value = float3_to_rgb9e5(clear_value->color.float32);
1340 internal_clear_value.color.uint32[0] = value;
1341 }
1342
1343 if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
1344 uint8_t r, g;
1345 format = VK_FORMAT_R8_UINT;
1346 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
1347 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
1348 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
1349 }
1350
1351 for (uint32_t r = 0; r < range_count; r++) {
1352 const VkImageSubresourceRange *range = &ranges[r];
1353 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
1354 const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
1355 radv_minify(image->info.depth, range->baseMipLevel + l) :
1356 radv_get_layerCount(image, range);
1357 for (uint32_t s = 0; s < layer_count; ++s) {
1358
1359 if (cs) {
1360 struct radv_meta_blit2d_surf surf;
1361 surf.format = format;
1362 surf.image = image;
1363 surf.level = range->baseMipLevel + l;
1364 surf.layer = range->baseArrayLayer + s;
1365 surf.aspect_mask = range->aspectMask;
1366 radv_meta_clear_image_cs(cmd_buffer, &surf,
1367 &internal_clear_value.color);
1368 } else {
1369 radv_clear_image_layer(cmd_buffer, image, image_layout,
1370 range, format, l, s, &internal_clear_value);
1371 }
1372 }
1373 }
1374 }
1375 }
1376
1377 void radv_CmdClearColorImage(
1378 VkCommandBuffer commandBuffer,
1379 VkImage image_h,
1380 VkImageLayout imageLayout,
1381 const VkClearColorValue* pColor,
1382 uint32_t rangeCount,
1383 const VkImageSubresourceRange* pRanges)
1384 {
1385 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1386 RADV_FROM_HANDLE(radv_image, image, image_h);
1387 struct radv_meta_saved_state saved_state;
1388 bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1389
1390 if (cs) {
1391 radv_meta_save(&saved_state, cmd_buffer,
1392 RADV_META_SAVE_COMPUTE_PIPELINE |
1393 RADV_META_SAVE_CONSTANTS |
1394 RADV_META_SAVE_DESCRIPTORS);
1395 } else {
1396 radv_meta_save(&saved_state, cmd_buffer,
1397 RADV_META_SAVE_GRAPHICS_PIPELINE |
1398 RADV_META_SAVE_CONSTANTS);
1399 }
1400
1401 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1402 (const VkClearValue *) pColor,
1403 rangeCount, pRanges, cs);
1404
1405 radv_meta_restore(&saved_state, cmd_buffer);
1406 }
1407
1408 void radv_CmdClearDepthStencilImage(
1409 VkCommandBuffer commandBuffer,
1410 VkImage image_h,
1411 VkImageLayout imageLayout,
1412 const VkClearDepthStencilValue* pDepthStencil,
1413 uint32_t rangeCount,
1414 const VkImageSubresourceRange* pRanges)
1415 {
1416 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1417 RADV_FROM_HANDLE(radv_image, image, image_h);
1418 struct radv_meta_saved_state saved_state;
1419
1420 radv_meta_save(&saved_state, cmd_buffer,
1421 RADV_META_SAVE_GRAPHICS_PIPELINE |
1422 RADV_META_SAVE_CONSTANTS);
1423
1424 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1425 (const VkClearValue *) pDepthStencil,
1426 rangeCount, pRanges, false);
1427
1428 radv_meta_restore(&saved_state, cmd_buffer);
1429 }
1430
1431 void radv_CmdClearAttachments(
1432 VkCommandBuffer commandBuffer,
1433 uint32_t attachmentCount,
1434 const VkClearAttachment* pAttachments,
1435 uint32_t rectCount,
1436 const VkClearRect* pRects)
1437 {
1438 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1439 struct radv_meta_saved_state saved_state;
1440 enum radv_cmd_flush_bits pre_flush = 0;
1441 enum radv_cmd_flush_bits post_flush = 0;
1442
1443 if (!cmd_buffer->state.subpass)
1444 return;
1445
1446 radv_meta_save(&saved_state, cmd_buffer,
1447 RADV_META_SAVE_GRAPHICS_PIPELINE |
1448 RADV_META_SAVE_CONSTANTS);
1449
1450 /* FINISHME: We can do better than this dumb loop. It thrashes too much
1451 * state.
1452 */
1453 for (uint32_t a = 0; a < attachmentCount; ++a) {
1454 for (uint32_t r = 0; r < rectCount; ++r) {
1455 emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush,
1456 cmd_buffer->state.subpass->view_mask);
1457 }
1458 }
1459
1460 radv_meta_restore(&saved_state, cmd_buffer);
1461 cmd_buffer->state.flush_bits |= post_flush;
1462 }