2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "radv_meta.h"
28 #include "radv_private.h"
37 create_pass(struct radv_device
*device
,
42 VkDevice device_h
= radv_device_to_handle(device
);
43 const VkAllocationCallbacks
*alloc
= &device
->meta_state
.alloc
;
44 VkAttachmentDescription attachment
;
47 attachment
.format
= VK_FORMAT_D32_SFLOAT_S8_UINT
;
48 attachment
.samples
= samples
;
49 attachment
.loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
;
50 attachment
.storeOp
= VK_ATTACHMENT_STORE_OP_STORE
;
51 attachment
.stencilLoadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
;
52 attachment
.stencilStoreOp
= VK_ATTACHMENT_STORE_OP_STORE
;
53 attachment
.initialLayout
= VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
;
54 attachment
.finalLayout
= VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
;
56 result
= radv_CreateRenderPass(device_h
,
57 &(VkRenderPassCreateInfo
) {
58 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
60 .pAttachments
= &attachment
,
62 .pSubpasses
= &(VkSubpassDescription
) {
63 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
64 .inputAttachmentCount
= 0,
65 .colorAttachmentCount
= 0,
66 .pColorAttachments
= NULL
,
67 .pResolveAttachments
= NULL
,
68 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
70 .layout
= VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
,
72 .preserveAttachmentCount
= 0,
73 .pPreserveAttachments
= NULL
,
84 create_pipeline_layout(struct radv_device
*device
, VkPipelineLayout
*layout
)
86 VkPipelineLayoutCreateInfo pl_create_info
= {
87 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
90 .pushConstantRangeCount
= 0,
91 .pPushConstantRanges
= NULL
,
94 return radv_CreatePipelineLayout(radv_device_to_handle(device
),
96 &device
->meta_state
.alloc
,
101 create_pipeline(struct radv_device
*device
,
102 VkShaderModule vs_module_h
,
105 VkPipelineLayout layout
,
106 enum radv_depth_op op
,
107 VkPipeline
*pipeline
)
110 VkDevice device_h
= radv_device_to_handle(device
);
111 struct radv_shader_module vs_module
= {0};
113 mtx_lock(&device
->meta_state
.mtx
);
115 mtx_unlock(&device
->meta_state
.mtx
);
120 vs_module
.nir
= radv_meta_build_nir_vs_generate_vertices();
121 vs_module_h
= radv_shader_module_to_handle(&vs_module
);
124 struct radv_shader_module fs_module
= {
125 .nir
= radv_meta_build_nir_fs_noop(),
128 if (!fs_module
.nir
) {
129 /* XXX: Need more accurate error */
130 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
134 const VkPipelineSampleLocationsStateCreateInfoEXT sample_locs_create_info
= {
135 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
,
136 .sampleLocationsEnable
= false,
139 const VkGraphicsPipelineCreateInfo pipeline_create_info
= {
140 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
142 .pStages
= (VkPipelineShaderStageCreateInfo
[]) {
144 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
145 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
146 .module
= vs_module_h
,
150 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
151 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
152 .module
= radv_shader_module_to_handle(&fs_module
),
156 .pVertexInputState
= &(VkPipelineVertexInputStateCreateInfo
) {
157 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
158 .vertexBindingDescriptionCount
= 0,
159 .vertexAttributeDescriptionCount
= 0,
161 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
162 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
163 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
164 .primitiveRestartEnable
= false,
166 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
167 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
171 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
172 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
173 .depthClampEnable
= false,
174 .rasterizerDiscardEnable
= false,
175 .polygonMode
= VK_POLYGON_MODE_FILL
,
176 .cullMode
= VK_CULL_MODE_NONE
,
177 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
,
179 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
180 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
181 .pNext
= &sample_locs_create_info
,
182 .rasterizationSamples
= samples
,
183 .sampleShadingEnable
= false,
185 .alphaToCoverageEnable
= false,
186 .alphaToOneEnable
= false,
188 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
189 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
190 .logicOpEnable
= false,
191 .attachmentCount
= 0,
192 .pAttachments
= NULL
,
194 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
195 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
196 .depthTestEnable
= false,
197 .depthWriteEnable
= false,
198 .depthBoundsTestEnable
= false,
199 .stencilTestEnable
= false,
201 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
202 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
203 .dynamicStateCount
= 3,
204 .pDynamicStates
= (VkDynamicState
[]) {
205 VK_DYNAMIC_STATE_VIEWPORT
,
206 VK_DYNAMIC_STATE_SCISSOR
,
207 VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
,
215 struct radv_graphics_pipeline_create_info extra
= {
216 .use_rectlist
= true,
217 .db_flush_depth_inplace
= true,
218 .db_flush_stencil_inplace
= true,
219 .db_resummarize
= op
== DEPTH_RESUMMARIZE
,
222 result
= radv_graphics_pipeline_create(device_h
,
223 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
224 &pipeline_create_info
, &extra
,
225 &device
->meta_state
.alloc
,
229 ralloc_free(fs_module
.nir
);
231 ralloc_free(vs_module
.nir
);
232 mtx_unlock(&device
->meta_state
.mtx
);
237 radv_device_finish_meta_depth_decomp_state(struct radv_device
*device
)
239 struct radv_meta_state
*state
= &device
->meta_state
;
241 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->depth_decomp
); ++i
) {
242 radv_DestroyRenderPass(radv_device_to_handle(device
),
243 state
->depth_decomp
[i
].pass
,
245 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
246 state
->depth_decomp
[i
].p_layout
,
248 radv_DestroyPipeline(radv_device_to_handle(device
),
249 state
->depth_decomp
[i
].decompress_pipeline
,
251 radv_DestroyPipeline(radv_device_to_handle(device
),
252 state
->depth_decomp
[i
].resummarize_pipeline
,
258 radv_device_init_meta_depth_decomp_state(struct radv_device
*device
, bool on_demand
)
260 struct radv_meta_state
*state
= &device
->meta_state
;
261 VkResult res
= VK_SUCCESS
;
263 struct radv_shader_module vs_module
= { .nir
= radv_meta_build_nir_vs_generate_vertices() };
264 if (!vs_module
.nir
) {
265 /* XXX: Need more accurate error */
266 res
= VK_ERROR_OUT_OF_HOST_MEMORY
;
270 VkShaderModule vs_module_h
= radv_shader_module_to_handle(&vs_module
);
272 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->depth_decomp
); ++i
) {
273 uint32_t samples
= 1 << i
;
275 res
= create_pass(device
, samples
, &state
->depth_decomp
[i
].pass
);
276 if (res
!= VK_SUCCESS
)
279 res
= create_pipeline_layout(device
,
280 &state
->depth_decomp
[i
].p_layout
);
281 if (res
!= VK_SUCCESS
)
287 res
= create_pipeline(device
, vs_module_h
, samples
,
288 state
->depth_decomp
[i
].pass
,
289 state
->depth_decomp
[i
].p_layout
,
291 &state
->depth_decomp
[i
].decompress_pipeline
);
292 if (res
!= VK_SUCCESS
)
295 res
= create_pipeline(device
, vs_module_h
, samples
,
296 state
->depth_decomp
[i
].pass
,
297 state
->depth_decomp
[i
].p_layout
,
299 &state
->depth_decomp
[i
].resummarize_pipeline
);
300 if (res
!= VK_SUCCESS
)
307 radv_device_finish_meta_depth_decomp_state(device
);
310 ralloc_free(vs_module
.nir
);
316 radv_get_depth_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
317 struct radv_image
*image
, enum radv_depth_op op
)
319 struct radv_meta_state
*state
= &cmd_buffer
->device
->meta_state
;
320 uint32_t samples
= image
->info
.samples
;
321 uint32_t samples_log2
= ffs(samples
) - 1;
322 VkPipeline
*pipeline
;
324 if (!state
->depth_decomp
[samples_log2
].decompress_pipeline
) {
327 ret
= create_pipeline(cmd_buffer
->device
, VK_NULL_HANDLE
, samples
,
328 state
->depth_decomp
[samples_log2
].pass
,
329 state
->depth_decomp
[samples_log2
].p_layout
,
331 &state
->depth_decomp
[samples_log2
].decompress_pipeline
);
332 if (ret
!= VK_SUCCESS
) {
333 cmd_buffer
->record_result
= ret
;
337 ret
= create_pipeline(cmd_buffer
->device
, VK_NULL_HANDLE
, samples
,
338 state
->depth_decomp
[samples_log2
].pass
,
339 state
->depth_decomp
[samples_log2
].p_layout
,
341 &state
->depth_decomp
[samples_log2
].resummarize_pipeline
);
342 if (ret
!= VK_SUCCESS
) {
343 cmd_buffer
->record_result
= ret
;
349 case DEPTH_DECOMPRESS
:
350 pipeline
= &state
->depth_decomp
[samples_log2
].decompress_pipeline
;
352 case DEPTH_RESUMMARIZE
:
353 pipeline
= &state
->depth_decomp
[samples_log2
].resummarize_pipeline
;
356 unreachable("unknown operation");
363 radv_process_depth_image_layer(struct radv_cmd_buffer
*cmd_buffer
,
364 struct radv_image
*image
,
365 const VkImageSubresourceRange
*range
,
366 int level
, int layer
)
368 struct radv_device
*device
= cmd_buffer
->device
;
369 struct radv_meta_state
*state
= &device
->meta_state
;
370 uint32_t samples_log2
= ffs(image
->info
.samples
) - 1;
371 struct radv_image_view iview
;
372 uint32_t width
, height
;
374 width
= radv_minify(image
->info
.width
, range
->baseMipLevel
+ level
);
375 height
= radv_minify(image
->info
.height
, range
->baseMipLevel
+ level
);
377 radv_image_view_init(&iview
, device
,
378 &(VkImageViewCreateInfo
) {
379 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
380 .image
= radv_image_to_handle(image
),
381 .viewType
= radv_meta_get_view_type(image
),
382 .format
= image
->vk_format
,
383 .subresourceRange
= {
384 .aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
,
385 .baseMipLevel
= range
->baseMipLevel
+ level
,
387 .baseArrayLayer
= range
->baseArrayLayer
+ layer
,
394 radv_CreateFramebuffer(radv_device_to_handle(device
),
395 &(VkFramebufferCreateInfo
) {
396 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
397 .attachmentCount
= 1,
398 .pAttachments
= (VkImageView
[]) {
399 radv_image_view_to_handle(&iview
)
404 }, &cmd_buffer
->pool
->alloc
, &fb_h
);
406 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
407 &(VkRenderPassBeginInfo
) {
408 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
409 .renderPass
= state
->depth_decomp
[samples_log2
].pass
,
421 .clearValueCount
= 0,
422 .pClearValues
= NULL
,
424 VK_SUBPASS_CONTENTS_INLINE
);
426 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer
), 3, 1, 0, 0);
427 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
));
429 radv_DestroyFramebuffer(radv_device_to_handle(device
), fb_h
,
430 &cmd_buffer
->pool
->alloc
);
433 static void radv_process_depth_image_inplace(struct radv_cmd_buffer
*cmd_buffer
,
434 struct radv_image
*image
,
435 const VkImageSubresourceRange
*subresourceRange
,
436 struct radv_sample_locations_state
*sample_locs
,
437 enum radv_depth_op op
)
439 struct radv_meta_saved_state saved_state
;
440 VkCommandBuffer cmd_buffer_h
= radv_cmd_buffer_to_handle(cmd_buffer
);
441 VkPipeline
*pipeline
;
443 if (!radv_image_has_htile(image
))
446 radv_meta_save(&saved_state
, cmd_buffer
,
447 RADV_META_SAVE_GRAPHICS_PIPELINE
|
448 RADV_META_SAVE_SAMPLE_LOCATIONS
|
449 RADV_META_SAVE_PASS
);
451 pipeline
= radv_get_depth_pipeline(cmd_buffer
, image
, op
);
453 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
454 VK_PIPELINE_BIND_POINT_GRAPHICS
, *pipeline
);
457 assert(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
);
459 /* Set the sample locations specified during explicit or
460 * automatic layout transitions, otherwise the depth decompress
461 * pass uses the default HW locations.
463 radv_CmdSetSampleLocationsEXT(cmd_buffer_h
, &(VkSampleLocationsInfoEXT
) {
464 .sampleLocationsPerPixel
= sample_locs
->per_pixel
,
465 .sampleLocationGridSize
= sample_locs
->grid_size
,
466 .sampleLocationsCount
= sample_locs
->count
,
467 .pSampleLocations
= sample_locs
->locations
,
471 for (uint32_t l
= 0; l
< radv_get_levelCount(image
, subresourceRange
); ++l
) {
473 radv_minify(image
->info
.width
,
474 subresourceRange
->baseMipLevel
+ l
);
476 radv_minify(image
->info
.height
,
477 subresourceRange
->baseMipLevel
+ l
);
479 radv_CmdSetViewport(cmd_buffer_h
, 0, 1,
489 radv_CmdSetScissor(cmd_buffer_h
, 0, 1,
492 .extent
= { width
, height
},
495 for (uint32_t s
= 0; s
< radv_get_layerCount(image
, subresourceRange
); s
++) {
496 radv_process_depth_image_layer(cmd_buffer
, image
,
497 subresourceRange
, l
, s
);
501 radv_meta_restore(&saved_state
, cmd_buffer
);
504 void radv_decompress_depth_image_inplace(struct radv_cmd_buffer
*cmd_buffer
,
505 struct radv_image
*image
,
506 const VkImageSubresourceRange
*subresourceRange
,
507 struct radv_sample_locations_state
*sample_locs
)
509 assert(cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
);
510 radv_process_depth_image_inplace(cmd_buffer
, image
, subresourceRange
,
511 sample_locs
, DEPTH_DECOMPRESS
);
514 void radv_resummarize_depth_image_inplace(struct radv_cmd_buffer
*cmd_buffer
,
515 struct radv_image
*image
,
516 const VkImageSubresourceRange
*subresourceRange
,
517 struct radv_sample_locations_state
*sample_locs
)
519 assert(cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
);
520 radv_process_depth_image_inplace(cmd_buffer
, image
, subresourceRange
,
521 sample_locs
, DEPTH_RESUMMARIZE
);