2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "radv_meta.h"
28 #include "radv_private.h"
33 build_dcc_decompress_compute_shader(struct radv_device
*dev
)
36 const struct glsl_type
*buf_type
= glsl_sampler_type(GLSL_SAMPLER_DIM_2D
,
40 const struct glsl_type
*img_type
= glsl_sampler_type(GLSL_SAMPLER_DIM_2D
,
44 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_COMPUTE
, NULL
);
45 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "dcc_decompress_compute");
47 /* We need at least 16/16/1 to cover an entire DCC block in a single workgroup. */
48 b
.shader
->info
.cs
.local_size
[0] = 16;
49 b
.shader
->info
.cs
.local_size
[1] = 16;
50 b
.shader
->info
.cs
.local_size
[2] = 1;
51 nir_variable
*input_img
= nir_variable_create(b
.shader
, nir_var_uniform
,
53 input_img
->data
.descriptor_set
= 0;
54 input_img
->data
.binding
= 0;
56 nir_variable
*output_img
= nir_variable_create(b
.shader
, nir_var_uniform
,
58 output_img
->data
.descriptor_set
= 0;
59 output_img
->data
.binding
= 1;
61 nir_ssa_def
*invoc_id
= nir_load_local_invocation_id(&b
);
62 nir_ssa_def
*wg_id
= nir_load_work_group_id(&b
);
63 nir_ssa_def
*block_size
= nir_imm_ivec4(&b
,
64 b
.shader
->info
.cs
.local_size
[0],
65 b
.shader
->info
.cs
.local_size
[1],
66 b
.shader
->info
.cs
.local_size
[2], 0);
68 nir_ssa_def
*global_id
= nir_iadd(&b
, nir_imul(&b
, wg_id
, block_size
), invoc_id
);
69 nir_ssa_def
*input_img_deref
= &nir_build_deref_var(&b
, input_img
)->dest
.ssa
;
71 nir_tex_instr
*tex
= nir_tex_instr_create(b
.shader
, 3);
72 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
73 tex
->op
= nir_texop_txf
;
74 tex
->src
[0].src_type
= nir_tex_src_coord
;
75 tex
->src
[0].src
= nir_src_for_ssa(nir_channels(&b
, global_id
, 3));
76 tex
->src
[1].src_type
= nir_tex_src_lod
;
77 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(&b
, 0));
78 tex
->src
[2].src_type
= nir_tex_src_texture_deref
;
79 tex
->src
[2].src
= nir_src_for_ssa(input_img_deref
);
80 tex
->dest_type
= nir_type_float
;
81 tex
->is_array
= false;
82 tex
->coord_components
= 2;
84 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
85 nir_builder_instr_insert(&b
, &tex
->instr
);
87 nir_intrinsic_instr
*membar
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_memory_barrier
);
88 nir_builder_instr_insert(&b
, &membar
->instr
);
90 nir_intrinsic_instr
*bar
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_control_barrier
);
91 nir_builder_instr_insert(&b
, &bar
->instr
);
93 nir_ssa_def
*outval
= &tex
->dest
.ssa
;
94 nir_intrinsic_instr
*store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_image_deref_store
);
95 store
->num_components
= 4;
96 store
->src
[0] = nir_src_for_ssa(&nir_build_deref_var(&b
, output_img
)->dest
.ssa
);
97 store
->src
[1] = nir_src_for_ssa(global_id
);
98 store
->src
[2] = nir_src_for_ssa(nir_ssa_undef(&b
, 1, 32));
99 store
->src
[3] = nir_src_for_ssa(outval
);
100 store
->src
[4] = nir_src_for_ssa(nir_imm_int(&b
, 0));
102 nir_builder_instr_insert(&b
, &store
->instr
);
107 create_dcc_compress_compute(struct radv_device
*device
)
109 VkResult result
= VK_SUCCESS
;
110 struct radv_shader_module cs
= { .nir
= NULL
};
112 cs
.nir
= build_dcc_decompress_compute_shader(device
);
114 VkDescriptorSetLayoutCreateInfo ds_create_info
= {
115 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
116 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
118 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
121 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
122 .descriptorCount
= 1,
123 .stageFlags
= VK_SHADER_STAGE_COMPUTE_BIT
,
124 .pImmutableSamplers
= NULL
128 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
,
129 .descriptorCount
= 1,
130 .stageFlags
= VK_SHADER_STAGE_COMPUTE_BIT
,
131 .pImmutableSamplers
= NULL
136 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
138 &device
->meta_state
.alloc
,
139 &device
->meta_state
.fast_clear_flush
.dcc_decompress_compute_ds_layout
);
140 if (result
!= VK_SUCCESS
)
144 VkPipelineLayoutCreateInfo pl_create_info
= {
145 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
147 .pSetLayouts
= &device
->meta_state
.fast_clear_flush
.dcc_decompress_compute_ds_layout
,
148 .pushConstantRangeCount
= 1,
149 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_COMPUTE_BIT
, 0, 8},
152 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
154 &device
->meta_state
.alloc
,
155 &device
->meta_state
.fast_clear_flush
.dcc_decompress_compute_p_layout
);
156 if (result
!= VK_SUCCESS
)
161 VkPipelineShaderStageCreateInfo pipeline_shader_stage
= {
162 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
163 .stage
= VK_SHADER_STAGE_COMPUTE_BIT
,
164 .module
= radv_shader_module_to_handle(&cs
),
166 .pSpecializationInfo
= NULL
,
169 VkComputePipelineCreateInfo vk_pipeline_info
= {
170 .sType
= VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
,
171 .stage
= pipeline_shader_stage
,
173 .layout
= device
->meta_state
.fast_clear_flush
.dcc_decompress_compute_p_layout
,
176 result
= radv_CreateComputePipelines(radv_device_to_handle(device
),
177 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
178 1, &vk_pipeline_info
, NULL
,
179 &device
->meta_state
.fast_clear_flush
.dcc_decompress_compute_pipeline
);
180 if (result
!= VK_SUCCESS
)
189 create_pass(struct radv_device
*device
)
192 VkDevice device_h
= radv_device_to_handle(device
);
193 const VkAllocationCallbacks
*alloc
= &device
->meta_state
.alloc
;
194 VkAttachmentDescription attachment
;
196 attachment
.format
= VK_FORMAT_UNDEFINED
;
197 attachment
.samples
= 1;
198 attachment
.loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
;
199 attachment
.storeOp
= VK_ATTACHMENT_STORE_OP_STORE
;
200 attachment
.initialLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
201 attachment
.finalLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
203 result
= radv_CreateRenderPass(device_h
,
204 &(VkRenderPassCreateInfo
) {
205 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
206 .attachmentCount
= 1,
207 .pAttachments
= &attachment
,
209 .pSubpasses
= &(VkSubpassDescription
) {
210 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
211 .inputAttachmentCount
= 0,
212 .colorAttachmentCount
= 1,
213 .pColorAttachments
= (VkAttachmentReference
[]) {
216 .layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
219 .pResolveAttachments
= NULL
,
220 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
221 .attachment
= VK_ATTACHMENT_UNUSED
,
223 .preserveAttachmentCount
= 0,
224 .pPreserveAttachments
= NULL
,
226 .dependencyCount
= 2,
227 .pDependencies
= (VkSubpassDependency
[]) {
229 .srcSubpass
= VK_SUBPASS_EXTERNAL
,
231 .srcStageMask
= VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
,
232 .dstStageMask
= VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
,
239 .dstSubpass
= VK_SUBPASS_EXTERNAL
,
240 .srcStageMask
= VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
,
241 .dstStageMask
= VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
,
249 &device
->meta_state
.fast_clear_flush
.pass
);
255 create_pipeline_layout(struct radv_device
*device
, VkPipelineLayout
*layout
)
257 VkPipelineLayoutCreateInfo pl_create_info
= {
258 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
261 .pushConstantRangeCount
= 0,
262 .pPushConstantRanges
= NULL
,
265 return radv_CreatePipelineLayout(radv_device_to_handle(device
),
267 &device
->meta_state
.alloc
,
272 create_pipeline(struct radv_device
*device
,
273 VkShaderModule vs_module_h
,
274 VkPipelineLayout layout
)
277 VkDevice device_h
= radv_device_to_handle(device
);
279 struct radv_shader_module fs_module
= {
280 .nir
= radv_meta_build_nir_fs_noop(),
283 if (!fs_module
.nir
) {
284 /* XXX: Need more accurate error */
285 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
289 const VkPipelineShaderStageCreateInfo stages
[2] = {
291 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
292 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
293 .module
= vs_module_h
,
297 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
298 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
299 .module
= radv_shader_module_to_handle(&fs_module
),
304 const VkPipelineVertexInputStateCreateInfo vi_state
= {
305 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
306 .vertexBindingDescriptionCount
= 0,
307 .vertexAttributeDescriptionCount
= 0,
310 const VkPipelineInputAssemblyStateCreateInfo ia_state
= {
311 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
312 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
313 .primitiveRestartEnable
= false,
316 const VkPipelineColorBlendStateCreateInfo blend_state
= {
317 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
318 .logicOpEnable
= false,
319 .attachmentCount
= 1,
320 .pAttachments
= (VkPipelineColorBlendAttachmentState
[]) {
322 .colorWriteMask
= VK_COLOR_COMPONENT_R_BIT
|
323 VK_COLOR_COMPONENT_G_BIT
|
324 VK_COLOR_COMPONENT_B_BIT
|
325 VK_COLOR_COMPONENT_A_BIT
,
329 const VkPipelineRasterizationStateCreateInfo rs_state
= {
330 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
331 .depthClampEnable
= false,
332 .rasterizerDiscardEnable
= false,
333 .polygonMode
= VK_POLYGON_MODE_FILL
,
334 .cullMode
= VK_CULL_MODE_NONE
,
335 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
,
338 result
= radv_graphics_pipeline_create(device_h
,
339 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
340 &(VkGraphicsPipelineCreateInfo
) {
341 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
345 .pVertexInputState
= &vi_state
,
346 .pInputAssemblyState
= &ia_state
,
348 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
349 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
353 .pRasterizationState
= &rs_state
,
354 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
355 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
356 .rasterizationSamples
= 1,
357 .sampleShadingEnable
= false,
359 .alphaToCoverageEnable
= false,
360 .alphaToOneEnable
= false,
362 .pColorBlendState
= &blend_state
,
363 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
364 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
365 .dynamicStateCount
= 2,
366 .pDynamicStates
= (VkDynamicState
[]) {
367 VK_DYNAMIC_STATE_VIEWPORT
,
368 VK_DYNAMIC_STATE_SCISSOR
,
372 .renderPass
= device
->meta_state
.fast_clear_flush
.pass
,
375 &(struct radv_graphics_pipeline_create_info
) {
376 .use_rectlist
= true,
377 .custom_blend_mode
= V_028808_CB_ELIMINATE_FAST_CLEAR
,
379 &device
->meta_state
.alloc
,
380 &device
->meta_state
.fast_clear_flush
.cmask_eliminate_pipeline
);
381 if (result
!= VK_SUCCESS
)
384 result
= radv_graphics_pipeline_create(device_h
,
385 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
386 &(VkGraphicsPipelineCreateInfo
) {
387 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
391 .pVertexInputState
= &vi_state
,
392 .pInputAssemblyState
= &ia_state
,
394 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
395 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
399 .pRasterizationState
= &rs_state
,
400 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
401 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
402 .rasterizationSamples
= 1,
403 .sampleShadingEnable
= false,
405 .alphaToCoverageEnable
= false,
406 .alphaToOneEnable
= false,
408 .pColorBlendState
= &blend_state
,
409 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
410 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
411 .dynamicStateCount
= 2,
412 .pDynamicStates
= (VkDynamicState
[]) {
413 VK_DYNAMIC_STATE_VIEWPORT
,
414 VK_DYNAMIC_STATE_SCISSOR
,
418 .renderPass
= device
->meta_state
.fast_clear_flush
.pass
,
421 &(struct radv_graphics_pipeline_create_info
) {
422 .use_rectlist
= true,
423 .custom_blend_mode
= V_028808_CB_FMASK_DECOMPRESS
,
425 &device
->meta_state
.alloc
,
426 &device
->meta_state
.fast_clear_flush
.fmask_decompress_pipeline
);
427 if (result
!= VK_SUCCESS
)
430 result
= radv_graphics_pipeline_create(device_h
,
431 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
432 &(VkGraphicsPipelineCreateInfo
) {
433 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
437 .pVertexInputState
= &vi_state
,
438 .pInputAssemblyState
= &ia_state
,
440 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
441 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
445 .pRasterizationState
= &rs_state
,
446 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
447 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
448 .rasterizationSamples
= 1,
449 .sampleShadingEnable
= false,
451 .alphaToCoverageEnable
= false,
452 .alphaToOneEnable
= false,
454 .pColorBlendState
= &blend_state
,
455 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
456 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
457 .dynamicStateCount
= 2,
458 .pDynamicStates
= (VkDynamicState
[]) {
459 VK_DYNAMIC_STATE_VIEWPORT
,
460 VK_DYNAMIC_STATE_SCISSOR
,
464 .renderPass
= device
->meta_state
.fast_clear_flush
.pass
,
467 &(struct radv_graphics_pipeline_create_info
) {
468 .use_rectlist
= true,
469 .custom_blend_mode
= V_028808_CB_DCC_DECOMPRESS
,
471 &device
->meta_state
.alloc
,
472 &device
->meta_state
.fast_clear_flush
.dcc_decompress_pipeline
);
473 if (result
!= VK_SUCCESS
)
479 ralloc_free(fs_module
.nir
);
484 radv_device_finish_meta_fast_clear_flush_state(struct radv_device
*device
)
486 struct radv_meta_state
*state
= &device
->meta_state
;
488 radv_DestroyPipeline(radv_device_to_handle(device
),
489 state
->fast_clear_flush
.dcc_decompress_pipeline
,
491 radv_DestroyPipeline(radv_device_to_handle(device
),
492 state
->fast_clear_flush
.fmask_decompress_pipeline
,
494 radv_DestroyPipeline(radv_device_to_handle(device
),
495 state
->fast_clear_flush
.cmask_eliminate_pipeline
,
497 radv_DestroyRenderPass(radv_device_to_handle(device
),
498 state
->fast_clear_flush
.pass
, &state
->alloc
);
499 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
500 state
->fast_clear_flush
.p_layout
,
503 radv_DestroyPipeline(radv_device_to_handle(device
),
504 state
->fast_clear_flush
.dcc_decompress_compute_pipeline
,
506 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
507 state
->fast_clear_flush
.dcc_decompress_compute_p_layout
,
509 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
510 state
->fast_clear_flush
.dcc_decompress_compute_ds_layout
,
515 radv_device_init_meta_fast_clear_flush_state_internal(struct radv_device
*device
)
517 VkResult res
= VK_SUCCESS
;
519 mtx_lock(&device
->meta_state
.mtx
);
520 if (device
->meta_state
.fast_clear_flush
.cmask_eliminate_pipeline
) {
521 mtx_unlock(&device
->meta_state
.mtx
);
525 struct radv_shader_module vs_module
= { .nir
= radv_meta_build_nir_vs_generate_vertices() };
526 if (!vs_module
.nir
) {
527 /* XXX: Need more accurate error */
528 res
= VK_ERROR_OUT_OF_HOST_MEMORY
;
532 res
= create_pass(device
);
533 if (res
!= VK_SUCCESS
)
536 res
= create_pipeline_layout(device
,
537 &device
->meta_state
.fast_clear_flush
.p_layout
);
538 if (res
!= VK_SUCCESS
)
541 VkShaderModule vs_module_h
= radv_shader_module_to_handle(&vs_module
);
542 res
= create_pipeline(device
, vs_module_h
,
543 device
->meta_state
.fast_clear_flush
.p_layout
);
544 if (res
!= VK_SUCCESS
)
547 res
= create_dcc_compress_compute(device
);
548 if (res
!= VK_SUCCESS
)
554 radv_device_finish_meta_fast_clear_flush_state(device
);
557 ralloc_free(vs_module
.nir
);
558 mtx_unlock(&device
->meta_state
.mtx
);
565 radv_device_init_meta_fast_clear_flush_state(struct radv_device
*device
, bool on_demand
)
570 return radv_device_init_meta_fast_clear_flush_state_internal(device
);
574 radv_emit_set_predication_state_from_image(struct radv_cmd_buffer
*cmd_buffer
,
575 struct radv_image
*image
,
576 uint64_t pred_offset
, bool value
)
581 va
= radv_buffer_get_va(image
->bo
) + image
->offset
;
585 si_emit_set_predication_state(cmd_buffer
, true, va
);
589 radv_process_color_image_layer(struct radv_cmd_buffer
*cmd_buffer
,
590 struct radv_image
*image
,
591 const VkImageSubresourceRange
*range
,
592 int level
, int layer
)
594 struct radv_device
*device
= cmd_buffer
->device
;
595 struct radv_image_view iview
;
596 uint32_t width
, height
;
598 width
= radv_minify(image
->info
.width
, range
->baseMipLevel
+ level
);
599 height
= radv_minify(image
->info
.height
, range
->baseMipLevel
+ level
);
601 radv_image_view_init(&iview
, device
,
602 &(VkImageViewCreateInfo
) {
603 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
604 .image
= radv_image_to_handle(image
),
605 .viewType
= radv_meta_get_view_type(image
),
606 .format
= image
->vk_format
,
607 .subresourceRange
= {
608 .aspectMask
= VK_IMAGE_ASPECT_COLOR_BIT
,
609 .baseMipLevel
= range
->baseMipLevel
+ level
,
611 .baseArrayLayer
= range
->baseArrayLayer
+ layer
,
617 radv_CreateFramebuffer(radv_device_to_handle(device
),
618 &(VkFramebufferCreateInfo
) {
619 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
620 .attachmentCount
= 1,
621 .pAttachments
= (VkImageView
[]) {
622 radv_image_view_to_handle(&iview
)
627 }, &cmd_buffer
->pool
->alloc
, &fb_h
);
629 radv_cmd_buffer_begin_render_pass(cmd_buffer
,
630 &(VkRenderPassBeginInfo
) {
631 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
632 .renderPass
= device
->meta_state
.fast_clear_flush
.pass
,
636 .extent
= { width
, height
, }
638 .clearValueCount
= 0,
639 .pClearValues
= NULL
,
642 radv_cmd_buffer_set_subpass(cmd_buffer
,
643 &cmd_buffer
->state
.pass
->subpasses
[0]);
645 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer
), 3, 1, 0, 0);
647 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
648 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
650 radv_cmd_buffer_end_render_pass(cmd_buffer
);
652 radv_DestroyFramebuffer(radv_device_to_handle(device
), fb_h
,
653 &cmd_buffer
->pool
->alloc
);
657 radv_process_color_image(struct radv_cmd_buffer
*cmd_buffer
,
658 struct radv_image
*image
,
659 const VkImageSubresourceRange
*subresourceRange
,
662 struct radv_meta_saved_state saved_state
;
663 VkPipeline
*pipeline
;
665 if (decompress_dcc
&& radv_dcc_enabled(image
, subresourceRange
->baseMipLevel
)) {
666 pipeline
= &cmd_buffer
->device
->meta_state
.fast_clear_flush
.dcc_decompress_pipeline
;
667 } else if (radv_image_has_fmask(image
) && !image
->tc_compatible_cmask
) {
668 pipeline
= &cmd_buffer
->device
->meta_state
.fast_clear_flush
.fmask_decompress_pipeline
;
670 pipeline
= &cmd_buffer
->device
->meta_state
.fast_clear_flush
.cmask_eliminate_pipeline
;
676 ret
= radv_device_init_meta_fast_clear_flush_state_internal(cmd_buffer
->device
);
677 if (ret
!= VK_SUCCESS
) {
678 cmd_buffer
->record_result
= ret
;
683 radv_meta_save(&saved_state
, cmd_buffer
,
684 RADV_META_SAVE_GRAPHICS_PIPELINE
|
685 RADV_META_SAVE_PASS
);
687 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
688 VK_PIPELINE_BIND_POINT_GRAPHICS
, *pipeline
);
690 for (uint32_t l
= 0; l
< radv_get_levelCount(image
, subresourceRange
); ++l
) {
691 uint32_t width
, height
;
693 /* Do not decompress levels without DCC. */
694 if (decompress_dcc
&&
695 !radv_dcc_enabled(image
, subresourceRange
->baseMipLevel
+ l
))
698 width
= radv_minify(image
->info
.width
,
699 subresourceRange
->baseMipLevel
+ l
);
700 height
= radv_minify(image
->info
.height
,
701 subresourceRange
->baseMipLevel
+ l
);
703 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1,
713 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1,
716 .extent
= { width
, height
},
719 for (uint32_t s
= 0; s
< radv_get_layerCount(image
, subresourceRange
); s
++) {
720 radv_process_color_image_layer(cmd_buffer
, image
,
721 subresourceRange
, l
, s
);
725 radv_meta_restore(&saved_state
, cmd_buffer
);
729 radv_emit_color_decompress(struct radv_cmd_buffer
*cmd_buffer
,
730 struct radv_image
*image
,
731 const VkImageSubresourceRange
*subresourceRange
,
734 bool old_predicating
= false;
736 assert(cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
);
738 if (radv_dcc_enabled(image
, subresourceRange
->baseMipLevel
)) {
739 uint64_t pred_offset
= decompress_dcc
? image
->dcc_pred_offset
:
740 image
->fce_pred_offset
;
741 pred_offset
+= 8 * subresourceRange
->baseMipLevel
;
743 old_predicating
= cmd_buffer
->state
.predicating
;
745 radv_emit_set_predication_state_from_image(cmd_buffer
, image
, pred_offset
, true);
746 cmd_buffer
->state
.predicating
= true;
749 radv_process_color_image(cmd_buffer
, image
, subresourceRange
,
752 if (radv_dcc_enabled(image
, subresourceRange
->baseMipLevel
)) {
753 uint64_t pred_offset
= decompress_dcc
? image
->dcc_pred_offset
:
754 image
->fce_pred_offset
;
755 pred_offset
+= 8 * subresourceRange
->baseMipLevel
;
757 cmd_buffer
->state
.predicating
= old_predicating
;
759 radv_emit_set_predication_state_from_image(cmd_buffer
, image
, pred_offset
, false);
761 if (cmd_buffer
->state
.predication_type
!= -1) {
762 /* Restore previous conditional rendering user state. */
763 si_emit_set_predication_state(cmd_buffer
,
764 cmd_buffer
->state
.predication_type
,
765 cmd_buffer
->state
.predication_va
);
769 if (radv_dcc_enabled(image
, subresourceRange
->baseMipLevel
)) {
770 /* Clear the image's fast-clear eliminate predicate because
771 * FMASK and DCC also imply a fast-clear eliminate.
773 radv_update_fce_metadata(cmd_buffer
, image
, subresourceRange
, false);
775 /* Mark the image as being decompressed. */
777 radv_update_dcc_metadata(cmd_buffer
, image
, subresourceRange
, false);
782 radv_fast_clear_flush_image_inplace(struct radv_cmd_buffer
*cmd_buffer
,
783 struct radv_image
*image
,
784 const VkImageSubresourceRange
*subresourceRange
)
786 struct radv_barrier_data barrier
= {};
788 if (radv_image_has_fmask(image
)) {
789 barrier
.layout_transitions
.fmask_decompress
= 1;
791 barrier
.layout_transitions
.fast_clear_eliminate
= 1;
793 radv_describe_layout_transition(cmd_buffer
, &barrier
);
795 radv_emit_color_decompress(cmd_buffer
, image
, subresourceRange
, false);
799 radv_decompress_dcc_gfx(struct radv_cmd_buffer
*cmd_buffer
,
800 struct radv_image
*image
,
801 const VkImageSubresourceRange
*subresourceRange
)
803 radv_emit_color_decompress(cmd_buffer
, image
, subresourceRange
, true);
807 radv_decompress_dcc_compute(struct radv_cmd_buffer
*cmd_buffer
,
808 struct radv_image
*image
,
809 const VkImageSubresourceRange
*subresourceRange
)
811 struct radv_meta_saved_state saved_state
;
812 struct radv_image_view load_iview
= {0};
813 struct radv_image_view store_iview
= {0};
814 struct radv_device
*device
= cmd_buffer
->device
;
816 /* This assumes the image is 2d with 1 layer */
817 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
819 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
820 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
822 if (!cmd_buffer
->device
->meta_state
.fast_clear_flush
.cmask_eliminate_pipeline
) {
823 VkResult ret
= radv_device_init_meta_fast_clear_flush_state_internal(cmd_buffer
->device
);
824 if (ret
!= VK_SUCCESS
) {
825 cmd_buffer
->record_result
= ret
;
830 radv_meta_save(&saved_state
, cmd_buffer
, RADV_META_SAVE_DESCRIPTORS
|
831 RADV_META_SAVE_COMPUTE_PIPELINE
);
833 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
834 VK_PIPELINE_BIND_POINT_COMPUTE
,
835 device
->meta_state
.fast_clear_flush
.dcc_decompress_compute_pipeline
);
837 for (uint32_t l
= 0; l
< radv_get_levelCount(image
, subresourceRange
); l
++) {
838 uint32_t width
, height
;
840 /* Do not decompress levels without DCC. */
841 if (!radv_dcc_enabled(image
, subresourceRange
->baseMipLevel
+ l
))
844 width
= radv_minify(image
->info
.width
,
845 subresourceRange
->baseMipLevel
+ l
);
846 height
= radv_minify(image
->info
.height
,
847 subresourceRange
->baseMipLevel
+ l
);
849 for (uint32_t s
= 0; s
< radv_get_layerCount(image
, subresourceRange
); s
++) {
850 radv_image_view_init(&load_iview
, cmd_buffer
->device
,
851 &(VkImageViewCreateInfo
) {
852 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
853 .image
= radv_image_to_handle(image
),
854 .viewType
= VK_IMAGE_VIEW_TYPE_2D
,
855 .format
= image
->vk_format
,
856 .subresourceRange
= {
857 .aspectMask
= VK_IMAGE_ASPECT_COLOR_BIT
,
858 .baseMipLevel
= subresourceRange
->baseMipLevel
+ l
,
860 .baseArrayLayer
= subresourceRange
->baseArrayLayer
+ s
,
864 radv_image_view_init(&store_iview
, cmd_buffer
->device
,
865 &(VkImageViewCreateInfo
) {
866 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
867 .image
= radv_image_to_handle(image
),
868 .viewType
= VK_IMAGE_VIEW_TYPE_2D
,
869 .format
= image
->vk_format
,
870 .subresourceRange
= {
871 .aspectMask
= VK_IMAGE_ASPECT_COLOR_BIT
,
872 .baseMipLevel
= subresourceRange
->baseMipLevel
+ l
,
874 .baseArrayLayer
= subresourceRange
->baseArrayLayer
+ s
,
877 }, &(struct radv_image_view_extra_create_info
) {
878 .disable_compression
= true
881 radv_meta_push_descriptor_set(cmd_buffer
,
882 VK_PIPELINE_BIND_POINT_COMPUTE
,
883 device
->meta_state
.fast_clear_flush
.dcc_decompress_compute_p_layout
,
885 2, /* descriptorWriteCount */
886 (VkWriteDescriptorSet
[]) {
888 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
890 .dstArrayElement
= 0,
891 .descriptorCount
= 1,
892 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
893 .pImageInfo
= (VkDescriptorImageInfo
[]) {
895 .sampler
= VK_NULL_HANDLE
,
896 .imageView
= radv_image_view_to_handle(&load_iview
),
897 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
902 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
904 .dstArrayElement
= 0,
905 .descriptorCount
= 1,
906 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
,
907 .pImageInfo
= (VkDescriptorImageInfo
[]) {
909 .sampler
= VK_NULL_HANDLE
,
910 .imageView
= radv_image_view_to_handle(&store_iview
),
911 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
917 radv_unaligned_dispatch(cmd_buffer
, width
, height
, 1);
921 /* Mark this image as actually being decompressed. */
922 radv_update_dcc_metadata(cmd_buffer
, image
, subresourceRange
, false);
924 /* The fill buffer below does its own saving */
925 radv_meta_restore(&saved_state
, cmd_buffer
);
927 state
->flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
928 RADV_CMD_FLAG_INV_VCACHE
;
931 /* Initialize the DCC metadata as "fully expanded". */
932 radv_initialize_dcc(cmd_buffer
, image
, subresourceRange
, 0xffffffff);
936 radv_decompress_dcc(struct radv_cmd_buffer
*cmd_buffer
,
937 struct radv_image
*image
,
938 const VkImageSubresourceRange
*subresourceRange
)
940 struct radv_barrier_data barrier
= {};
942 barrier
.layout_transitions
.dcc_decompress
= 1;
943 radv_describe_layout_transition(cmd_buffer
, &barrier
);
945 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
)
946 radv_decompress_dcc_gfx(cmd_buffer
, image
, subresourceRange
);
948 radv_decompress_dcc_compute(cmd_buffer
, image
, subresourceRange
);