radv: predicate cmask eliminate when using DCC.
[mesa.git] / src / amd / vulkan / radv_meta_fast_clear.c
1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26
27 #include "radv_meta.h"
28 #include "radv_private.h"
29 #include "sid.h"
30
31 static VkResult
32 create_pass(struct radv_device *device)
33 {
34 VkResult result;
35 VkDevice device_h = radv_device_to_handle(device);
36 const VkAllocationCallbacks *alloc = &device->meta_state.alloc;
37 VkAttachmentDescription attachment;
38
39 attachment.format = VK_FORMAT_UNDEFINED;
40 attachment.samples = 1;
41 attachment.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD;
42 attachment.storeOp = VK_ATTACHMENT_STORE_OP_STORE;
43 attachment.initialLayout = VK_IMAGE_LAYOUT_GENERAL;
44 attachment.finalLayout = VK_IMAGE_LAYOUT_GENERAL;
45
46 result = radv_CreateRenderPass(device_h,
47 &(VkRenderPassCreateInfo) {
48 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
49 .attachmentCount = 1,
50 .pAttachments = &attachment,
51 .subpassCount = 1,
52 .pSubpasses = &(VkSubpassDescription) {
53 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
54 .inputAttachmentCount = 0,
55 .colorAttachmentCount = 1,
56 .pColorAttachments = (VkAttachmentReference[]) {
57 {
58 .attachment = 0,
59 .layout = VK_IMAGE_LAYOUT_GENERAL,
60 },
61 },
62 .pResolveAttachments = NULL,
63 .pDepthStencilAttachment = &(VkAttachmentReference) {
64 .attachment = VK_ATTACHMENT_UNUSED,
65 },
66 .preserveAttachmentCount = 0,
67 .pPreserveAttachments = NULL,
68 },
69 .dependencyCount = 0,
70 },
71 alloc,
72 &device->meta_state.fast_clear_flush.pass);
73
74 return result;
75 }
76
77 static VkResult
78 create_pipeline(struct radv_device *device,
79 VkShaderModule vs_module_h)
80 {
81 VkResult result;
82 VkDevice device_h = radv_device_to_handle(device);
83
84 struct radv_shader_module fs_module = {
85 .nir = radv_meta_build_nir_fs_noop(),
86 };
87
88 if (!fs_module.nir) {
89 /* XXX: Need more accurate error */
90 result = VK_ERROR_OUT_OF_HOST_MEMORY;
91 goto cleanup;
92 }
93
94 const VkPipelineShaderStageCreateInfo stages[2] = {
95 {
96 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
97 .stage = VK_SHADER_STAGE_VERTEX_BIT,
98 .module = vs_module_h,
99 .pName = "main",
100 },
101 {
102 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
103 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
104 .module = radv_shader_module_to_handle(&fs_module),
105 .pName = "main",
106 },
107 };
108
109 const VkPipelineVertexInputStateCreateInfo vi_state = {
110 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
111 .vertexBindingDescriptionCount = 0,
112 .vertexAttributeDescriptionCount = 0,
113 };
114
115 const VkPipelineInputAssemblyStateCreateInfo ia_state = {
116 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
117 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
118 .primitiveRestartEnable = false,
119 };
120
121 const VkPipelineColorBlendStateCreateInfo blend_state = {
122 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
123 .logicOpEnable = false,
124 .attachmentCount = 1,
125 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
126 {
127 .colorWriteMask = VK_COLOR_COMPONENT_R_BIT |
128 VK_COLOR_COMPONENT_G_BIT |
129 VK_COLOR_COMPONENT_B_BIT |
130 VK_COLOR_COMPONENT_A_BIT,
131 },
132 }
133 };
134 const VkPipelineRasterizationStateCreateInfo rs_state = {
135 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
136 .depthClampEnable = false,
137 .rasterizerDiscardEnable = false,
138 .polygonMode = VK_POLYGON_MODE_FILL,
139 .cullMode = VK_CULL_MODE_NONE,
140 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
141 };
142
143 result = radv_graphics_pipeline_create(device_h,
144 radv_pipeline_cache_to_handle(&device->meta_state.cache),
145 &(VkGraphicsPipelineCreateInfo) {
146 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
147 .stageCount = 2,
148 .pStages = stages,
149
150 .pVertexInputState = &vi_state,
151 .pInputAssemblyState = &ia_state,
152
153 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
154 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
155 .viewportCount = 1,
156 .scissorCount = 1,
157 },
158 .pRasterizationState = &rs_state,
159 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
160 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
161 .rasterizationSamples = 1,
162 .sampleShadingEnable = false,
163 .pSampleMask = NULL,
164 .alphaToCoverageEnable = false,
165 .alphaToOneEnable = false,
166 },
167 .pColorBlendState = &blend_state,
168 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
169 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
170 .dynamicStateCount = 2,
171 .pDynamicStates = (VkDynamicState[]) {
172 VK_DYNAMIC_STATE_VIEWPORT,
173 VK_DYNAMIC_STATE_SCISSOR,
174 },
175 },
176 .renderPass = device->meta_state.fast_clear_flush.pass,
177 .subpass = 0,
178 },
179 &(struct radv_graphics_pipeline_create_info) {
180 .use_rectlist = true,
181 .custom_blend_mode = V_028808_CB_ELIMINATE_FAST_CLEAR,
182 },
183 &device->meta_state.alloc,
184 &device->meta_state.fast_clear_flush.cmask_eliminate_pipeline);
185 if (result != VK_SUCCESS)
186 goto cleanup;
187
188 result = radv_graphics_pipeline_create(device_h,
189 radv_pipeline_cache_to_handle(&device->meta_state.cache),
190 &(VkGraphicsPipelineCreateInfo) {
191 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
192 .stageCount = 2,
193 .pStages = stages,
194
195 .pVertexInputState = &vi_state,
196 .pInputAssemblyState = &ia_state,
197
198 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
199 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
200 .viewportCount = 1,
201 .scissorCount = 1,
202 },
203 .pRasterizationState = &rs_state,
204 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
205 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
206 .rasterizationSamples = 1,
207 .sampleShadingEnable = false,
208 .pSampleMask = NULL,
209 .alphaToCoverageEnable = false,
210 .alphaToOneEnable = false,
211 },
212 .pColorBlendState = &blend_state,
213 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
214 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
215 .dynamicStateCount = 2,
216 .pDynamicStates = (VkDynamicState[]) {
217 VK_DYNAMIC_STATE_VIEWPORT,
218 VK_DYNAMIC_STATE_SCISSOR,
219 },
220 },
221 .renderPass = device->meta_state.fast_clear_flush.pass,
222 .subpass = 0,
223 },
224 &(struct radv_graphics_pipeline_create_info) {
225 .use_rectlist = true,
226 .custom_blend_mode = V_028808_CB_FMASK_DECOMPRESS,
227 },
228 &device->meta_state.alloc,
229 &device->meta_state.fast_clear_flush.fmask_decompress_pipeline);
230 if (result != VK_SUCCESS)
231 goto cleanup_cmask;
232
233 goto cleanup;
234 cleanup_cmask:
235 radv_DestroyPipeline(device_h, device->meta_state.fast_clear_flush.cmask_eliminate_pipeline, &device->meta_state.alloc);
236 cleanup:
237 ralloc_free(fs_module.nir);
238 return result;
239 }
240
241 void
242 radv_device_finish_meta_fast_clear_flush_state(struct radv_device *device)
243 {
244 struct radv_meta_state *state = &device->meta_state;
245 VkDevice device_h = radv_device_to_handle(device);
246 VkRenderPass pass_h = device->meta_state.fast_clear_flush.pass;
247 const VkAllocationCallbacks *alloc = &device->meta_state.alloc;
248
249 if (pass_h)
250 radv_DestroyRenderPass(device_h, pass_h,
251 &device->meta_state.alloc);
252
253 VkPipeline pipeline_h = state->fast_clear_flush.cmask_eliminate_pipeline;
254 if (pipeline_h) {
255 radv_DestroyPipeline(device_h, pipeline_h, alloc);
256 }
257
258 pipeline_h = state->fast_clear_flush.fmask_decompress_pipeline;
259 if (pipeline_h) {
260 radv_DestroyPipeline(device_h, pipeline_h, alloc);
261 }
262 }
263
264 VkResult
265 radv_device_init_meta_fast_clear_flush_state(struct radv_device *device)
266 {
267 VkResult res = VK_SUCCESS;
268
269 zero(device->meta_state.fast_clear_flush);
270
271 struct radv_shader_module vs_module = { .nir = radv_meta_build_nir_vs_generate_vertices() };
272 if (!vs_module.nir) {
273 /* XXX: Need more accurate error */
274 res = VK_ERROR_OUT_OF_HOST_MEMORY;
275 goto fail;
276 }
277
278 res = create_pass(device);
279 if (res != VK_SUCCESS)
280 goto fail;
281
282 VkShaderModule vs_module_h = radv_shader_module_to_handle(&vs_module);
283 res = create_pipeline(device, vs_module_h);
284 if (res != VK_SUCCESS)
285 goto fail;
286
287 goto cleanup;
288
289 fail:
290 radv_device_finish_meta_fast_clear_flush_state(device);
291
292 cleanup:
293 ralloc_free(vs_module.nir);
294
295 return res;
296 }
297
298 static void
299 emit_fast_clear_flush(struct radv_cmd_buffer *cmd_buffer,
300 const VkExtent2D *resolve_extent,
301 bool fmask_decompress)
302 {
303 struct radv_device *device = cmd_buffer->device;
304 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
305
306 VkPipeline pipeline_h;
307 if (fmask_decompress)
308 pipeline_h = device->meta_state.fast_clear_flush.fmask_decompress_pipeline;
309 else
310 pipeline_h = device->meta_state.fast_clear_flush.cmask_eliminate_pipeline;
311 RADV_FROM_HANDLE(radv_pipeline, pipeline, pipeline_h);
312
313 if (cmd_buffer->state.pipeline != pipeline) {
314 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
315 pipeline_h);
316 }
317
318 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
319 .x = 0,
320 .y = 0,
321 .width = resolve_extent->width,
322 .height = resolve_extent->height,
323 .minDepth = 0.0f,
324 .maxDepth = 1.0f
325 });
326
327 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
328 .offset = (VkOffset2D) { 0, 0 },
329 .extent = (VkExtent2D) { resolve_extent->width, resolve_extent->height },
330 });
331
332 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
333 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
334 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META);
335 }
336
337 static void
338 radv_emit_set_predication_state_from_image(struct radv_cmd_buffer *cmd_buffer,
339 struct radv_image *image, bool value)
340 {
341 uint64_t va = 0;
342
343 if (value) {
344 va = cmd_buffer->device->ws->buffer_get_va(image->bo) + image->offset;
345 va += image->dcc_pred_offset;
346 }
347
348 si_emit_set_predication_state(cmd_buffer, va);
349 }
350
351 /**
352 */
353 void
354 radv_fast_clear_flush_image_inplace(struct radv_cmd_buffer *cmd_buffer,
355 struct radv_image *image,
356 const VkImageSubresourceRange *subresourceRange)
357 {
358 struct radv_meta_saved_state saved_state;
359 struct radv_meta_saved_pass_state saved_pass_state;
360 VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
361 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
362 uint32_t layer_count = radv_get_layerCount(image, subresourceRange);
363
364 assert(cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL);
365 radv_meta_save_pass(&saved_pass_state, cmd_buffer);
366 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
367
368 if (image->surface.dcc_size) {
369 radv_emit_set_predication_state_from_image(cmd_buffer, image, true);
370 cmd_buffer->state.predicating = true;
371 }
372 for (uint32_t layer = 0; layer < layer_count; ++layer) {
373 struct radv_image_view iview;
374
375 radv_image_view_init(&iview, cmd_buffer->device,
376 &(VkImageViewCreateInfo) {
377 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
378 .image = radv_image_to_handle(image),
379 .viewType = radv_meta_get_view_type(image),
380 .format = image->vk_format,
381 .subresourceRange = {
382 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
383 .baseMipLevel = 0,
384 .levelCount = 1,
385 .baseArrayLayer = subresourceRange->baseArrayLayer + layer,
386 .layerCount = 1,
387 },
388 });
389
390 VkFramebuffer fb_h;
391 radv_CreateFramebuffer(device_h,
392 &(VkFramebufferCreateInfo) {
393 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
394 .attachmentCount = 1,
395 .pAttachments = (VkImageView[]) {
396 radv_image_view_to_handle(&iview)
397 },
398 .width = image->info.width,
399 .height = image->info.height,
400 .layers = 1
401 },
402 &cmd_buffer->pool->alloc,
403 &fb_h);
404
405 radv_CmdBeginRenderPass(cmd_buffer_h,
406 &(VkRenderPassBeginInfo) {
407 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
408 .renderPass = cmd_buffer->device->meta_state.fast_clear_flush.pass,
409 .framebuffer = fb_h,
410 .renderArea = {
411 .offset = {
412 0,
413 0,
414 },
415 .extent = {
416 image->info.width,
417 image->info.height,
418 }
419 },
420 .clearValueCount = 0,
421 .pClearValues = NULL,
422 },
423 VK_SUBPASS_CONTENTS_INLINE);
424
425 emit_fast_clear_flush(cmd_buffer,
426 &(VkExtent2D) { image->info.width, image->info.height },
427 image->fmask.size > 0);
428 radv_CmdEndRenderPass(cmd_buffer_h);
429
430 radv_DestroyFramebuffer(device_h, fb_h,
431 &cmd_buffer->pool->alloc);
432
433 }
434 if (image->surface.dcc_size) {
435 cmd_buffer->state.predicating = false;
436 radv_emit_set_predication_state_from_image(cmd_buffer, image, false);
437 }
438 radv_meta_restore(&saved_state, cmd_buffer);
439 radv_meta_restore_pass(&saved_pass_state, cmd_buffer);
440 }