radv: set correct INDEX_TYPE for indexed indirect draws on GFX9
[mesa.git] / src / amd / vulkan / radv_meta_resolve_cs.c
1 /*
2 * Copyright © 2016 Dave Airlie
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24
25 #include <assert.h>
26 #include <stdbool.h>
27
28 #include "radv_meta.h"
29 #include "radv_private.h"
30 #include "nir/nir_builder.h"
31 #include "sid.h"
32 #include "vk_format.h"
33
34 static nir_ssa_def *radv_meta_build_resolve_srgb_conversion(nir_builder *b,
35 nir_ssa_def *input)
36 {
37 nir_const_value v;
38 unsigned i;
39 v.u32[0] = 0x3b4d2e1c; // 0.00313080009
40
41 nir_ssa_def *cmp[3];
42 for (i = 0; i < 3; i++)
43 cmp[i] = nir_flt(b, nir_channel(b, input, i),
44 nir_build_imm(b, 1, 32, v));
45
46 nir_ssa_def *ltvals[3];
47 v.f32[0] = 12.92;
48 for (i = 0; i < 3; i++)
49 ltvals[i] = nir_fmul(b, nir_channel(b, input, i),
50 nir_build_imm(b, 1, 32, v));
51
52 nir_ssa_def *gtvals[3];
53
54 for (i = 0; i < 3; i++) {
55 v.f32[0] = 1.0/2.4;
56 gtvals[i] = nir_fpow(b, nir_channel(b, input, i),
57 nir_build_imm(b, 1, 32, v));
58 v.f32[0] = 1.055;
59 gtvals[i] = nir_fmul(b, gtvals[i],
60 nir_build_imm(b, 1, 32, v));
61 v.f32[0] = 0.055;
62 gtvals[i] = nir_fsub(b, gtvals[i],
63 nir_build_imm(b, 1, 32, v));
64 }
65
66 nir_ssa_def *comp[4];
67 for (i = 0; i < 3; i++)
68 comp[i] = nir_bcsel(b, cmp[i], ltvals[i], gtvals[i]);
69 comp[3] = nir_channels(b, input, 1 << 3);
70 return nir_vec(b, comp, 4);
71 }
72
73 static nir_shader *
74 build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_srgb, int samples)
75 {
76 nir_builder b;
77 char name[64];
78 const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS,
79 false,
80 false,
81 GLSL_TYPE_FLOAT);
82 const struct glsl_type *img_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D,
83 false,
84 false,
85 GLSL_TYPE_FLOAT);
86 snprintf(name, 64, "meta_resolve_cs-%d-%s", samples, is_integer ? "int" : (is_srgb ? "srgb" : "float"));
87 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
88 b.shader->info.name = ralloc_strdup(b.shader, name);
89 b.shader->info.cs.local_size[0] = 16;
90 b.shader->info.cs.local_size[1] = 16;
91 b.shader->info.cs.local_size[2] = 1;
92
93 nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
94 sampler_type, "s_tex");
95 input_img->data.descriptor_set = 0;
96 input_img->data.binding = 0;
97
98 nir_variable *output_img = nir_variable_create(b.shader, nir_var_uniform,
99 img_type, "out_img");
100 output_img->data.descriptor_set = 0;
101 output_img->data.binding = 1;
102 nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
103 nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
104 nir_ssa_def *block_size = nir_imm_ivec4(&b,
105 b.shader->info.cs.local_size[0],
106 b.shader->info.cs.local_size[1],
107 b.shader->info.cs.local_size[2], 0);
108
109 nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
110
111 nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
112 nir_intrinsic_set_base(src_offset, 0);
113 nir_intrinsic_set_range(src_offset, 16);
114 src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
115 src_offset->num_components = 2;
116 nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
117 nir_builder_instr_insert(&b, &src_offset->instr);
118
119 nir_intrinsic_instr *dst_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
120 nir_intrinsic_set_base(dst_offset, 0);
121 nir_intrinsic_set_range(dst_offset, 16);
122 dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8));
123 dst_offset->num_components = 2;
124 nir_ssa_dest_init(&dst_offset->instr, &dst_offset->dest, 2, 32, "dst_offset");
125 nir_builder_instr_insert(&b, &dst_offset->instr);
126
127 nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, global_id, &src_offset->dest.ssa), 0x3);
128 nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
129
130 radv_meta_build_resolve_shader_core(&b, is_integer, samples, input_img,
131 color, img_coord);
132
133 nir_ssa_def *outval = nir_load_var(&b, color);
134 if (is_srgb)
135 outval = radv_meta_build_resolve_srgb_conversion(&b, outval);
136
137 nir_ssa_def *coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa);
138 nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_store);
139 store->src[0] = nir_src_for_ssa(coord);
140 store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
141 store->src[2] = nir_src_for_ssa(outval);
142 store->variables[0] = nir_deref_var_create(store, output_img);
143 nir_builder_instr_insert(&b, &store->instr);
144 return b.shader;
145 }
146
147
148 static VkResult
149 create_layout(struct radv_device *device)
150 {
151 VkResult result;
152 /*
153 * two descriptors one for the image being sampled
154 * one for the buffer being written.
155 */
156 VkDescriptorSetLayoutCreateInfo ds_create_info = {
157 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
158 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
159 .bindingCount = 2,
160 .pBindings = (VkDescriptorSetLayoutBinding[]) {
161 {
162 .binding = 0,
163 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
164 .descriptorCount = 1,
165 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
166 .pImmutableSamplers = NULL
167 },
168 {
169 .binding = 1,
170 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
171 .descriptorCount = 1,
172 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
173 .pImmutableSamplers = NULL
174 },
175 }
176 };
177
178 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
179 &ds_create_info,
180 &device->meta_state.alloc,
181 &device->meta_state.resolve_compute.ds_layout);
182 if (result != VK_SUCCESS)
183 goto fail;
184
185
186 VkPipelineLayoutCreateInfo pl_create_info = {
187 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
188 .setLayoutCount = 1,
189 .pSetLayouts = &device->meta_state.resolve_compute.ds_layout,
190 .pushConstantRangeCount = 1,
191 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
192 };
193
194 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
195 &pl_create_info,
196 &device->meta_state.alloc,
197 &device->meta_state.resolve_compute.p_layout);
198 if (result != VK_SUCCESS)
199 goto fail;
200 return VK_SUCCESS;
201 fail:
202 return result;
203 }
204
205 static VkResult
206 create_resolve_pipeline(struct radv_device *device,
207 int samples,
208 bool is_integer,
209 bool is_srgb,
210 VkPipeline *pipeline)
211 {
212 VkResult result;
213 struct radv_shader_module cs = { .nir = NULL };
214
215 cs.nir = build_resolve_compute_shader(device, is_integer, is_srgb, samples);
216
217 /* compute shader */
218
219 VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
220 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
221 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
222 .module = radv_shader_module_to_handle(&cs),
223 .pName = "main",
224 .pSpecializationInfo = NULL,
225 };
226
227 VkComputePipelineCreateInfo vk_pipeline_info = {
228 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
229 .stage = pipeline_shader_stage,
230 .flags = 0,
231 .layout = device->meta_state.resolve_compute.p_layout,
232 };
233
234 result = radv_CreateComputePipelines(radv_device_to_handle(device),
235 radv_pipeline_cache_to_handle(&device->meta_state.cache),
236 1, &vk_pipeline_info, NULL,
237 pipeline);
238 if (result != VK_SUCCESS)
239 goto fail;
240
241 ralloc_free(cs.nir);
242 return VK_SUCCESS;
243 fail:
244 ralloc_free(cs.nir);
245 return result;
246 }
247
248 VkResult
249 radv_device_init_meta_resolve_compute_state(struct radv_device *device)
250 {
251 struct radv_meta_state *state = &device->meta_state;
252 VkResult res;
253
254 res = create_layout(device);
255 if (res != VK_SUCCESS)
256 return res;
257
258 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
259 uint32_t samples = 1 << i;
260
261 res = create_resolve_pipeline(device, samples, false, false,
262 &state->resolve_compute.rc[i].pipeline);
263
264 res = create_resolve_pipeline(device, samples, true, false,
265 &state->resolve_compute.rc[i].i_pipeline);
266
267 res = create_resolve_pipeline(device, samples, false, true,
268 &state->resolve_compute.rc[i].srgb_pipeline);
269
270 }
271
272 return res;
273 }
274
275 void
276 radv_device_finish_meta_resolve_compute_state(struct radv_device *device)
277 {
278 struct radv_meta_state *state = &device->meta_state;
279 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
280 radv_DestroyPipeline(radv_device_to_handle(device),
281 state->resolve_compute.rc[i].pipeline,
282 &state->alloc);
283
284 radv_DestroyPipeline(radv_device_to_handle(device),
285 state->resolve_compute.rc[i].i_pipeline,
286 &state->alloc);
287
288 radv_DestroyPipeline(radv_device_to_handle(device),
289 state->resolve_compute.rc[i].srgb_pipeline,
290 &state->alloc);
291 }
292
293 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
294 state->resolve_compute.ds_layout,
295 &state->alloc);
296 radv_DestroyPipelineLayout(radv_device_to_handle(device),
297 state->resolve_compute.p_layout,
298 &state->alloc);
299 }
300
301 static void
302 emit_resolve(struct radv_cmd_buffer *cmd_buffer,
303 struct radv_image_view *src_iview,
304 struct radv_image_view *dest_iview,
305 const VkOffset2D *src_offset,
306 const VkOffset2D *dest_offset,
307 const VkExtent2D *resolve_extent)
308 {
309 struct radv_device *device = cmd_buffer->device;
310 const uint32_t samples = src_iview->image->info.samples;
311 const uint32_t samples_log2 = ffs(samples) - 1;
312 radv_meta_push_descriptor_set(cmd_buffer,
313 VK_PIPELINE_BIND_POINT_COMPUTE,
314 device->meta_state.resolve_compute.p_layout,
315 0, /* set */
316 2, /* descriptorWriteCount */
317 (VkWriteDescriptorSet[]) {
318 {
319 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
320 .dstBinding = 0,
321 .dstArrayElement = 0,
322 .descriptorCount = 1,
323 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
324 .pImageInfo = (VkDescriptorImageInfo[]) {
325 {
326 .sampler = VK_NULL_HANDLE,
327 .imageView = radv_image_view_to_handle(src_iview),
328 .imageLayout = VK_IMAGE_LAYOUT_GENERAL },
329 }
330 },
331 {
332 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
333 .dstBinding = 1,
334 .dstArrayElement = 0,
335 .descriptorCount = 1,
336 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
337 .pImageInfo = (VkDescriptorImageInfo[]) {
338 {
339 .sampler = VK_NULL_HANDLE,
340 .imageView = radv_image_view_to_handle(dest_iview),
341 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
342 },
343 }
344 }
345 });
346
347 VkPipeline pipeline;
348 if (vk_format_is_int(src_iview->image->vk_format))
349 pipeline = device->meta_state.resolve_compute.rc[samples_log2].i_pipeline;
350 else if (vk_format_is_srgb(src_iview->image->vk_format))
351 pipeline = device->meta_state.resolve_compute.rc[samples_log2].srgb_pipeline;
352 else
353 pipeline = device->meta_state.resolve_compute.rc[samples_log2].pipeline;
354
355 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
356 VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
357
358 unsigned push_constants[4] = {
359 src_offset->x,
360 src_offset->y,
361 dest_offset->x,
362 dest_offset->y,
363 };
364 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
365 device->meta_state.resolve_compute.p_layout,
366 VK_SHADER_STAGE_COMPUTE_BIT, 0, 16,
367 push_constants);
368 radv_unaligned_dispatch(cmd_buffer, resolve_extent->width, resolve_extent->height, 1);
369
370 }
371
372 void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer,
373 struct radv_image *src_image,
374 VkImageLayout src_image_layout,
375 struct radv_image *dest_image,
376 VkImageLayout dest_image_layout,
377 uint32_t region_count,
378 const VkImageResolve *regions)
379 {
380 struct radv_meta_saved_state saved_state;
381
382 for (uint32_t r = 0; r < region_count; ++r) {
383 const VkImageResolve *region = &regions[r];
384 const uint32_t src_base_layer =
385 radv_meta_get_iview_layer(src_image, &region->srcSubresource,
386 &region->srcOffset);
387 VkImageSubresourceRange range;
388 range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
389 range.baseMipLevel = region->srcSubresource.mipLevel;
390 range.levelCount = 1;
391 range.baseArrayLayer = src_base_layer;
392 range.layerCount = region->srcSubresource.layerCount;
393 radv_fast_clear_flush_image_inplace(cmd_buffer, src_image, &range);
394 }
395
396 radv_meta_save(&saved_state, cmd_buffer,
397 RADV_META_SAVE_COMPUTE_PIPELINE |
398 RADV_META_SAVE_CONSTANTS |
399 RADV_META_SAVE_DESCRIPTORS);
400
401 for (uint32_t r = 0; r < region_count; ++r) {
402 const VkImageResolve *region = &regions[r];
403
404 assert(region->srcSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
405 assert(region->dstSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
406 assert(region->srcSubresource.layerCount == region->dstSubresource.layerCount);
407
408 const uint32_t src_base_layer =
409 radv_meta_get_iview_layer(src_image, &region->srcSubresource,
410 &region->srcOffset);
411
412 const uint32_t dest_base_layer =
413 radv_meta_get_iview_layer(dest_image, &region->dstSubresource,
414 &region->dstOffset);
415
416 const struct VkExtent3D extent =
417 radv_sanitize_image_extent(src_image->type, region->extent);
418 const struct VkOffset3D srcOffset =
419 radv_sanitize_image_offset(src_image->type, region->srcOffset);
420 const struct VkOffset3D dstOffset =
421 radv_sanitize_image_offset(dest_image->type, region->dstOffset);
422
423 for (uint32_t layer = 0; layer < region->srcSubresource.layerCount;
424 ++layer) {
425
426 struct radv_image_view src_iview;
427 radv_image_view_init(&src_iview, cmd_buffer->device,
428 &(VkImageViewCreateInfo) {
429 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
430 .image = radv_image_to_handle(src_image),
431 .viewType = radv_meta_get_view_type(src_image),
432 .format = src_image->vk_format,
433 .subresourceRange = {
434 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
435 .baseMipLevel = region->srcSubresource.mipLevel,
436 .levelCount = 1,
437 .baseArrayLayer = src_base_layer + layer,
438 .layerCount = 1,
439 },
440 });
441
442 struct radv_image_view dest_iview;
443 radv_image_view_init(&dest_iview, cmd_buffer->device,
444 &(VkImageViewCreateInfo) {
445 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
446 .image = radv_image_to_handle(dest_image),
447 .viewType = radv_meta_get_view_type(dest_image),
448 .format = vk_to_non_srgb_format(dest_image->vk_format),
449 .subresourceRange = {
450 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
451 .baseMipLevel = region->dstSubresource.mipLevel,
452 .levelCount = 1,
453 .baseArrayLayer = dest_base_layer + layer,
454 .layerCount = 1,
455 },
456 });
457
458 emit_resolve(cmd_buffer,
459 &src_iview,
460 &dest_iview,
461 &(VkOffset2D) {srcOffset.x, srcOffset.y },
462 &(VkOffset2D) {dstOffset.x, dstOffset.y },
463 &(VkExtent2D) {extent.width, extent.height });
464 }
465 }
466 radv_meta_restore(&saved_state, cmd_buffer);
467 }
468
469 /**
470 * Emit any needed resolves for the current subpass.
471 */
472 void
473 radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer)
474 {
475 struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
476 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
477 struct radv_meta_saved_state saved_state;
478 /* FINISHME(perf): Skip clears for resolve attachments.
479 *
480 * From the Vulkan 1.0 spec:
481 *
482 * If the first use of an attachment in a render pass is as a resolve
483 * attachment, then the loadOp is effectively ignored as the resolve is
484 * guaranteed to overwrite all pixels in the render area.
485 */
486
487 if (!subpass->has_resolve)
488 return;
489
490 for (uint32_t i = 0; i < subpass->color_count; ++i) {
491 VkAttachmentReference src_att = subpass->color_attachments[i];
492 VkAttachmentReference dest_att = subpass->resolve_attachments[i];
493
494 if (src_att.attachment == VK_ATTACHMENT_UNUSED ||
495 dest_att.attachment == VK_ATTACHMENT_UNUSED)
496 continue;
497
498 struct radv_image *dst_img = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment->image;
499 struct radv_image_view *src_iview = cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
500
501 if (dst_img->surface.dcc_size) {
502 radv_initialize_dcc(cmd_buffer, dst_img, 0xffffffff);
503 cmd_buffer->state.attachments[dest_att.attachment].current_layout = VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
504 }
505
506 VkImageSubresourceRange range;
507 range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
508 range.baseMipLevel = 0;
509 range.levelCount = 1;
510 range.baseArrayLayer = 0;
511 range.layerCount = 1;
512 radv_fast_clear_flush_image_inplace(cmd_buffer, src_iview->image, &range);
513 }
514
515 radv_meta_save(&saved_state, cmd_buffer,
516 RADV_META_SAVE_COMPUTE_PIPELINE |
517 RADV_META_SAVE_CONSTANTS |
518 RADV_META_SAVE_DESCRIPTORS);
519
520 for (uint32_t i = 0; i < subpass->color_count; ++i) {
521 VkAttachmentReference src_att = subpass->color_attachments[i];
522 VkAttachmentReference dest_att = subpass->resolve_attachments[i];
523 struct radv_image_view *src_iview = cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
524 struct radv_image_view *dst_iview = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment;
525 if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
526 continue;
527
528 emit_resolve(cmd_buffer,
529 src_iview,
530 dst_iview,
531 &(VkOffset2D) { 0, 0 },
532 &(VkOffset2D) { 0, 0 },
533 &(VkExtent2D) { fb->width, fb->height });
534 }
535
536 radv_meta_restore(&saved_state, cmd_buffer);
537
538 for (uint32_t i = 0; i < subpass->color_count; ++i) {
539 VkAttachmentReference dest_att = subpass->resolve_attachments[i];
540 struct radv_image *dst_img = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment->image;
541 if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
542 continue;
543 VkImageSubresourceRange range;
544 range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
545 range.baseMipLevel = 0;
546 range.levelCount = 1;
547 range.baseArrayLayer = 0;
548 range.layerCount = 1;
549 radv_fast_clear_flush_image_inplace(cmd_buffer, dst_img, &range);
550 }
551 }