2 * Copyright © 2016 Dave Airlie
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_meta.h"
29 #include "radv_private.h"
30 #include "nir/nir_builder.h"
32 #include "vk_format.h"
35 build_nir_vertex_shader(void)
37 const struct glsl_type
*vec4
= glsl_vec4_type();
40 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
41 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "meta_resolve_vs");
43 nir_variable
*pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
45 pos_out
->data
.location
= VARYING_SLOT_POS
;
47 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices(&b
);
49 nir_store_var(&b
, pos_out
, outvec
, 0xf);
54 build_resolve_fragment_shader(struct radv_device
*dev
, bool is_integer
, int samples
)
58 const struct glsl_type
*vec4
= glsl_vec4_type();
59 const struct glsl_type
*sampler_type
= glsl_sampler_type(GLSL_SAMPLER_DIM_MS
,
64 snprintf(name
, 64, "meta_resolve_fs-%d-%s", samples
, is_integer
? "int" : "float");
65 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
66 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, name
);
68 nir_variable
*input_img
= nir_variable_create(b
.shader
, nir_var_uniform
,
69 sampler_type
, "s_tex");
70 input_img
->data
.descriptor_set
= 0;
71 input_img
->data
.binding
= 0;
73 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
75 color_out
->data
.location
= FRAG_RESULT_DATA0
;
77 nir_ssa_def
*pos_in
= nir_channels(&b
, nir_load_frag_coord(&b
), 0x3);
78 nir_intrinsic_instr
*src_offset
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
79 nir_intrinsic_set_base(src_offset
, 0);
80 nir_intrinsic_set_range(src_offset
, 8);
81 src_offset
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
82 src_offset
->num_components
= 2;
83 nir_ssa_dest_init(&src_offset
->instr
, &src_offset
->dest
, 2, 32, "src_offset");
84 nir_builder_instr_insert(&b
, &src_offset
->instr
);
86 nir_ssa_def
*pos_int
= nir_f2i32(&b
, pos_in
);
88 nir_ssa_def
*img_coord
= nir_channels(&b
, nir_iadd(&b
, pos_int
, &src_offset
->dest
.ssa
), 0x3);
89 nir_variable
*color
= nir_local_variable_create(b
.impl
, glsl_vec4_type(), "color");
91 radv_meta_build_resolve_shader_core(&b
, is_integer
, samples
, input_img
,
94 nir_ssa_def
*outval
= nir_load_var(&b
, color
);
95 nir_store_var(&b
, color_out
, outval
, 0xf);
101 create_layout(struct radv_device
*device
)
105 * one descriptors for the image being sampled
107 VkDescriptorSetLayoutCreateInfo ds_create_info
= {
108 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
109 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
111 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
114 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
115 .descriptorCount
= 1,
116 .stageFlags
= VK_SHADER_STAGE_FRAGMENT_BIT
,
117 .pImmutableSamplers
= NULL
122 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
124 &device
->meta_state
.alloc
,
125 &device
->meta_state
.resolve_fragment
.ds_layout
);
126 if (result
!= VK_SUCCESS
)
130 VkPipelineLayoutCreateInfo pl_create_info
= {
131 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
133 .pSetLayouts
= &device
->meta_state
.resolve_fragment
.ds_layout
,
134 .pushConstantRangeCount
= 1,
135 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 8},
138 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
140 &device
->meta_state
.alloc
,
141 &device
->meta_state
.resolve_fragment
.p_layout
);
142 if (result
!= VK_SUCCESS
)
149 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info
= {
150 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
151 .vertexBindingDescriptionCount
= 0,
152 .vertexAttributeDescriptionCount
= 0,
156 create_resolve_pipeline(struct radv_device
*device
,
160 mtx_lock(&device
->meta_state
.mtx
);
162 unsigned fs_key
= radv_format_meta_fs_key(format
);
163 VkPipeline
*pipeline
= &device
->meta_state
.resolve_fragment
.rc
[samples_log2
].pipeline
[fs_key
];
165 mtx_unlock(&device
->meta_state
.mtx
);
170 bool is_integer
= false;
171 uint32_t samples
= 1 << samples_log2
;
172 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
173 vi_create_info
= &normal_vi_create_info
;
174 if (vk_format_is_int(format
))
177 struct radv_shader_module fs
= { .nir
= NULL
};
178 fs
.nir
= build_resolve_fragment_shader(device
, is_integer
, samples
);
179 struct radv_shader_module vs
= {
180 .nir
= build_nir_vertex_shader(),
183 VkRenderPass
*rp
= &device
->meta_state
.resolve_fragment
.rc
[samples_log2
].render_pass
[fs_key
][0];
187 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
189 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
190 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
191 .module
= radv_shader_module_to_handle(&vs
),
193 .pSpecializationInfo
= NULL
195 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
196 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
197 .module
= radv_shader_module_to_handle(&fs
),
199 .pSpecializationInfo
= NULL
204 for (unsigned dst_layout
= 0; dst_layout
< RADV_META_DST_LAYOUT_COUNT
; ++dst_layout
) {
205 VkImageLayout layout
= radv_meta_dst_layout_to_layout(dst_layout
);
206 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
207 &(VkRenderPassCreateInfo
) {
208 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
209 .attachmentCount
= 1,
210 .pAttachments
= &(VkAttachmentDescription
) {
212 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
213 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
214 .initialLayout
= layout
,
215 .finalLayout
= layout
,
218 .pSubpasses
= &(VkSubpassDescription
) {
219 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
220 .inputAttachmentCount
= 0,
221 .colorAttachmentCount
= 1,
222 .pColorAttachments
= &(VkAttachmentReference
) {
226 .pResolveAttachments
= NULL
,
227 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
228 .attachment
= VK_ATTACHMENT_UNUSED
,
229 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
231 .preserveAttachmentCount
= 0,
232 .pPreserveAttachments
= NULL
,
234 .dependencyCount
= 2,
235 .pDependencies
= (VkSubpassDependency
[]) {
237 .srcSubpass
= VK_SUBPASS_EXTERNAL
,
239 .srcStageMask
= VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
,
240 .dstStageMask
= VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
,
247 .dstSubpass
= VK_SUBPASS_EXTERNAL
,
248 .srcStageMask
= VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
,
249 .dstStageMask
= VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
,
255 }, &device
->meta_state
.alloc
, rp
+ dst_layout
);
259 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
260 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
261 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
262 .pStages
= pipeline_shader_stages
,
263 .pVertexInputState
= vi_create_info
,
264 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
265 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
266 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
267 .primitiveRestartEnable
= false,
269 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
270 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
274 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
275 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
276 .rasterizerDiscardEnable
= false,
277 .polygonMode
= VK_POLYGON_MODE_FILL
,
278 .cullMode
= VK_CULL_MODE_NONE
,
279 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
281 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
282 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
283 .rasterizationSamples
= 1,
284 .sampleShadingEnable
= false,
285 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
287 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
288 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
289 .attachmentCount
= 1,
290 .pAttachments
= (VkPipelineColorBlendAttachmentState
[]) {
292 VK_COLOR_COMPONENT_A_BIT
|
293 VK_COLOR_COMPONENT_R_BIT
|
294 VK_COLOR_COMPONENT_G_BIT
|
295 VK_COLOR_COMPONENT_B_BIT
},
298 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
299 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
300 .dynamicStateCount
= 9,
301 .pDynamicStates
= (VkDynamicState
[]) {
302 VK_DYNAMIC_STATE_VIEWPORT
,
303 VK_DYNAMIC_STATE_SCISSOR
,
304 VK_DYNAMIC_STATE_LINE_WIDTH
,
305 VK_DYNAMIC_STATE_DEPTH_BIAS
,
306 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
307 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
308 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
309 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
310 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
314 .layout
= device
->meta_state
.resolve_fragment
.p_layout
,
319 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
323 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
324 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
325 &vk_pipeline_info
, &radv_pipeline_info
,
326 &device
->meta_state
.alloc
,
331 mtx_unlock(&device
->meta_state
.mtx
);
341 get_resolve_mode_str(VkResolveModeFlagBits resolve_mode
)
343 switch (resolve_mode
) {
344 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
346 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
348 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
350 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
353 unreachable("invalid resolve mode");
358 build_depth_stencil_resolve_fragment_shader(struct radv_device
*dev
, int samples
,
360 VkResolveModeFlagBits resolve_mode
)
364 const struct glsl_type
*vec4
= glsl_vec4_type();
365 const struct glsl_type
*sampler_type
= glsl_sampler_type(GLSL_SAMPLER_DIM_2D
,
370 snprintf(name
, 64, "meta_resolve_fs_%s-%s-%d",
371 index
== DEPTH_RESOLVE
? "depth" : "stencil",
372 get_resolve_mode_str(resolve_mode
), samples
);
374 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
375 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, name
);
377 nir_variable
*input_img
= nir_variable_create(b
.shader
, nir_var_uniform
,
378 sampler_type
, "s_tex");
379 input_img
->data
.descriptor_set
= 0;
380 input_img
->data
.binding
= 0;
382 nir_variable
*fs_out
= nir_variable_create(b
.shader
,
383 nir_var_shader_out
, vec4
,
385 fs_out
->data
.location
=
386 index
== DEPTH_RESOLVE
? FRAG_RESULT_DEPTH
: FRAG_RESULT_STENCIL
;
388 nir_ssa_def
*pos_in
= nir_channels(&b
, nir_load_frag_coord(&b
), 0x3);
390 nir_intrinsic_instr
*src_offset
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
391 nir_intrinsic_set_base(src_offset
, 0);
392 nir_intrinsic_set_range(src_offset
, 8);
393 src_offset
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
394 src_offset
->num_components
= 2;
395 nir_ssa_dest_init(&src_offset
->instr
, &src_offset
->dest
, 2, 32, "src_offset");
396 nir_builder_instr_insert(&b
, &src_offset
->instr
);
398 nir_ssa_def
*pos_int
= nir_f2i32(&b
, pos_in
);
400 nir_ssa_def
*img_coord
= nir_channels(&b
, nir_iadd(&b
, pos_int
, &src_offset
->dest
.ssa
), 0x3);
402 nir_ssa_def
*input_img_deref
= &nir_build_deref_var(&b
, input_img
)->dest
.ssa
;
404 nir_alu_type type
= index
== DEPTH_RESOLVE
? nir_type_float
: nir_type_uint
;
406 nir_tex_instr
*tex
= nir_tex_instr_create(b
.shader
, 3);
407 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
408 tex
->op
= nir_texop_txf_ms
;
409 tex
->src
[0].src_type
= nir_tex_src_coord
;
410 tex
->src
[0].src
= nir_src_for_ssa(img_coord
);
411 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
412 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(&b
, 0));
413 tex
->src
[2].src_type
= nir_tex_src_texture_deref
;
414 tex
->src
[2].src
= nir_src_for_ssa(input_img_deref
);
415 tex
->dest_type
= type
;
416 tex
->is_array
= false;
417 tex
->coord_components
= 2;
419 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
420 nir_builder_instr_insert(&b
, &tex
->instr
);
422 nir_ssa_def
*outval
= &tex
->dest
.ssa
;
424 if (resolve_mode
!= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
) {
425 for (int i
= 1; i
< samples
; i
++) {
426 nir_tex_instr
*tex_add
= nir_tex_instr_create(b
.shader
, 3);
427 tex_add
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
428 tex_add
->op
= nir_texop_txf_ms
;
429 tex_add
->src
[0].src_type
= nir_tex_src_coord
;
430 tex_add
->src
[0].src
= nir_src_for_ssa(img_coord
);
431 tex_add
->src
[1].src_type
= nir_tex_src_ms_index
;
432 tex_add
->src
[1].src
= nir_src_for_ssa(nir_imm_int(&b
, i
));
433 tex_add
->src
[2].src_type
= nir_tex_src_texture_deref
;
434 tex_add
->src
[2].src
= nir_src_for_ssa(input_img_deref
);
435 tex_add
->dest_type
= type
;
436 tex_add
->is_array
= false;
437 tex_add
->coord_components
= 2;
439 nir_ssa_dest_init(&tex_add
->instr
, &tex_add
->dest
, 4, 32, "tex");
440 nir_builder_instr_insert(&b
, &tex_add
->instr
);
442 switch (resolve_mode
) {
443 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
444 assert(index
== DEPTH_RESOLVE
);
445 outval
= nir_fadd(&b
, outval
, &tex_add
->dest
.ssa
);
447 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
448 if (index
== DEPTH_RESOLVE
)
449 outval
= nir_fmin(&b
, outval
, &tex_add
->dest
.ssa
);
451 outval
= nir_umin(&b
, outval
, &tex_add
->dest
.ssa
);
453 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
454 if (index
== DEPTH_RESOLVE
)
455 outval
= nir_fmax(&b
, outval
, &tex_add
->dest
.ssa
);
457 outval
= nir_umax(&b
, outval
, &tex_add
->dest
.ssa
);
460 unreachable("invalid resolve mode");
464 if (resolve_mode
== VK_RESOLVE_MODE_AVERAGE_BIT_KHR
)
465 outval
= nir_fdiv(&b
, outval
, nir_imm_float(&b
, samples
));
468 nir_store_var(&b
, fs_out
, outval
, 0x1);
474 create_depth_stencil_resolve_pipeline(struct radv_device
*device
,
477 VkResolveModeFlagBits resolve_mode
)
479 VkRenderPass
*render_pass
;
480 VkPipeline
*pipeline
;
484 mtx_lock(&device
->meta_state
.mtx
);
486 switch (resolve_mode
) {
487 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
488 if (index
== DEPTH_RESOLVE
)
489 pipeline
= &device
->meta_state
.resolve_fragment
.depth_zero_pipeline
;
491 pipeline
= &device
->meta_state
.resolve_fragment
.stencil_zero_pipeline
;
493 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
494 assert(index
== DEPTH_RESOLVE
);
495 pipeline
= &device
->meta_state
.resolve_fragment
.depth
[samples_log2
].average_pipeline
;
497 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
498 if (index
== DEPTH_RESOLVE
)
499 pipeline
= &device
->meta_state
.resolve_fragment
.depth
[samples_log2
].min_pipeline
;
501 pipeline
= &device
->meta_state
.resolve_fragment
.stencil
[samples_log2
].min_pipeline
;
503 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
504 if (index
== DEPTH_RESOLVE
)
505 pipeline
= &device
->meta_state
.resolve_fragment
.depth
[samples_log2
].max_pipeline
;
507 pipeline
= &device
->meta_state
.resolve_fragment
.stencil
[samples_log2
].max_pipeline
;
510 unreachable("invalid resolve mode");
514 mtx_unlock(&device
->meta_state
.mtx
);
518 struct radv_shader_module fs
= { .nir
= NULL
};
519 struct radv_shader_module vs
= { .nir
= NULL
};
520 uint32_t samples
= 1 << samples_log2
;
522 vs
.nir
= build_nir_vertex_shader();
523 fs
.nir
= build_depth_stencil_resolve_fragment_shader(device
, samples
,
524 index
, resolve_mode
);
526 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
528 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
529 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
530 .module
= radv_shader_module_to_handle(&vs
),
532 .pSpecializationInfo
= NULL
534 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
535 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
536 .module
= radv_shader_module_to_handle(&fs
),
538 .pSpecializationInfo
= NULL
542 if (index
== DEPTH_RESOLVE
) {
543 src_format
= VK_FORMAT_D32_SFLOAT
;
544 render_pass
= &device
->meta_state
.resolve_fragment
.depth_render_pass
;
546 render_pass
= &device
->meta_state
.resolve_fragment
.stencil_render_pass
;
547 src_format
= VK_FORMAT_S8_UINT
;
551 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
552 &(VkRenderPassCreateInfo
) {
553 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
554 .attachmentCount
= 1,
555 .pAttachments
= &(VkAttachmentDescription
) {
556 .format
= src_format
,
557 .loadOp
= VK_ATTACHMENT_LOAD_OP_DONT_CARE
,
558 .storeOp
= VK_ATTACHMENT_STORE_OP_DONT_CARE
,
559 .stencilLoadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
560 .stencilStoreOp
= VK_ATTACHMENT_STORE_OP_STORE
,
561 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
562 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
565 .pSubpasses
= &(VkSubpassDescription
) {
566 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
567 .inputAttachmentCount
= 0,
568 .colorAttachmentCount
= 0,
569 .pColorAttachments
= NULL
,
570 .pResolveAttachments
= NULL
,
571 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
573 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
575 .preserveAttachmentCount
= 0,
576 .pPreserveAttachments
= NULL
,
578 .dependencyCount
= 2,
579 .pDependencies
= (VkSubpassDependency
[]) {
581 .srcSubpass
= VK_SUBPASS_EXTERNAL
,
583 .srcStageMask
= VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
,
584 .dstStageMask
= VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
,
591 .dstSubpass
= VK_SUBPASS_EXTERNAL
,
592 .srcStageMask
= VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
,
593 .dstStageMask
= VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
,
599 }, &device
->meta_state
.alloc
, render_pass
);
602 VkStencilOp stencil_op
=
603 index
== DEPTH_RESOLVE
? VK_STENCIL_OP_KEEP
: VK_STENCIL_OP_REPLACE
;
605 VkPipelineDepthStencilStateCreateInfo depth_stencil_state
= {
606 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
607 .depthTestEnable
= true,
608 .depthWriteEnable
= index
== DEPTH_RESOLVE
,
609 .stencilTestEnable
= index
== STENCIL_RESOLVE
,
610 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
612 .failOp
= stencil_op
,
613 .passOp
= stencil_op
,
614 .depthFailOp
= stencil_op
,
615 .compareOp
= VK_COMPARE_OP_ALWAYS
,
618 .failOp
= stencil_op
,
619 .passOp
= stencil_op
,
620 .depthFailOp
= stencil_op
,
621 .compareOp
= VK_COMPARE_OP_ALWAYS
,
625 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
626 vi_create_info
= &normal_vi_create_info
;
628 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
629 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
630 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
631 .pStages
= pipeline_shader_stages
,
632 .pVertexInputState
= vi_create_info
,
633 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
634 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
635 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
636 .primitiveRestartEnable
= false,
638 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
639 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
643 .pDepthStencilState
= &depth_stencil_state
,
644 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
645 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
646 .rasterizerDiscardEnable
= false,
647 .polygonMode
= VK_POLYGON_MODE_FILL
,
648 .cullMode
= VK_CULL_MODE_NONE
,
649 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
651 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
652 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
653 .rasterizationSamples
= 1,
654 .sampleShadingEnable
= false,
655 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
657 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
658 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
659 .attachmentCount
= 0,
660 .pAttachments
= (VkPipelineColorBlendAttachmentState
[]) {
662 VK_COLOR_COMPONENT_A_BIT
|
663 VK_COLOR_COMPONENT_R_BIT
|
664 VK_COLOR_COMPONENT_G_BIT
|
665 VK_COLOR_COMPONENT_B_BIT
},
668 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
669 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
670 .dynamicStateCount
= 9,
671 .pDynamicStates
= (VkDynamicState
[]) {
672 VK_DYNAMIC_STATE_VIEWPORT
,
673 VK_DYNAMIC_STATE_SCISSOR
,
674 VK_DYNAMIC_STATE_LINE_WIDTH
,
675 VK_DYNAMIC_STATE_DEPTH_BIAS
,
676 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
677 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
678 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
679 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
680 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
684 .layout
= device
->meta_state
.resolve_fragment
.p_layout
,
685 .renderPass
= *render_pass
,
689 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
693 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
694 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
695 &vk_pipeline_info
, &radv_pipeline_info
,
696 &device
->meta_state
.alloc
,
702 mtx_unlock(&device
->meta_state
.mtx
);
707 radv_device_init_meta_resolve_fragment_state(struct radv_device
*device
, bool on_demand
)
711 res
= create_layout(device
);
712 if (res
!= VK_SUCCESS
)
718 for (uint32_t i
= 0; i
< MAX_SAMPLES_LOG2
; ++i
) {
719 for (unsigned j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
720 res
= create_resolve_pipeline(device
, i
, radv_fs_key_format_exemplars
[j
]);
721 if (res
!= VK_SUCCESS
)
725 res
= create_depth_stencil_resolve_pipeline(device
, i
, DEPTH_RESOLVE
,
726 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
);
727 if (res
!= VK_SUCCESS
)
730 res
= create_depth_stencil_resolve_pipeline(device
, i
, DEPTH_RESOLVE
,
731 VK_RESOLVE_MODE_MIN_BIT_KHR
);
732 if (res
!= VK_SUCCESS
)
735 res
= create_depth_stencil_resolve_pipeline(device
, i
, DEPTH_RESOLVE
,
736 VK_RESOLVE_MODE_MAX_BIT_KHR
);
737 if (res
!= VK_SUCCESS
)
740 res
= create_depth_stencil_resolve_pipeline(device
, i
, STENCIL_RESOLVE
,
741 VK_RESOLVE_MODE_MIN_BIT_KHR
);
742 if (res
!= VK_SUCCESS
)
745 res
= create_depth_stencil_resolve_pipeline(device
, i
, STENCIL_RESOLVE
,
746 VK_RESOLVE_MODE_MAX_BIT_KHR
);
747 if (res
!= VK_SUCCESS
)
751 res
= create_depth_stencil_resolve_pipeline(device
, 0, DEPTH_RESOLVE
,
752 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
);
753 if (res
!= VK_SUCCESS
)
756 res
= create_depth_stencil_resolve_pipeline(device
, 0, STENCIL_RESOLVE
,
757 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
);
758 if (res
!= VK_SUCCESS
)
763 radv_device_finish_meta_resolve_fragment_state(device
);
768 radv_device_finish_meta_resolve_fragment_state(struct radv_device
*device
)
770 struct radv_meta_state
*state
= &device
->meta_state
;
771 for (uint32_t i
= 0; i
< MAX_SAMPLES_LOG2
; ++i
) {
772 for (unsigned j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
773 for(unsigned k
=0; k
< RADV_META_DST_LAYOUT_COUNT
; ++k
) {
774 radv_DestroyRenderPass(radv_device_to_handle(device
),
775 state
->resolve_fragment
.rc
[i
].render_pass
[j
][k
],
778 radv_DestroyPipeline(radv_device_to_handle(device
),
779 state
->resolve_fragment
.rc
[i
].pipeline
[j
],
783 radv_DestroyPipeline(radv_device_to_handle(device
),
784 state
->resolve_fragment
.depth
[i
].average_pipeline
,
787 radv_DestroyPipeline(radv_device_to_handle(device
),
788 state
->resolve_fragment
.depth
[i
].max_pipeline
,
791 radv_DestroyPipeline(radv_device_to_handle(device
),
792 state
->resolve_fragment
.depth
[i
].min_pipeline
,
795 radv_DestroyPipeline(radv_device_to_handle(device
),
796 state
->resolve_fragment
.stencil
[i
].max_pipeline
,
799 radv_DestroyPipeline(radv_device_to_handle(device
),
800 state
->resolve_fragment
.stencil
[i
].min_pipeline
,
804 radv_DestroyRenderPass(radv_device_to_handle(device
),
805 state
->resolve_fragment
.depth_render_pass
,
807 radv_DestroyRenderPass(radv_device_to_handle(device
),
808 state
->resolve_fragment
.stencil_render_pass
,
811 radv_DestroyPipeline(radv_device_to_handle(device
),
812 state
->resolve_fragment
.depth_zero_pipeline
,
814 radv_DestroyPipeline(radv_device_to_handle(device
),
815 state
->resolve_fragment
.stencil_zero_pipeline
,
818 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
819 state
->resolve_fragment
.ds_layout
,
821 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
822 state
->resolve_fragment
.p_layout
,
827 radv_get_resolve_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
828 struct radv_image_view
*src_iview
,
829 struct radv_image_view
*dst_iview
)
831 struct radv_device
*device
= cmd_buffer
->device
;
832 unsigned fs_key
= radv_format_meta_fs_key(dst_iview
->vk_format
);
833 const uint32_t samples
= src_iview
->image
->info
.samples
;
834 const uint32_t samples_log2
= ffs(samples
) - 1;
835 VkPipeline
*pipeline
;
837 pipeline
= &device
->meta_state
.resolve_fragment
.rc
[samples_log2
].pipeline
[fs_key
];
841 ret
= create_resolve_pipeline(device
, samples_log2
,
842 radv_fs_key_format_exemplars
[fs_key
]);
843 if (ret
!= VK_SUCCESS
) {
844 cmd_buffer
->record_result
= ret
;
853 emit_resolve(struct radv_cmd_buffer
*cmd_buffer
,
854 struct radv_image_view
*src_iview
,
855 struct radv_image_view
*dest_iview
,
856 const VkOffset2D
*src_offset
,
857 const VkOffset2D
*dest_offset
,
858 const VkExtent2D
*resolve_extent
)
860 struct radv_device
*device
= cmd_buffer
->device
;
861 VkCommandBuffer cmd_buffer_h
= radv_cmd_buffer_to_handle(cmd_buffer
);
862 VkPipeline
*pipeline
;
864 radv_meta_push_descriptor_set(cmd_buffer
,
865 VK_PIPELINE_BIND_POINT_GRAPHICS
,
866 cmd_buffer
->device
->meta_state
.resolve_fragment
.p_layout
,
868 1, /* descriptorWriteCount */
869 (VkWriteDescriptorSet
[]) {
871 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
873 .dstArrayElement
= 0,
874 .descriptorCount
= 1,
875 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
876 .pImageInfo
= (VkDescriptorImageInfo
[]) {
878 .sampler
= VK_NULL_HANDLE
,
879 .imageView
= radv_image_view_to_handle(src_iview
),
880 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
886 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
888 unsigned push_constants
[2] = {
889 src_offset
->x
- dest_offset
->x
,
890 src_offset
->y
- dest_offset
->y
,
892 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
893 device
->meta_state
.resolve_fragment
.p_layout
,
894 VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 8,
897 pipeline
= radv_get_resolve_pipeline(cmd_buffer
, src_iview
, dest_iview
);
899 radv_CmdBindPipeline(cmd_buffer_h
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
902 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
905 .width
= resolve_extent
->width
,
906 .height
= resolve_extent
->height
,
911 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkRect2D
) {
912 .offset
= *dest_offset
,
913 .extent
= *resolve_extent
,
916 radv_CmdDraw(cmd_buffer_h
, 3, 1, 0, 0);
917 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
921 emit_depth_stencil_resolve(struct radv_cmd_buffer
*cmd_buffer
,
922 struct radv_image_view
*src_iview
,
923 struct radv_image_view
*dst_iview
,
924 const VkOffset2D
*src_offset
,
925 const VkOffset2D
*dst_offset
,
926 const VkExtent2D
*resolve_extent
,
927 VkImageAspectFlags aspects
,
928 VkResolveModeFlagBits resolve_mode
)
930 struct radv_device
*device
= cmd_buffer
->device
;
931 const uint32_t samples
= src_iview
->image
->info
.samples
;
932 const uint32_t samples_log2
= ffs(samples
) - 1;
933 VkPipeline
*pipeline
;
935 radv_meta_push_descriptor_set(cmd_buffer
,
936 VK_PIPELINE_BIND_POINT_GRAPHICS
,
937 cmd_buffer
->device
->meta_state
.resolve_fragment
.p_layout
,
939 1, /* descriptorWriteCount */
940 (VkWriteDescriptorSet
[]) {
942 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
944 .dstArrayElement
= 0,
945 .descriptorCount
= 1,
946 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
947 .pImageInfo
= (VkDescriptorImageInfo
[]) {
949 .sampler
= VK_NULL_HANDLE
,
950 .imageView
= radv_image_view_to_handle(src_iview
),
951 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
957 unsigned push_constants
[2] = {
958 src_offset
->x
- dst_offset
->x
,
959 src_offset
->y
- dst_offset
->y
,
961 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
962 device
->meta_state
.resolve_fragment
.p_layout
,
963 VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 8,
966 switch (resolve_mode
) {
967 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
968 if (aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
)
969 pipeline
= &device
->meta_state
.resolve_fragment
.depth_zero_pipeline
;
971 pipeline
= &device
->meta_state
.resolve_fragment
.stencil_zero_pipeline
;
973 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
974 assert(aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
);
975 pipeline
= &device
->meta_state
.resolve_fragment
.depth
[samples_log2
].average_pipeline
;
977 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
978 if (aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
)
979 pipeline
= &device
->meta_state
.resolve_fragment
.depth
[samples_log2
].min_pipeline
;
981 pipeline
= &device
->meta_state
.resolve_fragment
.stencil
[samples_log2
].min_pipeline
;
983 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
984 if (aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
)
985 pipeline
= &device
->meta_state
.resolve_fragment
.depth
[samples_log2
].max_pipeline
;
987 pipeline
= &device
->meta_state
.resolve_fragment
.stencil
[samples_log2
].max_pipeline
;
990 unreachable("invalid resolve mode");
994 int index
= aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
? DEPTH_RESOLVE
: STENCIL_RESOLVE
;
997 ret
= create_depth_stencil_resolve_pipeline(device
, samples_log2
,
998 index
, resolve_mode
);
999 if (ret
!= VK_SUCCESS
) {
1000 cmd_buffer
->record_result
= ret
;
1005 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
1006 VK_PIPELINE_BIND_POINT_GRAPHICS
, *pipeline
);
1008 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
1011 .width
= resolve_extent
->width
,
1012 .height
= resolve_extent
->height
,
1017 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkRect2D
) {
1018 .offset
= *dst_offset
,
1019 .extent
= *resolve_extent
,
1022 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer
), 3, 1, 0, 0);
1025 void radv_meta_resolve_fragment_image(struct radv_cmd_buffer
*cmd_buffer
,
1026 struct radv_image
*src_image
,
1027 VkImageLayout src_image_layout
,
1028 struct radv_image
*dest_image
,
1029 VkImageLayout dest_image_layout
,
1030 uint32_t region_count
,
1031 const VkImageResolve
*regions
)
1033 struct radv_device
*device
= cmd_buffer
->device
;
1034 struct radv_meta_saved_state saved_state
;
1035 const uint32_t samples
= src_image
->info
.samples
;
1036 const uint32_t samples_log2
= ffs(samples
) - 1;
1037 unsigned fs_key
= radv_format_meta_fs_key(dest_image
->vk_format
);
1038 unsigned dst_layout
= radv_meta_dst_layout_from_layout(dest_image_layout
);
1041 radv_decompress_resolve_src(cmd_buffer
, src_image
, src_image_layout
,
1042 region_count
, regions
);
1044 if (!device
->meta_state
.resolve_fragment
.rc
[samples_log2
].render_pass
[fs_key
][dst_layout
]) {
1045 VkResult ret
= create_resolve_pipeline(device
, samples_log2
, radv_fs_key_format_exemplars
[fs_key
]);
1046 if (ret
!= VK_SUCCESS
) {
1047 cmd_buffer
->record_result
= ret
;
1052 rp
= device
->meta_state
.resolve_fragment
.rc
[samples_log2
].render_pass
[fs_key
][dst_layout
];
1054 radv_meta_save(&saved_state
, cmd_buffer
,
1055 RADV_META_SAVE_GRAPHICS_PIPELINE
|
1056 RADV_META_SAVE_CONSTANTS
|
1057 RADV_META_SAVE_DESCRIPTORS
);
1059 for (uint32_t r
= 0; r
< region_count
; ++r
) {
1060 const VkImageResolve
*region
= ®ions
[r
];
1062 assert(region
->srcSubresource
.aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
);
1063 assert(region
->dstSubresource
.aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
);
1064 assert(region
->srcSubresource
.layerCount
== region
->dstSubresource
.layerCount
);
1066 const uint32_t src_base_layer
=
1067 radv_meta_get_iview_layer(src_image
, ®ion
->srcSubresource
,
1068 ®ion
->srcOffset
);
1070 const uint32_t dest_base_layer
=
1071 radv_meta_get_iview_layer(dest_image
, ®ion
->dstSubresource
,
1072 ®ion
->dstOffset
);
1074 const struct VkExtent3D extent
=
1075 radv_sanitize_image_extent(src_image
->type
, region
->extent
);
1076 const struct VkOffset3D srcOffset
=
1077 radv_sanitize_image_offset(src_image
->type
, region
->srcOffset
);
1078 const struct VkOffset3D dstOffset
=
1079 radv_sanitize_image_offset(dest_image
->type
, region
->dstOffset
);
1081 for (uint32_t layer
= 0; layer
< region
->srcSubresource
.layerCount
;
1084 struct radv_image_view src_iview
;
1085 radv_image_view_init(&src_iview
, cmd_buffer
->device
,
1086 &(VkImageViewCreateInfo
) {
1087 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
1088 .image
= radv_image_to_handle(src_image
),
1089 .viewType
= radv_meta_get_view_type(src_image
),
1090 .format
= src_image
->vk_format
,
1091 .subresourceRange
= {
1092 .aspectMask
= VK_IMAGE_ASPECT_COLOR_BIT
,
1093 .baseMipLevel
= region
->srcSubresource
.mipLevel
,
1095 .baseArrayLayer
= src_base_layer
+ layer
,
1100 struct radv_image_view dest_iview
;
1101 radv_image_view_init(&dest_iview
, cmd_buffer
->device
,
1102 &(VkImageViewCreateInfo
) {
1103 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
1104 .image
= radv_image_to_handle(dest_image
),
1105 .viewType
= radv_meta_get_view_type(dest_image
),
1106 .format
= dest_image
->vk_format
,
1107 .subresourceRange
= {
1108 .aspectMask
= VK_IMAGE_ASPECT_COLOR_BIT
,
1109 .baseMipLevel
= region
->dstSubresource
.mipLevel
,
1111 .baseArrayLayer
= dest_base_layer
+ layer
,
1118 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer
->device
),
1119 &(VkFramebufferCreateInfo
) {
1120 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
1121 .attachmentCount
= 1,
1122 .pAttachments
= (VkImageView
[]) {
1123 radv_image_view_to_handle(&dest_iview
),
1125 .width
= extent
.width
+ dstOffset
.x
,
1126 .height
= extent
.height
+ dstOffset
.y
,
1128 }, &cmd_buffer
->pool
->alloc
, &fb
);
1130 radv_cmd_buffer_begin_render_pass(cmd_buffer
,
1131 &(VkRenderPassBeginInfo
) {
1132 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
1136 .offset
= { dstOffset
.x
, dstOffset
.y
, },
1137 .extent
= { extent
.width
, extent
.height
},
1139 .clearValueCount
= 0,
1140 .pClearValues
= NULL
,
1143 radv_cmd_buffer_set_subpass(cmd_buffer
,
1144 &cmd_buffer
->state
.pass
->subpasses
[0]);
1146 emit_resolve(cmd_buffer
,
1149 &(VkOffset2D
) { srcOffset
.x
, srcOffset
.y
},
1150 &(VkOffset2D
) { dstOffset
.x
, dstOffset
.y
},
1151 &(VkExtent2D
) { extent
.width
, extent
.height
});
1153 radv_cmd_buffer_end_render_pass(cmd_buffer
);
1155 radv_DestroyFramebuffer(radv_device_to_handle(cmd_buffer
->device
), fb
, &cmd_buffer
->pool
->alloc
);
1159 radv_meta_restore(&saved_state
, cmd_buffer
);
1164 * Emit any needed resolves for the current subpass.
1167 radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
)
1169 struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1170 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1171 struct radv_meta_saved_state saved_state
;
1172 struct radv_subpass_barrier barrier
;
1174 /* Resolves happen before the end-of-subpass barriers get executed,
1175 * so we have to make the attachment shader-readable */
1176 barrier
.src_stage_mask
= VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
;
1177 barrier
.src_access_mask
= VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
;
1178 barrier
.dst_access_mask
= VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
;
1179 radv_subpass_barrier(cmd_buffer
, &barrier
);
1181 radv_decompress_resolve_subpass_src(cmd_buffer
);
1183 radv_meta_save(&saved_state
, cmd_buffer
,
1184 RADV_META_SAVE_GRAPHICS_PIPELINE
|
1185 RADV_META_SAVE_CONSTANTS
|
1186 RADV_META_SAVE_DESCRIPTORS
);
1188 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
1189 struct radv_subpass_attachment src_att
= subpass
->color_attachments
[i
];
1190 struct radv_subpass_attachment dest_att
= subpass
->resolve_attachments
[i
];
1192 if (dest_att
.attachment
== VK_ATTACHMENT_UNUSED
)
1195 struct radv_image_view
*dest_iview
= cmd_buffer
->state
.attachments
[dest_att
.attachment
].iview
;
1196 struct radv_image_view
*src_iview
= cmd_buffer
->state
.attachments
[src_att
.attachment
].iview
;
1198 struct radv_subpass resolve_subpass
= {
1200 .color_attachments
= (struct radv_subpass_attachment
[]) { dest_att
},
1201 .depth_stencil_attachment
= NULL
,
1204 radv_cmd_buffer_set_subpass(cmd_buffer
, &resolve_subpass
);
1206 emit_resolve(cmd_buffer
,
1209 &(VkOffset2D
) { 0, 0 },
1210 &(VkOffset2D
) { 0, 0 },
1211 &(VkExtent2D
) { fb
->width
, fb
->height
});
1214 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
1216 radv_meta_restore(&saved_state
, cmd_buffer
);
1220 * Depth/stencil resolves for the current subpass.
1223 radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
,
1224 VkImageAspectFlags aspects
,
1225 VkResolveModeFlagBits resolve_mode
)
1227 struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1228 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1229 struct radv_meta_saved_state saved_state
;
1230 struct radv_subpass_barrier barrier
;
1232 /* Resolves happen before the end-of-subpass barriers get executed,
1233 * so we have to make the attachment shader-readable */
1234 barrier
.src_stage_mask
= VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
;
1235 barrier
.src_access_mask
= VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
;
1236 barrier
.dst_access_mask
= VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
;
1237 radv_subpass_barrier(cmd_buffer
, &barrier
);
1239 radv_decompress_resolve_subpass_src(cmd_buffer
);
1241 radv_meta_save(&saved_state
, cmd_buffer
,
1242 RADV_META_SAVE_GRAPHICS_PIPELINE
|
1243 RADV_META_SAVE_CONSTANTS
|
1244 RADV_META_SAVE_DESCRIPTORS
);
1246 struct radv_subpass_attachment src_att
= *subpass
->depth_stencil_attachment
;
1247 struct radv_subpass_attachment dst_att
= *subpass
->ds_resolve_attachment
;
1249 struct radv_image_view
*src_iview
=
1250 cmd_buffer
->state
.attachments
[src_att
.attachment
].iview
;
1251 struct radv_image
*src_image
= src_iview
->image
;
1252 struct radv_image_view
*dst_iview
=
1253 cmd_buffer
->state
.attachments
[dst_att
.attachment
].iview
;
1255 struct radv_subpass resolve_subpass
= {
1257 .color_attachments
= NULL
,
1258 .depth_stencil_attachment
= (struct radv_subpass_attachment
*) { &dst_att
},
1261 radv_cmd_buffer_set_subpass(cmd_buffer
, &resolve_subpass
);
1263 struct radv_image_view tsrc_iview
;
1264 radv_image_view_init(&tsrc_iview
, cmd_buffer
->device
,
1265 &(VkImageViewCreateInfo
) {
1266 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
1267 .image
= radv_image_to_handle(src_image
),
1268 .viewType
= radv_meta_get_view_type(src_image
),
1269 .format
= src_iview
->vk_format
,
1270 .subresourceRange
= {
1271 .aspectMask
= aspects
,
1274 .baseArrayLayer
= 0,
1279 emit_depth_stencil_resolve(cmd_buffer
, &tsrc_iview
, dst_iview
,
1280 &(VkOffset2D
) { 0, 0 },
1281 &(VkOffset2D
) { 0, 0 },
1282 &(VkExtent2D
) { fb
->width
, fb
->height
},
1286 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
1288 radv_meta_restore(&saved_state
, cmd_buffer
);