mesa: use _mesa_set_scissor() in ScissorIndexed()
[mesa.git] / src / amd / vulkan / radv_meta_resolve_fs.c
1 /*
2 * Copyright © 2016 Dave Airlie
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24
25 #include <assert.h>
26 #include <stdbool.h>
27
28 #include "radv_meta.h"
29 #include "radv_private.h"
30 #include "nir/nir_builder.h"
31 #include "sid.h"
32 #include "vk_format.h"
33
34 static nir_shader *
35 build_nir_vertex_shader(void)
36 {
37 const struct glsl_type *vec4 = glsl_vec4_type();
38 nir_builder b;
39
40 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
41 b.shader->info.name = ralloc_strdup(b.shader, "meta_resolve_vs");
42
43 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
44 vec4, "gl_Position");
45 pos_out->data.location = VARYING_SLOT_POS;
46
47 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
48
49 nir_store_var(&b, pos_out, outvec, 0xf);
50 return b.shader;
51 }
52
53 static nir_shader *
54 build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, bool is_srgb, int samples)
55 {
56 nir_builder b;
57 char name[64];
58 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
59 const struct glsl_type *vec4 = glsl_vec4_type();
60 const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS,
61 false,
62 false,
63 GLSL_TYPE_FLOAT);
64
65 snprintf(name, 64, "meta_resolve_fs-%d-%s", samples, is_integer ? "int" : (is_srgb ? "srgb" : "float"));
66 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
67 b.shader->info.name = ralloc_strdup(b.shader, name);
68
69 nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
70 sampler_type, "s_tex");
71 input_img->data.descriptor_set = 0;
72 input_img->data.binding = 0;
73
74 nir_variable *fs_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "fs_pos_in");
75 fs_pos_in->data.location = VARYING_SLOT_POS;
76
77 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
78 vec4, "f_color");
79 color_out->data.location = FRAG_RESULT_DATA0;
80
81 nir_ssa_def *pos_in = nir_load_var(&b, fs_pos_in);
82 nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
83 nir_intrinsic_set_base(src_offset, 0);
84 nir_intrinsic_set_range(src_offset, 8);
85 src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
86 src_offset->num_components = 2;
87 nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
88 nir_builder_instr_insert(&b, &src_offset->instr);
89
90 nir_ssa_def *pos_int = nir_f2i32(&b, pos_in);
91
92 nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, pos_int, &src_offset->dest.ssa), 0x3);
93 nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
94
95 radv_meta_build_resolve_shader_core(&b, is_integer, is_srgb,samples,
96 input_img, color, img_coord);
97
98 nir_ssa_def *outval = nir_load_var(&b, color);
99 nir_store_var(&b, color_out, outval, 0xf);
100 return b.shader;
101 }
102
103
104 static VkResult
105 create_layout(struct radv_device *device)
106 {
107 VkResult result;
108 /*
109 * one descriptors for the image being sampled
110 */
111 VkDescriptorSetLayoutCreateInfo ds_create_info = {
112 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
113 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
114 .bindingCount = 1,
115 .pBindings = (VkDescriptorSetLayoutBinding[]) {
116 {
117 .binding = 0,
118 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
119 .descriptorCount = 1,
120 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
121 .pImmutableSamplers = NULL
122 },
123 }
124 };
125
126 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
127 &ds_create_info,
128 &device->meta_state.alloc,
129 &device->meta_state.resolve_fragment.ds_layout);
130 if (result != VK_SUCCESS)
131 goto fail;
132
133
134 VkPipelineLayoutCreateInfo pl_create_info = {
135 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
136 .setLayoutCount = 1,
137 .pSetLayouts = &device->meta_state.resolve_fragment.ds_layout,
138 .pushConstantRangeCount = 1,
139 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8},
140 };
141
142 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
143 &pl_create_info,
144 &device->meta_state.alloc,
145 &device->meta_state.resolve_fragment.p_layout);
146 if (result != VK_SUCCESS)
147 goto fail;
148 return VK_SUCCESS;
149 fail:
150 return result;
151 }
152
153 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
154 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
155 .vertexBindingDescriptionCount = 1,
156 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
157 {
158 .binding = 0,
159 .stride = 2 * sizeof(float),
160 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
161 },
162 },
163 .vertexAttributeDescriptionCount = 1,
164 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
165 {
166 /* Texture Coordinate */
167 .location = 0,
168 .binding = 0,
169 .format = VK_FORMAT_R32G32_SFLOAT,
170 .offset = 0
171 },
172 },
173 };
174
175 static VkFormat pipeline_formats[] = {
176 VK_FORMAT_R8G8B8A8_UNORM,
177 VK_FORMAT_R8G8B8A8_UINT,
178 VK_FORMAT_R8G8B8A8_SINT,
179 VK_FORMAT_R16G16B16A16_UNORM,
180 VK_FORMAT_R16G16B16A16_SNORM,
181 VK_FORMAT_R16G16B16A16_UINT,
182 VK_FORMAT_R16G16B16A16_SINT,
183 VK_FORMAT_R32_SFLOAT,
184 VK_FORMAT_R32G32_SFLOAT,
185 VK_FORMAT_R32G32B32A32_SFLOAT
186 };
187
188 static VkResult
189 create_resolve_pipeline(struct radv_device *device,
190 int samples_log2,
191 VkFormat format)
192 {
193 VkResult result;
194 bool is_integer = false, is_srgb = false;
195 uint32_t samples = 1 << samples_log2;
196 unsigned fs_key = radv_format_meta_fs_key(format);
197 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
198 vi_create_info = &normal_vi_create_info;
199 if (vk_format_is_int(format))
200 is_integer = true;
201 else if (vk_format_is_srgb(format))
202 is_srgb = true;
203
204 struct radv_shader_module fs = { .nir = NULL };
205 fs.nir = build_resolve_fragment_shader(device, is_integer, is_srgb, samples);
206 struct radv_shader_module vs = {
207 .nir = build_nir_vertex_shader(),
208 };
209
210 VkRenderPass *rp = is_srgb ?
211 &device->meta_state.resolve_fragment.rc[samples_log2].srgb_render_pass :
212 &device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key];
213
214 assert(!*rp);
215
216 VkPipeline *pipeline = is_srgb ?
217 &device->meta_state.resolve_fragment.rc[samples_log2].srgb_pipeline :
218 &device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
219 assert(!*pipeline);
220
221 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
222 {
223 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
224 .stage = VK_SHADER_STAGE_VERTEX_BIT,
225 .module = radv_shader_module_to_handle(&vs),
226 .pName = "main",
227 .pSpecializationInfo = NULL
228 }, {
229 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
230 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
231 .module = radv_shader_module_to_handle(&fs),
232 .pName = "main",
233 .pSpecializationInfo = NULL
234 },
235 };
236
237
238 result = radv_CreateRenderPass(radv_device_to_handle(device),
239 &(VkRenderPassCreateInfo) {
240 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
241 .attachmentCount = 1,
242 .pAttachments = &(VkAttachmentDescription) {
243 .format = format,
244 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
245 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
246 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
247 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
248 },
249 .subpassCount = 1,
250 .pSubpasses = &(VkSubpassDescription) {
251 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
252 .inputAttachmentCount = 0,
253 .colorAttachmentCount = 1,
254 .pColorAttachments = &(VkAttachmentReference) {
255 .attachment = 0,
256 .layout = VK_IMAGE_LAYOUT_GENERAL,
257 },
258 .pResolveAttachments = NULL,
259 .pDepthStencilAttachment = &(VkAttachmentReference) {
260 .attachment = VK_ATTACHMENT_UNUSED,
261 .layout = VK_IMAGE_LAYOUT_GENERAL,
262 },
263 .preserveAttachmentCount = 1,
264 .pPreserveAttachments = (uint32_t[]) { 0 },
265 },
266 .dependencyCount = 0,
267 }, &device->meta_state.alloc, rp);
268
269
270 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
271 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
272 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
273 .pStages = pipeline_shader_stages,
274 .pVertexInputState = vi_create_info,
275 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
276 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
277 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
278 .primitiveRestartEnable = false,
279 },
280 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
281 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
282 .viewportCount = 1,
283 .scissorCount = 1,
284 },
285 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
286 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
287 .rasterizerDiscardEnable = false,
288 .polygonMode = VK_POLYGON_MODE_FILL,
289 .cullMode = VK_CULL_MODE_NONE,
290 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
291 },
292 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
293 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
294 .rasterizationSamples = 1,
295 .sampleShadingEnable = false,
296 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
297 },
298 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
299 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
300 .attachmentCount = 1,
301 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
302 { .colorWriteMask =
303 VK_COLOR_COMPONENT_A_BIT |
304 VK_COLOR_COMPONENT_R_BIT |
305 VK_COLOR_COMPONENT_G_BIT |
306 VK_COLOR_COMPONENT_B_BIT },
307 }
308 },
309 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
310 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
311 .dynamicStateCount = 9,
312 .pDynamicStates = (VkDynamicState[]) {
313 VK_DYNAMIC_STATE_VIEWPORT,
314 VK_DYNAMIC_STATE_SCISSOR,
315 VK_DYNAMIC_STATE_LINE_WIDTH,
316 VK_DYNAMIC_STATE_DEPTH_BIAS,
317 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
318 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
319 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
320 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
321 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
322 },
323 },
324 .flags = 0,
325 .layout = device->meta_state.resolve_fragment.p_layout,
326 .renderPass = *rp,
327 .subpass = 0,
328 };
329
330 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
331 .use_rectlist = true
332 };
333
334 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
335 radv_pipeline_cache_to_handle(&device->meta_state.cache),
336 &vk_pipeline_info, &radv_pipeline_info,
337 &device->meta_state.alloc,
338 pipeline);
339
340 ralloc_free(vs.nir);
341 ralloc_free(fs.nir);
342 if (result != VK_SUCCESS)
343 goto fail;
344
345 return VK_SUCCESS;
346 fail:
347 ralloc_free(vs.nir);
348 ralloc_free(fs.nir);
349 return result;
350 }
351
352 VkResult
353 radv_device_init_meta_resolve_fragment_state(struct radv_device *device)
354 {
355 struct radv_meta_state *state = &device->meta_state;
356 VkResult res;
357 memset(&state->resolve_fragment, 0, sizeof(state->resolve_fragment));
358
359 res = create_layout(device);
360 if (res != VK_SUCCESS)
361 return res;
362
363 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
364 for (unsigned j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
365 res = create_resolve_pipeline(device, i, pipeline_formats[j]);
366 }
367
368 res = create_resolve_pipeline(device, i, VK_FORMAT_R8G8B8A8_SRGB);
369 }
370
371 return res;
372 }
373
374 void
375 radv_device_finish_meta_resolve_fragment_state(struct radv_device *device)
376 {
377 struct radv_meta_state *state = &device->meta_state;
378 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
379 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
380 radv_DestroyRenderPass(radv_device_to_handle(device),
381 state->resolve_fragment.rc[i].render_pass[j],
382 &state->alloc);
383 radv_DestroyPipeline(radv_device_to_handle(device),
384 state->resolve_fragment.rc[i].pipeline[j],
385 &state->alloc);
386 }
387 radv_DestroyRenderPass(radv_device_to_handle(device),
388 state->resolve_fragment.rc[i].srgb_render_pass,
389 &state->alloc);
390 radv_DestroyPipeline(radv_device_to_handle(device),
391 state->resolve_fragment.rc[i].srgb_pipeline,
392 &state->alloc);
393 }
394
395 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
396 state->resolve_fragment.ds_layout,
397 &state->alloc);
398 radv_DestroyPipelineLayout(radv_device_to_handle(device),
399 state->resolve_fragment.p_layout,
400 &state->alloc);
401 }
402
403 static void
404 emit_resolve(struct radv_cmd_buffer *cmd_buffer,
405 struct radv_image_view *src_iview,
406 struct radv_image_view *dest_iview,
407 const VkOffset2D *src_offset,
408 const VkOffset2D *dest_offset,
409 const VkExtent2D *resolve_extent)
410 {
411 struct radv_device *device = cmd_buffer->device;
412 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
413 const uint32_t samples = src_iview->image->info.samples;
414 const uint32_t samples_log2 = ffs(samples) - 1;
415 radv_meta_push_descriptor_set(cmd_buffer,
416 VK_PIPELINE_BIND_POINT_GRAPHICS,
417 cmd_buffer->device->meta_state.resolve_fragment.p_layout,
418 0, /* set */
419 1, /* descriptorWriteCount */
420 (VkWriteDescriptorSet[]) {
421 {
422 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
423 .dstBinding = 0,
424 .dstArrayElement = 0,
425 .descriptorCount = 1,
426 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
427 .pImageInfo = (VkDescriptorImageInfo[]) {
428 {
429 .sampler = VK_NULL_HANDLE,
430 .imageView = radv_image_view_to_handle(src_iview),
431 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
432 },
433 }
434 },
435 });
436
437 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
438
439 unsigned push_constants[2] = {
440 src_offset->x,
441 src_offset->y,
442 };
443 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
444 device->meta_state.resolve_fragment.p_layout,
445 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8,
446 push_constants);
447
448 unsigned fs_key = radv_format_meta_fs_key(dest_iview->vk_format);
449 VkPipeline pipeline_h = vk_format_is_srgb(dest_iview->vk_format) ?
450 device->meta_state.resolve_fragment.rc[samples_log2].srgb_pipeline :
451 device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
452
453 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
454 pipeline_h);
455
456 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
457 .x = dest_offset->x,
458 .y = dest_offset->y,
459 .width = resolve_extent->width,
460 .height = resolve_extent->height,
461 .minDepth = 0.0f,
462 .maxDepth = 1.0f
463 });
464
465 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
466 .offset = *dest_offset,
467 .extent = *resolve_extent,
468 });
469
470 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
471 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
472 }
473
474 void radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer,
475 struct radv_image *src_image,
476 VkImageLayout src_image_layout,
477 struct radv_image *dest_image,
478 VkImageLayout dest_image_layout,
479 uint32_t region_count,
480 const VkImageResolve *regions)
481 {
482 struct radv_device *device = cmd_buffer->device;
483 struct radv_meta_saved_state saved_state;
484 const uint32_t samples = src_image->info.samples;
485 const uint32_t samples_log2 = ffs(samples) - 1;
486 unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format);
487 VkRenderPass rp;
488 for (uint32_t r = 0; r < region_count; ++r) {
489 const VkImageResolve *region = &regions[r];
490 const uint32_t src_base_layer =
491 radv_meta_get_iview_layer(src_image, &region->srcSubresource,
492 &region->srcOffset);
493 VkImageSubresourceRange range;
494 range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
495 range.baseMipLevel = region->srcSubresource.mipLevel;
496 range.levelCount = 1;
497 range.baseArrayLayer = src_base_layer;
498 range.layerCount = region->srcSubresource.layerCount;
499 radv_fast_clear_flush_image_inplace(cmd_buffer, src_image, &range);
500 }
501
502 rp = vk_format_is_srgb(dest_image->vk_format) ?
503 device->meta_state.resolve_fragment.rc[samples_log2].srgb_render_pass :
504 device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key];
505 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
506
507 for (uint32_t r = 0; r < region_count; ++r) {
508 const VkImageResolve *region = &regions[r];
509
510 assert(region->srcSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
511 assert(region->dstSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
512 assert(region->srcSubresource.layerCount == region->dstSubresource.layerCount);
513
514 const uint32_t src_base_layer =
515 radv_meta_get_iview_layer(src_image, &region->srcSubresource,
516 &region->srcOffset);
517
518 const uint32_t dest_base_layer =
519 radv_meta_get_iview_layer(dest_image, &region->dstSubresource,
520 &region->dstOffset);
521
522 const struct VkExtent3D extent =
523 radv_sanitize_image_extent(src_image->type, region->extent);
524 const struct VkOffset3D srcOffset =
525 radv_sanitize_image_offset(src_image->type, region->srcOffset);
526 const struct VkOffset3D dstOffset =
527 radv_sanitize_image_offset(dest_image->type, region->dstOffset);
528
529 for (uint32_t layer = 0; layer < region->srcSubresource.layerCount;
530 ++layer) {
531
532 struct radv_image_view src_iview;
533 radv_image_view_init(&src_iview, cmd_buffer->device,
534 &(VkImageViewCreateInfo) {
535 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
536 .image = radv_image_to_handle(src_image),
537 .viewType = radv_meta_get_view_type(src_image),
538 .format = src_image->vk_format,
539 .subresourceRange = {
540 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
541 .baseMipLevel = region->srcSubresource.mipLevel,
542 .levelCount = 1,
543 .baseArrayLayer = src_base_layer + layer,
544 .layerCount = 1,
545 },
546 },
547 cmd_buffer, VK_IMAGE_USAGE_SAMPLED_BIT);
548
549 struct radv_image_view dest_iview;
550 radv_image_view_init(&dest_iview, cmd_buffer->device,
551 &(VkImageViewCreateInfo) {
552 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
553 .image = radv_image_to_handle(dest_image),
554 .viewType = radv_meta_get_view_type(dest_image),
555 .format = dest_image->vk_format,
556 .subresourceRange = {
557 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
558 .baseMipLevel = region->dstSubresource.mipLevel,
559 .levelCount = 1,
560 .baseArrayLayer = dest_base_layer + layer,
561 .layerCount = 1,
562 },
563 },
564 cmd_buffer, VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT);
565
566
567 VkFramebuffer fb;
568 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer->device),
569 &(VkFramebufferCreateInfo) {
570 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
571 .attachmentCount = 1,
572 .pAttachments = (VkImageView[]) {
573 radv_image_view_to_handle(&dest_iview),
574 },
575 .width = extent.width,
576 .height = extent.height,
577 .layers = 1
578 }, &cmd_buffer->pool->alloc, &fb);
579
580 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
581 &(VkRenderPassBeginInfo) {
582 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
583 .renderPass = rp,
584 .framebuffer = fb,
585 .renderArea = {
586 .offset = { dstOffset.x, dstOffset.y, },
587 .extent = { extent.width, extent.height },
588 },
589 .clearValueCount = 0,
590 .pClearValues = NULL,
591 }, VK_SUBPASS_CONTENTS_INLINE);
592
593
594
595 emit_resolve(cmd_buffer,
596 &src_iview,
597 &dest_iview,
598 &(VkOffset2D) { srcOffset.x, srcOffset.y },
599 &(VkOffset2D) { dstOffset.x, dstOffset.y },
600 &(VkExtent2D) { extent.width, extent.height });
601
602 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
603
604 radv_DestroyFramebuffer(radv_device_to_handle(cmd_buffer->device), fb, &cmd_buffer->pool->alloc);
605 }
606 }
607
608 radv_meta_restore(&saved_state, cmd_buffer);
609 }
610
611
612 /**
613 * Emit any needed resolves for the current subpass.
614 */
615 void
616 radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer)
617 {
618 struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
619 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
620 struct radv_meta_saved_state saved_state;
621
622 /* FINISHME(perf): Skip clears for resolve attachments.
623 *
624 * From the Vulkan 1.0 spec:
625 *
626 * If the first use of an attachment in a render pass is as a resolve
627 * attachment, then the loadOp is effectively ignored as the resolve is
628 * guaranteed to overwrite all pixels in the render area.
629 */
630
631 if (!subpass->has_resolve)
632 return;
633
634 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
635
636 for (uint32_t i = 0; i < subpass->color_count; ++i) {
637 VkAttachmentReference src_att = subpass->color_attachments[i];
638 VkAttachmentReference dest_att = subpass->resolve_attachments[i];
639 struct radv_image_view *dest_iview = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment;
640 struct radv_image *dst_img = dest_iview->image;
641 struct radv_image_view *src_iview = cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
642 if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
643 continue;
644
645 if (dst_img->surface.dcc_size) {
646 radv_initialize_dcc(cmd_buffer, dst_img, 0xffffffff);
647 cmd_buffer->state.attachments[dest_att.attachment].current_layout = VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
648 }
649 {
650 VkImageSubresourceRange range;
651 range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
652 range.baseMipLevel = 0;
653 range.levelCount = 1;
654 range.baseArrayLayer = 0;
655 range.layerCount = 1;
656 radv_fast_clear_flush_image_inplace(cmd_buffer, src_iview->image, &range);
657 }
658
659 struct radv_subpass resolve_subpass = {
660 .color_count = 1,
661 .color_attachments = (VkAttachmentReference[]) { dest_att },
662 .depth_stencil_attachment = { .attachment = VK_ATTACHMENT_UNUSED },
663 };
664
665 radv_cmd_buffer_set_subpass(cmd_buffer, &resolve_subpass, false);
666
667 /* Subpass resolves must respect the render area. We can ignore the
668 * render area here because vkCmdBeginRenderPass set the render area
669 * with 3DSTATE_DRAWING_RECTANGLE.
670 *
671 * XXX(chadv): Does the hardware really respect
672 * 3DSTATE_DRAWING_RECTANGLE when draing a 3DPRIM_RECTLIST?
673 */
674 emit_resolve(cmd_buffer,
675 src_iview,
676 dest_iview,
677 &(VkOffset2D) { 0, 0 },
678 &(VkOffset2D) { 0, 0 },
679 &(VkExtent2D) { fb->width, fb->height });
680 }
681
682 cmd_buffer->state.subpass = subpass;
683 radv_meta_restore(&saved_state, cmd_buffer);
684 }