2 * Copyright © 2016 Dave Airlie
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_meta.h"
29 #include "radv_private.h"
30 #include "nir/nir_builder.h"
32 #include "vk_format.h"
35 build_nir_vertex_shader(void)
37 const struct glsl_type
*vec4
= glsl_vec4_type();
40 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
41 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "meta_resolve_vs");
43 nir_variable
*pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
45 pos_out
->data
.location
= VARYING_SLOT_POS
;
47 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices(&b
);
49 nir_store_var(&b
, pos_out
, outvec
, 0xf);
54 build_resolve_fragment_shader(struct radv_device
*dev
, bool is_integer
, int samples
)
58 const struct glsl_type
*vec4
= glsl_vec4_type();
59 const struct glsl_type
*sampler_type
= glsl_sampler_type(GLSL_SAMPLER_DIM_MS
,
64 snprintf(name
, 64, "meta_resolve_fs-%d-%s", samples
, is_integer
? "int" : "float");
65 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
66 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, name
);
68 nir_variable
*input_img
= nir_variable_create(b
.shader
, nir_var_uniform
,
69 sampler_type
, "s_tex");
70 input_img
->data
.descriptor_set
= 0;
71 input_img
->data
.binding
= 0;
73 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
75 color_out
->data
.location
= FRAG_RESULT_DATA0
;
77 nir_ssa_def
*pos_in
= nir_channels(&b
, nir_load_frag_coord(&b
), 0x3);
78 nir_intrinsic_instr
*src_offset
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
79 nir_intrinsic_set_base(src_offset
, 0);
80 nir_intrinsic_set_range(src_offset
, 8);
81 src_offset
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
82 src_offset
->num_components
= 2;
83 nir_ssa_dest_init(&src_offset
->instr
, &src_offset
->dest
, 2, 32, "src_offset");
84 nir_builder_instr_insert(&b
, &src_offset
->instr
);
86 nir_ssa_def
*pos_int
= nir_f2i32(&b
, pos_in
);
88 nir_ssa_def
*img_coord
= nir_channels(&b
, nir_iadd(&b
, pos_int
, &src_offset
->dest
.ssa
), 0x3);
89 nir_variable
*color
= nir_local_variable_create(b
.impl
, glsl_vec4_type(), "color");
91 radv_meta_build_resolve_shader_core(&b
, is_integer
, samples
, input_img
,
94 nir_ssa_def
*outval
= nir_load_var(&b
, color
);
95 nir_store_var(&b
, color_out
, outval
, 0xf);
101 create_layout(struct radv_device
*device
)
105 * one descriptors for the image being sampled
107 VkDescriptorSetLayoutCreateInfo ds_create_info
= {
108 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
109 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
111 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
114 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
115 .descriptorCount
= 1,
116 .stageFlags
= VK_SHADER_STAGE_FRAGMENT_BIT
,
117 .pImmutableSamplers
= NULL
122 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
124 &device
->meta_state
.alloc
,
125 &device
->meta_state
.resolve_fragment
.ds_layout
);
126 if (result
!= VK_SUCCESS
)
130 VkPipelineLayoutCreateInfo pl_create_info
= {
131 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
133 .pSetLayouts
= &device
->meta_state
.resolve_fragment
.ds_layout
,
134 .pushConstantRangeCount
= 1,
135 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 8},
138 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
140 &device
->meta_state
.alloc
,
141 &device
->meta_state
.resolve_fragment
.p_layout
);
142 if (result
!= VK_SUCCESS
)
149 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info
= {
150 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
151 .vertexBindingDescriptionCount
= 0,
152 .vertexAttributeDescriptionCount
= 0,
156 create_resolve_pipeline(struct radv_device
*device
,
160 mtx_lock(&device
->meta_state
.mtx
);
162 unsigned fs_key
= radv_format_meta_fs_key(format
);
163 VkPipeline
*pipeline
= &device
->meta_state
.resolve_fragment
.rc
[samples_log2
].pipeline
[fs_key
];
165 mtx_unlock(&device
->meta_state
.mtx
);
170 bool is_integer
= false;
171 uint32_t samples
= 1 << samples_log2
;
172 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
173 vi_create_info
= &normal_vi_create_info
;
174 if (vk_format_is_int(format
))
177 struct radv_shader_module fs
= { .nir
= NULL
};
178 fs
.nir
= build_resolve_fragment_shader(device
, is_integer
, samples
);
179 struct radv_shader_module vs
= {
180 .nir
= build_nir_vertex_shader(),
183 VkRenderPass
*rp
= &device
->meta_state
.resolve_fragment
.rc
[samples_log2
].render_pass
[fs_key
][0];
187 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
189 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
190 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
191 .module
= radv_shader_module_to_handle(&vs
),
193 .pSpecializationInfo
= NULL
195 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
196 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
197 .module
= radv_shader_module_to_handle(&fs
),
199 .pSpecializationInfo
= NULL
204 for (unsigned dst_layout
= 0; dst_layout
< RADV_META_DST_LAYOUT_COUNT
; ++dst_layout
) {
205 VkImageLayout layout
= radv_meta_dst_layout_to_layout(dst_layout
);
206 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
207 &(VkRenderPassCreateInfo
) {
208 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
209 .attachmentCount
= 1,
210 .pAttachments
= &(VkAttachmentDescription
) {
212 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
213 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
214 .initialLayout
= layout
,
215 .finalLayout
= layout
,
218 .pSubpasses
= &(VkSubpassDescription
) {
219 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
220 .inputAttachmentCount
= 0,
221 .colorAttachmentCount
= 1,
222 .pColorAttachments
= &(VkAttachmentReference
) {
226 .pResolveAttachments
= NULL
,
227 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
228 .attachment
= VK_ATTACHMENT_UNUSED
,
229 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
231 .preserveAttachmentCount
= 0,
232 .pPreserveAttachments
= NULL
,
234 .dependencyCount
= 0,
235 }, &device
->meta_state
.alloc
, rp
+ dst_layout
);
239 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
240 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
241 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
242 .pStages
= pipeline_shader_stages
,
243 .pVertexInputState
= vi_create_info
,
244 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
245 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
246 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
247 .primitiveRestartEnable
= false,
249 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
250 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
254 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
255 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
256 .rasterizerDiscardEnable
= false,
257 .polygonMode
= VK_POLYGON_MODE_FILL
,
258 .cullMode
= VK_CULL_MODE_NONE
,
259 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
261 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
262 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
263 .rasterizationSamples
= 1,
264 .sampleShadingEnable
= false,
265 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
267 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
268 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
269 .attachmentCount
= 1,
270 .pAttachments
= (VkPipelineColorBlendAttachmentState
[]) {
272 VK_COLOR_COMPONENT_A_BIT
|
273 VK_COLOR_COMPONENT_R_BIT
|
274 VK_COLOR_COMPONENT_G_BIT
|
275 VK_COLOR_COMPONENT_B_BIT
},
278 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
279 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
280 .dynamicStateCount
= 9,
281 .pDynamicStates
= (VkDynamicState
[]) {
282 VK_DYNAMIC_STATE_VIEWPORT
,
283 VK_DYNAMIC_STATE_SCISSOR
,
284 VK_DYNAMIC_STATE_LINE_WIDTH
,
285 VK_DYNAMIC_STATE_DEPTH_BIAS
,
286 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
287 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
288 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
289 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
290 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
294 .layout
= device
->meta_state
.resolve_fragment
.p_layout
,
299 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
303 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
304 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
305 &vk_pipeline_info
, &radv_pipeline_info
,
306 &device
->meta_state
.alloc
,
311 mtx_unlock(&device
->meta_state
.mtx
);
321 get_resolve_mode_str(VkResolveModeFlagBitsKHR resolve_mode
)
323 switch (resolve_mode
) {
324 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
326 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
328 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
330 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
333 unreachable("invalid resolve mode");
338 build_depth_stencil_resolve_fragment_shader(struct radv_device
*dev
, int samples
,
340 VkResolveModeFlagBitsKHR resolve_mode
)
344 const struct glsl_type
*vec4
= glsl_vec4_type();
345 const struct glsl_type
*sampler_type
= glsl_sampler_type(GLSL_SAMPLER_DIM_2D
,
350 snprintf(name
, 64, "meta_resolve_fs_%s-%s-%d",
351 index
== DEPTH_RESOLVE
? "depth" : "stencil",
352 get_resolve_mode_str(resolve_mode
), samples
);
354 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
355 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, name
);
357 nir_variable
*input_img
= nir_variable_create(b
.shader
, nir_var_uniform
,
358 sampler_type
, "s_tex");
359 input_img
->data
.descriptor_set
= 0;
360 input_img
->data
.binding
= 0;
362 nir_variable
*fs_out
= nir_variable_create(b
.shader
,
363 nir_var_shader_out
, vec4
,
365 fs_out
->data
.location
=
366 index
== DEPTH_RESOLVE
? FRAG_RESULT_DEPTH
: FRAG_RESULT_STENCIL
;
368 nir_ssa_def
*pos_in
= nir_channels(&b
, nir_load_frag_coord(&b
), 0x3);
370 nir_intrinsic_instr
*src_offset
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
371 nir_intrinsic_set_base(src_offset
, 0);
372 nir_intrinsic_set_range(src_offset
, 8);
373 src_offset
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
374 src_offset
->num_components
= 2;
375 nir_ssa_dest_init(&src_offset
->instr
, &src_offset
->dest
, 2, 32, "src_offset");
376 nir_builder_instr_insert(&b
, &src_offset
->instr
);
378 nir_ssa_def
*pos_int
= nir_f2i32(&b
, pos_in
);
380 nir_ssa_def
*img_coord
= nir_channels(&b
, nir_iadd(&b
, pos_int
, &src_offset
->dest
.ssa
), 0x3);
382 nir_ssa_def
*input_img_deref
= &nir_build_deref_var(&b
, input_img
)->dest
.ssa
;
384 nir_alu_type type
= index
== DEPTH_RESOLVE
? nir_type_float
: nir_type_uint
;
386 nir_tex_instr
*tex
= nir_tex_instr_create(b
.shader
, 3);
387 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
388 tex
->op
= nir_texop_txf_ms
;
389 tex
->src
[0].src_type
= nir_tex_src_coord
;
390 tex
->src
[0].src
= nir_src_for_ssa(img_coord
);
391 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
392 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(&b
, 0));
393 tex
->src
[2].src_type
= nir_tex_src_texture_deref
;
394 tex
->src
[2].src
= nir_src_for_ssa(input_img_deref
);
395 tex
->dest_type
= type
;
396 tex
->is_array
= false;
397 tex
->coord_components
= 2;
399 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
400 nir_builder_instr_insert(&b
, &tex
->instr
);
402 nir_ssa_def
*outval
= &tex
->dest
.ssa
;
404 if (resolve_mode
!= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
) {
405 for (int i
= 1; i
< samples
; i
++) {
406 nir_tex_instr
*tex_add
= nir_tex_instr_create(b
.shader
, 3);
407 tex_add
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
408 tex_add
->op
= nir_texop_txf_ms
;
409 tex_add
->src
[0].src_type
= nir_tex_src_coord
;
410 tex_add
->src
[0].src
= nir_src_for_ssa(img_coord
);
411 tex_add
->src
[1].src_type
= nir_tex_src_ms_index
;
412 tex_add
->src
[1].src
= nir_src_for_ssa(nir_imm_int(&b
, i
));
413 tex_add
->src
[2].src_type
= nir_tex_src_texture_deref
;
414 tex_add
->src
[2].src
= nir_src_for_ssa(input_img_deref
);
415 tex_add
->dest_type
= type
;
416 tex_add
->is_array
= false;
417 tex_add
->coord_components
= 2;
419 nir_ssa_dest_init(&tex_add
->instr
, &tex_add
->dest
, 4, 32, "tex");
420 nir_builder_instr_insert(&b
, &tex_add
->instr
);
422 switch (resolve_mode
) {
423 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
424 assert(index
== DEPTH_RESOLVE
);
425 outval
= nir_fadd(&b
, outval
, &tex_add
->dest
.ssa
);
427 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
428 if (index
== DEPTH_RESOLVE
)
429 outval
= nir_fmin(&b
, outval
, &tex_add
->dest
.ssa
);
431 outval
= nir_umin(&b
, outval
, &tex_add
->dest
.ssa
);
433 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
434 if (index
== DEPTH_RESOLVE
)
435 outval
= nir_fmax(&b
, outval
, &tex_add
->dest
.ssa
);
437 outval
= nir_umax(&b
, outval
, &tex_add
->dest
.ssa
);
440 unreachable("invalid resolve mode");
444 if (resolve_mode
== VK_RESOLVE_MODE_AVERAGE_BIT_KHR
)
445 outval
= nir_fdiv(&b
, outval
, nir_imm_float(&b
, samples
));
448 nir_store_var(&b
, fs_out
, outval
, 0x1);
454 create_depth_stencil_resolve_pipeline(struct radv_device
*device
,
457 VkResolveModeFlagBitsKHR resolve_mode
)
459 VkRenderPass
*render_pass
;
460 VkPipeline
*pipeline
;
464 mtx_lock(&device
->meta_state
.mtx
);
466 switch (resolve_mode
) {
467 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
468 if (index
== DEPTH_RESOLVE
)
469 pipeline
= &device
->meta_state
.resolve_fragment
.depth_zero_pipeline
;
471 pipeline
= &device
->meta_state
.resolve_fragment
.stencil_zero_pipeline
;
473 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
474 assert(index
== DEPTH_RESOLVE
);
475 pipeline
= &device
->meta_state
.resolve_fragment
.depth
[samples_log2
].average_pipeline
;
477 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
478 if (index
== DEPTH_RESOLVE
)
479 pipeline
= &device
->meta_state
.resolve_fragment
.depth
[samples_log2
].min_pipeline
;
481 pipeline
= &device
->meta_state
.resolve_fragment
.stencil
[samples_log2
].min_pipeline
;
483 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
484 if (index
== DEPTH_RESOLVE
)
485 pipeline
= &device
->meta_state
.resolve_fragment
.depth
[samples_log2
].max_pipeline
;
487 pipeline
= &device
->meta_state
.resolve_fragment
.stencil
[samples_log2
].max_pipeline
;
490 unreachable("invalid resolve mode");
494 mtx_unlock(&device
->meta_state
.mtx
);
498 struct radv_shader_module fs
= { .nir
= NULL
};
499 struct radv_shader_module vs
= { .nir
= NULL
};
500 uint32_t samples
= 1 << samples_log2
;
502 vs
.nir
= build_nir_vertex_shader();
503 fs
.nir
= build_depth_stencil_resolve_fragment_shader(device
, samples
,
504 index
, resolve_mode
);
506 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
508 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
509 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
510 .module
= radv_shader_module_to_handle(&vs
),
512 .pSpecializationInfo
= NULL
514 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
515 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
516 .module
= radv_shader_module_to_handle(&fs
),
518 .pSpecializationInfo
= NULL
522 if (index
== DEPTH_RESOLVE
) {
523 src_format
= VK_FORMAT_D32_SFLOAT
;
524 render_pass
= &device
->meta_state
.resolve_fragment
.depth_render_pass
;
526 render_pass
= &device
->meta_state
.resolve_fragment
.stencil_render_pass
;
527 src_format
= VK_FORMAT_S8_UINT
;
531 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
532 &(VkRenderPassCreateInfo
) {
533 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
534 .attachmentCount
= 1,
535 .pAttachments
= &(VkAttachmentDescription
) {
536 .format
= src_format
,
537 .loadOp
= VK_ATTACHMENT_LOAD_OP_DONT_CARE
,
538 .storeOp
= VK_ATTACHMENT_LOAD_OP_DONT_CARE
,
539 .stencilLoadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
540 .stencilStoreOp
= VK_ATTACHMENT_STORE_OP_STORE
,
541 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
542 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
545 .pSubpasses
= &(VkSubpassDescription
) {
546 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
547 .inputAttachmentCount
= 0,
548 .colorAttachmentCount
= 0,
549 .pColorAttachments
= NULL
,
550 .pResolveAttachments
= NULL
,
551 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
553 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
555 .preserveAttachmentCount
= 0,
556 .pPreserveAttachments
= NULL
,
558 .dependencyCount
= 0,
559 }, &device
->meta_state
.alloc
, render_pass
);
562 VkStencilOp stencil_op
=
563 index
== DEPTH_RESOLVE
? VK_STENCIL_OP_KEEP
: VK_STENCIL_OP_REPLACE
;
565 VkPipelineDepthStencilStateCreateInfo depth_stencil_state
= {
566 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
567 .depthTestEnable
= true,
568 .depthWriteEnable
= index
== DEPTH_RESOLVE
,
569 .stencilTestEnable
= index
== STENCIL_RESOLVE
,
570 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
572 .failOp
= stencil_op
,
573 .passOp
= stencil_op
,
574 .depthFailOp
= stencil_op
,
575 .compareOp
= VK_COMPARE_OP_ALWAYS
,
578 .failOp
= stencil_op
,
579 .passOp
= stencil_op
,
580 .depthFailOp
= stencil_op
,
581 .compareOp
= VK_COMPARE_OP_ALWAYS
,
585 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
586 vi_create_info
= &normal_vi_create_info
;
588 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
589 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
590 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
591 .pStages
= pipeline_shader_stages
,
592 .pVertexInputState
= vi_create_info
,
593 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
594 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
595 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
596 .primitiveRestartEnable
= false,
598 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
599 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
603 .pDepthStencilState
= &depth_stencil_state
,
604 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
605 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
606 .rasterizerDiscardEnable
= false,
607 .polygonMode
= VK_POLYGON_MODE_FILL
,
608 .cullMode
= VK_CULL_MODE_NONE
,
609 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
611 .pMultisampleState
= NULL
,
612 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
613 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
614 .attachmentCount
= 0,
615 .pAttachments
= (VkPipelineColorBlendAttachmentState
[]) {
617 VK_COLOR_COMPONENT_A_BIT
|
618 VK_COLOR_COMPONENT_R_BIT
|
619 VK_COLOR_COMPONENT_G_BIT
|
620 VK_COLOR_COMPONENT_B_BIT
},
623 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
624 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
625 .dynamicStateCount
= 9,
626 .pDynamicStates
= (VkDynamicState
[]) {
627 VK_DYNAMIC_STATE_VIEWPORT
,
628 VK_DYNAMIC_STATE_SCISSOR
,
629 VK_DYNAMIC_STATE_LINE_WIDTH
,
630 VK_DYNAMIC_STATE_DEPTH_BIAS
,
631 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
632 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
633 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
634 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
635 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
639 .layout
= device
->meta_state
.resolve_fragment
.p_layout
,
640 .renderPass
= *render_pass
,
644 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
648 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
649 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
650 &vk_pipeline_info
, &radv_pipeline_info
,
651 &device
->meta_state
.alloc
,
657 mtx_unlock(&device
->meta_state
.mtx
);
662 radv_device_init_meta_resolve_fragment_state(struct radv_device
*device
, bool on_demand
)
666 res
= create_layout(device
);
667 if (res
!= VK_SUCCESS
)
673 for (uint32_t i
= 0; i
< MAX_SAMPLES_LOG2
; ++i
) {
674 for (unsigned j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
675 res
= create_resolve_pipeline(device
, i
, radv_fs_key_format_exemplars
[j
]);
676 if (res
!= VK_SUCCESS
)
680 res
= create_depth_stencil_resolve_pipeline(device
, i
, DEPTH_RESOLVE
,
681 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
);
682 if (res
!= VK_SUCCESS
)
685 res
= create_depth_stencil_resolve_pipeline(device
, i
, DEPTH_RESOLVE
,
686 VK_RESOLVE_MODE_MIN_BIT_KHR
);
687 if (res
!= VK_SUCCESS
)
690 res
= create_depth_stencil_resolve_pipeline(device
, i
, DEPTH_RESOLVE
,
691 VK_RESOLVE_MODE_MAX_BIT_KHR
);
692 if (res
!= VK_SUCCESS
)
695 res
= create_depth_stencil_resolve_pipeline(device
, i
, STENCIL_RESOLVE
,
696 VK_RESOLVE_MODE_MIN_BIT_KHR
);
697 if (res
!= VK_SUCCESS
)
700 res
= create_depth_stencil_resolve_pipeline(device
, i
, STENCIL_RESOLVE
,
701 VK_RESOLVE_MODE_MAX_BIT_KHR
);
702 if (res
!= VK_SUCCESS
)
706 res
= create_depth_stencil_resolve_pipeline(device
, 0, DEPTH_RESOLVE
,
707 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
);
708 if (res
!= VK_SUCCESS
)
711 res
= create_depth_stencil_resolve_pipeline(device
, 0, STENCIL_RESOLVE
,
712 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
);
713 if (res
!= VK_SUCCESS
)
718 radv_device_finish_meta_resolve_fragment_state(device
);
723 radv_device_finish_meta_resolve_fragment_state(struct radv_device
*device
)
725 struct radv_meta_state
*state
= &device
->meta_state
;
726 for (uint32_t i
= 0; i
< MAX_SAMPLES_LOG2
; ++i
) {
727 for (unsigned j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
728 for(unsigned k
=0; k
< RADV_META_DST_LAYOUT_COUNT
; ++k
) {
729 radv_DestroyRenderPass(radv_device_to_handle(device
),
730 state
->resolve_fragment
.rc
[i
].render_pass
[j
][k
],
733 radv_DestroyPipeline(radv_device_to_handle(device
),
734 state
->resolve_fragment
.rc
[i
].pipeline
[j
],
738 radv_DestroyPipeline(radv_device_to_handle(device
),
739 state
->resolve_fragment
.depth
[i
].average_pipeline
,
742 radv_DestroyPipeline(radv_device_to_handle(device
),
743 state
->resolve_fragment
.depth
[i
].max_pipeline
,
746 radv_DestroyPipeline(radv_device_to_handle(device
),
747 state
->resolve_fragment
.depth
[i
].min_pipeline
,
750 radv_DestroyPipeline(radv_device_to_handle(device
),
751 state
->resolve_fragment
.stencil
[i
].max_pipeline
,
754 radv_DestroyPipeline(radv_device_to_handle(device
),
755 state
->resolve_fragment
.stencil
[i
].min_pipeline
,
759 radv_DestroyRenderPass(radv_device_to_handle(device
),
760 state
->resolve_fragment
.depth_render_pass
,
762 radv_DestroyRenderPass(radv_device_to_handle(device
),
763 state
->resolve_fragment
.stencil_render_pass
,
766 radv_DestroyPipeline(radv_device_to_handle(device
),
767 state
->resolve_fragment
.depth_zero_pipeline
,
769 radv_DestroyPipeline(radv_device_to_handle(device
),
770 state
->resolve_fragment
.stencil_zero_pipeline
,
773 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
774 state
->resolve_fragment
.ds_layout
,
776 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
777 state
->resolve_fragment
.p_layout
,
782 radv_get_resolve_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
783 struct radv_image_view
*src_iview
,
784 struct radv_image_view
*dst_iview
)
786 struct radv_device
*device
= cmd_buffer
->device
;
787 unsigned fs_key
= radv_format_meta_fs_key(dst_iview
->vk_format
);
788 const uint32_t samples
= src_iview
->image
->info
.samples
;
789 const uint32_t samples_log2
= ffs(samples
) - 1;
790 VkPipeline
*pipeline
;
792 pipeline
= &device
->meta_state
.resolve_fragment
.rc
[samples_log2
].pipeline
[fs_key
];
796 ret
= create_resolve_pipeline(device
, samples_log2
,
797 radv_fs_key_format_exemplars
[fs_key
]);
798 if (ret
!= VK_SUCCESS
) {
799 cmd_buffer
->record_result
= ret
;
808 emit_resolve(struct radv_cmd_buffer
*cmd_buffer
,
809 struct radv_image_view
*src_iview
,
810 struct radv_image_view
*dest_iview
,
811 const VkOffset2D
*src_offset
,
812 const VkOffset2D
*dest_offset
,
813 const VkExtent2D
*resolve_extent
)
815 struct radv_device
*device
= cmd_buffer
->device
;
816 VkCommandBuffer cmd_buffer_h
= radv_cmd_buffer_to_handle(cmd_buffer
);
817 VkPipeline
*pipeline
;
819 radv_meta_push_descriptor_set(cmd_buffer
,
820 VK_PIPELINE_BIND_POINT_GRAPHICS
,
821 cmd_buffer
->device
->meta_state
.resolve_fragment
.p_layout
,
823 1, /* descriptorWriteCount */
824 (VkWriteDescriptorSet
[]) {
826 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
828 .dstArrayElement
= 0,
829 .descriptorCount
= 1,
830 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
831 .pImageInfo
= (VkDescriptorImageInfo
[]) {
833 .sampler
= VK_NULL_HANDLE
,
834 .imageView
= radv_image_view_to_handle(src_iview
),
835 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
841 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
843 unsigned push_constants
[2] = {
844 src_offset
->x
- dest_offset
->x
,
845 src_offset
->y
- dest_offset
->y
,
847 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
848 device
->meta_state
.resolve_fragment
.p_layout
,
849 VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 8,
852 pipeline
= radv_get_resolve_pipeline(cmd_buffer
, src_iview
, dest_iview
);
854 radv_CmdBindPipeline(cmd_buffer_h
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
857 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
860 .width
= resolve_extent
->width
,
861 .height
= resolve_extent
->height
,
866 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkRect2D
) {
867 .offset
= *dest_offset
,
868 .extent
= *resolve_extent
,
871 radv_CmdDraw(cmd_buffer_h
, 3, 1, 0, 0);
872 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
876 emit_depth_stencil_resolve(struct radv_cmd_buffer
*cmd_buffer
,
877 struct radv_image_view
*src_iview
,
878 struct radv_image_view
*dst_iview
,
879 const VkOffset2D
*src_offset
,
880 const VkOffset2D
*dst_offset
,
881 const VkExtent2D
*resolve_extent
,
882 VkImageAspectFlags aspects
,
883 VkResolveModeFlagBitsKHR resolve_mode
)
885 struct radv_device
*device
= cmd_buffer
->device
;
886 const uint32_t samples
= src_iview
->image
->info
.samples
;
887 const uint32_t samples_log2
= ffs(samples
) - 1;
888 VkPipeline
*pipeline
;
890 radv_meta_push_descriptor_set(cmd_buffer
,
891 VK_PIPELINE_BIND_POINT_GRAPHICS
,
892 cmd_buffer
->device
->meta_state
.resolve_fragment
.p_layout
,
894 1, /* descriptorWriteCount */
895 (VkWriteDescriptorSet
[]) {
897 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
899 .dstArrayElement
= 0,
900 .descriptorCount
= 1,
901 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
902 .pImageInfo
= (VkDescriptorImageInfo
[]) {
904 .sampler
= VK_NULL_HANDLE
,
905 .imageView
= radv_image_view_to_handle(src_iview
),
906 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
912 unsigned push_constants
[2] = {
913 src_offset
->x
- dst_offset
->x
,
914 src_offset
->y
- dst_offset
->y
,
916 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
917 device
->meta_state
.resolve_fragment
.p_layout
,
918 VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 8,
921 switch (resolve_mode
) {
922 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
923 if (aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
)
924 pipeline
= &device
->meta_state
.resolve_fragment
.depth_zero_pipeline
;
926 pipeline
= &device
->meta_state
.resolve_fragment
.stencil_zero_pipeline
;
928 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
929 assert(aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
);
930 pipeline
= &device
->meta_state
.resolve_fragment
.depth
[samples_log2
].average_pipeline
;
932 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
933 if (aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
)
934 pipeline
= &device
->meta_state
.resolve_fragment
.depth
[samples_log2
].min_pipeline
;
936 pipeline
= &device
->meta_state
.resolve_fragment
.stencil
[samples_log2
].min_pipeline
;
938 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
939 if (aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
)
940 pipeline
= &device
->meta_state
.resolve_fragment
.depth
[samples_log2
].max_pipeline
;
942 pipeline
= &device
->meta_state
.resolve_fragment
.stencil
[samples_log2
].max_pipeline
;
945 unreachable("invalid resolve mode");
949 int index
= aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
? DEPTH_RESOLVE
: STENCIL_RESOLVE
;
952 ret
= create_depth_stencil_resolve_pipeline(device
, samples_log2
,
953 index
, resolve_mode
);
954 if (ret
!= VK_SUCCESS
) {
955 cmd_buffer
->record_result
= ret
;
960 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
961 VK_PIPELINE_BIND_POINT_GRAPHICS
, *pipeline
);
963 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
966 .width
= resolve_extent
->width
,
967 .height
= resolve_extent
->height
,
972 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkRect2D
) {
973 .offset
= *dst_offset
,
974 .extent
= *resolve_extent
,
977 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer
), 3, 1, 0, 0);
980 void radv_meta_resolve_fragment_image(struct radv_cmd_buffer
*cmd_buffer
,
981 struct radv_image
*src_image
,
982 VkImageLayout src_image_layout
,
983 struct radv_image
*dest_image
,
984 VkImageLayout dest_image_layout
,
985 uint32_t region_count
,
986 const VkImageResolve
*regions
)
988 struct radv_device
*device
= cmd_buffer
->device
;
989 struct radv_meta_saved_state saved_state
;
990 const uint32_t samples
= src_image
->info
.samples
;
991 const uint32_t samples_log2
= ffs(samples
) - 1;
992 unsigned fs_key
= radv_format_meta_fs_key(dest_image
->vk_format
);
993 unsigned dst_layout
= radv_meta_dst_layout_from_layout(dest_image_layout
);
996 radv_decompress_resolve_src(cmd_buffer
, src_image
, src_image_layout
,
997 region_count
, regions
);
999 if (!device
->meta_state
.resolve_fragment
.rc
[samples_log2
].render_pass
[fs_key
][dst_layout
]) {
1000 VkResult ret
= create_resolve_pipeline(device
, samples_log2
, radv_fs_key_format_exemplars
[fs_key
]);
1001 if (ret
!= VK_SUCCESS
) {
1002 cmd_buffer
->record_result
= ret
;
1007 rp
= device
->meta_state
.resolve_fragment
.rc
[samples_log2
].render_pass
[fs_key
][dst_layout
];
1009 radv_meta_save(&saved_state
, cmd_buffer
,
1010 RADV_META_SAVE_GRAPHICS_PIPELINE
|
1011 RADV_META_SAVE_CONSTANTS
|
1012 RADV_META_SAVE_DESCRIPTORS
);
1014 for (uint32_t r
= 0; r
< region_count
; ++r
) {
1015 const VkImageResolve
*region
= ®ions
[r
];
1017 assert(region
->srcSubresource
.aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
);
1018 assert(region
->dstSubresource
.aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
);
1019 assert(region
->srcSubresource
.layerCount
== region
->dstSubresource
.layerCount
);
1021 const uint32_t src_base_layer
=
1022 radv_meta_get_iview_layer(src_image
, ®ion
->srcSubresource
,
1023 ®ion
->srcOffset
);
1025 const uint32_t dest_base_layer
=
1026 radv_meta_get_iview_layer(dest_image
, ®ion
->dstSubresource
,
1027 ®ion
->dstOffset
);
1029 const struct VkExtent3D extent
=
1030 radv_sanitize_image_extent(src_image
->type
, region
->extent
);
1031 const struct VkOffset3D srcOffset
=
1032 radv_sanitize_image_offset(src_image
->type
, region
->srcOffset
);
1033 const struct VkOffset3D dstOffset
=
1034 radv_sanitize_image_offset(dest_image
->type
, region
->dstOffset
);
1036 for (uint32_t layer
= 0; layer
< region
->srcSubresource
.layerCount
;
1039 struct radv_image_view src_iview
;
1040 radv_image_view_init(&src_iview
, cmd_buffer
->device
,
1041 &(VkImageViewCreateInfo
) {
1042 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
1043 .image
= radv_image_to_handle(src_image
),
1044 .viewType
= radv_meta_get_view_type(src_image
),
1045 .format
= src_image
->vk_format
,
1046 .subresourceRange
= {
1047 .aspectMask
= VK_IMAGE_ASPECT_COLOR_BIT
,
1048 .baseMipLevel
= region
->srcSubresource
.mipLevel
,
1050 .baseArrayLayer
= src_base_layer
+ layer
,
1055 struct radv_image_view dest_iview
;
1056 radv_image_view_init(&dest_iview
, cmd_buffer
->device
,
1057 &(VkImageViewCreateInfo
) {
1058 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
1059 .image
= radv_image_to_handle(dest_image
),
1060 .viewType
= radv_meta_get_view_type(dest_image
),
1061 .format
= dest_image
->vk_format
,
1062 .subresourceRange
= {
1063 .aspectMask
= VK_IMAGE_ASPECT_COLOR_BIT
,
1064 .baseMipLevel
= region
->dstSubresource
.mipLevel
,
1066 .baseArrayLayer
= dest_base_layer
+ layer
,
1073 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer
->device
),
1074 &(VkFramebufferCreateInfo
) {
1075 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
1076 .attachmentCount
= 1,
1077 .pAttachments
= (VkImageView
[]) {
1078 radv_image_view_to_handle(&dest_iview
),
1080 .width
= extent
.width
+ dstOffset
.x
,
1081 .height
= extent
.height
+ dstOffset
.y
,
1083 }, &cmd_buffer
->pool
->alloc
, &fb
);
1085 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
1086 &(VkRenderPassBeginInfo
) {
1087 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
1091 .offset
= { dstOffset
.x
, dstOffset
.y
, },
1092 .extent
= { extent
.width
, extent
.height
},
1094 .clearValueCount
= 0,
1095 .pClearValues
= NULL
,
1096 }, VK_SUBPASS_CONTENTS_INLINE
);
1100 emit_resolve(cmd_buffer
,
1103 &(VkOffset2D
) { srcOffset
.x
, srcOffset
.y
},
1104 &(VkOffset2D
) { dstOffset
.x
, dstOffset
.y
},
1105 &(VkExtent2D
) { extent
.width
, extent
.height
});
1107 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
));
1109 radv_DestroyFramebuffer(radv_device_to_handle(cmd_buffer
->device
), fb
, &cmd_buffer
->pool
->alloc
);
1113 radv_meta_restore(&saved_state
, cmd_buffer
);
1118 * Emit any needed resolves for the current subpass.
1121 radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
)
1123 struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1124 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1125 struct radv_meta_saved_state saved_state
;
1126 struct radv_subpass_barrier barrier
;
1128 /* Resolves happen before the end-of-subpass barriers get executed,
1129 * so we have to make the attachment shader-readable */
1130 barrier
.src_stage_mask
= VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
;
1131 barrier
.src_access_mask
= VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
;
1132 barrier
.dst_access_mask
= VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
;
1133 radv_subpass_barrier(cmd_buffer
, &barrier
);
1135 radv_decompress_resolve_subpass_src(cmd_buffer
);
1137 radv_meta_save(&saved_state
, cmd_buffer
,
1138 RADV_META_SAVE_GRAPHICS_PIPELINE
|
1139 RADV_META_SAVE_CONSTANTS
|
1140 RADV_META_SAVE_DESCRIPTORS
);
1142 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
1143 struct radv_subpass_attachment src_att
= subpass
->color_attachments
[i
];
1144 struct radv_subpass_attachment dest_att
= subpass
->resolve_attachments
[i
];
1146 if (dest_att
.attachment
== VK_ATTACHMENT_UNUSED
)
1149 struct radv_image_view
*dest_iview
= cmd_buffer
->state
.framebuffer
->attachments
[dest_att
.attachment
];
1150 struct radv_image_view
*src_iview
= cmd_buffer
->state
.framebuffer
->attachments
[src_att
.attachment
];
1152 struct radv_subpass resolve_subpass
= {
1154 .color_attachments
= (struct radv_subpass_attachment
[]) { dest_att
},
1155 .depth_stencil_attachment
= NULL
,
1158 radv_cmd_buffer_set_subpass(cmd_buffer
, &resolve_subpass
);
1160 emit_resolve(cmd_buffer
,
1163 &(VkOffset2D
) { 0, 0 },
1164 &(VkOffset2D
) { 0, 0 },
1165 &(VkExtent2D
) { fb
->width
, fb
->height
});
1168 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
1170 radv_meta_restore(&saved_state
, cmd_buffer
);
1174 * Depth/stencil resolves for the current subpass.
1177 radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
,
1178 VkImageAspectFlags aspects
,
1179 VkResolveModeFlagBitsKHR resolve_mode
)
1181 struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1182 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1183 struct radv_meta_saved_state saved_state
;
1184 struct radv_subpass_barrier barrier
;
1186 /* Resolves happen before the end-of-subpass barriers get executed,
1187 * so we have to make the attachment shader-readable */
1188 barrier
.src_stage_mask
= VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
;
1189 barrier
.src_access_mask
= VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
;
1190 barrier
.dst_access_mask
= VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
;
1191 radv_subpass_barrier(cmd_buffer
, &barrier
);
1193 radv_decompress_resolve_subpass_src(cmd_buffer
);
1195 radv_meta_save(&saved_state
, cmd_buffer
,
1196 RADV_META_SAVE_GRAPHICS_PIPELINE
|
1197 RADV_META_SAVE_CONSTANTS
|
1198 RADV_META_SAVE_DESCRIPTORS
);
1200 struct radv_subpass_attachment src_att
= *subpass
->depth_stencil_attachment
;
1201 struct radv_subpass_attachment dst_att
= *subpass
->ds_resolve_attachment
;
1203 struct radv_image_view
*src_iview
=
1204 cmd_buffer
->state
.framebuffer
->attachments
[src_att
.attachment
];
1205 struct radv_image
*src_image
= src_iview
->image
;
1206 struct radv_image_view
*dst_iview
=
1207 cmd_buffer
->state
.framebuffer
->attachments
[dst_att
.attachment
];
1209 struct radv_subpass resolve_subpass
= {
1211 .color_attachments
= NULL
,
1212 .depth_stencil_attachment
= (struct radv_subpass_attachment
*) { &dst_att
},
1215 radv_cmd_buffer_set_subpass(cmd_buffer
, &resolve_subpass
);
1217 struct radv_image_view tsrc_iview
;
1218 radv_image_view_init(&tsrc_iview
, cmd_buffer
->device
,
1219 &(VkImageViewCreateInfo
) {
1220 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
1221 .image
= radv_image_to_handle(src_image
),
1222 .viewType
= radv_meta_get_view_type(src_image
),
1223 .format
= src_iview
->vk_format
,
1224 .subresourceRange
= {
1225 .aspectMask
= aspects
,
1228 .baseArrayLayer
= 0,
1233 emit_depth_stencil_resolve(cmd_buffer
, &tsrc_iview
, dst_iview
,
1234 &(VkOffset2D
) { 0, 0 },
1235 &(VkOffset2D
) { 0, 0 },
1236 &(VkExtent2D
) { fb
->width
, fb
->height
},
1240 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
1242 radv_meta_restore(&saved_state
, cmd_buffer
);