src/amd/vulkan/radv_meta_resolve_fs.c

   1 /*
   2  * Copyright © 2016 Dave Airlie
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24
  25 #include <assert.h>
  26 #include <stdbool.h>
  27
  28 #include "radv_meta.h"
  29 #include "radv_private.h"
  30 #include "nir/nir_builder.h"
  31 #include "sid.h"
  32 #include "vk_format.h"
  33
  34 static nir_shader *
  35 build_nir_vertex_shader(void)
  36 {
  37         const struct glsl_type *vec4 = glsl_vec4_type();
  38         nir_builder b;
  39
  40         nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
  41         b.shader->info.name = ralloc_strdup(b.shader, "meta_resolve_vs");
  42
  43         nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
  44                                                     vec4, "gl_Position");
  45         pos_out->data.location = VARYING_SLOT_POS;
  46
  47         nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
  48
  49         nir_store_var(&b, pos_out, outvec, 0xf);
  50         return b.shader;
  51 }
  52
  53 static nir_shader *
  54 build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, int samples)
  55 {
  56         nir_builder b;
  57         char name[64];
  58         const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
  59         const struct glsl_type *vec4 = glsl_vec4_type();
  60         const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS,
  61                                                                  false,
  62                                                                  false,
  63                                                                  GLSL_TYPE_FLOAT);
  64
  65         snprintf(name, 64, "meta_resolve_fs-%d-%s", samples, is_integer ? "int" : "float");
  66         nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
  67         b.shader->info.name = ralloc_strdup(b.shader, name);
  68
  69         nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
  70                                                       sampler_type, "s_tex");
  71         input_img->data.descriptor_set = 0;
  72         input_img->data.binding = 0;
  73
  74         nir_variable *fs_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "fs_pos_in");
  75         fs_pos_in->data.location = VARYING_SLOT_POS;
  76
  77         nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
  78                                                       vec4, "f_color");
  79         color_out->data.location = FRAG_RESULT_DATA0;
  80
  81         nir_ssa_def *pos_in = nir_load_var(&b, fs_pos_in);
  82         nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
  83         nir_intrinsic_set_base(src_offset, 0);
  84         nir_intrinsic_set_range(src_offset, 8);
  85         src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
  86         src_offset->num_components = 2;
  87         nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
  88         nir_builder_instr_insert(&b, &src_offset->instr);
  89
  90         nir_ssa_def *pos_int = nir_f2i32(&b, pos_in);
  91
  92         nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, pos_int, &src_offset->dest.ssa), 0x3);
  93         nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
  94
  95         radv_meta_build_resolve_shader_core(&b, is_integer, samples, input_img,
  96                                             color, img_coord);
  97
  98         nir_ssa_def *outval = nir_load_var(&b, color);
  99         nir_store_var(&b, color_out, outval, 0xf);
 100         return b.shader;
 101 }
 102
 103
 104 static VkResult
 105 create_layout(struct radv_device *device)
 106 {
 107         VkResult result;
 108         /*
 109          * one descriptors for the image being sampled
 110          */
 111         VkDescriptorSetLayoutCreateInfo ds_create_info = {
 112                 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
 113                 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
 114                 .bindingCount = 1,
 115                 .pBindings = (VkDescriptorSetLayoutBinding[]) {
 116                         {
 117                                 .binding = 0,
 118                                 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
 119                                 .descriptorCount = 1,
 120                                 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
 121                                 .pImmutableSamplers = NULL
 122                         },
 123                 }
 124         };
 125
 126         result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
 127                                                 &ds_create_info,
 128                                                 &device->meta_state.alloc,
 129                                                 &device->meta_state.resolve_fragment.ds_layout);
 130         if (result != VK_SUCCESS)
 131                 goto fail;
 132
 133
 134         VkPipelineLayoutCreateInfo pl_create_info = {
 135                 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
 136                 .setLayoutCount = 1,
 137                 .pSetLayouts = &device->meta_state.resolve_fragment.ds_layout,
 138                 .pushConstantRangeCount = 1,
 139                 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8},
 140         };
 141
 142         result = radv_CreatePipelineLayout(radv_device_to_handle(device),
 143                                           &pl_create_info,
 144                                           &device->meta_state.alloc,
 145                                           &device->meta_state.resolve_fragment.p_layout);
 146         if (result != VK_SUCCESS)
 147                 goto fail;
 148         return VK_SUCCESS;
 149 fail:
 150         return result;
 151 }
 152
 153 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
 154         .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
 155         .vertexBindingDescriptionCount = 0,
 156         .vertexAttributeDescriptionCount = 0,
 157 };
 158
 159 static VkResult
 160 create_resolve_pipeline(struct radv_device *device,
 161                         int samples_log2,
 162                         VkFormat format)
 163 {
 164         mtx_lock(&device->meta_state.mtx);
 165
 166         unsigned fs_key = radv_format_meta_fs_key(format);
 167         VkPipeline *pipeline = &device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
 168         if (*pipeline) {
 169                 mtx_unlock(&device->meta_state.mtx);
 170                 return VK_SUCCESS;
 171         }
 172
 173         VkResult result;
 174         bool is_integer = false;
 175         uint32_t samples = 1 << samples_log2;
 176         const VkPipelineVertexInputStateCreateInfo *vi_create_info;
 177         vi_create_info = &normal_vi_create_info;
 178         if (vk_format_is_int(format))
 179                 is_integer = true;
 180
 181         struct radv_shader_module fs = { .nir = NULL };
 182         fs.nir = build_resolve_fragment_shader(device, is_integer, samples);
 183         struct radv_shader_module vs = {
 184                 .nir = build_nir_vertex_shader(),
 185         };
 186
 187         VkRenderPass *rp = &device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key][0];
 188
 189         assert(!*rp);
 190
 191         VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
 192                 {
 193                         .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
 194                         .stage = VK_SHADER_STAGE_VERTEX_BIT,
 195                         .module = radv_shader_module_to_handle(&vs),
 196                         .pName = "main",
 197                         .pSpecializationInfo = NULL
 198                 }, {
 199                         .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
 200                         .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
 201                         .module = radv_shader_module_to_handle(&fs),
 202                         .pName = "main",
 203                         .pSpecializationInfo = NULL
 204                 },
 205         };
 206
 207
 208         for (unsigned dst_layout = 0; dst_layout < RADV_META_DST_LAYOUT_COUNT; ++dst_layout) {
 209                 VkImageLayout layout = radv_meta_dst_layout_to_layout(dst_layout);
 210                 result = radv_CreateRenderPass(radv_device_to_handle(device),
 211                                         &(VkRenderPassCreateInfo) {
 212                                                 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
 213                                                 .attachmentCount = 1,
 214                                                 .pAttachments = &(VkAttachmentDescription) {
 215                                                         .format = format,
 216                                                         .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
 217                                                         .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
 218                                                         .initialLayout = layout,
 219                                                         .finalLayout = layout,
 220                                                 },
 221                                                 .subpassCount = 1,
 222                                                 .pSubpasses = &(VkSubpassDescription) {
 223                                                         .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
 224                                                         .inputAttachmentCount = 0,
 225                                                         .colorAttachmentCount = 1,
 226                                                         .pColorAttachments = &(VkAttachmentReference) {
 227                                                                 .attachment = 0,
 228                                                                 .layout = layout,
 229                                                         },
 230                                                 .pResolveAttachments = NULL,
 231                                                 .pDepthStencilAttachment = &(VkAttachmentReference) {
 232                                                         .attachment = VK_ATTACHMENT_UNUSED,
 233                                                         .layout = VK_IMAGE_LAYOUT_GENERAL,
 234                                                 },
 235                                                 .preserveAttachmentCount = 0,
 236                                                 .pPreserveAttachments = NULL,
 237                                         },
 238                                         .dependencyCount = 0,
 239                                 }, &device->meta_state.alloc, rp + dst_layout);
 240         }
 241
 242
 243         const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
 244                 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
 245                 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
 246                 .pStages = pipeline_shader_stages,
 247                 .pVertexInputState = vi_create_info,
 248                 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
 249                         .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
 250                         .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
 251                         .primitiveRestartEnable = false,
 252                 },
 253                 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
 254                         .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
 255                         .viewportCount = 1,
 256                         .scissorCount = 1,
 257                 },
 258                 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
 259                         .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
 260                         .rasterizerDiscardEnable = false,
 261                         .polygonMode = VK_POLYGON_MODE_FILL,
 262                         .cullMode = VK_CULL_MODE_NONE,
 263                         .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
 264                 },
 265                 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
 266                         .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
 267                         .rasterizationSamples = 1,
 268                         .sampleShadingEnable = false,
 269                         .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
 270                 },
 271                 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
 272                         .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
 273                         .attachmentCount = 1,
 274                         .pAttachments = (VkPipelineColorBlendAttachmentState []) {
 275                                 { .colorWriteMask =
 276                                   VK_COLOR_COMPONENT_A_BIT |
 277                                   VK_COLOR_COMPONENT_R_BIT |
 278                                   VK_COLOR_COMPONENT_G_BIT |
 279                                   VK_COLOR_COMPONENT_B_BIT },
 280                         }
 281                 },
 282                 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
 283                         .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
 284                         .dynamicStateCount = 9,
 285                         .pDynamicStates = (VkDynamicState[]) {
 286                                 VK_DYNAMIC_STATE_VIEWPORT,
 287                                 VK_DYNAMIC_STATE_SCISSOR,
 288                                 VK_DYNAMIC_STATE_LINE_WIDTH,
 289                                 VK_DYNAMIC_STATE_DEPTH_BIAS,
 290                                 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
 291                                 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
 292                                 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
 293                                 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
 294                                 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
 295                         },
 296                 },
 297                 .flags = 0,
 298                 .layout = device->meta_state.resolve_fragment.p_layout,
 299                 .renderPass = *rp,
 300                 .subpass = 0,
 301         };
 302
 303         const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
 304                 .use_rectlist = true
 305         };
 306
 307         result = radv_graphics_pipeline_create(radv_device_to_handle(device),
 308                                                radv_pipeline_cache_to_handle(&device->meta_state.cache),
 309                                                &vk_pipeline_info, &radv_pipeline_info,
 310                                                &device->meta_state.alloc,
 311                                                pipeline);
 312         ralloc_free(vs.nir);
 313         ralloc_free(fs.nir);
 314
 315         mtx_unlock(&device->meta_state.mtx);
 316         return result;
 317 }
 318
 319 enum {
 320         DEPTH_RESOLVE,
 321         STENCIL_RESOLVE
 322 };
 323
 324 static const char *
 325 get_resolve_mode_str(VkResolveModeFlagBitsKHR resolve_mode)
 326 {
 327         switch (resolve_mode) {
 328         case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR:
 329                 return "zero";
 330         case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
 331                 return "average";
 332         case VK_RESOLVE_MODE_MIN_BIT_KHR:
 333                 return "min";
 334         case VK_RESOLVE_MODE_MAX_BIT_KHR:
 335                 return "max";
 336         default:
 337                 unreachable("invalid resolve mode");
 338         }
 339 }
 340
 341 static nir_shader *
 342 build_depth_stencil_resolve_fragment_shader(struct radv_device *dev, int samples,
 343                                             int index,
 344                                             VkResolveModeFlagBitsKHR resolve_mode)
 345 {
 346         nir_builder b;
 347         char name[64];
 348         const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
 349         const struct glsl_type *vec4 = glsl_vec4_type();
 350         const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D,
 351                                                                  false,
 352                                                                  false,
 353                                                                  GLSL_TYPE_FLOAT);
 354
 355         snprintf(name, 64, "meta_resolve_fs_%s-%s-%d",
 356                  index == DEPTH_RESOLVE ? "depth" : "stencil",
 357                  get_resolve_mode_str(resolve_mode), samples);
 358
 359         nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
 360         b.shader->info.name = ralloc_strdup(b.shader, name);
 361
 362         nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
 363                                                       sampler_type, "s_tex");
 364         input_img->data.descriptor_set = 0;
 365         input_img->data.binding = 0;
 366
 367         nir_variable *fs_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "fs_pos_in");
 368         fs_pos_in->data.location = VARYING_SLOT_POS;
 369
 370         nir_variable *fs_out = nir_variable_create(b.shader,
 371                                                    nir_var_shader_out, vec4,
 372                                                    "f_out");
 373         fs_out->data.location =
 374                 index == DEPTH_RESOLVE ? FRAG_RESULT_DEPTH : FRAG_RESULT_STENCIL;
 375
 376         nir_ssa_def *pos_in = nir_load_var(&b, fs_pos_in);
 377
 378         nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
 379         nir_intrinsic_set_base(src_offset, 0);
 380         nir_intrinsic_set_range(src_offset, 8);
 381         src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
 382         src_offset->num_components = 2;
 383         nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
 384         nir_builder_instr_insert(&b, &src_offset->instr);
 385
 386         nir_ssa_def *pos_int = nir_f2i32(&b, pos_in);
 387
 388         nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, pos_int, &src_offset->dest.ssa), 0x3);
 389
 390         nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa;
 391
 392         nir_alu_type type = index == DEPTH_RESOLVE ? nir_type_float : nir_type_uint;
 393
 394         nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
 395         tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
 396         tex->op = nir_texop_txf_ms;
 397         tex->src[0].src_type = nir_tex_src_coord;
 398         tex->src[0].src = nir_src_for_ssa(img_coord);
 399         tex->src[1].src_type = nir_tex_src_ms_index;
 400         tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
 401         tex->src[2].src_type = nir_tex_src_texture_deref;
 402         tex->src[2].src = nir_src_for_ssa(input_img_deref);
 403         tex->dest_type = type;
 404         tex->is_array = false;
 405         tex->coord_components = 2;
 406
 407         nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
 408         nir_builder_instr_insert(&b, &tex->instr);
 409
 410         nir_ssa_def *outval = &tex->dest.ssa;
 411
 412         if (resolve_mode != VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR) {
 413                 for (int i = 1; i < samples; i++) {
 414                         nir_tex_instr *tex_add = nir_tex_instr_create(b.shader, 3);
 415                         tex_add->sampler_dim = GLSL_SAMPLER_DIM_MS;
 416                         tex_add->op = nir_texop_txf_ms;
 417                         tex_add->src[0].src_type = nir_tex_src_coord;
 418                         tex_add->src[0].src = nir_src_for_ssa(img_coord);
 419                         tex_add->src[1].src_type = nir_tex_src_ms_index;
 420                         tex_add->src[1].src = nir_src_for_ssa(nir_imm_int(&b, i));
 421                         tex_add->src[2].src_type = nir_tex_src_texture_deref;
 422                         tex_add->src[2].src = nir_src_for_ssa(input_img_deref);
 423                         tex_add->dest_type = type;
 424                         tex_add->is_array = false;
 425                         tex_add->coord_components = 2;
 426
 427                         nir_ssa_dest_init(&tex_add->instr, &tex_add->dest, 4, 32, "tex");
 428                         nir_builder_instr_insert(&b, &tex_add->instr);
 429
 430                         switch (resolve_mode) {
 431                         case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
 432                                 assert(index == DEPTH_RESOLVE);
 433                                 outval = nir_fadd(&b, outval, &tex_add->dest.ssa);
 434                                 break;
 435                         case VK_RESOLVE_MODE_MIN_BIT_KHR:
 436                                 if (index == DEPTH_RESOLVE)
 437                                         outval = nir_fmin(&b, outval, &tex_add->dest.ssa);
 438                                 else
 439                                         outval = nir_umin(&b, outval, &tex_add->dest.ssa);
 440                                 break;
 441                         case VK_RESOLVE_MODE_MAX_BIT_KHR:
 442                                 if (index == DEPTH_RESOLVE)
 443                                         outval = nir_fmax(&b, outval, &tex_add->dest.ssa);
 444                                 else
 445                                         outval = nir_umax(&b, outval, &tex_add->dest.ssa);
 446                                 break;
 447                         default:
 448                                 unreachable("invalid resolve mode");
 449                         }
 450                 }
 451
 452                 if (resolve_mode == VK_RESOLVE_MODE_AVERAGE_BIT_KHR)
 453                         outval = nir_fdiv(&b, outval, nir_imm_float(&b, samples));
 454         }
 455
 456         nir_store_var(&b, fs_out, outval, 0x1);
 457
 458         return b.shader;
 459 }
 460
 461 static VkResult
 462 create_depth_stencil_resolve_pipeline(struct radv_device *device,
 463                                       int samples_log2,
 464                                       int index,
 465                                       VkResolveModeFlagBitsKHR resolve_mode)
 466 {
 467         VkRenderPass *render_pass;
 468         VkPipeline *pipeline;
 469         VkFormat src_format;
 470         VkResult result;
 471
 472         mtx_lock(&device->meta_state.mtx);
 473
 474         switch (resolve_mode) {
 475         case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR:
 476                 if (index == DEPTH_RESOLVE)
 477                         pipeline = &device->meta_state.resolve_fragment.depth_zero_pipeline;
 478                 else
 479                         pipeline = &device->meta_state.resolve_fragment.stencil_zero_pipeline;
 480                 break;
 481         case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
 482                 assert(index == DEPTH_RESOLVE);
 483                 pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].average_pipeline;
 484                 break;
 485         case VK_RESOLVE_MODE_MIN_BIT_KHR:
 486                 if (index == DEPTH_RESOLVE)
 487                         pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].min_pipeline;
 488                 else
 489                         pipeline = &device->meta_state.resolve_fragment.stencil[samples_log2].min_pipeline;
 490                 break;
 491         case VK_RESOLVE_MODE_MAX_BIT_KHR:
 492                 if (index == DEPTH_RESOLVE)
 493                         pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].max_pipeline;
 494                 else
 495                         pipeline = &device->meta_state.resolve_fragment.stencil[samples_log2].max_pipeline;
 496                 break;
 497         default:
 498                 unreachable("invalid resolve mode");
 499         }
 500
 501         if (*pipeline) {
 502                 mtx_unlock(&device->meta_state.mtx);
 503                 return VK_SUCCESS;
 504         }
 505
 506         struct radv_shader_module fs = { .nir = NULL };
 507         struct radv_shader_module vs = { .nir = NULL };
 508         uint32_t samples = 1 << samples_log2;
 509
 510         vs.nir = build_nir_vertex_shader();
 511         fs.nir = build_depth_stencil_resolve_fragment_shader(device, samples,
 512                                                              index, resolve_mode);
 513
 514         VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
 515                 {
 516                         .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
 517                         .stage = VK_SHADER_STAGE_VERTEX_BIT,
 518                         .module = radv_shader_module_to_handle(&vs),
 519                         .pName = "main",
 520                         .pSpecializationInfo = NULL
 521                 }, {
 522                         .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
 523                         .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
 524                         .module = radv_shader_module_to_handle(&fs),
 525                         .pName = "main",
 526                         .pSpecializationInfo = NULL
 527                 },
 528         };
 529
 530         if (index == DEPTH_RESOLVE) {
 531                 src_format = VK_FORMAT_D32_SFLOAT;
 532                 render_pass = &device->meta_state.resolve_fragment.depth_render_pass;
 533         } else {
 534                 render_pass = &device->meta_state.resolve_fragment.stencil_render_pass;
 535                 src_format = VK_FORMAT_S8_UINT;
 536         }
 537
 538         if (!*render_pass) {
 539                 result = radv_CreateRenderPass(radv_device_to_handle(device),
 540                                                &(VkRenderPassCreateInfo) {
 541                                                         .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
 542                                                         .attachmentCount = 1,
 543                                                         .pAttachments = &(VkAttachmentDescription) {
 544                                                                 .format = src_format,
 545                                                                 .loadOp = VK_ATTACHMENT_LOAD_OP_DONT_CARE,
 546                                                                 .storeOp = VK_ATTACHMENT_LOAD_OP_DONT_CARE,
 547                                                                 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
 548                                                                 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
 549                                                                 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
 550                                                                 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
 551                                                         },
 552                                                         .subpassCount = 1,
 553                                                         .pSubpasses = &(VkSubpassDescription) {
 554                                                                 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
 555                                                                 .inputAttachmentCount = 0,
 556                                                                 .colorAttachmentCount = 0,
 557                                                                 .pColorAttachments = NULL,
 558                                                         .pResolveAttachments = NULL,
 559                                                         .pDepthStencilAttachment = &(VkAttachmentReference) {
 560                                                                 .attachment = 0,
 561                                                                 .layout = VK_IMAGE_LAYOUT_GENERAL,
 562                                                         },
 563                                                         .preserveAttachmentCount = 0,
 564                                                         .pPreserveAttachments = NULL,
 565                                                 },
 566                                                 .dependencyCount = 0,
 567                                         }, &device->meta_state.alloc, render_pass);
 568         }
 569
 570         VkStencilOp stencil_op =
 571                 index == DEPTH_RESOLVE ? VK_STENCIL_OP_KEEP : VK_STENCIL_OP_REPLACE;
 572
 573         VkPipelineDepthStencilStateCreateInfo depth_stencil_state = {
 574                 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
 575                 .depthTestEnable = true,
 576                 .depthWriteEnable = index == DEPTH_RESOLVE,
 577                 .stencilTestEnable = index == STENCIL_RESOLVE,
 578                 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
 579                 .front = {
 580                         .failOp = stencil_op,
 581                         .passOp = stencil_op,
 582                         .depthFailOp = stencil_op,
 583                         .compareOp = VK_COMPARE_OP_ALWAYS,
 584                 },
 585                 .back = {
 586                         .failOp = stencil_op,
 587                         .passOp = stencil_op,
 588                         .depthFailOp = stencil_op,
 589                         .compareOp = VK_COMPARE_OP_ALWAYS,
 590                 }
 591         };
 592
 593         const VkPipelineVertexInputStateCreateInfo *vi_create_info;
 594         vi_create_info = &normal_vi_create_info;
 595
 596         const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
 597                 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
 598                 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
 599                 .pStages = pipeline_shader_stages,
 600                 .pVertexInputState = vi_create_info,
 601                 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
 602                         .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
 603                         .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
 604                         .primitiveRestartEnable = false,
 605                 },
 606                 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
 607                         .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
 608                         .viewportCount = 1,
 609                         .scissorCount = 1,
 610                 },
 611                 .pDepthStencilState = &depth_stencil_state,
 612                 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
 613                         .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
 614                         .rasterizerDiscardEnable = false,
 615                         .polygonMode = VK_POLYGON_MODE_FILL,
 616                         .cullMode = VK_CULL_MODE_NONE,
 617                         .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
 618                 },
 619                 .pMultisampleState = NULL,
 620                 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
 621                         .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
 622                         .attachmentCount = 0,
 623                         .pAttachments = (VkPipelineColorBlendAttachmentState []) {
 624                                 { .colorWriteMask =
 625                                   VK_COLOR_COMPONENT_A_BIT |
 626                                   VK_COLOR_COMPONENT_R_BIT |
 627                                   VK_COLOR_COMPONENT_G_BIT |
 628                                   VK_COLOR_COMPONENT_B_BIT },
 629                         }
 630                 },
 631                 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
 632                         .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
 633                         .dynamicStateCount = 9,
 634                         .pDynamicStates = (VkDynamicState[]) {
 635                                 VK_DYNAMIC_STATE_VIEWPORT,
 636                                 VK_DYNAMIC_STATE_SCISSOR,
 637                                 VK_DYNAMIC_STATE_LINE_WIDTH,
 638                                 VK_DYNAMIC_STATE_DEPTH_BIAS,
 639                                 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
 640                                 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
 641                                 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
 642                                 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
 643                                 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
 644                         },
 645                 },
 646                 .flags = 0,
 647                 .layout = device->meta_state.resolve_fragment.p_layout,
 648                 .renderPass = *render_pass,
 649                 .subpass = 0,
 650         };
 651
 652         const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
 653                 .use_rectlist = true
 654         };
 655
 656         result = radv_graphics_pipeline_create(radv_device_to_handle(device),
 657                                                radv_pipeline_cache_to_handle(&device->meta_state.cache),
 658                                                &vk_pipeline_info, &radv_pipeline_info,
 659                                                &device->meta_state.alloc,
 660                                                pipeline);
 661
 662         ralloc_free(vs.nir);
 663         ralloc_free(fs.nir);
 664
 665         mtx_unlock(&device->meta_state.mtx);
 666         return result;
 667 }
 668
 669 VkResult
 670 radv_device_init_meta_resolve_fragment_state(struct radv_device *device, bool on_demand)
 671 {
 672         VkResult res;
 673
 674         res = create_layout(device);
 675         if (res != VK_SUCCESS)
 676                 goto fail;
 677
 678         if (on_demand)
 679                 return VK_SUCCESS;
 680
 681         for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
 682                 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
 683                         res = create_resolve_pipeline(device, i, radv_fs_key_format_exemplars[j]);
 684                         if (res != VK_SUCCESS)
 685                                 goto fail;
 686                 }
 687
 688                 res = create_depth_stencil_resolve_pipeline(device, i, DEPTH_RESOLVE,
 689                                                             VK_RESOLVE_MODE_AVERAGE_BIT_KHR);
 690                 if (res != VK_SUCCESS)
 691                         goto fail;
 692
 693                 res = create_depth_stencil_resolve_pipeline(device, i, DEPTH_RESOLVE,
 694                                                             VK_RESOLVE_MODE_MIN_BIT_KHR);
 695                 if (res != VK_SUCCESS)
 696                         goto fail;
 697
 698                 res = create_depth_stencil_resolve_pipeline(device, i, DEPTH_RESOLVE,
 699                                                             VK_RESOLVE_MODE_MAX_BIT_KHR);
 700                 if (res != VK_SUCCESS)
 701                         goto fail;
 702
 703                 res = create_depth_stencil_resolve_pipeline(device, i, STENCIL_RESOLVE,
 704                                                             VK_RESOLVE_MODE_MIN_BIT_KHR);
 705                 if (res != VK_SUCCESS)
 706                         goto fail;
 707
 708                 res = create_depth_stencil_resolve_pipeline(device, i, STENCIL_RESOLVE,
 709                                                             VK_RESOLVE_MODE_MAX_BIT_KHR);
 710                 if (res != VK_SUCCESS)
 711                         goto fail;
 712         }
 713
 714         res = create_depth_stencil_resolve_pipeline(device, 0, DEPTH_RESOLVE,
 715                                                     VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR);
 716         if (res != VK_SUCCESS)
 717                 goto fail;
 718
 719         res = create_depth_stencil_resolve_pipeline(device, 0, STENCIL_RESOLVE,
 720                                                     VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR);
 721         if (res != VK_SUCCESS)
 722                 goto fail;
 723
 724         return VK_SUCCESS;
 725 fail:
 726         radv_device_finish_meta_resolve_fragment_state(device);
 727         return res;
 728 }
 729
 730 void
 731 radv_device_finish_meta_resolve_fragment_state(struct radv_device *device)
 732 {
 733         struct radv_meta_state *state = &device->meta_state;
 734         for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
 735                 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
 736                         for(unsigned k =0; k < RADV_META_DST_LAYOUT_COUNT; ++k) {
 737                                 radv_DestroyRenderPass(radv_device_to_handle(device),
 738                                                        state->resolve_fragment.rc[i].render_pass[j][k],
 739                                                        &state->alloc);
 740                         }
 741                         radv_DestroyPipeline(radv_device_to_handle(device),
 742                                              state->resolve_fragment.rc[i].pipeline[j],
 743                                              &state->alloc);
 744                 }
 745
 746                 radv_DestroyPipeline(radv_device_to_handle(device),
 747                                      state->resolve_fragment.depth[i].average_pipeline,
 748                                      &state->alloc);
 749
 750                 radv_DestroyPipeline(radv_device_to_handle(device),
 751                                      state->resolve_fragment.depth[i].max_pipeline,
 752                                      &state->alloc);
 753
 754                 radv_DestroyPipeline(radv_device_to_handle(device),
 755                                      state->resolve_fragment.depth[i].min_pipeline,
 756                                      &state->alloc);
 757
 758                 radv_DestroyPipeline(radv_device_to_handle(device),
 759                                      state->resolve_fragment.stencil[i].max_pipeline,
 760                                      &state->alloc);
 761
 762                 radv_DestroyPipeline(radv_device_to_handle(device),
 763                                      state->resolve_fragment.stencil[i].min_pipeline,
 764                                      &state->alloc);
 765         }
 766
 767         radv_DestroyRenderPass(radv_device_to_handle(device),
 768                                state->resolve_fragment.depth_render_pass,
 769                                &state->alloc);
 770         radv_DestroyRenderPass(radv_device_to_handle(device),
 771                                state->resolve_fragment.stencil_render_pass,
 772                                &state->alloc);
 773
 774         radv_DestroyPipeline(radv_device_to_handle(device),
 775                              state->resolve_fragment.depth_zero_pipeline,
 776                              &state->alloc);
 777         radv_DestroyPipeline(radv_device_to_handle(device),
 778                              state->resolve_fragment.stencil_zero_pipeline,
 779                              &state->alloc);
 780
 781         radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
 782                                         state->resolve_fragment.ds_layout,
 783                                         &state->alloc);
 784         radv_DestroyPipelineLayout(radv_device_to_handle(device),
 785                                    state->resolve_fragment.p_layout,
 786                                    &state->alloc);
 787 }
 788
 789 static VkPipeline *
 790 radv_get_resolve_pipeline(struct radv_cmd_buffer *cmd_buffer,
 791                           struct radv_image_view *src_iview,
 792                           struct radv_image_view *dst_iview)
 793 {
 794         struct radv_device *device = cmd_buffer->device;
 795         unsigned fs_key = radv_format_meta_fs_key(dst_iview->vk_format);
 796         const uint32_t samples = src_iview->image->info.samples;
 797         const uint32_t samples_log2 = ffs(samples) - 1;
 798         VkPipeline *pipeline;
 799
 800         pipeline = &device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
 801         if (!*pipeline ) {
 802                 VkResult ret;
 803
 804                 ret = create_resolve_pipeline(device, samples_log2,
 805                                               radv_fs_key_format_exemplars[fs_key]);
 806                 if (ret != VK_SUCCESS) {
 807                         cmd_buffer->record_result = ret;
 808                         return NULL;
 809                 }
 810         }
 811
 812         return pipeline;
 813 }
 814
 815 static void
 816 emit_resolve(struct radv_cmd_buffer *cmd_buffer,
 817              struct radv_image_view *src_iview,
 818              struct radv_image_view *dest_iview,
 819              const VkOffset2D *src_offset,
 820              const VkOffset2D *dest_offset,
 821              const VkExtent2D *resolve_extent)
 822 {
 823         struct radv_device *device = cmd_buffer->device;
 824         VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
 825         VkPipeline *pipeline;
 826
 827         radv_meta_push_descriptor_set(cmd_buffer,
 828                                       VK_PIPELINE_BIND_POINT_GRAPHICS,
 829                                       cmd_buffer->device->meta_state.resolve_fragment.p_layout,
 830                                       0, /* set */
 831                                       1, /* descriptorWriteCount */
 832                                       (VkWriteDescriptorSet[]) {
 833                                               {
 834                                                       .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
 835                                                       .dstBinding = 0,
 836                                                       .dstArrayElement = 0,
 837                                                       .descriptorCount = 1,
 838                                                       .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
 839                                                       .pImageInfo = (VkDescriptorImageInfo[]) {
 840                                                       {
 841                                                       .sampler = VK_NULL_HANDLE,
 842                                                       .imageView = radv_image_view_to_handle(src_iview),
 843                                                       .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
 844                                                       },
 845                                                       }
 846                                               },
 847                                       });
 848
 849         cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
 850
 851         unsigned push_constants[2] = {
 852                 src_offset->x - dest_offset->x,
 853                 src_offset->y - dest_offset->y,
 854         };
 855         radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
 856                               device->meta_state.resolve_fragment.p_layout,
 857                               VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8,
 858                               push_constants);
 859
 860         pipeline = radv_get_resolve_pipeline(cmd_buffer, src_iview, dest_iview);
 861
 862         radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
 863                              *pipeline);
 864
 865         radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
 866                 .x = dest_offset->x,
 867                 .y = dest_offset->y,
 868                 .width = resolve_extent->width,
 869                 .height = resolve_extent->height,
 870                 .minDepth = 0.0f,
 871                 .maxDepth = 1.0f
 872         });
 873
 874         radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
 875                 .offset = *dest_offset,
 876                 .extent = *resolve_extent,
 877         });
 878
 879         radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
 880         cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
 881 }
 882
 883 static void
 884 emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer,
 885                            struct radv_image_view *src_iview,
 886                            struct radv_image_view *dst_iview,
 887                            const VkOffset2D *src_offset,
 888                            const VkOffset2D *dst_offset,
 889                            const VkExtent2D *resolve_extent,
 890                            VkImageAspectFlags aspects,
 891                            VkResolveModeFlagBitsKHR resolve_mode)
 892 {
 893         struct radv_device *device = cmd_buffer->device;
 894         const uint32_t samples = src_iview->image->info.samples;
 895         const uint32_t samples_log2 = ffs(samples) - 1;
 896         VkPipeline *pipeline;
 897
 898         radv_meta_push_descriptor_set(cmd_buffer,
 899                                       VK_PIPELINE_BIND_POINT_GRAPHICS,
 900                                       cmd_buffer->device->meta_state.resolve_fragment.p_layout,
 901                                       0, /* set */
 902                                       1, /* descriptorWriteCount */
 903                                       (VkWriteDescriptorSet[]) {
 904                                               {
 905                                                       .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
 906                                                       .dstBinding = 0,
 907                                                       .dstArrayElement = 0,
 908                                                       .descriptorCount = 1,
 909                                                       .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
 910                                                       .pImageInfo = (VkDescriptorImageInfo[]) {
 911                                                       {
 912                                                       .sampler = VK_NULL_HANDLE,
 913                                                       .imageView = radv_image_view_to_handle(src_iview),
 914                                                       .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
 915                                                       },
 916                                                       }
 917                                               },
 918                                       });
 919
 920         unsigned push_constants[2] = {
 921                 src_offset->x - dst_offset->x,
 922                 src_offset->y - dst_offset->y,
 923         };
 924         radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
 925                               device->meta_state.resolve_fragment.p_layout,
 926                               VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8,
 927                               push_constants);
 928
 929         switch (resolve_mode) {
 930         case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR:
 931                 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
 932                         pipeline = &device->meta_state.resolve_fragment.depth_zero_pipeline;
 933                 else
 934                         pipeline = &device->meta_state.resolve_fragment.stencil_zero_pipeline;
 935                 break;
 936         case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
 937                 assert(aspects == VK_IMAGE_ASPECT_DEPTH_BIT);
 938                 pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].average_pipeline;
 939                 break;
 940         case VK_RESOLVE_MODE_MIN_BIT_KHR:
 941                 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
 942                         pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].min_pipeline;
 943                 else
 944                         pipeline = &device->meta_state.resolve_fragment.stencil[samples_log2].min_pipeline;
 945                 break;
 946         case VK_RESOLVE_MODE_MAX_BIT_KHR:
 947                 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
 948                         pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].max_pipeline;
 949                 else
 950                         pipeline = &device->meta_state.resolve_fragment.stencil[samples_log2].max_pipeline;
 951                 break;
 952         default:
 953                 unreachable("invalid resolve mode");
 954         }
 955
 956         if (!*pipeline) {
 957                 int index = aspects == VK_IMAGE_ASPECT_DEPTH_BIT ? DEPTH_RESOLVE : STENCIL_RESOLVE;
 958                 VkResult ret;
 959
 960                 ret = create_depth_stencil_resolve_pipeline(device, samples_log2,
 961                                                             index, resolve_mode);
 962                 if (ret != VK_SUCCESS) {
 963                         cmd_buffer->record_result = ret;
 964                         return;
 965                 }
 966         }
 967
 968         radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
 969                              VK_PIPELINE_BIND_POINT_GRAPHICS, *pipeline);
 970
 971         radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
 972                 .x = dst_offset->x,
 973                 .y = dst_offset->y,
 974                 .width = resolve_extent->width,
 975                 .height = resolve_extent->height,
 976                 .minDepth = 0.0f,
 977                 .maxDepth = 1.0f
 978         });
 979
 980         radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
 981                 .offset = *dst_offset,
 982                 .extent = *resolve_extent,
 983         });
 984
 985         radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
 986 }
 987
 988 void radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer,
 989                                       struct radv_image *src_image,
 990                                       VkImageLayout src_image_layout,
 991                                       struct radv_image *dest_image,
 992                                       VkImageLayout dest_image_layout,
 993                                       uint32_t region_count,
 994                                       const VkImageResolve *regions)
 995 {
 996         struct radv_device *device = cmd_buffer->device;
 997         struct radv_meta_saved_state saved_state;
 998         const uint32_t samples = src_image->info.samples;
 999         const uint32_t samples_log2 = ffs(samples) - 1;
1000         unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format);
1001         unsigned dst_layout = radv_meta_dst_layout_from_layout(dest_image_layout);
1002         VkRenderPass rp;
1003
1004         radv_decompress_resolve_src(cmd_buffer, src_image, src_image_layout,
1005                                     region_count, regions);
1006
1007         if (!device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key][dst_layout]) {
1008                 VkResult ret = create_resolve_pipeline(device, samples_log2, radv_fs_key_format_exemplars[fs_key]);
1009                 if (ret != VK_SUCCESS) {
1010                         cmd_buffer->record_result = ret;
1011                         return;
1012                 }
1013         }
1014
1015         rp = device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key][dst_layout];
1016
1017         radv_meta_save(&saved_state, cmd_buffer,
1018                        RADV_META_SAVE_GRAPHICS_PIPELINE |
1019                        RADV_META_SAVE_CONSTANTS |
1020                        RADV_META_SAVE_DESCRIPTORS);
1021
1022         for (uint32_t r = 0; r < region_count; ++r) {
1023                 const VkImageResolve *region = &regions[r];
1024
1025                 assert(region->srcSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
1026                 assert(region->dstSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
1027                 assert(region->srcSubresource.layerCount == region->dstSubresource.layerCount);
1028
1029                 const uint32_t src_base_layer =
1030                         radv_meta_get_iview_layer(src_image, &region->srcSubresource,
1031                                                   &region->srcOffset);
1032
1033                 const uint32_t dest_base_layer =
1034                         radv_meta_get_iview_layer(dest_image, &region->dstSubresource,
1035                                                   &region->dstOffset);
1036
1037                 const struct VkExtent3D extent =
1038                         radv_sanitize_image_extent(src_image->type, region->extent);
1039                 const struct VkOffset3D srcOffset =
1040                         radv_sanitize_image_offset(src_image->type, region->srcOffset);
1041                 const struct VkOffset3D dstOffset =
1042                         radv_sanitize_image_offset(dest_image->type, region->dstOffset);
1043
1044                 for (uint32_t layer = 0; layer < region->srcSubresource.layerCount;
1045                      ++layer) {
1046
1047                         struct radv_image_view src_iview;
1048                         radv_image_view_init(&src_iview, cmd_buffer->device,
1049                                              &(VkImageViewCreateInfo) {
1050                                                      .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1051                                                              .image = radv_image_to_handle(src_image),
1052                                                              .viewType = radv_meta_get_view_type(src_image),
1053                                                              .format = src_image->vk_format,
1054                                                              .subresourceRange = {
1055                                                              .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1056                                                              .baseMipLevel = region->srcSubresource.mipLevel,
1057                                                              .levelCount = 1,
1058                                                              .baseArrayLayer = src_base_layer + layer,
1059                                                              .layerCount = 1,
1060                                                      },
1061                                              });
1062
1063                         struct radv_image_view dest_iview;
1064                         radv_image_view_init(&dest_iview, cmd_buffer->device,
1065                                              &(VkImageViewCreateInfo) {
1066                                                      .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1067                                                              .image = radv_image_to_handle(dest_image),
1068                                                              .viewType = radv_meta_get_view_type(dest_image),
1069                                                              .format = dest_image->vk_format,
1070                                                              .subresourceRange = {
1071                                                              .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1072                                                              .baseMipLevel = region->dstSubresource.mipLevel,
1073                                                              .levelCount = 1,
1074                                                              .baseArrayLayer = dest_base_layer + layer,
1075                                                              .layerCount = 1,
1076                                                      },
1077                                              });
1078
1079
1080                         VkFramebuffer fb;
1081                         radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer->device),
1082                                &(VkFramebufferCreateInfo) {
1083                                        .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1084                                                .attachmentCount = 1,
1085                                                .pAttachments = (VkImageView[]) {
1086                                                radv_image_view_to_handle(&dest_iview),
1087                                        },
1088                                        .width = extent.width + dstOffset.x,
1089                                        .height = extent.height + dstOffset.y,
1090                                        .layers = 1
1091                                 }, &cmd_buffer->pool->alloc, &fb);
1092
1093                         radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1094                                                 &(VkRenderPassBeginInfo) {
1095                                                         .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1096                                                                 .renderPass = rp,
1097                                                                 .framebuffer = fb,
1098                                                                 .renderArea = {
1099                                                                 .offset = { dstOffset.x, dstOffset.y, },
1100                                                                 .extent = { extent.width, extent.height },
1101                                                         },
1102                                                                 .clearValueCount = 0,
1103                                                                 .pClearValues = NULL,
1104                                                 }, VK_SUBPASS_CONTENTS_INLINE);
1105
1106
1107
1108                         emit_resolve(cmd_buffer,
1109                                      &src_iview,
1110                                      &dest_iview,
1111                                      &(VkOffset2D) { srcOffset.x, srcOffset.y },
1112                                      &(VkOffset2D) { dstOffset.x, dstOffset.y },
1113                                      &(VkExtent2D) { extent.width, extent.height });
1114
1115                         radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1116
1117                         radv_DestroyFramebuffer(radv_device_to_handle(cmd_buffer->device), fb, &cmd_buffer->pool->alloc);
1118                 }
1119         }
1120
1121         radv_meta_restore(&saved_state, cmd_buffer);
1122 }
1123
1124
1125 /**
1126  * Emit any needed resolves for the current subpass.
1127  */
1128 void
1129 radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer)
1130 {
1131         struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
1132         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1133         struct radv_meta_saved_state saved_state;
1134         struct radv_subpass_barrier barrier;
1135
1136         /* Resolves happen before the end-of-subpass barriers get executed,
1137          * so we have to make the attachment shader-readable */
1138         barrier.src_stage_mask = VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
1139         barrier.src_access_mask = VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT;
1140         barrier.dst_access_mask = VK_ACCESS_INPUT_ATTACHMENT_READ_BIT;
1141         radv_subpass_barrier(cmd_buffer, &barrier);
1142
1143         radv_decompress_resolve_subpass_src(cmd_buffer);
1144
1145         radv_meta_save(&saved_state, cmd_buffer,
1146                        RADV_META_SAVE_GRAPHICS_PIPELINE |
1147                        RADV_META_SAVE_CONSTANTS |
1148                        RADV_META_SAVE_DESCRIPTORS);
1149
1150         for (uint32_t i = 0; i < subpass->color_count; ++i) {
1151                 struct radv_subpass_attachment src_att = subpass->color_attachments[i];
1152                 struct radv_subpass_attachment dest_att = subpass->resolve_attachments[i];
1153
1154                 if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
1155                         continue;
1156
1157                 struct radv_image_view *dest_iview = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment;
1158                 struct radv_image_view *src_iview = cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
1159
1160                 struct radv_subpass resolve_subpass = {
1161                         .color_count = 1,
1162                         .color_attachments = (struct radv_subpass_attachment[]) { dest_att },
1163                         .depth_stencil_attachment = NULL,
1164                 };
1165
1166                 radv_cmd_buffer_set_subpass(cmd_buffer, &resolve_subpass);
1167
1168                 emit_resolve(cmd_buffer,
1169                              src_iview,
1170                              dest_iview,
1171                              &(VkOffset2D) { 0, 0 },
1172                              &(VkOffset2D) { 0, 0 },
1173                              &(VkExtent2D) { fb->width, fb->height });
1174         }
1175
1176         radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
1177
1178         radv_meta_restore(&saved_state, cmd_buffer);
1179 }
1180
1181 /**
1182  * Depth/stencil resolves for the current subpass.
1183  */
1184 void
1185 radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
1186                                       VkImageAspectFlags aspects,
1187                                       VkResolveModeFlagBitsKHR resolve_mode)
1188 {
1189         struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
1190         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1191         struct radv_meta_saved_state saved_state;
1192         struct radv_subpass_barrier barrier;
1193
1194         /* Resolves happen before the end-of-subpass barriers get executed,
1195          * so we have to make the attachment shader-readable */
1196         barrier.src_stage_mask = VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
1197         barrier.src_access_mask = VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT;
1198         barrier.dst_access_mask = VK_ACCESS_INPUT_ATTACHMENT_READ_BIT;
1199         radv_subpass_barrier(cmd_buffer, &barrier);
1200
1201         radv_decompress_resolve_subpass_src(cmd_buffer);
1202
1203         radv_meta_save(&saved_state, cmd_buffer,
1204                        RADV_META_SAVE_GRAPHICS_PIPELINE |
1205                        RADV_META_SAVE_CONSTANTS |
1206                        RADV_META_SAVE_DESCRIPTORS);
1207
1208         struct radv_subpass_attachment src_att = *subpass->depth_stencil_attachment;
1209         struct radv_subpass_attachment dst_att = *subpass->ds_resolve_attachment;
1210
1211         struct radv_image_view *src_iview =
1212                 cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
1213         struct radv_image *src_image = src_iview->image;
1214         struct radv_image_view *dst_iview =
1215                 cmd_buffer->state.framebuffer->attachments[dst_att.attachment].attachment;
1216
1217         struct radv_subpass resolve_subpass = {
1218                 .color_count = 0,
1219                 .color_attachments = NULL,
1220                 .depth_stencil_attachment = (struct radv_subpass_attachment *) { &dst_att },
1221         };
1222
1223         radv_cmd_buffer_set_subpass(cmd_buffer, &resolve_subpass);
1224
1225         struct radv_image_view tsrc_iview;
1226         radv_image_view_init(&tsrc_iview, cmd_buffer->device,
1227                              &(VkImageViewCreateInfo) {
1228                                 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1229                                 .image = radv_image_to_handle(src_image),
1230                                 .viewType = radv_meta_get_view_type(src_image),
1231                                 .format = src_iview->vk_format,
1232                                 .subresourceRange = {
1233                                         .aspectMask = aspects,
1234                                         .baseMipLevel = 0,
1235                                         .levelCount = 1,
1236                                         .baseArrayLayer = 0,
1237                                         .layerCount = 1,
1238                                 },
1239                               });
1240
1241         emit_depth_stencil_resolve(cmd_buffer, &tsrc_iview, dst_iview,
1242                                    &(VkOffset2D) { 0, 0 },
1243                                    &(VkOffset2D) { 0, 0 },
1244                                    &(VkExtent2D) { fb->width, fb->height },
1245                                    aspects,
1246                                    resolve_mode);
1247
1248         radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
1249
1250         radv_meta_restore(&saved_state, cmd_buffer);
1251 }