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0d62768ecd55d5032d76f993dd7d0dbfb96a24c0
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "nir/nir.h"
31
32 #include <llvm-c/Core.h>
33 #include <llvm-c/TargetMachine.h>
34 #include <llvm-c/Transforms/Scalar.h>
35
36 #include "sid.h"
37 #include "gfx9d.h"
38 #include "ac_binary.h"
39 #include "ac_llvm_util.h"
40 #include "ac_llvm_build.h"
41 #include "ac_shader_abi.h"
42 #include "ac_shader_util.h"
43 #include "ac_exp_param.h"
44
45 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
46
47 struct radv_shader_context {
48 struct ac_llvm_context ac;
49 const struct radv_nir_compiler_options *options;
50 struct radv_shader_variant_info *shader_info;
51 struct ac_shader_abi abi;
52
53 unsigned max_workgroup_size;
54 LLVMContextRef context;
55 LLVMValueRef main_function;
56
57 LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
58 LLVMValueRef ring_offsets;
59
60 LLVMValueRef vertex_buffers;
61 LLVMValueRef rel_auto_id;
62 LLVMValueRef vs_prim_id;
63 LLVMValueRef ls_out_layout;
64 LLVMValueRef es2gs_offset;
65
66 LLVMValueRef tcs_offchip_layout;
67 LLVMValueRef tcs_out_offsets;
68 LLVMValueRef tcs_out_layout;
69 LLVMValueRef tcs_in_layout;
70 LLVMValueRef oc_lds;
71 LLVMValueRef merged_wave_info;
72 LLVMValueRef tess_factor_offset;
73 LLVMValueRef tes_rel_patch_id;
74 LLVMValueRef tes_u;
75 LLVMValueRef tes_v;
76
77 LLVMValueRef gsvs_ring_stride;
78 LLVMValueRef gsvs_num_entries;
79 LLVMValueRef gs2vs_offset;
80 LLVMValueRef gs_wave_id;
81 LLVMValueRef gs_vtx_offset[6];
82
83 LLVMValueRef esgs_ring;
84 LLVMValueRef gsvs_ring;
85 LLVMValueRef hs_ring_tess_offchip;
86 LLVMValueRef hs_ring_tess_factor;
87
88 LLVMValueRef sample_pos_offset;
89 LLVMValueRef persp_sample, persp_center, persp_centroid;
90 LLVMValueRef linear_sample, linear_center, linear_centroid;
91
92 gl_shader_stage stage;
93
94 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
95
96 uint64_t input_mask;
97 uint64_t output_mask;
98 uint8_t num_output_clips;
99 uint8_t num_output_culls;
100
101 bool is_gs_copy_shader;
102 LLVMValueRef gs_next_vertex;
103 unsigned gs_max_out_vertices;
104
105 unsigned tes_primitive_mode;
106 uint64_t tess_outputs_written;
107 uint64_t tess_patch_outputs_written;
108
109 uint32_t tcs_patch_outputs_read;
110 uint64_t tcs_outputs_read;
111 uint32_t tcs_vertices_per_patch;
112 };
113
114 enum radeon_llvm_calling_convention {
115 RADEON_LLVM_AMDGPU_VS = 87,
116 RADEON_LLVM_AMDGPU_GS = 88,
117 RADEON_LLVM_AMDGPU_PS = 89,
118 RADEON_LLVM_AMDGPU_CS = 90,
119 RADEON_LLVM_AMDGPU_HS = 93,
120 };
121
122 static inline struct radv_shader_context *
123 radv_shader_context_from_abi(struct ac_shader_abi *abi)
124 {
125 struct radv_shader_context *ctx = NULL;
126 return container_of(abi, ctx, abi);
127 }
128
129 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
130 {
131 switch (ctx->stage) {
132 case MESA_SHADER_TESS_CTRL:
133 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
134 case MESA_SHADER_TESS_EVAL:
135 return ctx->tes_rel_patch_id;
136 break;
137 default:
138 unreachable("Illegal stage");
139 }
140 }
141
142 /* Tessellation shaders pass outputs to the next shader using LDS.
143 *
144 * LS outputs = TCS inputs
145 * TCS outputs = TES inputs
146 *
147 * The LDS layout is:
148 * - TCS inputs for patch 0
149 * - TCS inputs for patch 1
150 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
151 * - ...
152 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
153 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
154 * - TCS outputs for patch 1
155 * - Per-patch TCS outputs for patch 1
156 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
157 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
158 * - ...
159 *
160 * All three shaders VS(LS), TCS, TES share the same LDS space.
161 */
162 static LLVMValueRef
163 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
164 {
165 if (ctx->stage == MESA_SHADER_VERTEX)
166 return ac_unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
167 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
168 return ac_unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
169 else {
170 assert(0);
171 return NULL;
172 }
173 }
174
175 static LLVMValueRef
176 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
177 {
178 return ac_unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
179 }
180
181 static LLVMValueRef
182 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
183 {
184 return ac_unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
185 }
186
187 static LLVMValueRef
188 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
189 {
190 return LLVMBuildMul(ctx->ac.builder,
191 ac_unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
192 LLVMConstInt(ctx->ac.i32, 4, false), "");
193 }
194
195 static LLVMValueRef
196 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
197 {
198 return LLVMBuildMul(ctx->ac.builder,
199 ac_unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
200 LLVMConstInt(ctx->ac.i32, 4, false), "");
201 }
202
203 static LLVMValueRef
204 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
205 {
206 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
207 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
208
209 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
210 }
211
212 static LLVMValueRef
213 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
214 {
215 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
216 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
217 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
218
219 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
220 LLVMBuildMul(ctx->ac.builder, patch_stride,
221 rel_patch_id, ""),
222 "");
223 }
224
225 static LLVMValueRef
226 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
227 {
228 LLVMValueRef patch0_patch_data_offset =
229 get_tcs_out_patch0_patch_data_offset(ctx);
230 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
231 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
232
233 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
234 LLVMBuildMul(ctx->ac.builder, patch_stride,
235 rel_patch_id, ""),
236 "");
237 }
238
239 #define MAX_ARGS 23
240 struct arg_info {
241 LLVMTypeRef types[MAX_ARGS];
242 LLVMValueRef *assign[MAX_ARGS];
243 unsigned array_params_mask;
244 uint8_t count;
245 uint8_t sgpr_count;
246 uint8_t num_sgprs_used;
247 uint8_t num_vgprs_used;
248 };
249
250 enum ac_arg_regfile {
251 ARG_SGPR,
252 ARG_VGPR,
253 };
254
255 static void
256 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
257 LLVMValueRef *param_ptr)
258 {
259 assert(info->count < MAX_ARGS);
260
261 info->assign[info->count] = param_ptr;
262 info->types[info->count] = type;
263 info->count++;
264
265 if (regfile == ARG_SGPR) {
266 info->num_sgprs_used += ac_get_type_size(type) / 4;
267 info->sgpr_count++;
268 } else {
269 assert(regfile == ARG_VGPR);
270 info->num_vgprs_used += ac_get_type_size(type) / 4;
271 }
272 }
273
274 static inline void
275 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
276 {
277 info->array_params_mask |= (1 << info->count);
278 add_arg(info, ARG_SGPR, type, param_ptr);
279 }
280
281 static void assign_arguments(LLVMValueRef main_function,
282 struct arg_info *info)
283 {
284 unsigned i;
285 for (i = 0; i < info->count; i++) {
286 if (info->assign[i])
287 *info->assign[i] = LLVMGetParam(main_function, i);
288 }
289 }
290
291 static LLVMValueRef
292 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
293 LLVMBuilderRef builder, LLVMTypeRef *return_types,
294 unsigned num_return_elems,
295 struct arg_info *args,
296 unsigned max_workgroup_size,
297 bool unsafe_math)
298 {
299 LLVMTypeRef main_function_type, ret_type;
300 LLVMBasicBlockRef main_function_body;
301
302 if (num_return_elems)
303 ret_type = LLVMStructTypeInContext(ctx, return_types,
304 num_return_elems, true);
305 else
306 ret_type = LLVMVoidTypeInContext(ctx);
307
308 /* Setup the function */
309 main_function_type =
310 LLVMFunctionType(ret_type, args->types, args->count, 0);
311 LLVMValueRef main_function =
312 LLVMAddFunction(module, "main", main_function_type);
313 main_function_body =
314 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
315 LLVMPositionBuilderAtEnd(builder, main_function_body);
316
317 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
318 for (unsigned i = 0; i < args->sgpr_count; ++i) {
319 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
320
321 if (args->array_params_mask & (1 << i)) {
322 LLVMValueRef P = LLVMGetParam(main_function, i);
323 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
324 ac_add_attr_dereferenceable(P, UINT64_MAX);
325 }
326 }
327
328 if (max_workgroup_size) {
329 ac_llvm_add_target_dep_function_attr(main_function,
330 "amdgpu-max-work-group-size",
331 max_workgroup_size);
332 }
333 if (unsafe_math) {
334 /* These were copied from some LLVM test. */
335 LLVMAddTargetDependentFunctionAttr(main_function,
336 "less-precise-fpmad",
337 "true");
338 LLVMAddTargetDependentFunctionAttr(main_function,
339 "no-infs-fp-math",
340 "true");
341 LLVMAddTargetDependentFunctionAttr(main_function,
342 "no-nans-fp-math",
343 "true");
344 LLVMAddTargetDependentFunctionAttr(main_function,
345 "unsafe-fp-math",
346 "true");
347 LLVMAddTargetDependentFunctionAttr(main_function,
348 "no-signed-zeros-fp-math",
349 "true");
350 }
351 return main_function;
352 }
353
354
355 static void
356 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
357 uint32_t indirect_offset)
358 {
359 ud_info->sgpr_idx = *sgpr_idx;
360 ud_info->num_sgprs = num_sgprs;
361 ud_info->indirect = indirect_offset > 0;
362 ud_info->indirect_offset = indirect_offset;
363 *sgpr_idx += num_sgprs;
364 }
365
366 static void
367 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
368 uint8_t num_sgprs)
369 {
370 struct radv_userdata_info *ud_info =
371 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
372 assert(ud_info);
373
374 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
375 }
376
377 static void
378 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
379 uint32_t indirect_offset)
380 {
381 struct radv_userdata_info *ud_info =
382 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
383 assert(ud_info);
384
385 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
386 }
387
388 struct user_sgpr_info {
389 bool need_ring_offsets;
390 uint8_t sgpr_count;
391 bool indirect_all_descriptor_sets;
392 };
393
394 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
395 gl_shader_stage stage)
396 {
397 switch (stage) {
398 case MESA_SHADER_VERTEX:
399 if (ctx->shader_info->info.needs_multiview_view_index ||
400 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
401 return true;
402 break;
403 case MESA_SHADER_TESS_EVAL:
404 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
405 return true;
406 break;
407 case MESA_SHADER_GEOMETRY:
408 case MESA_SHADER_TESS_CTRL:
409 if (ctx->shader_info->info.needs_multiview_view_index)
410 return true;
411 break;
412 default:
413 break;
414 }
415 return false;
416 }
417
418 static uint8_t
419 count_vs_user_sgprs(struct radv_shader_context *ctx)
420 {
421 uint8_t count = 0;
422
423 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
424 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
425
426 return count;
427 }
428
429 static void allocate_user_sgprs(struct radv_shader_context *ctx,
430 gl_shader_stage stage,
431 bool has_previous_stage,
432 gl_shader_stage previous_stage,
433 bool needs_view_index,
434 struct user_sgpr_info *user_sgpr_info)
435 {
436 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
437
438 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
439 if (stage == MESA_SHADER_GEOMETRY ||
440 stage == MESA_SHADER_VERTEX ||
441 stage == MESA_SHADER_TESS_CTRL ||
442 stage == MESA_SHADER_TESS_EVAL ||
443 ctx->is_gs_copy_shader)
444 user_sgpr_info->need_ring_offsets = true;
445
446 if (stage == MESA_SHADER_FRAGMENT &&
447 ctx->shader_info->info.ps.needs_sample_positions)
448 user_sgpr_info->need_ring_offsets = true;
449
450 /* 2 user sgprs will nearly always be allocated for scratch/rings */
451 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
452 user_sgpr_info->sgpr_count += 2;
453 }
454
455 switch (stage) {
456 case MESA_SHADER_COMPUTE:
457 if (ctx->shader_info->info.cs.uses_grid_size)
458 user_sgpr_info->sgpr_count += 3;
459 break;
460 case MESA_SHADER_FRAGMENT:
461 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
462 break;
463 case MESA_SHADER_VERTEX:
464 if (!ctx->is_gs_copy_shader)
465 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
466 if (ctx->options->key.vs.as_ls)
467 user_sgpr_info->sgpr_count++;
468 break;
469 case MESA_SHADER_TESS_CTRL:
470 if (has_previous_stage) {
471 if (previous_stage == MESA_SHADER_VERTEX)
472 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
473 user_sgpr_info->sgpr_count++;
474 }
475 user_sgpr_info->sgpr_count += 4;
476 break;
477 case MESA_SHADER_TESS_EVAL:
478 user_sgpr_info->sgpr_count += 1;
479 break;
480 case MESA_SHADER_GEOMETRY:
481 if (has_previous_stage) {
482 if (previous_stage == MESA_SHADER_VERTEX) {
483 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
484 } else {
485 user_sgpr_info->sgpr_count++;
486 }
487 }
488 user_sgpr_info->sgpr_count += 2;
489 break;
490 default:
491 break;
492 }
493
494 if (needs_view_index)
495 user_sgpr_info->sgpr_count++;
496
497 if (ctx->shader_info->info.loads_push_constants)
498 user_sgpr_info->sgpr_count += 2;
499
500 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
501 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
502
503 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
504 user_sgpr_info->sgpr_count += 2;
505 user_sgpr_info->indirect_all_descriptor_sets = true;
506 } else {
507 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
508 }
509 }
510
511 static void
512 declare_global_input_sgprs(struct radv_shader_context *ctx,
513 gl_shader_stage stage,
514 bool has_previous_stage,
515 gl_shader_stage previous_stage,
516 const struct user_sgpr_info *user_sgpr_info,
517 struct arg_info *args,
518 LLVMValueRef *desc_sets)
519 {
520 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
521 unsigned num_sets = ctx->options->layout ?
522 ctx->options->layout->num_sets : 0;
523 unsigned stage_mask = 1 << stage;
524
525 if (has_previous_stage)
526 stage_mask |= 1 << previous_stage;
527
528 /* 1 for each descriptor set */
529 if (!user_sgpr_info->indirect_all_descriptor_sets) {
530 for (unsigned i = 0; i < num_sets; ++i) {
531 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
532 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
533 add_array_arg(args, type,
534 &ctx->descriptor_sets[i]);
535 }
536 }
537 } else {
538 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
539 }
540
541 if (ctx->shader_info->info.loads_push_constants) {
542 /* 1 for push constants and dynamic descriptors */
543 add_array_arg(args, type, &ctx->abi.push_constants);
544 }
545 }
546
547 static void
548 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
549 gl_shader_stage stage,
550 bool has_previous_stage,
551 gl_shader_stage previous_stage,
552 struct arg_info *args)
553 {
554 if (!ctx->is_gs_copy_shader &&
555 (stage == MESA_SHADER_VERTEX ||
556 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
557 if (ctx->shader_info->info.vs.has_vertex_buffers) {
558 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
559 &ctx->vertex_buffers);
560 }
561 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
562 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
563 if (ctx->shader_info->info.vs.needs_draw_id) {
564 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
565 }
566 }
567 }
568
569 static void
570 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
571 {
572 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
573 if (!ctx->is_gs_copy_shader) {
574 if (ctx->options->key.vs.as_ls) {
575 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
576 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
577 } else {
578 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
579 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
580 }
581 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
582 }
583 }
584
585 static void
586 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
587 {
588 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
589 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
590 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
591 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
592 }
593
594 static void
595 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
596 bool has_previous_stage, gl_shader_stage previous_stage,
597 const struct user_sgpr_info *user_sgpr_info,
598 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
599 {
600 unsigned num_sets = ctx->options->layout ?
601 ctx->options->layout->num_sets : 0;
602 unsigned stage_mask = 1 << stage;
603
604 if (has_previous_stage)
605 stage_mask |= 1 << previous_stage;
606
607 if (!user_sgpr_info->indirect_all_descriptor_sets) {
608 for (unsigned i = 0; i < num_sets; ++i) {
609 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
610 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
611 set_loc_desc(ctx, i, user_sgpr_idx, 0);
612 } else
613 ctx->descriptor_sets[i] = NULL;
614 }
615 } else {
616 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
617 user_sgpr_idx, 2);
618
619 for (unsigned i = 0; i < num_sets; ++i) {
620 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
621 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
622 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
623 ctx->descriptor_sets[i] =
624 ac_build_load_to_sgpr(&ctx->ac,
625 desc_sets,
626 LLVMConstInt(ctx->ac.i32, i, false));
627
628 } else
629 ctx->descriptor_sets[i] = NULL;
630 }
631 ctx->shader_info->need_indirect_descriptor_sets = true;
632 }
633
634 if (ctx->shader_info->info.loads_push_constants) {
635 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
636 }
637 }
638
639 static void
640 set_vs_specific_input_locs(struct radv_shader_context *ctx,
641 gl_shader_stage stage, bool has_previous_stage,
642 gl_shader_stage previous_stage,
643 uint8_t *user_sgpr_idx)
644 {
645 if (!ctx->is_gs_copy_shader &&
646 (stage == MESA_SHADER_VERTEX ||
647 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
648 if (ctx->shader_info->info.vs.has_vertex_buffers) {
649 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
650 user_sgpr_idx, 2);
651 }
652
653 unsigned vs_num = 2;
654 if (ctx->shader_info->info.vs.needs_draw_id)
655 vs_num++;
656
657 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
658 user_sgpr_idx, vs_num);
659 }
660 }
661
662 static void set_llvm_calling_convention(LLVMValueRef func,
663 gl_shader_stage stage)
664 {
665 enum radeon_llvm_calling_convention calling_conv;
666
667 switch (stage) {
668 case MESA_SHADER_VERTEX:
669 case MESA_SHADER_TESS_EVAL:
670 calling_conv = RADEON_LLVM_AMDGPU_VS;
671 break;
672 case MESA_SHADER_GEOMETRY:
673 calling_conv = RADEON_LLVM_AMDGPU_GS;
674 break;
675 case MESA_SHADER_TESS_CTRL:
676 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
677 break;
678 case MESA_SHADER_FRAGMENT:
679 calling_conv = RADEON_LLVM_AMDGPU_PS;
680 break;
681 case MESA_SHADER_COMPUTE:
682 calling_conv = RADEON_LLVM_AMDGPU_CS;
683 break;
684 default:
685 unreachable("Unhandle shader type");
686 }
687
688 LLVMSetFunctionCallConv(func, calling_conv);
689 }
690
691 static void create_function(struct radv_shader_context *ctx,
692 gl_shader_stage stage,
693 bool has_previous_stage,
694 gl_shader_stage previous_stage)
695 {
696 uint8_t user_sgpr_idx;
697 struct user_sgpr_info user_sgpr_info;
698 struct arg_info args = {};
699 LLVMValueRef desc_sets;
700 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
701 allocate_user_sgprs(ctx, stage, has_previous_stage,
702 previous_stage, needs_view_index, &user_sgpr_info);
703
704 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
705 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
706 &ctx->ring_offsets);
707 }
708
709 switch (stage) {
710 case MESA_SHADER_COMPUTE:
711 declare_global_input_sgprs(ctx, stage, has_previous_stage,
712 previous_stage, &user_sgpr_info,
713 &args, &desc_sets);
714
715 if (ctx->shader_info->info.cs.uses_grid_size) {
716 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
717 &ctx->abi.num_work_groups);
718 }
719
720 for (int i = 0; i < 3; i++) {
721 ctx->abi.workgroup_ids[i] = NULL;
722 if (ctx->shader_info->info.cs.uses_block_id[i]) {
723 add_arg(&args, ARG_SGPR, ctx->ac.i32,
724 &ctx->abi.workgroup_ids[i]);
725 }
726 }
727
728 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
729 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
730 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
731 &ctx->abi.local_invocation_ids);
732 break;
733 case MESA_SHADER_VERTEX:
734 declare_global_input_sgprs(ctx, stage, has_previous_stage,
735 previous_stage, &user_sgpr_info,
736 &args, &desc_sets);
737 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
738 previous_stage, &args);
739
740 if (needs_view_index)
741 add_arg(&args, ARG_SGPR, ctx->ac.i32,
742 &ctx->abi.view_index);
743 if (ctx->options->key.vs.as_es)
744 add_arg(&args, ARG_SGPR, ctx->ac.i32,
745 &ctx->es2gs_offset);
746 else if (ctx->options->key.vs.as_ls)
747 add_arg(&args, ARG_SGPR, ctx->ac.i32,
748 &ctx->ls_out_layout);
749
750 declare_vs_input_vgprs(ctx, &args);
751 break;
752 case MESA_SHADER_TESS_CTRL:
753 if (has_previous_stage) {
754 // First 6 system regs
755 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
756 add_arg(&args, ARG_SGPR, ctx->ac.i32,
757 &ctx->merged_wave_info);
758 add_arg(&args, ARG_SGPR, ctx->ac.i32,
759 &ctx->tess_factor_offset);
760
761 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
762 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
763 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
764
765 declare_global_input_sgprs(ctx, stage,
766 has_previous_stage,
767 previous_stage,
768 &user_sgpr_info, &args,
769 &desc_sets);
770 declare_vs_specific_input_sgprs(ctx, stage,
771 has_previous_stage,
772 previous_stage, &args);
773
774 add_arg(&args, ARG_SGPR, ctx->ac.i32,
775 &ctx->ls_out_layout);
776
777 add_arg(&args, ARG_SGPR, ctx->ac.i32,
778 &ctx->tcs_offchip_layout);
779 add_arg(&args, ARG_SGPR, ctx->ac.i32,
780 &ctx->tcs_out_offsets);
781 add_arg(&args, ARG_SGPR, ctx->ac.i32,
782 &ctx->tcs_out_layout);
783 add_arg(&args, ARG_SGPR, ctx->ac.i32,
784 &ctx->tcs_in_layout);
785 if (needs_view_index)
786 add_arg(&args, ARG_SGPR, ctx->ac.i32,
787 &ctx->abi.view_index);
788
789 add_arg(&args, ARG_VGPR, ctx->ac.i32,
790 &ctx->abi.tcs_patch_id);
791 add_arg(&args, ARG_VGPR, ctx->ac.i32,
792 &ctx->abi.tcs_rel_ids);
793
794 declare_vs_input_vgprs(ctx, &args);
795 } else {
796 declare_global_input_sgprs(ctx, stage,
797 has_previous_stage,
798 previous_stage,
799 &user_sgpr_info, &args,
800 &desc_sets);
801
802 add_arg(&args, ARG_SGPR, ctx->ac.i32,
803 &ctx->tcs_offchip_layout);
804 add_arg(&args, ARG_SGPR, ctx->ac.i32,
805 &ctx->tcs_out_offsets);
806 add_arg(&args, ARG_SGPR, ctx->ac.i32,
807 &ctx->tcs_out_layout);
808 add_arg(&args, ARG_SGPR, ctx->ac.i32,
809 &ctx->tcs_in_layout);
810 if (needs_view_index)
811 add_arg(&args, ARG_SGPR, ctx->ac.i32,
812 &ctx->abi.view_index);
813
814 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
815 add_arg(&args, ARG_SGPR, ctx->ac.i32,
816 &ctx->tess_factor_offset);
817 add_arg(&args, ARG_VGPR, ctx->ac.i32,
818 &ctx->abi.tcs_patch_id);
819 add_arg(&args, ARG_VGPR, ctx->ac.i32,
820 &ctx->abi.tcs_rel_ids);
821 }
822 break;
823 case MESA_SHADER_TESS_EVAL:
824 declare_global_input_sgprs(ctx, stage, has_previous_stage,
825 previous_stage, &user_sgpr_info,
826 &args, &desc_sets);
827
828 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
829 if (needs_view_index)
830 add_arg(&args, ARG_SGPR, ctx->ac.i32,
831 &ctx->abi.view_index);
832
833 if (ctx->options->key.tes.as_es) {
834 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
835 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
836 add_arg(&args, ARG_SGPR, ctx->ac.i32,
837 &ctx->es2gs_offset);
838 } else {
839 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
840 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
841 }
842 declare_tes_input_vgprs(ctx, &args);
843 break;
844 case MESA_SHADER_GEOMETRY:
845 if (has_previous_stage) {
846 // First 6 system regs
847 add_arg(&args, ARG_SGPR, ctx->ac.i32,
848 &ctx->gs2vs_offset);
849 add_arg(&args, ARG_SGPR, ctx->ac.i32,
850 &ctx->merged_wave_info);
851 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
852
853 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
854 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
855 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
856
857 declare_global_input_sgprs(ctx, stage,
858 has_previous_stage,
859 previous_stage,
860 &user_sgpr_info, &args,
861 &desc_sets);
862
863 if (previous_stage == MESA_SHADER_TESS_EVAL) {
864 add_arg(&args, ARG_SGPR, ctx->ac.i32,
865 &ctx->tcs_offchip_layout);
866 } else {
867 declare_vs_specific_input_sgprs(ctx, stage,
868 has_previous_stage,
869 previous_stage,
870 &args);
871 }
872
873 add_arg(&args, ARG_SGPR, ctx->ac.i32,
874 &ctx->gsvs_ring_stride);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->gsvs_num_entries);
877 if (needs_view_index)
878 add_arg(&args, ARG_SGPR, ctx->ac.i32,
879 &ctx->abi.view_index);
880
881 add_arg(&args, ARG_VGPR, ctx->ac.i32,
882 &ctx->gs_vtx_offset[0]);
883 add_arg(&args, ARG_VGPR, ctx->ac.i32,
884 &ctx->gs_vtx_offset[2]);
885 add_arg(&args, ARG_VGPR, ctx->ac.i32,
886 &ctx->abi.gs_prim_id);
887 add_arg(&args, ARG_VGPR, ctx->ac.i32,
888 &ctx->abi.gs_invocation_id);
889 add_arg(&args, ARG_VGPR, ctx->ac.i32,
890 &ctx->gs_vtx_offset[4]);
891
892 if (previous_stage == MESA_SHADER_VERTEX) {
893 declare_vs_input_vgprs(ctx, &args);
894 } else {
895 declare_tes_input_vgprs(ctx, &args);
896 }
897 } else {
898 declare_global_input_sgprs(ctx, stage,
899 has_previous_stage,
900 previous_stage,
901 &user_sgpr_info, &args,
902 &desc_sets);
903
904 add_arg(&args, ARG_SGPR, ctx->ac.i32,
905 &ctx->gsvs_ring_stride);
906 add_arg(&args, ARG_SGPR, ctx->ac.i32,
907 &ctx->gsvs_num_entries);
908 if (needs_view_index)
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->abi.view_index);
911
912 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
914 add_arg(&args, ARG_VGPR, ctx->ac.i32,
915 &ctx->gs_vtx_offset[0]);
916 add_arg(&args, ARG_VGPR, ctx->ac.i32,
917 &ctx->gs_vtx_offset[1]);
918 add_arg(&args, ARG_VGPR, ctx->ac.i32,
919 &ctx->abi.gs_prim_id);
920 add_arg(&args, ARG_VGPR, ctx->ac.i32,
921 &ctx->gs_vtx_offset[2]);
922 add_arg(&args, ARG_VGPR, ctx->ac.i32,
923 &ctx->gs_vtx_offset[3]);
924 add_arg(&args, ARG_VGPR, ctx->ac.i32,
925 &ctx->gs_vtx_offset[4]);
926 add_arg(&args, ARG_VGPR, ctx->ac.i32,
927 &ctx->gs_vtx_offset[5]);
928 add_arg(&args, ARG_VGPR, ctx->ac.i32,
929 &ctx->abi.gs_invocation_id);
930 }
931 break;
932 case MESA_SHADER_FRAGMENT:
933 declare_global_input_sgprs(ctx, stage, has_previous_stage,
934 previous_stage, &user_sgpr_info,
935 &args, &desc_sets);
936
937 if (ctx->shader_info->info.ps.needs_sample_positions)
938 add_arg(&args, ARG_SGPR, ctx->ac.i32,
939 &ctx->sample_pos_offset);
940
941 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
942 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
943 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
944 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
945 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
946 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
947 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
948 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
949 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
950 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
951 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
952 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
953 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
954 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
955 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
956 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
957 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
958 break;
959 default:
960 unreachable("Shader stage not implemented");
961 }
962
963 ctx->main_function = create_llvm_function(
964 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
965 ctx->max_workgroup_size,
966 ctx->options->unsafe_math);
967 set_llvm_calling_convention(ctx->main_function, stage);
968
969
970 ctx->shader_info->num_input_vgprs = 0;
971 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
972
973 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
974
975 if (ctx->stage != MESA_SHADER_FRAGMENT)
976 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
977
978 assign_arguments(ctx->main_function, &args);
979
980 user_sgpr_idx = 0;
981
982 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
983 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
984 &user_sgpr_idx, 2);
985 if (ctx->options->supports_spill) {
986 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
987 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
988 NULL, 0, AC_FUNC_ATTR_READNONE);
989 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
990 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
991 }
992 }
993
994 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
995 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
996 if (has_previous_stage)
997 user_sgpr_idx = 0;
998
999 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1000 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1001
1002 switch (stage) {
1003 case MESA_SHADER_COMPUTE:
1004 if (ctx->shader_info->info.cs.uses_grid_size) {
1005 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1006 &user_sgpr_idx, 3);
1007 }
1008 break;
1009 case MESA_SHADER_VERTEX:
1010 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1011 previous_stage, &user_sgpr_idx);
1012 if (ctx->abi.view_index)
1013 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1014 if (ctx->options->key.vs.as_ls) {
1015 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1016 &user_sgpr_idx, 1);
1017 }
1018 break;
1019 case MESA_SHADER_TESS_CTRL:
1020 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1021 previous_stage, &user_sgpr_idx);
1022 if (has_previous_stage)
1023 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1024 &user_sgpr_idx, 1);
1025 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1026 if (ctx->abi.view_index)
1027 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1028 break;
1029 case MESA_SHADER_TESS_EVAL:
1030 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1031 if (ctx->abi.view_index)
1032 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1033 break;
1034 case MESA_SHADER_GEOMETRY:
1035 if (has_previous_stage) {
1036 if (previous_stage == MESA_SHADER_VERTEX)
1037 set_vs_specific_input_locs(ctx, stage,
1038 has_previous_stage,
1039 previous_stage,
1040 &user_sgpr_idx);
1041 else
1042 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1043 &user_sgpr_idx, 1);
1044 }
1045 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1046 &user_sgpr_idx, 2);
1047 if (ctx->abi.view_index)
1048 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1049 break;
1050 case MESA_SHADER_FRAGMENT:
1051 if (ctx->shader_info->info.ps.needs_sample_positions) {
1052 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1053 &user_sgpr_idx, 1);
1054 }
1055 break;
1056 default:
1057 unreachable("Shader stage not implemented");
1058 }
1059
1060 if (stage == MESA_SHADER_TESS_CTRL ||
1061 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1062 /* GFX9 has the ESGS ring buffer in LDS. */
1063 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1064 ac_declare_lds_as_pointer(&ctx->ac);
1065 }
1066
1067 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1068 }
1069
1070
1071 static LLVMValueRef
1072 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1073 unsigned desc_set, unsigned binding)
1074 {
1075 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1076 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1077 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1078 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1079 unsigned base_offset = layout->binding[binding].offset;
1080 LLVMValueRef offset, stride;
1081
1082 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1083 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1084 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1085 layout->binding[binding].dynamic_offset_offset;
1086 desc_ptr = ctx->abi.push_constants;
1087 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1088 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1089 } else
1090 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1091
1092 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
1093 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
1094 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
1095
1096 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1097 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1098 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1099
1100 return desc_ptr;
1101 }
1102
1103
1104 /* The offchip buffer layout for TCS->TES is
1105 *
1106 * - attribute 0 of patch 0 vertex 0
1107 * - attribute 0 of patch 0 vertex 1
1108 * - attribute 0 of patch 0 vertex 2
1109 * ...
1110 * - attribute 0 of patch 1 vertex 0
1111 * - attribute 0 of patch 1 vertex 1
1112 * ...
1113 * - attribute 1 of patch 0 vertex 0
1114 * - attribute 1 of patch 0 vertex 1
1115 * ...
1116 * - per patch attribute 0 of patch 0
1117 * - per patch attribute 0 of patch 1
1118 * ...
1119 *
1120 * Note that every attribute has 4 components.
1121 */
1122 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1123 LLVMValueRef vertex_index,
1124 LLVMValueRef param_index)
1125 {
1126 LLVMValueRef base_addr, vertices_per_patch, num_patches;
1127 LLVMValueRef param_stride, constant16;
1128 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1129
1130 vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
1131 num_patches = ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
1132
1133 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1134 if (vertex_index) {
1135 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
1136 vertices_per_patch, "");
1137
1138 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1139 vertex_index, "");
1140
1141 param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
1142 num_patches, "");
1143 } else {
1144 base_addr = rel_patch_id;
1145 param_stride = num_patches;
1146 }
1147
1148 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1149 LLVMBuildMul(ctx->ac.builder, param_index,
1150 param_stride, ""), "");
1151
1152 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1153
1154 if (!vertex_index) {
1155 LLVMValueRef patch_data_offset =
1156 ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
1157
1158 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1159 patch_data_offset, "");
1160 }
1161 return base_addr;
1162 }
1163
1164 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1165 unsigned param,
1166 unsigned const_index,
1167 bool is_compact,
1168 LLVMValueRef vertex_index,
1169 LLVMValueRef indir_index)
1170 {
1171 LLVMValueRef param_index;
1172
1173 if (indir_index)
1174 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1175 indir_index, "");
1176 else {
1177 if (const_index && !is_compact)
1178 param += const_index;
1179 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1180 }
1181 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1182 }
1183
1184 static void
1185 mark_tess_output(struct radv_shader_context *ctx,
1186 bool is_patch, uint32_t param, int num_slots)
1187
1188 {
1189 uint64_t slot_mask = (1ull << num_slots) - 1;
1190 if (is_patch) {
1191 ctx->tess_patch_outputs_written |= (slot_mask << param);
1192 } else
1193 ctx->tess_outputs_written |= (slot_mask << param);
1194 }
1195
1196 static LLVMValueRef
1197 get_dw_address(struct radv_shader_context *ctx,
1198 LLVMValueRef dw_addr,
1199 unsigned param,
1200 unsigned const_index,
1201 bool compact_const_index,
1202 LLVMValueRef vertex_index,
1203 LLVMValueRef stride,
1204 LLVMValueRef indir_index)
1205
1206 {
1207
1208 if (vertex_index) {
1209 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1210 LLVMBuildMul(ctx->ac.builder,
1211 vertex_index,
1212 stride, ""), "");
1213 }
1214
1215 if (indir_index)
1216 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1217 LLVMBuildMul(ctx->ac.builder, indir_index,
1218 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1219 else if (const_index && !compact_const_index)
1220 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1221 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1222
1223 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1224 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1225
1226 if (const_index && compact_const_index)
1227 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1228 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1229 return dw_addr;
1230 }
1231
1232 static LLVMValueRef
1233 load_tcs_varyings(struct ac_shader_abi *abi,
1234 LLVMTypeRef type,
1235 LLVMValueRef vertex_index,
1236 LLVMValueRef indir_index,
1237 unsigned const_index,
1238 unsigned location,
1239 unsigned driver_location,
1240 unsigned component,
1241 unsigned num_components,
1242 bool is_patch,
1243 bool is_compact,
1244 bool load_input)
1245 {
1246 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1247 LLVMValueRef dw_addr, stride;
1248 LLVMValueRef value[4], result;
1249 unsigned param = shader_io_get_unique_index(location);
1250
1251 if (load_input) {
1252 stride = ac_unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
1253 dw_addr = get_tcs_in_current_patch_offset(ctx);
1254 } else {
1255 if (!is_patch) {
1256 stride = get_tcs_out_vertex_stride(ctx);
1257 dw_addr = get_tcs_out_current_patch_offset(ctx);
1258 } else {
1259 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1260 stride = NULL;
1261 }
1262 }
1263
1264 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1265 indir_index);
1266
1267 for (unsigned i = 0; i < num_components + component; i++) {
1268 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1269 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1270 ctx->ac.i32_1, "");
1271 }
1272 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1273 return result;
1274 }
1275
1276 static void
1277 store_tcs_output(struct ac_shader_abi *abi,
1278 const nir_variable *var,
1279 LLVMValueRef vertex_index,
1280 LLVMValueRef param_index,
1281 unsigned const_index,
1282 LLVMValueRef src,
1283 unsigned writemask)
1284 {
1285 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1286 const unsigned location = var->data.location;
1287 const unsigned component = var->data.location_frac;
1288 const bool is_patch = var->data.patch;
1289 const bool is_compact = var->data.compact;
1290 const unsigned count = glsl_count_attribute_slots(var->type, false);
1291 LLVMValueRef dw_addr;
1292 LLVMValueRef stride = NULL;
1293 LLVMValueRef buf_addr = NULL;
1294 unsigned param;
1295 bool store_lds = true;
1296
1297 if (is_patch) {
1298 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1299 store_lds = false;
1300 } else {
1301 if (!(ctx->tcs_outputs_read & (1ULL << location)))
1302 store_lds = false;
1303 }
1304
1305 param = shader_io_get_unique_index(location);
1306 if (location == VARYING_SLOT_CLIP_DIST0 &&
1307 is_compact && const_index > 3) {
1308 const_index -= 3;
1309 param++;
1310 }
1311
1312 if (!is_patch) {
1313 stride = get_tcs_out_vertex_stride(ctx);
1314 dw_addr = get_tcs_out_current_patch_offset(ctx);
1315 } else {
1316 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1317 }
1318
1319 if (param_index)
1320 mark_tess_output(ctx, is_patch, param, count);
1321 else
1322 mark_tess_output(ctx, is_patch, param, 1);
1323
1324 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1325 param_index);
1326 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1327 vertex_index, param_index);
1328
1329 bool is_tess_factor = false;
1330 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1331 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1332 is_tess_factor = true;
1333
1334 unsigned base = is_compact ? const_index : 0;
1335 for (unsigned chan = 0; chan < 8; chan++) {
1336 if (!(writemask & (1 << chan)))
1337 continue;
1338 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1339
1340 if (store_lds || is_tess_factor) {
1341 LLVMValueRef dw_addr_chan =
1342 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1343 LLVMConstInt(ctx->ac.i32, chan, false), "");
1344 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1345 }
1346
1347 if (!is_tess_factor && writemask != 0xF)
1348 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1349 buf_addr, ctx->oc_lds,
1350 4 * (base + chan), 1, 0, true, false);
1351 }
1352
1353 if (writemask == 0xF) {
1354 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1355 buf_addr, ctx->oc_lds,
1356 (base * 4), 1, 0, true, false);
1357 }
1358 }
1359
1360 static LLVMValueRef
1361 load_tes_input(struct ac_shader_abi *abi,
1362 LLVMTypeRef type,
1363 LLVMValueRef vertex_index,
1364 LLVMValueRef param_index,
1365 unsigned const_index,
1366 unsigned location,
1367 unsigned driver_location,
1368 unsigned component,
1369 unsigned num_components,
1370 bool is_patch,
1371 bool is_compact,
1372 bool load_input)
1373 {
1374 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1375 LLVMValueRef buf_addr;
1376 LLVMValueRef result;
1377 unsigned param = shader_io_get_unique_index(location);
1378
1379 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
1380 const_index -= 3;
1381 param++;
1382 }
1383
1384 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1385 is_compact, vertex_index, param_index);
1386
1387 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1388 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1389
1390 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1391 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
1392 result = ac_trim_vector(&ctx->ac, result, num_components);
1393 return result;
1394 }
1395
1396 static LLVMValueRef
1397 load_gs_input(struct ac_shader_abi *abi,
1398 unsigned location,
1399 unsigned driver_location,
1400 unsigned component,
1401 unsigned num_components,
1402 unsigned vertex_index,
1403 unsigned const_index,
1404 LLVMTypeRef type)
1405 {
1406 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1407 LLVMValueRef vtx_offset;
1408 unsigned param, vtx_offset_param;
1409 LLVMValueRef value[4], result;
1410
1411 vtx_offset_param = vertex_index;
1412 assert(vtx_offset_param < 6);
1413 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1414 LLVMConstInt(ctx->ac.i32, 4, false), "");
1415
1416 param = shader_io_get_unique_index(location);
1417
1418 for (unsigned i = component; i < num_components + component; i++) {
1419 if (ctx->ac.chip_class >= GFX9) {
1420 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1421 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1422 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1423 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1424 } else {
1425 LLVMValueRef soffset =
1426 LLVMConstInt(ctx->ac.i32,
1427 (param * 4 + i + const_index) * 256,
1428 false);
1429
1430 value[i] = ac_build_buffer_load(&ctx->ac,
1431 ctx->esgs_ring, 1,
1432 ctx->ac.i32_0,
1433 vtx_offset, soffset,
1434 0, 1, 0, true, false);
1435
1436 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
1437 type, "");
1438 }
1439 }
1440 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1441 result = ac_to_integer(&ctx->ac, result);
1442 return result;
1443 }
1444
1445
1446 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1447 {
1448 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1449 ac_build_kill_if_false(&ctx->ac, visible);
1450 }
1451
1452 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
1453 enum glsl_interp_mode interp, unsigned location)
1454 {
1455 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1456
1457 switch (interp) {
1458 case INTERP_MODE_FLAT:
1459 default:
1460 return NULL;
1461 case INTERP_MODE_SMOOTH:
1462 case INTERP_MODE_NONE:
1463 if (location == INTERP_CENTER)
1464 return ctx->persp_center;
1465 else if (location == INTERP_CENTROID)
1466 return ctx->persp_centroid;
1467 else if (location == INTERP_SAMPLE)
1468 return ctx->persp_sample;
1469 break;
1470 case INTERP_MODE_NOPERSPECTIVE:
1471 if (location == INTERP_CENTER)
1472 return ctx->linear_center;
1473 else if (location == INTERP_CENTROID)
1474 return ctx->linear_centroid;
1475 else if (location == INTERP_SAMPLE)
1476 return ctx->linear_sample;
1477 break;
1478 }
1479 return NULL;
1480 }
1481
1482 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1483 LLVMValueRef sample_id)
1484 {
1485 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1486
1487 LLVMValueRef result;
1488 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
1489
1490 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1491 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1492
1493 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
1494 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1495
1496 return result;
1497 }
1498
1499
1500 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1501 {
1502 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1503 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
1504 ctx->options->key.fs.log2_num_samples :
1505 ctx->options->key.fs.log2_ps_iter_samples;
1506
1507 /* The bit pattern matches that used by fixed function fragment
1508 * processing. */
1509 static const uint16_t ps_iter_masks[] = {
1510 0xffff, /* not used */
1511 0x5555,
1512 0x1111,
1513 0x0101,
1514 0x0001,
1515 };
1516 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1517
1518 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1519
1520 LLVMValueRef result, sample_id;
1521 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1522 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1523 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1524 return result;
1525 }
1526
1527
1528 static void
1529 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1530 {
1531 LLVMValueRef gs_next_vertex;
1532 LLVMValueRef can_emit;
1533 int idx;
1534 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1535
1536 assert(stream == 0);
1537
1538 /* Write vertex attribute values to GSVS ring */
1539 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1540 ctx->gs_next_vertex,
1541 "");
1542
1543 /* If this thread has already emitted the declared maximum number of
1544 * vertices, kill it: excessive vertex emissions are not supposed to
1545 * have any effect, and GS threads have no externally observable
1546 * effects other than emitting vertices.
1547 */
1548 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1549 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
1550 ac_build_kill_if_false(&ctx->ac, can_emit);
1551
1552 /* loop num outputs */
1553 idx = 0;
1554 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1555 LLVMValueRef *out_ptr = &addrs[i * 4];
1556 int length = 4;
1557 int slot = idx;
1558 int slot_inc = 1;
1559
1560 if (!(ctx->output_mask & (1ull << i)))
1561 continue;
1562
1563 if (i == VARYING_SLOT_CLIP_DIST0) {
1564 /* pack clip and cull into a single set of slots */
1565 length = ctx->num_output_clips + ctx->num_output_culls;
1566 if (length > 4)
1567 slot_inc = 2;
1568 }
1569 for (unsigned j = 0; j < length; j++) {
1570 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1571 out_ptr[j], "");
1572 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
1573 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1574 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1575
1576 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1577
1578 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
1579 out_val, 1,
1580 voffset, ctx->gs2vs_offset, 0,
1581 1, 1, true, true);
1582 }
1583 idx += slot_inc;
1584 }
1585
1586 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1587 ctx->ac.i32_1, "");
1588 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
1589
1590 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
1591 }
1592
1593 static void
1594 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1595 {
1596 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1597 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1598 }
1599
1600 static LLVMValueRef
1601 load_tess_coord(struct ac_shader_abi *abi)
1602 {
1603 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1604
1605 LLVMValueRef coord[4] = {
1606 ctx->tes_u,
1607 ctx->tes_v,
1608 ctx->ac.f32_0,
1609 ctx->ac.f32_0,
1610 };
1611
1612 if (ctx->tes_primitive_mode == GL_TRIANGLES)
1613 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1614 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1615
1616 return ac_build_gather_values(&ctx->ac, coord, 3);
1617 }
1618
1619 static LLVMValueRef
1620 load_patch_vertices_in(struct ac_shader_abi *abi)
1621 {
1622 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1623 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1624 }
1625
1626
1627 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1628 {
1629 return abi->base_vertex;
1630 }
1631
1632 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1633 LLVMValueRef buffer_ptr, bool write)
1634 {
1635 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1636 LLVMValueRef result;
1637
1638 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1639
1640 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1641 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1642
1643 return result;
1644 }
1645
1646 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1647 {
1648 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1649 LLVMValueRef result;
1650
1651 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1652
1653 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1654 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1655
1656 return result;
1657 }
1658
1659 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1660 unsigned descriptor_set,
1661 unsigned base_index,
1662 unsigned constant_index,
1663 LLVMValueRef index,
1664 enum ac_descriptor_type desc_type,
1665 bool image, bool write)
1666 {
1667 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1668 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1669 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1670 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1671 unsigned offset = binding->offset;
1672 unsigned stride = binding->size;
1673 unsigned type_size;
1674 LLVMBuilderRef builder = ctx->ac.builder;
1675 LLVMTypeRef type;
1676
1677 assert(base_index < layout->binding_count);
1678
1679 switch (desc_type) {
1680 case AC_DESC_IMAGE:
1681 type = ctx->ac.v8i32;
1682 type_size = 32;
1683 break;
1684 case AC_DESC_FMASK:
1685 type = ctx->ac.v8i32;
1686 offset += 32;
1687 type_size = 32;
1688 break;
1689 case AC_DESC_SAMPLER:
1690 type = ctx->ac.v4i32;
1691 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
1692 offset += 64;
1693
1694 type_size = 16;
1695 break;
1696 case AC_DESC_BUFFER:
1697 type = ctx->ac.v4i32;
1698 type_size = 16;
1699 break;
1700 default:
1701 unreachable("invalid desc_type\n");
1702 }
1703
1704 offset += constant_index * stride;
1705
1706 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1707 (!index || binding->immutable_samplers_equal)) {
1708 if (binding->immutable_samplers_equal)
1709 constant_index = 0;
1710
1711 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1712
1713 LLVMValueRef constants[] = {
1714 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1715 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1716 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1717 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1718 };
1719 return ac_build_gather_values(&ctx->ac, constants, 4);
1720 }
1721
1722 assert(stride % type_size == 0);
1723
1724 if (!index)
1725 index = ctx->ac.i32_0;
1726
1727 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1728
1729 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
1730 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
1731
1732 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1733 }
1734
1735
1736 static void
1737 handle_vs_input_decl(struct radv_shader_context *ctx,
1738 struct nir_variable *variable)
1739 {
1740 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
1741 LLVMValueRef t_offset;
1742 LLVMValueRef t_list;
1743 LLVMValueRef input;
1744 LLVMValueRef buffer_index;
1745 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
1746 int idx = variable->data.location;
1747 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1748 uint8_t input_usage_mask =
1749 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
1750 unsigned num_channels = util_last_bit(input_usage_mask);
1751
1752 variable->data.driver_location = idx * 4;
1753
1754 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
1755 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
1756 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
1757 ctx->abi.start_instance, "");
1758 if (ctx->options->key.vs.as_ls) {
1759 ctx->shader_info->vs.vgpr_comp_cnt =
1760 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
1761 } else {
1762 ctx->shader_info->vs.vgpr_comp_cnt =
1763 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
1764 }
1765 } else
1766 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
1767 ctx->abi.base_vertex, "");
1768 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
1769
1770 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1771
1772 input = ac_build_buffer_load_format(&ctx->ac, t_list,
1773 buffer_index,
1774 ctx->ac.i32_0,
1775 num_channels, false, true);
1776
1777 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
1778
1779 for (unsigned chan = 0; chan < 4; chan++) {
1780 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1781 ctx->inputs[ac_llvm_reg_index_soa(idx, chan)] =
1782 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
1783 input, llvm_chan, ""));
1784 }
1785 }
1786 }
1787
1788 static void interp_fs_input(struct radv_shader_context *ctx,
1789 unsigned attr,
1790 LLVMValueRef interp_param,
1791 LLVMValueRef prim_mask,
1792 LLVMValueRef result[4])
1793 {
1794 LLVMValueRef attr_number;
1795 unsigned chan;
1796 LLVMValueRef i, j;
1797 bool interp = interp_param != NULL;
1798
1799 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
1800
1801 /* fs.constant returns the param from the middle vertex, so it's not
1802 * really useful for flat shading. It's meant to be used for custom
1803 * interpolation (but the intrinsic can't fetch from the other two
1804 * vertices).
1805 *
1806 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1807 * to do the right thing. The only reason we use fs.constant is that
1808 * fs.interp cannot be used on integers, because they can be equal
1809 * to NaN.
1810 */
1811 if (interp) {
1812 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1813 ctx->ac.v2f32, "");
1814
1815 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1816 ctx->ac.i32_0, "");
1817 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1818 ctx->ac.i32_1, "");
1819 }
1820
1821 for (chan = 0; chan < 4; chan++) {
1822 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1823
1824 if (interp) {
1825 result[chan] = ac_build_fs_interp(&ctx->ac,
1826 llvm_chan,
1827 attr_number,
1828 prim_mask, i, j);
1829 } else {
1830 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
1831 LLVMConstInt(ctx->ac.i32, 2, false),
1832 llvm_chan,
1833 attr_number,
1834 prim_mask);
1835 }
1836 }
1837 }
1838
1839 static void
1840 handle_fs_input_decl(struct radv_shader_context *ctx,
1841 struct nir_variable *variable)
1842 {
1843 int idx = variable->data.location;
1844 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1845 LLVMValueRef interp;
1846
1847 variable->data.driver_location = idx * 4;
1848 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
1849
1850 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
1851 unsigned interp_type;
1852 if (variable->data.sample)
1853 interp_type = INTERP_SAMPLE;
1854 else if (variable->data.centroid)
1855 interp_type = INTERP_CENTROID;
1856 else
1857 interp_type = INTERP_CENTER;
1858
1859 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
1860 } else
1861 interp = NULL;
1862
1863 for (unsigned i = 0; i < attrib_count; ++i)
1864 ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
1865
1866 }
1867
1868 static void
1869 handle_vs_inputs(struct radv_shader_context *ctx,
1870 struct nir_shader *nir) {
1871 nir_foreach_variable(variable, &nir->inputs)
1872 handle_vs_input_decl(ctx, variable);
1873 }
1874
1875 static void
1876 prepare_interp_optimize(struct radv_shader_context *ctx,
1877 struct nir_shader *nir)
1878 {
1879 if (!ctx->options->key.fs.multisample)
1880 return;
1881
1882 bool uses_center = false;
1883 bool uses_centroid = false;
1884 nir_foreach_variable(variable, &nir->inputs) {
1885 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
1886 variable->data.sample)
1887 continue;
1888
1889 if (variable->data.centroid)
1890 uses_centroid = true;
1891 else
1892 uses_center = true;
1893 }
1894
1895 if (uses_center && uses_centroid) {
1896 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
1897 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
1898 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
1899 }
1900 }
1901
1902 static void
1903 handle_fs_inputs(struct radv_shader_context *ctx,
1904 struct nir_shader *nir)
1905 {
1906 prepare_interp_optimize(ctx, nir);
1907
1908 nir_foreach_variable(variable, &nir->inputs)
1909 handle_fs_input_decl(ctx, variable);
1910
1911 unsigned index = 0;
1912
1913 if (ctx->shader_info->info.ps.uses_input_attachments ||
1914 ctx->shader_info->info.needs_multiview_view_index)
1915 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
1916
1917 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
1918 LLVMValueRef interp_param;
1919 LLVMValueRef *inputs = ctx->inputs +ac_llvm_reg_index_soa(i, 0);
1920
1921 if (!(ctx->input_mask & (1ull << i)))
1922 continue;
1923
1924 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
1925 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
1926 interp_param = *inputs;
1927 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
1928 inputs);
1929
1930 if (!interp_param)
1931 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
1932 ++index;
1933 } else if (i == VARYING_SLOT_POS) {
1934 for(int i = 0; i < 3; ++i)
1935 inputs[i] = ctx->abi.frag_pos[i];
1936
1937 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
1938 ctx->abi.frag_pos[3]);
1939 }
1940 }
1941 ctx->shader_info->fs.num_interp = index;
1942 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
1943
1944 if (ctx->shader_info->info.needs_multiview_view_index)
1945 ctx->abi.view_index = ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
1946 }
1947
1948 static void
1949 scan_shader_output_decl(struct radv_shader_context *ctx,
1950 struct nir_variable *variable,
1951 struct nir_shader *shader,
1952 gl_shader_stage stage)
1953 {
1954 int idx = variable->data.location + variable->data.index;
1955 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1956 uint64_t mask_attribs;
1957
1958 variable->data.driver_location = idx * 4;
1959
1960 /* tess ctrl has it's own load/store paths for outputs */
1961 if (stage == MESA_SHADER_TESS_CTRL)
1962 return;
1963
1964 mask_attribs = ((1ull << attrib_count) - 1) << idx;
1965 if (stage == MESA_SHADER_VERTEX ||
1966 stage == MESA_SHADER_TESS_EVAL ||
1967 stage == MESA_SHADER_GEOMETRY) {
1968 if (idx == VARYING_SLOT_CLIP_DIST0) {
1969 int length = shader->info.clip_distance_array_size +
1970 shader->info.cull_distance_array_size;
1971 if (stage == MESA_SHADER_VERTEX) {
1972 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
1973 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
1974 }
1975 if (stage == MESA_SHADER_TESS_EVAL) {
1976 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
1977 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
1978 }
1979
1980 if (length > 4)
1981 attrib_count = 2;
1982 else
1983 attrib_count = 1;
1984 mask_attribs = 1ull << idx;
1985 }
1986 }
1987
1988 ctx->output_mask |= mask_attribs;
1989 }
1990
1991
1992 /* Initialize arguments for the shader export intrinsic */
1993 static void
1994 si_llvm_init_export_args(struct radv_shader_context *ctx,
1995 LLVMValueRef *values,
1996 unsigned enabled_channels,
1997 unsigned target,
1998 struct ac_export_args *args)
1999 {
2000 /* Specify the channels that are enabled. */
2001 args->enabled_channels = enabled_channels;
2002
2003 /* Specify whether the EXEC mask represents the valid mask */
2004 args->valid_mask = 0;
2005
2006 /* Specify whether this is the last export */
2007 args->done = 0;
2008
2009 /* Specify the target we are exporting */
2010 args->target = target;
2011
2012 args->compr = false;
2013 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2014 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2015 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2016 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2017
2018 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
2019 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2020 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2021 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2022 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2023 unsigned chan;
2024
2025 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2026 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2027 unsigned bits, bool hi) = NULL;
2028
2029 switch(col_format) {
2030 case V_028714_SPI_SHADER_ZERO:
2031 args->enabled_channels = 0; /* writemask */
2032 args->target = V_008DFC_SQ_EXP_NULL;
2033 break;
2034
2035 case V_028714_SPI_SHADER_32_R:
2036 args->enabled_channels = 1;
2037 args->out[0] = values[0];
2038 break;
2039
2040 case V_028714_SPI_SHADER_32_GR:
2041 args->enabled_channels = 0x3;
2042 args->out[0] = values[0];
2043 args->out[1] = values[1];
2044 break;
2045
2046 case V_028714_SPI_SHADER_32_AR:
2047 args->enabled_channels = 0x9;
2048 args->out[0] = values[0];
2049 args->out[3] = values[3];
2050 break;
2051
2052 case V_028714_SPI_SHADER_FP16_ABGR:
2053 args->enabled_channels = 0x5;
2054 packf = ac_build_cvt_pkrtz_f16;
2055 break;
2056
2057 case V_028714_SPI_SHADER_UNORM16_ABGR:
2058 args->enabled_channels = 0x5;
2059 packf = ac_build_cvt_pknorm_u16;
2060 break;
2061
2062 case V_028714_SPI_SHADER_SNORM16_ABGR:
2063 args->enabled_channels = 0x5;
2064 packf = ac_build_cvt_pknorm_i16;
2065 break;
2066
2067 case V_028714_SPI_SHADER_UINT16_ABGR:
2068 args->enabled_channels = 0x5;
2069 packi = ac_build_cvt_pk_u16;
2070 break;
2071
2072 case V_028714_SPI_SHADER_SINT16_ABGR:
2073 args->enabled_channels = 0x5;
2074 packi = ac_build_cvt_pk_i16;
2075 break;
2076
2077 default:
2078 case V_028714_SPI_SHADER_32_ABGR:
2079 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2080 break;
2081 }
2082
2083 /* Pack f16 or norm_i16/u16. */
2084 if (packf) {
2085 for (chan = 0; chan < 2; chan++) {
2086 LLVMValueRef pack_args[2] = {
2087 values[2 * chan],
2088 values[2 * chan + 1]
2089 };
2090 LLVMValueRef packed;
2091
2092 packed = packf(&ctx->ac, pack_args);
2093 args->out[chan] = ac_to_float(&ctx->ac, packed);
2094 }
2095 args->compr = 1; /* COMPR flag */
2096 }
2097
2098 /* Pack i16/u16. */
2099 if (packi) {
2100 for (chan = 0; chan < 2; chan++) {
2101 LLVMValueRef pack_args[2] = {
2102 ac_to_integer(&ctx->ac, values[2 * chan]),
2103 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2104 };
2105 LLVMValueRef packed;
2106
2107 packed = packi(&ctx->ac, pack_args,
2108 is_int8 ? 8 : is_int10 ? 10 : 16,
2109 chan == 1);
2110 args->out[chan] = ac_to_float(&ctx->ac, packed);
2111 }
2112 args->compr = 1; /* COMPR flag */
2113 }
2114 return;
2115 }
2116
2117 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2118
2119 for (unsigned i = 0; i < 4; ++i) {
2120 if (!(args->enabled_channels & (1 << i)))
2121 continue;
2122
2123 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2124 }
2125 }
2126
2127 static void
2128 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2129 LLVMValueRef *values, unsigned enabled_channels)
2130 {
2131 struct ac_export_args args;
2132
2133 si_llvm_init_export_args(ctx, values, enabled_channels,
2134 V_008DFC_SQ_EXP_PARAM + index, &args);
2135 ac_build_export(&ctx->ac, &args);
2136 }
2137
2138 static LLVMValueRef
2139 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2140 {
2141 LLVMValueRef output =
2142 ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2143
2144 return LLVMBuildLoad(ctx->ac.builder, output, "");
2145 }
2146
2147 static void
2148 handle_vs_outputs_post(struct radv_shader_context *ctx,
2149 bool export_prim_id,
2150 struct radv_vs_output_info *outinfo)
2151 {
2152 uint32_t param_count = 0;
2153 unsigned target;
2154 unsigned pos_idx, num_pos_exports = 0;
2155 struct ac_export_args args, pos_args[4] = {};
2156 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2157 int i;
2158
2159 if (ctx->options->key.has_multiview_view_index) {
2160 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2161 if(!*tmp_out) {
2162 for(unsigned i = 0; i < 4; ++i)
2163 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2164 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2165 }
2166
2167 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2168 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2169 }
2170
2171 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2172 sizeof(outinfo->vs_output_param_offset));
2173
2174 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
2175 LLVMValueRef slots[8];
2176 unsigned j;
2177
2178 if (outinfo->cull_dist_mask)
2179 outinfo->cull_dist_mask <<= ctx->num_output_clips;
2180
2181 i = VARYING_SLOT_CLIP_DIST0;
2182 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
2183 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2184
2185 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
2186 slots[i] = LLVMGetUndef(ctx->ac.f32);
2187
2188 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
2189 target = V_008DFC_SQ_EXP_POS + 3;
2190 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
2191 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2192 &args, sizeof(args));
2193 }
2194
2195 target = V_008DFC_SQ_EXP_POS + 2;
2196 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
2197 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2198 &args, sizeof(args));
2199
2200 }
2201
2202 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
2203 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
2204 for (unsigned j = 0; j < 4; j++)
2205 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
2206 }
2207 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
2208
2209 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
2210 outinfo->writes_pointsize = true;
2211 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
2212 }
2213
2214 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
2215 outinfo->writes_layer = true;
2216 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
2217 }
2218
2219 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
2220 outinfo->writes_viewport_index = true;
2221 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
2222 }
2223
2224 if (outinfo->writes_pointsize ||
2225 outinfo->writes_layer ||
2226 outinfo->writes_viewport_index) {
2227 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2228 (outinfo->writes_layer == true ? 4 : 0));
2229 pos_args[1].valid_mask = 0;
2230 pos_args[1].done = 0;
2231 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2232 pos_args[1].compr = 0;
2233 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2234 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2235 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2236 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2237
2238 if (outinfo->writes_pointsize == true)
2239 pos_args[1].out[0] = psize_value;
2240 if (outinfo->writes_layer == true)
2241 pos_args[1].out[2] = layer_value;
2242 if (outinfo->writes_viewport_index == true) {
2243 if (ctx->options->chip_class >= GFX9) {
2244 /* GFX9 has the layer in out.z[10:0] and the viewport
2245 * index in out.z[19:16].
2246 */
2247 LLVMValueRef v = viewport_index_value;
2248 v = ac_to_integer(&ctx->ac, v);
2249 v = LLVMBuildShl(ctx->ac.builder, v,
2250 LLVMConstInt(ctx->ac.i32, 16, false),
2251 "");
2252 v = LLVMBuildOr(ctx->ac.builder, v,
2253 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2254
2255 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2256 pos_args[1].enabled_channels |= 1 << 2;
2257 } else {
2258 pos_args[1].out[3] = viewport_index_value;
2259 pos_args[1].enabled_channels |= 1 << 3;
2260 }
2261 }
2262 }
2263 for (i = 0; i < 4; i++) {
2264 if (pos_args[i].out[0])
2265 num_pos_exports++;
2266 }
2267
2268 pos_idx = 0;
2269 for (i = 0; i < 4; i++) {
2270 if (!pos_args[i].out[0])
2271 continue;
2272
2273 /* Specify the target we are exporting */
2274 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2275 if (pos_idx == num_pos_exports)
2276 pos_args[i].done = 1;
2277 ac_build_export(&ctx->ac, &pos_args[i]);
2278 }
2279
2280 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2281 LLVMValueRef values[4];
2282 if (!(ctx->output_mask & (1ull << i)))
2283 continue;
2284
2285 if (i != VARYING_SLOT_LAYER &&
2286 i != VARYING_SLOT_PRIMITIVE_ID &&
2287 i < VARYING_SLOT_VAR0)
2288 continue;
2289
2290 for (unsigned j = 0; j < 4; j++)
2291 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2292
2293 unsigned output_usage_mask;
2294
2295 if (ctx->stage == MESA_SHADER_VERTEX &&
2296 !ctx->is_gs_copy_shader) {
2297 output_usage_mask =
2298 ctx->shader_info->info.vs.output_usage_mask[i];
2299 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2300 output_usage_mask =
2301 ctx->shader_info->info.tes.output_usage_mask[i];
2302 } else {
2303 /* Enable all channels for the GS copy shader because
2304 * we don't know the output usage mask currently.
2305 */
2306 output_usage_mask = 0xf;
2307 }
2308
2309 radv_export_param(ctx, param_count, values, output_usage_mask);
2310
2311 outinfo->vs_output_param_offset[i] = param_count++;
2312 }
2313
2314 if (export_prim_id) {
2315 LLVMValueRef values[4];
2316
2317 values[0] = ctx->vs_prim_id;
2318 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
2319 ctx->shader_info->vs.vgpr_comp_cnt);
2320 for (unsigned j = 1; j < 4; j++)
2321 values[j] = ctx->ac.f32_0;
2322
2323 radv_export_param(ctx, param_count, values, 0xf);
2324
2325 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2326 outinfo->export_prim_id = true;
2327 }
2328
2329 outinfo->pos_exports = num_pos_exports;
2330 outinfo->param_exports = param_count;
2331 }
2332
2333 static void
2334 handle_es_outputs_post(struct radv_shader_context *ctx,
2335 struct radv_es_output_info *outinfo)
2336 {
2337 int j;
2338 uint64_t max_output_written = 0;
2339 LLVMValueRef lds_base = NULL;
2340
2341 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2342 int param_index;
2343 int length = 4;
2344
2345 if (!(ctx->output_mask & (1ull << i)))
2346 continue;
2347
2348 if (i == VARYING_SLOT_CLIP_DIST0)
2349 length = ctx->num_output_clips + ctx->num_output_culls;
2350
2351 param_index = shader_io_get_unique_index(i);
2352
2353 max_output_written = MAX2(param_index + (length > 4), max_output_written);
2354 }
2355
2356 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
2357
2358 if (ctx->ac.chip_class >= GFX9) {
2359 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2360 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2361 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2362 LLVMConstInt(ctx->ac.i32, 24, false),
2363 LLVMConstInt(ctx->ac.i32, 4, false), false);
2364 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2365 LLVMBuildMul(ctx->ac.builder, wave_idx,
2366 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
2367 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2368 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2369 }
2370
2371 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2372 LLVMValueRef dw_addr = NULL;
2373 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2374 int param_index;
2375 int length = 4;
2376
2377 if (!(ctx->output_mask & (1ull << i)))
2378 continue;
2379
2380 if (i == VARYING_SLOT_CLIP_DIST0)
2381 length = ctx->num_output_clips + ctx->num_output_culls;
2382
2383 param_index = shader_io_get_unique_index(i);
2384
2385 if (lds_base) {
2386 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2387 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2388 "");
2389 }
2390 for (j = 0; j < length; j++) {
2391 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2392 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2393
2394 if (ctx->ac.chip_class >= GFX9) {
2395 ac_lds_store(&ctx->ac, dw_addr,
2396 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2397 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2398 } else {
2399 ac_build_buffer_store_dword(&ctx->ac,
2400 ctx->esgs_ring,
2401 out_val, 1,
2402 NULL, ctx->es2gs_offset,
2403 (4 * param_index + j) * 4,
2404 1, 1, true, true);
2405 }
2406 }
2407 }
2408 }
2409
2410 static void
2411 handle_ls_outputs_post(struct radv_shader_context *ctx)
2412 {
2413 LLVMValueRef vertex_id = ctx->rel_auto_id;
2414 LLVMValueRef vertex_dw_stride = ac_unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
2415 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2416 vertex_dw_stride, "");
2417
2418 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2419 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2420 int length = 4;
2421
2422 if (!(ctx->output_mask & (1ull << i)))
2423 continue;
2424
2425 if (i == VARYING_SLOT_CLIP_DIST0)
2426 length = ctx->num_output_clips + ctx->num_output_culls;
2427 int param = shader_io_get_unique_index(i);
2428 mark_tess_output(ctx, false, param, 1);
2429 if (length > 4)
2430 mark_tess_output(ctx, false, param + 1, 1);
2431 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2432 LLVMConstInt(ctx->ac.i32, param * 4, false),
2433 "");
2434 for (unsigned j = 0; j < length; j++) {
2435 ac_lds_store(&ctx->ac, dw_addr,
2436 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2437 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2438 }
2439 }
2440 }
2441
2442 struct ac_build_if_state
2443 {
2444 struct radv_shader_context *ctx;
2445 LLVMValueRef condition;
2446 LLVMBasicBlockRef entry_block;
2447 LLVMBasicBlockRef true_block;
2448 LLVMBasicBlockRef false_block;
2449 LLVMBasicBlockRef merge_block;
2450 };
2451
2452 static LLVMBasicBlockRef
2453 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
2454 {
2455 LLVMBasicBlockRef current_block;
2456 LLVMBasicBlockRef next_block;
2457 LLVMBasicBlockRef new_block;
2458
2459 /* get current basic block */
2460 current_block = LLVMGetInsertBlock(ctx->ac.builder);
2461
2462 /* chqeck if there's another block after this one */
2463 next_block = LLVMGetNextBasicBlock(current_block);
2464 if (next_block) {
2465 /* insert the new block before the next block */
2466 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
2467 }
2468 else {
2469 /* append new block after current block */
2470 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
2471 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
2472 }
2473 return new_block;
2474 }
2475
2476 static void
2477 ac_nir_build_if(struct ac_build_if_state *ifthen,
2478 struct radv_shader_context *ctx,
2479 LLVMValueRef condition)
2480 {
2481 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
2482
2483 memset(ifthen, 0, sizeof *ifthen);
2484 ifthen->ctx = ctx;
2485 ifthen->condition = condition;
2486 ifthen->entry_block = block;
2487
2488 /* create endif/merge basic block for the phi functions */
2489 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
2490
2491 /* create/insert true_block before merge_block */
2492 ifthen->true_block =
2493 LLVMInsertBasicBlockInContext(ctx->context,
2494 ifthen->merge_block,
2495 "if-true-block");
2496
2497 /* successive code goes into the true block */
2498 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
2499 }
2500
2501 /**
2502 * End a conditional.
2503 */
2504 static void
2505 ac_nir_build_endif(struct ac_build_if_state *ifthen)
2506 {
2507 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
2508
2509 /* Insert branch to the merge block from current block */
2510 LLVMBuildBr(builder, ifthen->merge_block);
2511
2512 /*
2513 * Now patch in the various branch instructions.
2514 */
2515
2516 /* Insert the conditional branch instruction at the end of entry_block */
2517 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
2518 if (ifthen->false_block) {
2519 /* we have an else clause */
2520 LLVMBuildCondBr(builder, ifthen->condition,
2521 ifthen->true_block, ifthen->false_block);
2522 }
2523 else {
2524 /* no else clause */
2525 LLVMBuildCondBr(builder, ifthen->condition,
2526 ifthen->true_block, ifthen->merge_block);
2527 }
2528
2529 /* Resume building code at end of the ifthen->merge_block */
2530 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
2531 }
2532
2533 static void
2534 write_tess_factors(struct radv_shader_context *ctx)
2535 {
2536 unsigned stride, outer_comps, inner_comps;
2537 struct ac_build_if_state if_ctx, inner_if_ctx;
2538 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
2539 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
2540 unsigned tess_inner_index = 0, tess_outer_index;
2541 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
2542 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2543 int i;
2544 ac_emit_barrier(&ctx->ac, ctx->stage);
2545
2546 switch (ctx->options->key.tcs.primitive_mode) {
2547 case GL_ISOLINES:
2548 stride = 2;
2549 outer_comps = 2;
2550 inner_comps = 0;
2551 break;
2552 case GL_TRIANGLES:
2553 stride = 4;
2554 outer_comps = 3;
2555 inner_comps = 1;
2556 break;
2557 case GL_QUADS:
2558 stride = 6;
2559 outer_comps = 4;
2560 inner_comps = 2;
2561 break;
2562 default:
2563 return;
2564 }
2565
2566 ac_nir_build_if(&if_ctx, ctx,
2567 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2568 invocation_id, ctx->ac.i32_0, ""));
2569
2570 lds_base = get_tcs_out_current_patch_data_offset(ctx);
2571
2572 if (inner_comps) {
2573 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2574 mark_tess_output(ctx, true, tess_inner_index, 1);
2575 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2576 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
2577 }
2578
2579 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2580 mark_tess_output(ctx, true, tess_outer_index, 1);
2581 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2582 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
2583
2584 for (i = 0; i < 4; i++) {
2585 inner[i] = LLVMGetUndef(ctx->ac.i32);
2586 outer[i] = LLVMGetUndef(ctx->ac.i32);
2587 }
2588
2589 // LINES reverseal
2590 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
2591 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
2592 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2593 ctx->ac.i32_1, "");
2594 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
2595 } else {
2596 for (i = 0; i < outer_comps; i++) {
2597 outer[i] = out[i] =
2598 ac_lds_load(&ctx->ac, lds_outer);
2599 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2600 ctx->ac.i32_1, "");
2601 }
2602 for (i = 0; i < inner_comps; i++) {
2603 inner[i] = out[outer_comps+i] =
2604 ac_lds_load(&ctx->ac, lds_inner);
2605 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
2606 ctx->ac.i32_1, "");
2607 }
2608 }
2609
2610 /* Convert the outputs to vectors for stores. */
2611 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
2612 vec1 = NULL;
2613
2614 if (stride > 4)
2615 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
2616
2617
2618 buffer = ctx->hs_ring_tess_factor;
2619 tf_base = ctx->tess_factor_offset;
2620 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2621 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
2622 unsigned tf_offset = 0;
2623
2624 if (ctx->options->chip_class <= VI) {
2625 ac_nir_build_if(&inner_if_ctx, ctx,
2626 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2627 rel_patch_id, ctx->ac.i32_0, ""));
2628
2629 /* Store the dynamic HS control word. */
2630 ac_build_buffer_store_dword(&ctx->ac, buffer,
2631 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
2632 1, ctx->ac.i32_0, tf_base,
2633 0, 1, 0, true, false);
2634 tf_offset += 4;
2635
2636 ac_nir_build_endif(&inner_if_ctx);
2637 }
2638
2639 /* Store the tessellation factors. */
2640 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2641 MIN2(stride, 4), byteoffset, tf_base,
2642 tf_offset, 1, 0, true, false);
2643 if (vec1)
2644 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2645 stride - 4, byteoffset, tf_base,
2646 16 + tf_offset, 1, 0, true, false);
2647
2648 //store to offchip for TES to read - only if TES reads them
2649 if (ctx->options->key.tcs.tes_reads_tess_factors) {
2650 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
2651 LLVMValueRef tf_inner_offset;
2652 unsigned param_outer, param_inner;
2653
2654 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2655 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
2656 LLVMConstInt(ctx->ac.i32, param_outer, 0));
2657
2658 outer_vec = ac_build_gather_values(&ctx->ac, outer,
2659 util_next_power_of_two(outer_comps));
2660
2661 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
2662 outer_comps, tf_outer_offset,
2663 ctx->oc_lds, 0, 1, 0, true, false);
2664 if (inner_comps) {
2665 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2666 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
2667 LLVMConstInt(ctx->ac.i32, param_inner, 0));
2668
2669 inner_vec = inner_comps == 1 ? inner[0] :
2670 ac_build_gather_values(&ctx->ac, inner, inner_comps);
2671 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
2672 inner_comps, tf_inner_offset,
2673 ctx->oc_lds, 0, 1, 0, true, false);
2674 }
2675 }
2676 ac_nir_build_endif(&if_ctx);
2677 }
2678
2679 static void
2680 handle_tcs_outputs_post(struct radv_shader_context *ctx)
2681 {
2682 write_tess_factors(ctx);
2683 }
2684
2685 static bool
2686 si_export_mrt_color(struct radv_shader_context *ctx,
2687 LLVMValueRef *color, unsigned index,
2688 struct ac_export_args *args)
2689 {
2690 /* Export */
2691 si_llvm_init_export_args(ctx, color, 0xf,
2692 V_008DFC_SQ_EXP_MRT + index, args);
2693 if (!args->enabled_channels)
2694 return false; /* unnecessary NULL export */
2695
2696 return true;
2697 }
2698
2699 static void
2700 radv_export_mrt_z(struct radv_shader_context *ctx,
2701 LLVMValueRef depth, LLVMValueRef stencil,
2702 LLVMValueRef samplemask)
2703 {
2704 struct ac_export_args args;
2705
2706 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
2707
2708 ac_build_export(&ctx->ac, &args);
2709 }
2710
2711 static void
2712 handle_fs_outputs_post(struct radv_shader_context *ctx)
2713 {
2714 unsigned index = 0;
2715 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2716 struct ac_export_args color_args[8];
2717
2718 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2719 LLVMValueRef values[4];
2720
2721 if (!(ctx->output_mask & (1ull << i)))
2722 continue;
2723
2724 if (i < FRAG_RESULT_DATA0)
2725 continue;
2726
2727 for (unsigned j = 0; j < 4; j++)
2728 values[j] = ac_to_float(&ctx->ac,
2729 radv_load_output(ctx, i, j));
2730
2731 bool ret = si_export_mrt_color(ctx, values,
2732 i - FRAG_RESULT_DATA0,
2733 &color_args[index]);
2734 if (ret)
2735 index++;
2736 }
2737
2738 /* Process depth, stencil, samplemask. */
2739 if (ctx->shader_info->info.ps.writes_z) {
2740 depth = ac_to_float(&ctx->ac,
2741 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
2742 }
2743 if (ctx->shader_info->info.ps.writes_stencil) {
2744 stencil = ac_to_float(&ctx->ac,
2745 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
2746 }
2747 if (ctx->shader_info->info.ps.writes_sample_mask) {
2748 samplemask = ac_to_float(&ctx->ac,
2749 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
2750 }
2751
2752 /* Set the DONE bit on last non-null color export only if Z isn't
2753 * exported.
2754 */
2755 if (index > 0 &&
2756 !ctx->shader_info->info.ps.writes_z &&
2757 !ctx->shader_info->info.ps.writes_stencil &&
2758 !ctx->shader_info->info.ps.writes_sample_mask) {
2759 unsigned last = index - 1;
2760
2761 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
2762 color_args[last].done = 1; /* DONE bit */
2763 }
2764
2765 /* Export PS outputs. */
2766 for (unsigned i = 0; i < index; i++)
2767 ac_build_export(&ctx->ac, &color_args[i]);
2768
2769 if (depth || stencil || samplemask)
2770 radv_export_mrt_z(ctx, depth, stencil, samplemask);
2771 else if (!index)
2772 ac_build_export_null(&ctx->ac);
2773 }
2774
2775 static void
2776 emit_gs_epilogue(struct radv_shader_context *ctx)
2777 {
2778 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
2779 }
2780
2781 static void
2782 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
2783 LLVMValueRef *addrs)
2784 {
2785 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2786
2787 switch (ctx->stage) {
2788 case MESA_SHADER_VERTEX:
2789 if (ctx->options->key.vs.as_ls)
2790 handle_ls_outputs_post(ctx);
2791 else if (ctx->options->key.vs.as_es)
2792 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
2793 else
2794 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
2795 &ctx->shader_info->vs.outinfo);
2796 break;
2797 case MESA_SHADER_FRAGMENT:
2798 handle_fs_outputs_post(ctx);
2799 break;
2800 case MESA_SHADER_GEOMETRY:
2801 emit_gs_epilogue(ctx);
2802 break;
2803 case MESA_SHADER_TESS_CTRL:
2804 handle_tcs_outputs_post(ctx);
2805 break;
2806 case MESA_SHADER_TESS_EVAL:
2807 if (ctx->options->key.tes.as_es)
2808 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
2809 else
2810 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
2811 &ctx->shader_info->tes.outinfo);
2812 break;
2813 default:
2814 break;
2815 }
2816 }
2817
2818 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
2819 {
2820 LLVMPassManagerRef passmgr;
2821 /* Create the pass manager */
2822 passmgr = LLVMCreateFunctionPassManagerForModule(
2823 ctx->ac.module);
2824
2825 /* This pass should eliminate all the load and store instructions */
2826 LLVMAddPromoteMemoryToRegisterPass(passmgr);
2827
2828 /* Add some optimization passes */
2829 LLVMAddScalarReplAggregatesPass(passmgr);
2830 LLVMAddLICMPass(passmgr);
2831 LLVMAddAggressiveDCEPass(passmgr);
2832 LLVMAddCFGSimplificationPass(passmgr);
2833 LLVMAddInstructionCombiningPass(passmgr);
2834
2835 /* Run the pass */
2836 LLVMInitializeFunctionPassManager(passmgr);
2837 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
2838 LLVMFinalizeFunctionPassManager(passmgr);
2839
2840 LLVMDisposeBuilder(ctx->ac.builder);
2841 LLVMDisposePassManager(passmgr);
2842
2843 ac_llvm_context_dispose(&ctx->ac);
2844 }
2845
2846 static void
2847 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
2848 {
2849 struct radv_vs_output_info *outinfo;
2850
2851 switch (ctx->stage) {
2852 case MESA_SHADER_FRAGMENT:
2853 case MESA_SHADER_COMPUTE:
2854 case MESA_SHADER_TESS_CTRL:
2855 case MESA_SHADER_GEOMETRY:
2856 return;
2857 case MESA_SHADER_VERTEX:
2858 if (ctx->options->key.vs.as_ls ||
2859 ctx->options->key.vs.as_es)
2860 return;
2861 outinfo = &ctx->shader_info->vs.outinfo;
2862 break;
2863 case MESA_SHADER_TESS_EVAL:
2864 if (ctx->options->key.vs.as_es)
2865 return;
2866 outinfo = &ctx->shader_info->tes.outinfo;
2867 break;
2868 default:
2869 unreachable("Unhandled shader type");
2870 }
2871
2872 ac_optimize_vs_outputs(&ctx->ac,
2873 ctx->main_function,
2874 outinfo->vs_output_param_offset,
2875 VARYING_SLOT_MAX,
2876 &outinfo->param_exports);
2877 }
2878
2879 static void
2880 ac_setup_rings(struct radv_shader_context *ctx)
2881 {
2882 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
2883 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
2884 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
2885 }
2886
2887 if (ctx->is_gs_copy_shader) {
2888 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
2889 }
2890 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2891 LLVMValueRef tmp;
2892 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
2893 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
2894
2895 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
2896
2897 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
2898 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
2899 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
2900 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
2901 }
2902
2903 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
2904 ctx->stage == MESA_SHADER_TESS_EVAL) {
2905 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
2906 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
2907 }
2908 }
2909
2910 static unsigned
2911 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
2912 const struct nir_shader *nir)
2913 {
2914 switch (nir->info.stage) {
2915 case MESA_SHADER_TESS_CTRL:
2916 return chip_class >= CIK ? 128 : 64;
2917 case MESA_SHADER_GEOMETRY:
2918 return chip_class >= GFX9 ? 128 : 64;
2919 case MESA_SHADER_COMPUTE:
2920 break;
2921 default:
2922 return 0;
2923 }
2924
2925 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
2926 nir->info.cs.local_size[1] *
2927 nir->info.cs.local_size[2];
2928 return max_workgroup_size;
2929 }
2930
2931 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
2932 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
2933 {
2934 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2935 LLVMConstInt(ctx->ac.i32, 8, false),
2936 LLVMConstInt(ctx->ac.i32, 8, false), false);
2937 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
2938 ctx->ac.i32_0, "");
2939 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
2940 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
2941 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
2942 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
2943 }
2944
2945 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
2946 {
2947 for(int i = 5; i >= 0; --i) {
2948 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
2949 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
2950 LLVMConstInt(ctx->ac.i32, 16, false), false);
2951 }
2952
2953 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2954 LLVMConstInt(ctx->ac.i32, 16, false),
2955 LLVMConstInt(ctx->ac.i32, 8, false), false);
2956 }
2957
2958
2959 static
2960 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
2961 struct nir_shader *const *shaders,
2962 int shader_count,
2963 struct radv_shader_variant_info *shader_info,
2964 const struct radv_nir_compiler_options *options)
2965 {
2966 struct radv_shader_context ctx = {0};
2967 unsigned i;
2968 ctx.options = options;
2969 ctx.shader_info = shader_info;
2970 ctx.context = LLVMContextCreate();
2971
2972 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
2973 options->family);
2974 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
2975 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
2976
2977 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
2978 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
2979 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
2980 LLVMDisposeTargetData(data_layout);
2981 LLVMDisposeMessage(data_layout_str);
2982
2983 enum ac_float_mode float_mode =
2984 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
2985 AC_FLOAT_MODE_DEFAULT;
2986
2987 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
2988
2989 memset(shader_info, 0, sizeof(*shader_info));
2990
2991 for(int i = 0; i < shader_count; ++i)
2992 radv_nir_shader_info_pass(shaders[i], options, &shader_info->info);
2993
2994 for (i = 0; i < RADV_UD_MAX_SETS; i++)
2995 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
2996 for (i = 0; i < AC_UD_MAX_UD; i++)
2997 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
2998
2999 ctx.max_workgroup_size = 0;
3000 for (int i = 0; i < shader_count; ++i) {
3001 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3002 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
3003 shaders[i]));
3004 }
3005
3006 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
3007 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
3008
3009 ctx.abi.inputs = &ctx.inputs[0];
3010 ctx.abi.emit_outputs = handle_shader_outputs_post;
3011 ctx.abi.emit_vertex = visit_emit_vertex;
3012 ctx.abi.load_ubo = radv_load_ubo;
3013 ctx.abi.load_ssbo = radv_load_ssbo;
3014 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3015 ctx.abi.load_resource = radv_load_resource;
3016 ctx.abi.clamp_shadow_reference = false;
3017
3018 if (shader_count >= 2)
3019 ac_init_exec_full_mask(&ctx.ac);
3020
3021 if (ctx.ac.chip_class == GFX9 &&
3022 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3023 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3024
3025 for(int i = 0; i < shader_count; ++i) {
3026 ctx.stage = shaders[i]->info.stage;
3027 ctx.output_mask = 0;
3028 ctx.tess_outputs_written = 0;
3029 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
3030 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
3031
3032 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3033 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
3034 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
3035 ctx.abi.load_inputs = load_gs_input;
3036 ctx.abi.emit_primitive = visit_end_primitive;
3037 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3038 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
3039 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
3040 ctx.abi.load_tess_varyings = load_tcs_varyings;
3041 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3042 ctx.abi.store_tcs_outputs = store_tcs_output;
3043 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3044 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
3045 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
3046 ctx.abi.load_tess_varyings = load_tes_input;
3047 ctx.abi.load_tess_coord = load_tess_coord;
3048 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3049 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3050 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
3051 if (shader_info->info.vs.needs_instance_id) {
3052 if (ctx.options->key.vs.as_ls) {
3053 ctx.shader_info->vs.vgpr_comp_cnt =
3054 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
3055 } else {
3056 ctx.shader_info->vs.vgpr_comp_cnt =
3057 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
3058 }
3059 }
3060 ctx.abi.load_base_vertex = radv_load_base_vertex;
3061 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
3062 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
3063 ctx.abi.lookup_interp_param = lookup_interp_param;
3064 ctx.abi.load_sample_position = load_sample_position;
3065 ctx.abi.load_sample_mask_in = load_sample_mask_in;
3066 ctx.abi.emit_kill = radv_emit_kill;
3067 }
3068
3069 if (i)
3070 ac_emit_barrier(&ctx.ac, ctx.stage);
3071
3072 ac_setup_rings(&ctx);
3073
3074 LLVMBasicBlockRef merge_block;
3075 if (shader_count >= 2) {
3076 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
3077 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3078 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3079
3080 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
3081 LLVMConstInt(ctx.ac.i32, 8 * i, false),
3082 LLVMConstInt(ctx.ac.i32, 8, false), false);
3083 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
3084 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
3085 thread_id, count, "");
3086 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
3087
3088 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
3089 }
3090
3091 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
3092 handle_fs_inputs(&ctx, shaders[i]);
3093 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
3094 handle_vs_inputs(&ctx, shaders[i]);
3095 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
3096 prepare_gs_input_vgprs(&ctx);
3097
3098 nir_foreach_variable(variable, &shaders[i]->outputs)
3099 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
3100
3101 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
3102
3103 if (shader_count >= 2) {
3104 LLVMBuildBr(ctx.ac.builder, merge_block);
3105 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
3106 }
3107
3108 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3109 unsigned addclip = shaders[i]->info.clip_distance_array_size +
3110 shaders[i]->info.cull_distance_array_size > 4;
3111 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
3112 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
3113 shaders[i]->info.gs.vertices_out;
3114 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3115 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
3116 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
3117 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
3118 shader_info->vs.outputs_written = ctx.tess_outputs_written;
3119 }
3120 }
3121
3122 LLVMBuildRetVoid(ctx.ac.builder);
3123
3124 if (options->dump_preoptir)
3125 ac_dump_module(ctx.ac.module);
3126
3127 ac_llvm_finalize_module(&ctx);
3128
3129 if (shader_count == 1)
3130 ac_nir_eliminate_const_vs_outputs(&ctx);
3131
3132 if (options->dump_shader) {
3133 ctx.shader_info->private_mem_vgprs =
3134 ac_count_scratch_private_memory(ctx.main_function);
3135 }
3136
3137 return ctx.ac.module;
3138 }
3139
3140 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
3141 {
3142 unsigned *retval = (unsigned *)context;
3143 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
3144 char *description = LLVMGetDiagInfoDescription(di);
3145
3146 if (severity == LLVMDSError) {
3147 *retval = 1;
3148 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
3149 description);
3150 }
3151
3152 LLVMDisposeMessage(description);
3153 }
3154
3155 static unsigned ac_llvm_compile(LLVMModuleRef M,
3156 struct ac_shader_binary *binary,
3157 LLVMTargetMachineRef tm)
3158 {
3159 unsigned retval = 0;
3160 char *err;
3161 LLVMContextRef llvm_ctx;
3162 LLVMMemoryBufferRef out_buffer;
3163 unsigned buffer_size;
3164 const char *buffer_data;
3165 LLVMBool mem_err;
3166
3167 /* Setup Diagnostic Handler*/
3168 llvm_ctx = LLVMGetModuleContext(M);
3169
3170 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
3171 &retval);
3172
3173 /* Compile IR*/
3174 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
3175 &err, &out_buffer);
3176
3177 /* Process Errors/Warnings */
3178 if (mem_err) {
3179 fprintf(stderr, "%s: %s", __FUNCTION__, err);
3180 free(err);
3181 retval = 1;
3182 goto out;
3183 }
3184
3185 /* Extract Shader Code*/
3186 buffer_size = LLVMGetBufferSize(out_buffer);
3187 buffer_data = LLVMGetBufferStart(out_buffer);
3188
3189 ac_elf_read(buffer_data, buffer_size, binary);
3190
3191 /* Clean up */
3192 LLVMDisposeMemoryBuffer(out_buffer);
3193
3194 out:
3195 return retval;
3196 }
3197
3198 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
3199 LLVMModuleRef llvm_module,
3200 struct ac_shader_binary *binary,
3201 struct ac_shader_config *config,
3202 struct radv_shader_variant_info *shader_info,
3203 gl_shader_stage stage,
3204 const struct radv_nir_compiler_options *options)
3205 {
3206 if (options->dump_shader)
3207 ac_dump_module(llvm_module);
3208
3209 memset(binary, 0, sizeof(*binary));
3210
3211 if (options->record_llvm_ir) {
3212 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
3213 binary->llvm_ir_string = strdup(llvm_ir);
3214 LLVMDisposeMessage(llvm_ir);
3215 }
3216
3217 int v = ac_llvm_compile(llvm_module, binary, tm);
3218 if (v) {
3219 fprintf(stderr, "compile failed\n");
3220 }
3221
3222 if (options->dump_shader)
3223 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
3224
3225 ac_shader_binary_read_config(binary, config, 0, options->supports_spill);
3226
3227 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
3228 LLVMDisposeModule(llvm_module);
3229 LLVMContextDispose(ctx);
3230
3231 if (stage == MESA_SHADER_FRAGMENT) {
3232 shader_info->num_input_vgprs = 0;
3233 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
3234 shader_info->num_input_vgprs += 2;
3235 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
3236 shader_info->num_input_vgprs += 2;
3237 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
3238 shader_info->num_input_vgprs += 2;
3239 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
3240 shader_info->num_input_vgprs += 3;
3241 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
3242 shader_info->num_input_vgprs += 2;
3243 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
3244 shader_info->num_input_vgprs += 2;
3245 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
3246 shader_info->num_input_vgprs += 2;
3247 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
3248 shader_info->num_input_vgprs += 1;
3249 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
3250 shader_info->num_input_vgprs += 1;
3251 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
3252 shader_info->num_input_vgprs += 1;
3253 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
3254 shader_info->num_input_vgprs += 1;
3255 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
3256 shader_info->num_input_vgprs += 1;
3257 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
3258 shader_info->num_input_vgprs += 1;
3259 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
3260 shader_info->num_input_vgprs += 1;
3261 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
3262 shader_info->num_input_vgprs += 1;
3263 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
3264 shader_info->num_input_vgprs += 1;
3265 }
3266 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
3267
3268 /* +3 for scratch wave offset and VCC */
3269 config->num_sgprs = MAX2(config->num_sgprs,
3270 shader_info->num_input_sgprs + 3);
3271
3272 /* Enable 64-bit and 16-bit denormals, because there is no performance
3273 * cost.
3274 *
3275 * If denormals are enabled, all floating-point output modifiers are
3276 * ignored.
3277 *
3278 * Don't enable denormals for 32-bit floats, because:
3279 * - Floating-point output modifiers would be ignored by the hw.
3280 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3281 * have to stop using those.
3282 * - SI & CI would be very slow.
3283 */
3284 config->float_mode |= V_00B028_FP_64_DENORMS;
3285 }
3286
3287 static void
3288 ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct radv_nir_compiler_options *options)
3289 {
3290 switch (nir->info.stage) {
3291 case MESA_SHADER_COMPUTE:
3292 for (int i = 0; i < 3; ++i)
3293 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
3294 break;
3295 case MESA_SHADER_FRAGMENT:
3296 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
3297 break;
3298 case MESA_SHADER_GEOMETRY:
3299 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
3300 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
3301 shader_info->gs.output_prim = nir->info.gs.output_primitive;
3302 shader_info->gs.invocations = nir->info.gs.invocations;
3303 break;
3304 case MESA_SHADER_TESS_EVAL:
3305 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
3306 shader_info->tes.spacing = nir->info.tess.spacing;
3307 shader_info->tes.ccw = nir->info.tess.ccw;
3308 shader_info->tes.point_mode = nir->info.tess.point_mode;
3309 shader_info->tes.as_es = options->key.tes.as_es;
3310 break;
3311 case MESA_SHADER_TESS_CTRL:
3312 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
3313 break;
3314 case MESA_SHADER_VERTEX:
3315 shader_info->vs.as_es = options->key.vs.as_es;
3316 shader_info->vs.as_ls = options->key.vs.as_ls;
3317 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3318 if (options->key.vs.as_ls)
3319 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
3320 break;
3321 default:
3322 break;
3323 }
3324 }
3325
3326 void
3327 radv_compile_nir_shader(LLVMTargetMachineRef tm,
3328 struct ac_shader_binary *binary,
3329 struct ac_shader_config *config,
3330 struct radv_shader_variant_info *shader_info,
3331 struct nir_shader *const *nir,
3332 int nir_count,
3333 const struct radv_nir_compiler_options *options)
3334 {
3335
3336 LLVMModuleRef llvm_module;
3337
3338 llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
3339 options);
3340
3341 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info,
3342 nir[0]->info.stage, options);
3343
3344 for (int i = 0; i < nir_count; ++i)
3345 ac_fill_shader_info(shader_info, nir[i], options);
3346
3347 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3348 if (options->chip_class == GFX9) {
3349 if (nir_count == 2 &&
3350 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
3351 shader_info->gs.es_type = nir[0]->info.stage;
3352 }
3353 }
3354 }
3355
3356 static void
3357 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
3358 {
3359 LLVMValueRef vtx_offset =
3360 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
3361 LLVMConstInt(ctx->ac.i32, 4, false), "");
3362 int idx = 0;
3363
3364 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3365 int length = 4;
3366 int slot = idx;
3367 int slot_inc = 1;
3368 if (!(ctx->output_mask & (1ull << i)))
3369 continue;
3370
3371 if (i == VARYING_SLOT_CLIP_DIST0) {
3372 /* unpack clip and cull from a single set of slots */
3373 length = ctx->num_output_clips + ctx->num_output_culls;
3374 if (length > 4)
3375 slot_inc = 2;
3376 }
3377
3378 for (unsigned j = 0; j < length; j++) {
3379 LLVMValueRef value, soffset;
3380
3381 soffset = LLVMConstInt(ctx->ac.i32,
3382 (slot * 4 + j) *
3383 ctx->gs_max_out_vertices * 16 * 4, false);
3384
3385 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
3386 1, ctx->ac.i32_0,
3387 vtx_offset, soffset,
3388 0, 1, 1, true, false);
3389
3390 LLVMBuildStore(ctx->ac.builder,
3391 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3392 }
3393 idx += slot_inc;
3394 }
3395 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
3396 }
3397
3398 void
3399 radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
3400 struct nir_shader *geom_shader,
3401 struct ac_shader_binary *binary,
3402 struct ac_shader_config *config,
3403 struct radv_shader_variant_info *shader_info,
3404 const struct radv_nir_compiler_options *options)
3405 {
3406 struct radv_shader_context ctx = {0};
3407 ctx.context = LLVMContextCreate();
3408 ctx.options = options;
3409 ctx.shader_info = shader_info;
3410
3411 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3412 options->family);
3413 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3414
3415 ctx.is_gs_copy_shader = true;
3416 LLVMSetTarget(ctx.ac.module, "amdgcn--");
3417
3418 enum ac_float_mode float_mode =
3419 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3420 AC_FLOAT_MODE_DEFAULT;
3421
3422 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3423 ctx.stage = MESA_SHADER_VERTEX;
3424
3425 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
3426
3427 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
3428 ac_setup_rings(&ctx);
3429
3430 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
3431 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
3432
3433 nir_foreach_variable(variable, &geom_shader->outputs) {
3434 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
3435 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
3436 variable, MESA_SHADER_VERTEX);
3437 }
3438
3439 ac_gs_copy_shader_emit(&ctx);
3440
3441 LLVMBuildRetVoid(ctx.ac.builder);
3442
3443 ac_llvm_finalize_module(&ctx);
3444
3445 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
3446 MESA_SHADER_VERTEX, options);
3447 }