2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #if HAVE_LLVM >= 0x0700
37 #include <llvm-c/Transforms/Utils.h>
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_llvm_build.h"
45 #include "ac_shader_abi.h"
46 #include "ac_shader_util.h"
47 #include "ac_exp_param.h"
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
51 struct radv_shader_context
{
52 struct ac_llvm_context ac
;
53 const struct radv_nir_compiler_options
*options
;
54 struct radv_shader_variant_info
*shader_info
;
55 struct ac_shader_abi abi
;
57 unsigned max_workgroup_size
;
58 LLVMContextRef context
;
59 LLVMValueRef main_function
;
61 LLVMValueRef descriptor_sets
[RADV_UD_MAX_SETS
];
62 LLVMValueRef ring_offsets
;
64 LLVMValueRef vertex_buffers
;
65 LLVMValueRef rel_auto_id
;
66 LLVMValueRef vs_prim_id
;
67 LLVMValueRef es2gs_offset
;
70 LLVMValueRef merged_wave_info
;
71 LLVMValueRef tess_factor_offset
;
72 LLVMValueRef tes_rel_patch_id
;
76 LLVMValueRef gs2vs_offset
;
77 LLVMValueRef gs_wave_id
;
78 LLVMValueRef gs_vtx_offset
[6];
80 LLVMValueRef esgs_ring
;
81 LLVMValueRef gsvs_ring
[4];
82 LLVMValueRef hs_ring_tess_offchip
;
83 LLVMValueRef hs_ring_tess_factor
;
85 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
86 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
89 LLVMValueRef streamout_buffers
;
90 LLVMValueRef streamout_write_idx
;
91 LLVMValueRef streamout_config
;
92 LLVMValueRef streamout_offset
[4];
94 gl_shader_stage stage
;
96 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
101 bool is_gs_copy_shader
;
102 LLVMValueRef gs_next_vertex
[4];
103 unsigned gs_max_out_vertices
;
105 unsigned tes_primitive_mode
;
107 uint32_t tcs_patch_outputs_read
;
108 uint64_t tcs_outputs_read
;
109 uint32_t tcs_vertices_per_patch
;
110 uint32_t tcs_num_inputs
;
111 uint32_t tcs_num_patches
;
112 uint32_t max_gsvs_emit_size
;
113 uint32_t gsvs_vertex_size
;
116 enum radeon_llvm_calling_convention
{
117 RADEON_LLVM_AMDGPU_VS
= 87,
118 RADEON_LLVM_AMDGPU_GS
= 88,
119 RADEON_LLVM_AMDGPU_PS
= 89,
120 RADEON_LLVM_AMDGPU_CS
= 90,
121 RADEON_LLVM_AMDGPU_HS
= 93,
124 static inline struct radv_shader_context
*
125 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
127 struct radv_shader_context
*ctx
= NULL
;
128 return container_of(abi
, ctx
, abi
);
131 struct ac_build_if_state
133 struct radv_shader_context
*ctx
;
134 LLVMValueRef condition
;
135 LLVMBasicBlockRef entry_block
;
136 LLVMBasicBlockRef true_block
;
137 LLVMBasicBlockRef false_block
;
138 LLVMBasicBlockRef merge_block
;
141 static LLVMBasicBlockRef
142 ac_build_insert_new_block(struct radv_shader_context
*ctx
, const char *name
)
144 LLVMBasicBlockRef current_block
;
145 LLVMBasicBlockRef next_block
;
146 LLVMBasicBlockRef new_block
;
148 /* get current basic block */
149 current_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
151 /* chqeck if there's another block after this one */
152 next_block
= LLVMGetNextBasicBlock(current_block
);
154 /* insert the new block before the next block */
155 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
158 /* append new block after current block */
159 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
160 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
166 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
167 struct radv_shader_context
*ctx
,
168 LLVMValueRef condition
)
170 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
172 memset(ifthen
, 0, sizeof *ifthen
);
174 ifthen
->condition
= condition
;
175 ifthen
->entry_block
= block
;
177 /* create endif/merge basic block for the phi functions */
178 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
180 /* create/insert true_block before merge_block */
182 LLVMInsertBasicBlockInContext(ctx
->context
,
186 /* successive code goes into the true block */
187 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ifthen
->true_block
);
194 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
196 LLVMBuilderRef builder
= ifthen
->ctx
->ac
.builder
;
198 /* Insert branch to the merge block from current block */
199 LLVMBuildBr(builder
, ifthen
->merge_block
);
202 * Now patch in the various branch instructions.
205 /* Insert the conditional branch instruction at the end of entry_block */
206 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
207 if (ifthen
->false_block
) {
208 /* we have an else clause */
209 LLVMBuildCondBr(builder
, ifthen
->condition
,
210 ifthen
->true_block
, ifthen
->false_block
);
214 LLVMBuildCondBr(builder
, ifthen
->condition
,
215 ifthen
->true_block
, ifthen
->merge_block
);
218 /* Resume building code at end of the ifthen->merge_block */
219 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
223 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
225 switch (ctx
->stage
) {
226 case MESA_SHADER_TESS_CTRL
:
227 return ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
228 case MESA_SHADER_TESS_EVAL
:
229 return ctx
->tes_rel_patch_id
;
232 unreachable("Illegal stage");
237 get_tcs_num_patches(struct radv_shader_context
*ctx
)
239 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
240 unsigned num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
241 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
242 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
243 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
244 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
245 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
246 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
247 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
248 unsigned num_patches
;
249 unsigned hardware_lds_size
;
251 /* Ensure that we only need one wave per SIMD so we don't need to check
252 * resource usage. Also ensures that the number of tcs in and out
253 * vertices per threadgroup are at most 256.
255 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
256 /* Make sure that the data fits in LDS. This assumes the shaders only
257 * use LDS for the inputs and outputs.
259 hardware_lds_size
= ctx
->options
->chip_class
>= CIK
? 65536 : 32768;
260 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
261 /* Make sure the output data fits in the offchip buffer */
262 num_patches
= MIN2(num_patches
, (ctx
->options
->tess_offchip_block_dw_size
* 4) / output_patch_size
);
263 /* Not necessary for correctness, but improves performance. The
264 * specific value is taken from the proprietary driver.
266 num_patches
= MIN2(num_patches
, 40);
268 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
269 if (ctx
->options
->chip_class
== SI
) {
270 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
271 num_patches
= MIN2(num_patches
, one_wave
);
277 calculate_tess_lds_size(struct radv_shader_context
*ctx
)
279 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
280 unsigned num_tcs_output_cp
;
281 unsigned num_tcs_outputs
, num_tcs_patch_outputs
;
282 unsigned input_vertex_size
, output_vertex_size
;
283 unsigned input_patch_size
, output_patch_size
;
284 unsigned pervertex_output_patch_size
;
285 unsigned output_patch0_offset
;
286 unsigned num_patches
;
289 num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
290 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
291 num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
293 input_vertex_size
= ctx
->tcs_num_inputs
* 16;
294 output_vertex_size
= num_tcs_outputs
* 16;
296 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
298 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
299 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
301 num_patches
= ctx
->tcs_num_patches
;
302 output_patch0_offset
= input_patch_size
* num_patches
;
304 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
308 /* Tessellation shaders pass outputs to the next shader using LDS.
310 * LS outputs = TCS inputs
311 * TCS outputs = TES inputs
314 * - TCS inputs for patch 0
315 * - TCS inputs for patch 1
316 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
318 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
319 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
320 * - TCS outputs for patch 1
321 * - Per-patch TCS outputs for patch 1
322 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
323 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
326 * All three shaders VS(LS), TCS, TES share the same LDS space.
329 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
331 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
332 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
333 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
335 input_patch_size
/= 4;
336 return LLVMConstInt(ctx
->ac
.i32
, input_patch_size
, false);
340 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
342 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
343 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
344 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
345 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
346 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
347 output_patch_size
/= 4;
348 return LLVMConstInt(ctx
->ac
.i32
, output_patch_size
, false);
352 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
354 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
355 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
356 output_vertex_size
/= 4;
357 return LLVMConstInt(ctx
->ac
.i32
, output_vertex_size
, false);
361 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
363 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
364 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
365 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
366 uint32_t output_patch0_offset
= input_patch_size
;
367 unsigned num_patches
= ctx
->tcs_num_patches
;
369 output_patch0_offset
*= num_patches
;
370 output_patch0_offset
/= 4;
371 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
375 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
377 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
378 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
379 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
380 uint32_t output_patch0_offset
= input_patch_size
;
382 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
383 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
384 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
385 unsigned num_patches
= ctx
->tcs_num_patches
;
387 output_patch0_offset
*= num_patches
;
388 output_patch0_offset
+= pervertex_output_patch_size
;
389 output_patch0_offset
/= 4;
390 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
394 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
396 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
397 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
399 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
403 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
405 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
406 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
407 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
409 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
414 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
416 LLVMValueRef patch0_patch_data_offset
=
417 get_tcs_out_patch0_patch_data_offset(ctx
);
418 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
419 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
421 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
422 patch0_patch_data_offset
);
427 LLVMTypeRef types
[MAX_ARGS
];
428 LLVMValueRef
*assign
[MAX_ARGS
];
429 unsigned array_params_mask
;
432 uint8_t num_sgprs_used
;
433 uint8_t num_vgprs_used
;
436 enum ac_arg_regfile
{
442 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
443 LLVMValueRef
*param_ptr
)
445 assert(info
->count
< MAX_ARGS
);
447 info
->assign
[info
->count
] = param_ptr
;
448 info
->types
[info
->count
] = type
;
451 if (regfile
== ARG_SGPR
) {
452 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
455 assert(regfile
== ARG_VGPR
);
456 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
461 add_array_arg(struct arg_info
*info
, LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
463 info
->array_params_mask
|= (1 << info
->count
);
464 add_arg(info
, ARG_SGPR
, type
, param_ptr
);
467 static void assign_arguments(LLVMValueRef main_function
,
468 struct arg_info
*info
)
471 for (i
= 0; i
< info
->count
; i
++) {
473 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
478 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
479 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
480 unsigned num_return_elems
,
481 struct arg_info
*args
,
482 unsigned max_workgroup_size
,
483 const struct radv_nir_compiler_options
*options
)
485 LLVMTypeRef main_function_type
, ret_type
;
486 LLVMBasicBlockRef main_function_body
;
488 if (num_return_elems
)
489 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
490 num_return_elems
, true);
492 ret_type
= LLVMVoidTypeInContext(ctx
);
494 /* Setup the function */
496 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
497 LLVMValueRef main_function
=
498 LLVMAddFunction(module
, "main", main_function_type
);
500 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
501 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
503 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
504 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
505 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
507 if (args
->array_params_mask
& (1 << i
)) {
508 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
509 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_NOALIAS
);
510 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
514 if (options
->address32_hi
) {
515 ac_llvm_add_target_dep_function_attr(main_function
,
516 "amdgpu-32bit-address-high-bits",
517 options
->address32_hi
);
520 if (max_workgroup_size
) {
521 ac_llvm_add_target_dep_function_attr(main_function
,
522 "amdgpu-max-work-group-size",
525 if (options
->unsafe_math
) {
526 /* These were copied from some LLVM test. */
527 LLVMAddTargetDependentFunctionAttr(main_function
,
528 "less-precise-fpmad",
530 LLVMAddTargetDependentFunctionAttr(main_function
,
533 LLVMAddTargetDependentFunctionAttr(main_function
,
536 LLVMAddTargetDependentFunctionAttr(main_function
,
539 LLVMAddTargetDependentFunctionAttr(main_function
,
540 "no-signed-zeros-fp-math",
543 return main_function
;
548 set_loc(struct radv_userdata_info
*ud_info
, uint8_t *sgpr_idx
,
549 uint8_t num_sgprs
, bool indirect
)
551 ud_info
->sgpr_idx
= *sgpr_idx
;
552 ud_info
->num_sgprs
= num_sgprs
;
553 ud_info
->indirect
= indirect
;
554 *sgpr_idx
+= num_sgprs
;
558 set_loc_shader(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
561 struct radv_userdata_info
*ud_info
=
562 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
565 set_loc(ud_info
, sgpr_idx
, num_sgprs
, false);
569 set_loc_shader_ptr(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
571 bool use_32bit_pointers
= HAVE_32BIT_POINTERS
&&
572 idx
!= AC_UD_SCRATCH_RING_OFFSETS
;
574 set_loc_shader(ctx
, idx
, sgpr_idx
, use_32bit_pointers
? 1 : 2);
578 set_loc_desc(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
581 struct radv_userdata_locations
*locs
=
582 &ctx
->shader_info
->user_sgprs_locs
;
583 struct radv_userdata_info
*ud_info
= &locs
->descriptor_sets
[idx
];
586 set_loc(ud_info
, sgpr_idx
, HAVE_32BIT_POINTERS
? 1 : 2, indirect
);
589 locs
->descriptor_sets_enabled
|= 1 << idx
;
592 struct user_sgpr_info
{
593 bool need_ring_offsets
;
594 bool indirect_all_descriptor_sets
;
597 static bool needs_view_index_sgpr(struct radv_shader_context
*ctx
,
598 gl_shader_stage stage
)
601 case MESA_SHADER_VERTEX
:
602 if (ctx
->shader_info
->info
.needs_multiview_view_index
||
603 (!ctx
->options
->key
.vs
.as_es
&& !ctx
->options
->key
.vs
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
606 case MESA_SHADER_TESS_EVAL
:
607 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.tes
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
610 case MESA_SHADER_GEOMETRY
:
611 case MESA_SHADER_TESS_CTRL
:
612 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
622 count_vs_user_sgprs(struct radv_shader_context
*ctx
)
626 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
)
627 count
+= HAVE_32BIT_POINTERS
? 1 : 2;
628 count
+= ctx
->shader_info
->info
.vs
.needs_draw_id
? 3 : 2;
633 static void allocate_user_sgprs(struct radv_shader_context
*ctx
,
634 gl_shader_stage stage
,
635 bool has_previous_stage
,
636 gl_shader_stage previous_stage
,
637 bool needs_view_index
,
638 struct user_sgpr_info
*user_sgpr_info
)
640 uint8_t user_sgpr_count
= 0;
642 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
644 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
645 if (stage
== MESA_SHADER_GEOMETRY
||
646 stage
== MESA_SHADER_VERTEX
||
647 stage
== MESA_SHADER_TESS_CTRL
||
648 stage
== MESA_SHADER_TESS_EVAL
||
649 ctx
->is_gs_copy_shader
)
650 user_sgpr_info
->need_ring_offsets
= true;
652 if (stage
== MESA_SHADER_FRAGMENT
&&
653 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
654 user_sgpr_info
->need_ring_offsets
= true;
656 /* 2 user sgprs will nearly always be allocated for scratch/rings */
657 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
658 user_sgpr_count
+= 2;
662 case MESA_SHADER_COMPUTE
:
663 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
664 user_sgpr_count
+= 3;
666 case MESA_SHADER_FRAGMENT
:
667 user_sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
669 case MESA_SHADER_VERTEX
:
670 if (!ctx
->is_gs_copy_shader
)
671 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
673 case MESA_SHADER_TESS_CTRL
:
674 if (has_previous_stage
) {
675 if (previous_stage
== MESA_SHADER_VERTEX
)
676 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
679 case MESA_SHADER_TESS_EVAL
:
681 case MESA_SHADER_GEOMETRY
:
682 if (has_previous_stage
) {
683 if (previous_stage
== MESA_SHADER_VERTEX
) {
684 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
692 if (needs_view_index
)
695 if (ctx
->shader_info
->info
.loads_push_constants
)
696 user_sgpr_count
+= HAVE_32BIT_POINTERS
? 1 : 2;
698 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
&& stage
!= MESA_SHADER_COMPUTE
? 32 : 16;
699 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_count
;
700 uint32_t num_desc_set
=
701 util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
);
703 if (remaining_sgprs
/ (HAVE_32BIT_POINTERS
? 1 : 2) < num_desc_set
) {
704 user_sgpr_info
->indirect_all_descriptor_sets
= true;
709 declare_global_input_sgprs(struct radv_shader_context
*ctx
,
710 gl_shader_stage stage
,
711 bool has_previous_stage
,
712 gl_shader_stage previous_stage
,
713 const struct user_sgpr_info
*user_sgpr_info
,
714 struct arg_info
*args
,
715 LLVMValueRef
*desc_sets
)
717 LLVMTypeRef type
= ac_array_in_const32_addr_space(ctx
->ac
.i8
);
718 unsigned num_sets
= ctx
->options
->layout
?
719 ctx
->options
->layout
->num_sets
: 0;
720 unsigned stage_mask
= 1 << stage
;
722 if (has_previous_stage
)
723 stage_mask
|= 1 << previous_stage
;
725 /* 1 for each descriptor set */
726 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
727 for (unsigned i
= 0; i
< num_sets
; ++i
) {
728 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
729 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
730 add_array_arg(args
, type
,
731 &ctx
->descriptor_sets
[i
]);
735 add_array_arg(args
, ac_array_in_const32_addr_space(type
), desc_sets
);
738 if (ctx
->shader_info
->info
.loads_push_constants
) {
739 /* 1 for push constants and dynamic descriptors */
740 add_array_arg(args
, type
, &ctx
->abi
.push_constants
);
743 if (ctx
->shader_info
->info
.so
.num_outputs
) {
744 add_arg(args
, ARG_SGPR
,
745 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
746 &ctx
->streamout_buffers
);
751 declare_vs_specific_input_sgprs(struct radv_shader_context
*ctx
,
752 gl_shader_stage stage
,
753 bool has_previous_stage
,
754 gl_shader_stage previous_stage
,
755 struct arg_info
*args
)
757 if (!ctx
->is_gs_copy_shader
&&
758 (stage
== MESA_SHADER_VERTEX
||
759 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
760 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
761 add_arg(args
, ARG_SGPR
,
762 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
763 &ctx
->vertex_buffers
);
765 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
766 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
767 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
768 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
774 declare_vs_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
776 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
777 if (!ctx
->is_gs_copy_shader
) {
778 if (ctx
->options
->key
.vs
.as_ls
) {
779 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
780 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
782 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
783 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
785 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
790 declare_streamout_sgprs(struct radv_shader_context
*ctx
, gl_shader_stage stage
,
791 struct arg_info
*args
)
795 /* Streamout SGPRs. */
796 if (ctx
->shader_info
->info
.so
.num_outputs
) {
797 assert(stage
== MESA_SHADER_VERTEX
||
798 stage
== MESA_SHADER_TESS_EVAL
);
800 if (stage
!= MESA_SHADER_TESS_EVAL
) {
801 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_config
);
803 args
->assign
[args
->count
- 1] = &ctx
->streamout_config
;
804 args
->types
[args
->count
- 1] = ctx
->ac
.i32
;
807 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_write_idx
);
810 /* A streamout buffer offset is loaded if the stride is non-zero. */
811 for (i
= 0; i
< 4; i
++) {
812 if (!ctx
->shader_info
->info
.so
.strides
[i
])
815 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_offset
[i
]);
820 declare_tes_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
822 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
823 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
824 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
825 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
829 set_global_input_locs(struct radv_shader_context
*ctx
, gl_shader_stage stage
,
830 bool has_previous_stage
, gl_shader_stage previous_stage
,
831 const struct user_sgpr_info
*user_sgpr_info
,
832 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
834 unsigned num_sets
= ctx
->options
->layout
?
835 ctx
->options
->layout
->num_sets
: 0;
836 unsigned stage_mask
= 1 << stage
;
838 if (has_previous_stage
)
839 stage_mask
|= 1 << previous_stage
;
841 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
842 for (unsigned i
= 0; i
< num_sets
; ++i
) {
843 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
844 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
845 set_loc_desc(ctx
, i
, user_sgpr_idx
, false);
847 ctx
->descriptor_sets
[i
] = NULL
;
850 set_loc_shader_ptr(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
853 for (unsigned i
= 0; i
< num_sets
; ++i
) {
854 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
855 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
856 ctx
->descriptor_sets
[i
] =
857 ac_build_load_to_sgpr(&ctx
->ac
,
859 LLVMConstInt(ctx
->ac
.i32
, i
, false));
862 ctx
->descriptor_sets
[i
] = NULL
;
864 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
867 if (ctx
->shader_info
->info
.loads_push_constants
) {
868 set_loc_shader_ptr(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
);
871 if (ctx
->streamout_buffers
) {
872 set_loc_shader_ptr(ctx
, AC_UD_STREAMOUT_BUFFERS
,
878 set_vs_specific_input_locs(struct radv_shader_context
*ctx
,
879 gl_shader_stage stage
, bool has_previous_stage
,
880 gl_shader_stage previous_stage
,
881 uint8_t *user_sgpr_idx
)
883 if (!ctx
->is_gs_copy_shader
&&
884 (stage
== MESA_SHADER_VERTEX
||
885 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
886 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
887 set_loc_shader_ptr(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
892 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
895 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
896 user_sgpr_idx
, vs_num
);
900 static void set_llvm_calling_convention(LLVMValueRef func
,
901 gl_shader_stage stage
)
903 enum radeon_llvm_calling_convention calling_conv
;
906 case MESA_SHADER_VERTEX
:
907 case MESA_SHADER_TESS_EVAL
:
908 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
910 case MESA_SHADER_GEOMETRY
:
911 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
913 case MESA_SHADER_TESS_CTRL
:
914 calling_conv
= RADEON_LLVM_AMDGPU_HS
;
916 case MESA_SHADER_FRAGMENT
:
917 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
919 case MESA_SHADER_COMPUTE
:
920 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
923 unreachable("Unhandle shader type");
926 LLVMSetFunctionCallConv(func
, calling_conv
);
929 static void create_function(struct radv_shader_context
*ctx
,
930 gl_shader_stage stage
,
931 bool has_previous_stage
,
932 gl_shader_stage previous_stage
)
934 uint8_t user_sgpr_idx
;
935 struct user_sgpr_info user_sgpr_info
;
936 struct arg_info args
= {};
937 LLVMValueRef desc_sets
;
938 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
939 allocate_user_sgprs(ctx
, stage
, has_previous_stage
,
940 previous_stage
, needs_view_index
, &user_sgpr_info
);
942 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
943 add_arg(&args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
948 case MESA_SHADER_COMPUTE
:
949 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
950 previous_stage
, &user_sgpr_info
,
953 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
954 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
955 &ctx
->abi
.num_work_groups
);
958 for (int i
= 0; i
< 3; i
++) {
959 ctx
->abi
.workgroup_ids
[i
] = NULL
;
960 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
961 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
962 &ctx
->abi
.workgroup_ids
[i
]);
966 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
967 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.tg_size
);
968 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
969 &ctx
->abi
.local_invocation_ids
);
971 case MESA_SHADER_VERTEX
:
972 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
973 previous_stage
, &user_sgpr_info
,
975 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
976 previous_stage
, &args
);
978 if (needs_view_index
)
979 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
980 &ctx
->abi
.view_index
);
981 if (ctx
->options
->key
.vs
.as_es
) {
982 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
984 } else if (ctx
->options
->key
.vs
.as_ls
) {
985 /* no extra parameters */
987 declare_streamout_sgprs(ctx
, stage
, &args
);
990 declare_vs_input_vgprs(ctx
, &args
);
992 case MESA_SHADER_TESS_CTRL
:
993 if (has_previous_stage
) {
994 // First 6 system regs
995 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
996 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
997 &ctx
->merged_wave_info
);
998 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
999 &ctx
->tess_factor_offset
);
1001 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1002 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1003 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1005 declare_global_input_sgprs(ctx
, stage
,
1008 &user_sgpr_info
, &args
,
1010 declare_vs_specific_input_sgprs(ctx
, stage
,
1012 previous_stage
, &args
);
1014 if (needs_view_index
)
1015 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1016 &ctx
->abi
.view_index
);
1018 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1019 &ctx
->abi
.tcs_patch_id
);
1020 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1021 &ctx
->abi
.tcs_rel_ids
);
1023 declare_vs_input_vgprs(ctx
, &args
);
1025 declare_global_input_sgprs(ctx
, stage
,
1028 &user_sgpr_info
, &args
,
1031 if (needs_view_index
)
1032 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1033 &ctx
->abi
.view_index
);
1035 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1036 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1037 &ctx
->tess_factor_offset
);
1038 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1039 &ctx
->abi
.tcs_patch_id
);
1040 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1041 &ctx
->abi
.tcs_rel_ids
);
1044 case MESA_SHADER_TESS_EVAL
:
1045 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
1046 previous_stage
, &user_sgpr_info
,
1049 if (needs_view_index
)
1050 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1051 &ctx
->abi
.view_index
);
1053 if (ctx
->options
->key
.tes
.as_es
) {
1054 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1055 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1056 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1057 &ctx
->es2gs_offset
);
1059 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1060 declare_streamout_sgprs(ctx
, stage
, &args
);
1061 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1063 declare_tes_input_vgprs(ctx
, &args
);
1065 case MESA_SHADER_GEOMETRY
:
1066 if (has_previous_stage
) {
1067 // First 6 system regs
1068 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1069 &ctx
->gs2vs_offset
);
1070 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1071 &ctx
->merged_wave_info
);
1072 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1074 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1075 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1076 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1078 declare_global_input_sgprs(ctx
, stage
,
1081 &user_sgpr_info
, &args
,
1084 if (previous_stage
!= MESA_SHADER_TESS_EVAL
) {
1085 declare_vs_specific_input_sgprs(ctx
, stage
,
1091 if (needs_view_index
)
1092 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1093 &ctx
->abi
.view_index
);
1095 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1096 &ctx
->gs_vtx_offset
[0]);
1097 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1098 &ctx
->gs_vtx_offset
[2]);
1099 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1100 &ctx
->abi
.gs_prim_id
);
1101 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1102 &ctx
->abi
.gs_invocation_id
);
1103 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1104 &ctx
->gs_vtx_offset
[4]);
1106 if (previous_stage
== MESA_SHADER_VERTEX
) {
1107 declare_vs_input_vgprs(ctx
, &args
);
1109 declare_tes_input_vgprs(ctx
, &args
);
1112 declare_global_input_sgprs(ctx
, stage
,
1115 &user_sgpr_info
, &args
,
1118 if (needs_view_index
)
1119 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1120 &ctx
->abi
.view_index
);
1122 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
1123 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
1124 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1125 &ctx
->gs_vtx_offset
[0]);
1126 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1127 &ctx
->gs_vtx_offset
[1]);
1128 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1129 &ctx
->abi
.gs_prim_id
);
1130 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1131 &ctx
->gs_vtx_offset
[2]);
1132 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1133 &ctx
->gs_vtx_offset
[3]);
1134 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1135 &ctx
->gs_vtx_offset
[4]);
1136 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1137 &ctx
->gs_vtx_offset
[5]);
1138 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1139 &ctx
->abi
.gs_invocation_id
);
1142 case MESA_SHADER_FRAGMENT
:
1143 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
1144 previous_stage
, &user_sgpr_info
,
1147 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.prim_mask
);
1148 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_sample
);
1149 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_center
);
1150 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
);
1151 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1152 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_sample
);
1153 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_center
);
1154 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
);
1155 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1156 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1157 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1158 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1159 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1160 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1161 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1162 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1163 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1166 unreachable("Shader stage not implemented");
1169 ctx
->main_function
= create_llvm_function(
1170 ctx
->context
, ctx
->ac
.module
, ctx
->ac
.builder
, NULL
, 0, &args
,
1171 ctx
->max_workgroup_size
, ctx
->options
);
1172 set_llvm_calling_convention(ctx
->main_function
, stage
);
1175 ctx
->shader_info
->num_input_vgprs
= 0;
1176 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1178 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1180 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1181 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1183 assign_arguments(ctx
->main_function
, &args
);
1187 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1188 set_loc_shader_ptr(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1190 if (ctx
->options
->supports_spill
) {
1191 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1192 LLVMPointerType(ctx
->ac
.i8
, AC_ADDR_SPACE_CONST
),
1193 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1194 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
1195 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1199 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1200 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1201 if (has_previous_stage
)
1204 set_global_input_locs(ctx
, stage
, has_previous_stage
, previous_stage
,
1205 &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1208 case MESA_SHADER_COMPUTE
:
1209 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1210 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1214 case MESA_SHADER_VERTEX
:
1215 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1216 previous_stage
, &user_sgpr_idx
);
1217 if (ctx
->abi
.view_index
)
1218 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1220 case MESA_SHADER_TESS_CTRL
:
1221 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1222 previous_stage
, &user_sgpr_idx
);
1223 if (ctx
->abi
.view_index
)
1224 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1226 case MESA_SHADER_TESS_EVAL
:
1227 if (ctx
->abi
.view_index
)
1228 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1230 case MESA_SHADER_GEOMETRY
:
1231 if (has_previous_stage
) {
1232 if (previous_stage
== MESA_SHADER_VERTEX
)
1233 set_vs_specific_input_locs(ctx
, stage
,
1238 if (ctx
->abi
.view_index
)
1239 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1241 case MESA_SHADER_FRAGMENT
:
1244 unreachable("Shader stage not implemented");
1247 if (stage
== MESA_SHADER_TESS_CTRL
||
1248 (stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_ls
) ||
1249 /* GFX9 has the ESGS ring buffer in LDS. */
1250 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
1251 ac_declare_lds_as_pointer(&ctx
->ac
);
1254 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1259 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
1260 unsigned desc_set
, unsigned binding
)
1262 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1263 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
1264 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
1265 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
1266 unsigned base_offset
= layout
->binding
[binding
].offset
;
1267 LLVMValueRef offset
, stride
;
1269 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
1270 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
1271 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
1272 layout
->binding
[binding
].dynamic_offset_offset
;
1273 desc_ptr
= ctx
->abi
.push_constants
;
1274 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
1275 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1277 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
1279 offset
= ac_build_imad(&ctx
->ac
, index
, stride
,
1280 LLVMConstInt(ctx
->ac
.i32
, base_offset
, false));
1282 desc_ptr
= ac_build_gep0(&ctx
->ac
, desc_ptr
, offset
);
1283 desc_ptr
= ac_cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
1284 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1290 /* The offchip buffer layout for TCS->TES is
1292 * - attribute 0 of patch 0 vertex 0
1293 * - attribute 0 of patch 0 vertex 1
1294 * - attribute 0 of patch 0 vertex 2
1296 * - attribute 0 of patch 1 vertex 0
1297 * - attribute 0 of patch 1 vertex 1
1299 * - attribute 1 of patch 0 vertex 0
1300 * - attribute 1 of patch 0 vertex 1
1302 * - per patch attribute 0 of patch 0
1303 * - per patch attribute 0 of patch 1
1306 * Note that every attribute has 4 components.
1308 static LLVMValueRef
get_non_vertex_index_offset(struct radv_shader_context
*ctx
)
1310 uint32_t num_patches
= ctx
->tcs_num_patches
;
1311 uint32_t num_tcs_outputs
;
1312 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
1313 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
1315 num_tcs_outputs
= ctx
->options
->key
.tes
.tcs_num_outputs
;
1317 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
1318 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
1320 return LLVMConstInt(ctx
->ac
.i32
, pervertex_output_patch_size
* num_patches
, false);
1323 static LLVMValueRef
calc_param_stride(struct radv_shader_context
*ctx
,
1324 LLVMValueRef vertex_index
)
1326 LLVMValueRef param_stride
;
1328 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
* ctx
->tcs_num_patches
, false);
1330 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_num_patches
, false);
1331 return param_stride
;
1334 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
1335 LLVMValueRef vertex_index
,
1336 LLVMValueRef param_index
)
1338 LLVMValueRef base_addr
;
1339 LLVMValueRef param_stride
, constant16
;
1340 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
1341 LLVMValueRef vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
, false);
1342 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1343 param_stride
= calc_param_stride(ctx
, vertex_index
);
1345 base_addr
= ac_build_imad(&ctx
->ac
, rel_patch_id
,
1346 vertices_per_patch
, vertex_index
);
1348 base_addr
= rel_patch_id
;
1351 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1352 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
1353 param_stride
, ""), "");
1355 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
1357 if (!vertex_index
) {
1358 LLVMValueRef patch_data_offset
= get_non_vertex_index_offset(ctx
);
1360 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1361 patch_data_offset
, "");
1366 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
1368 unsigned const_index
,
1370 LLVMValueRef vertex_index
,
1371 LLVMValueRef indir_index
)
1373 LLVMValueRef param_index
;
1376 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
1379 if (const_index
&& !is_compact
)
1380 param
+= const_index
;
1381 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
1383 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
1387 get_dw_address(struct radv_shader_context
*ctx
,
1388 LLVMValueRef dw_addr
,
1390 unsigned const_index
,
1391 bool compact_const_index
,
1392 LLVMValueRef vertex_index
,
1393 LLVMValueRef stride
,
1394 LLVMValueRef indir_index
)
1399 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1400 LLVMBuildMul(ctx
->ac
.builder
,
1406 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1407 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
1408 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
1409 else if (const_index
&& !compact_const_index
)
1410 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1411 LLVMConstInt(ctx
->ac
.i32
, const_index
* 4, false), "");
1413 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1414 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
1416 if (const_index
&& compact_const_index
)
1417 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1418 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
1423 load_tcs_varyings(struct ac_shader_abi
*abi
,
1425 LLVMValueRef vertex_index
,
1426 LLVMValueRef indir_index
,
1427 unsigned const_index
,
1429 unsigned driver_location
,
1431 unsigned num_components
,
1436 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1437 LLVMValueRef dw_addr
, stride
;
1438 LLVMValueRef value
[4], result
;
1439 unsigned param
= shader_io_get_unique_index(location
);
1442 uint32_t input_vertex_size
= (ctx
->tcs_num_inputs
* 16) / 4;
1443 stride
= LLVMConstInt(ctx
->ac
.i32
, input_vertex_size
, false);
1444 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1447 stride
= get_tcs_out_vertex_stride(ctx
);
1448 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1450 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1455 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1458 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
1459 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1460 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1463 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1468 store_tcs_output(struct ac_shader_abi
*abi
,
1469 const nir_variable
*var
,
1470 LLVMValueRef vertex_index
,
1471 LLVMValueRef param_index
,
1472 unsigned const_index
,
1476 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1477 const unsigned location
= var
->data
.location
;
1478 const unsigned component
= var
->data
.location_frac
;
1479 const bool is_patch
= var
->data
.patch
;
1480 const bool is_compact
= var
->data
.compact
;
1481 LLVMValueRef dw_addr
;
1482 LLVMValueRef stride
= NULL
;
1483 LLVMValueRef buf_addr
= NULL
;
1485 bool store_lds
= true;
1488 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
1491 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
1495 param
= shader_io_get_unique_index(location
);
1496 if (location
== VARYING_SLOT_CLIP_DIST0
&&
1497 is_compact
&& const_index
> 3) {
1503 stride
= get_tcs_out_vertex_stride(ctx
);
1504 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1506 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1509 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1511 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
1512 vertex_index
, param_index
);
1514 bool is_tess_factor
= false;
1515 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
1516 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
1517 is_tess_factor
= true;
1519 unsigned base
= is_compact
? const_index
: 0;
1520 for (unsigned chan
= 0; chan
< 8; chan
++) {
1521 if (!(writemask
& (1 << chan
)))
1523 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
1524 value
= ac_to_integer(&ctx
->ac
, value
);
1525 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
1527 if (store_lds
|| is_tess_factor
) {
1528 LLVMValueRef dw_addr_chan
=
1529 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1530 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
1531 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
1534 if (!is_tess_factor
&& writemask
!= 0xF)
1535 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
1536 buf_addr
, ctx
->oc_lds
,
1537 4 * (base
+ chan
), 1, 0, true, false);
1540 if (writemask
== 0xF) {
1541 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
1542 buf_addr
, ctx
->oc_lds
,
1543 (base
* 4), 1, 0, true, false);
1548 load_tes_input(struct ac_shader_abi
*abi
,
1550 LLVMValueRef vertex_index
,
1551 LLVMValueRef param_index
,
1552 unsigned const_index
,
1554 unsigned driver_location
,
1556 unsigned num_components
,
1561 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1562 LLVMValueRef buf_addr
;
1563 LLVMValueRef result
;
1564 unsigned param
= shader_io_get_unique_index(location
);
1566 if (location
== VARYING_SLOT_CLIP_DIST0
&& is_compact
&& const_index
> 3) {
1571 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
1572 is_compact
, vertex_index
, param_index
);
1574 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
1575 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
1577 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
1578 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, 1, 0, true, false);
1579 result
= ac_trim_vector(&ctx
->ac
, result
, num_components
);
1584 load_gs_input(struct ac_shader_abi
*abi
,
1586 unsigned driver_location
,
1588 unsigned num_components
,
1589 unsigned vertex_index
,
1590 unsigned const_index
,
1593 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1594 LLVMValueRef vtx_offset
;
1595 unsigned param
, vtx_offset_param
;
1596 LLVMValueRef value
[4], result
;
1598 vtx_offset_param
= vertex_index
;
1599 assert(vtx_offset_param
< 6);
1600 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
1601 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1603 param
= shader_io_get_unique_index(location
);
1605 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
1606 if (ctx
->ac
.chip_class
>= GFX9
) {
1607 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
1608 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1609 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
1610 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1612 LLVMValueRef soffset
=
1613 LLVMConstInt(ctx
->ac
.i32
,
1614 (param
* 4 + i
+ const_index
) * 256,
1617 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
1620 vtx_offset
, soffset
,
1621 0, 1, 0, true, false);
1624 if (ac_get_type_size(type
) == 2) {
1625 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i32
, "");
1626 value
[i
] = LLVMBuildTrunc(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i16
, "");
1628 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], type
, "");
1630 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1631 result
= ac_to_integer(&ctx
->ac
, result
);
1636 static void radv_emit_kill(struct ac_shader_abi
*abi
, LLVMValueRef visible
)
1638 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1639 ac_build_kill_if_false(&ctx
->ac
, visible
);
1642 static LLVMValueRef
lookup_interp_param(struct ac_shader_abi
*abi
,
1643 enum glsl_interp_mode interp
, unsigned location
)
1645 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1648 case INTERP_MODE_FLAT
:
1651 case INTERP_MODE_SMOOTH
:
1652 case INTERP_MODE_NONE
:
1653 if (location
== INTERP_CENTER
)
1654 return ctx
->persp_center
;
1655 else if (location
== INTERP_CENTROID
)
1656 return ctx
->persp_centroid
;
1657 else if (location
== INTERP_SAMPLE
)
1658 return ctx
->persp_sample
;
1660 case INTERP_MODE_NOPERSPECTIVE
:
1661 if (location
== INTERP_CENTER
)
1662 return ctx
->linear_center
;
1663 else if (location
== INTERP_CENTROID
)
1664 return ctx
->linear_centroid
;
1665 else if (location
== INTERP_SAMPLE
)
1666 return ctx
->linear_sample
;
1673 radv_get_sample_pos_offset(uint32_t num_samples
)
1675 uint32_t sample_pos_offset
= 0;
1677 switch (num_samples
) {
1679 sample_pos_offset
= 1;
1682 sample_pos_offset
= 3;
1685 sample_pos_offset
= 7;
1688 sample_pos_offset
= 15;
1693 return sample_pos_offset
;
1696 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
1697 LLVMValueRef sample_id
)
1699 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1701 LLVMValueRef result
;
1702 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false));
1704 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
1705 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
1707 uint32_t sample_pos_offset
=
1708 radv_get_sample_pos_offset(ctx
->options
->key
.fs
.num_samples
);
1711 LLVMBuildAdd(ctx
->ac
.builder
, sample_id
,
1712 LLVMConstInt(ctx
->ac
.i32
, sample_pos_offset
, false), "");
1713 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
1719 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
1721 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1722 uint8_t log2_ps_iter_samples
;
1724 if (ctx
->shader_info
->info
.ps
.force_persample
) {
1725 log2_ps_iter_samples
=
1726 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
1728 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
1731 /* The bit pattern matches that used by fixed function fragment
1733 static const uint16_t ps_iter_masks
[] = {
1734 0xffff, /* not used */
1740 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
1742 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
1744 LLVMValueRef result
, sample_id
;
1745 sample_id
= ac_unpack_param(&ctx
->ac
, abi
->ancillary
, 8, 4);
1746 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
1747 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
, abi
->sample_coverage
, "");
1753 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
1755 LLVMValueRef gs_next_vertex
;
1756 LLVMValueRef can_emit
;
1757 unsigned offset
= 0;
1758 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1760 /* Write vertex attribute values to GSVS ring */
1761 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
1762 ctx
->gs_next_vertex
[stream
],
1765 /* If this thread has already emitted the declared maximum number of
1766 * vertices, kill it: excessive vertex emissions are not supposed to
1767 * have any effect, and GS threads have no externally observable
1768 * effects other than emitting vertices.
1770 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
1771 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
1772 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
1774 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
1775 unsigned output_usage_mask
=
1776 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
1777 uint8_t output_stream
=
1778 ctx
->shader_info
->info
.gs
.output_streams
[i
];
1779 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
1780 int length
= util_last_bit(output_usage_mask
);
1782 if (!(ctx
->output_mask
& (1ull << i
)) ||
1783 output_stream
!= stream
)
1786 for (unsigned j
= 0; j
< length
; j
++) {
1787 if (!(output_usage_mask
& (1 << j
)))
1790 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
1792 LLVMValueRef voffset
=
1793 LLVMConstInt(ctx
->ac
.i32
, offset
*
1794 ctx
->gs_max_out_vertices
, false);
1798 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
1799 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1801 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
1802 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
1804 ac_build_buffer_store_dword(&ctx
->ac
,
1805 ctx
->gsvs_ring
[stream
],
1807 voffset
, ctx
->gs2vs_offset
, 0,
1812 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
1814 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
1816 ac_build_sendmsg(&ctx
->ac
,
1817 AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
1822 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
1824 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1825 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
1829 load_tess_coord(struct ac_shader_abi
*abi
)
1831 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1833 LLVMValueRef coord
[4] = {
1840 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
1841 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
1842 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
1844 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
1848 load_patch_vertices_in(struct ac_shader_abi
*abi
)
1850 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1851 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
1855 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
1857 return abi
->base_vertex
;
1860 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
1861 LLVMValueRef buffer_ptr
, bool write
)
1863 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1864 LLVMValueRef result
;
1866 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1868 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1869 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1874 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
1876 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1877 LLVMValueRef result
;
1879 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1881 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1882 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1887 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
1888 unsigned descriptor_set
,
1889 unsigned base_index
,
1890 unsigned constant_index
,
1892 enum ac_descriptor_type desc_type
,
1893 bool image
, bool write
,
1896 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1897 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
1898 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
1899 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
1900 unsigned offset
= binding
->offset
;
1901 unsigned stride
= binding
->size
;
1903 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1906 assert(base_index
< layout
->binding_count
);
1908 switch (desc_type
) {
1910 type
= ctx
->ac
.v8i32
;
1914 type
= ctx
->ac
.v8i32
;
1918 case AC_DESC_SAMPLER
:
1919 type
= ctx
->ac
.v4i32
;
1920 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1925 case AC_DESC_BUFFER
:
1926 type
= ctx
->ac
.v4i32
;
1930 unreachable("invalid desc_type\n");
1933 offset
+= constant_index
* stride
;
1935 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
1936 (!index
|| binding
->immutable_samplers_equal
)) {
1937 if (binding
->immutable_samplers_equal
)
1940 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
1942 LLVMValueRef constants
[] = {
1943 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
1944 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
1945 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
1946 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
1948 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
1951 assert(stride
% type_size
== 0);
1954 index
= ctx
->ac
.i32_0
;
1956 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
1958 list
= ac_build_gep0(&ctx
->ac
, list
, LLVMConstInt(ctx
->ac
.i32
, offset
, 0));
1959 list
= LLVMBuildPointerCast(builder
, list
,
1960 ac_array_in_const32_addr_space(type
), "");
1962 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
1965 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1966 * so we may need to fix it up. */
1968 adjust_vertex_fetch_alpha(struct radv_shader_context
*ctx
,
1969 unsigned adjustment
,
1972 if (adjustment
== RADV_ALPHA_ADJUST_NONE
)
1975 LLVMValueRef c30
= LLVMConstInt(ctx
->ac
.i32
, 30, 0);
1977 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
1978 alpha
= LLVMBuildFPToUI(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
1980 alpha
= ac_to_integer(&ctx
->ac
, alpha
);
1982 /* For the integer-like cases, do a natural sign extension.
1984 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1985 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1988 alpha
= LLVMBuildShl(ctx
->ac
.builder
, alpha
,
1989 adjustment
== RADV_ALPHA_ADJUST_SNORM
?
1990 LLVMConstInt(ctx
->ac
.i32
, 7, 0) : c30
, "");
1991 alpha
= LLVMBuildAShr(ctx
->ac
.builder
, alpha
, c30
, "");
1993 /* Convert back to the right type. */
1994 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
1996 LLVMValueRef neg_one
= LLVMConstReal(ctx
->ac
.f32
, -1.0);
1997 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1998 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, alpha
, neg_one
, "");
1999 alpha
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, alpha
, "");
2000 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
2001 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2008 handle_vs_input_decl(struct radv_shader_context
*ctx
,
2009 struct nir_variable
*variable
)
2011 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
2012 LLVMValueRef t_offset
;
2013 LLVMValueRef t_list
;
2015 LLVMValueRef buffer_index
;
2016 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
2017 uint8_t input_usage_mask
=
2018 ctx
->shader_info
->info
.vs
.input_usage_mask
[variable
->data
.location
];
2019 unsigned num_channels
= util_last_bit(input_usage_mask
);
2021 variable
->data
.driver_location
= variable
->data
.location
* 4;
2023 enum glsl_base_type type
= glsl_get_base_type(variable
->type
);
2024 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
2025 LLVMValueRef output
[4];
2026 unsigned attrib_index
= variable
->data
.location
+ i
- VERT_ATTRIB_GENERIC0
;
2028 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << attrib_index
)) {
2029 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[attrib_index
];
2032 buffer_index
= ctx
->abi
.instance_id
;
2035 buffer_index
= LLVMBuildUDiv(ctx
->ac
.builder
, buffer_index
,
2036 LLVMConstInt(ctx
->ac
.i32
, divisor
, 0), "");
2039 if (ctx
->options
->key
.vs
.as_ls
) {
2040 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
2041 MAX2(2, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
2043 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
2044 MAX2(1, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
2047 buffer_index
= ctx
->ac
.i32_0
;
2050 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.start_instance
, buffer_index
, "");
2052 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
2053 ctx
->abi
.base_vertex
, "");
2054 t_offset
= LLVMConstInt(ctx
->ac
.i32
, attrib_index
, false);
2056 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
2058 input
= ac_build_buffer_load_format(&ctx
->ac
, t_list
,
2061 num_channels
, false, true);
2063 input
= ac_build_expand_to_vec4(&ctx
->ac
, input
, num_channels
);
2065 for (unsigned chan
= 0; chan
< 4; chan
++) {
2066 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
2067 output
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
, input
, llvm_chan
, "");
2068 if (type
== GLSL_TYPE_FLOAT16
) {
2069 output
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f32
, "");
2070 output
[chan
] = LLVMBuildFPTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f16
, "");
2074 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (attrib_index
* 2)) & 3;
2075 output
[3] = adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, output
[3]);
2077 for (unsigned chan
= 0; chan
< 4; chan
++) {
2078 output
[chan
] = ac_to_integer(&ctx
->ac
, output
[chan
]);
2079 if (type
== GLSL_TYPE_UINT16
|| type
== GLSL_TYPE_INT16
)
2080 output
[chan
] = LLVMBuildTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.i16
, "");
2082 ctx
->inputs
[ac_llvm_reg_index_soa(variable
->data
.location
+ i
, chan
)] = output
[chan
];
2087 static void interp_fs_input(struct radv_shader_context
*ctx
,
2089 LLVMValueRef interp_param
,
2090 LLVMValueRef prim_mask
,
2091 LLVMValueRef result
[4])
2093 LLVMValueRef attr_number
;
2096 bool interp
= !LLVMIsUndef(interp_param
);
2098 attr_number
= LLVMConstInt(ctx
->ac
.i32
, attr
, false);
2100 /* fs.constant returns the param from the middle vertex, so it's not
2101 * really useful for flat shading. It's meant to be used for custom
2102 * interpolation (but the intrinsic can't fetch from the other two
2105 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
2106 * to do the right thing. The only reason we use fs.constant is that
2107 * fs.interp cannot be used on integers, because they can be equal
2111 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_param
,
2114 i
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
2116 j
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
2120 for (chan
= 0; chan
< 4; chan
++) {
2121 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
2124 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
2129 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
2130 LLVMConstInt(ctx
->ac
.i32
, 2, false),
2134 result
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, result
[chan
], ctx
->ac
.i32
, "");
2135 result
[chan
] = LLVMBuildTruncOrBitCast(ctx
->ac
.builder
, result
[chan
], LLVMTypeOf(interp_param
), "");
2141 handle_fs_input_decl(struct radv_shader_context
*ctx
,
2142 struct nir_variable
*variable
)
2144 int idx
= variable
->data
.location
;
2145 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
2146 LLVMValueRef interp
= NULL
;
2149 variable
->data
.driver_location
= idx
* 4;
2150 mask
= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
2152 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
) {
2153 unsigned interp_type
;
2154 if (variable
->data
.sample
)
2155 interp_type
= INTERP_SAMPLE
;
2156 else if (variable
->data
.centroid
)
2157 interp_type
= INTERP_CENTROID
;
2159 interp_type
= INTERP_CENTER
;
2161 interp
= lookup_interp_param(&ctx
->abi
, variable
->data
.interpolation
, interp_type
);
2163 bool is_16bit
= glsl_type_is_16bit(variable
->type
);
2164 LLVMTypeRef type
= is_16bit
? ctx
->ac
.i16
: ctx
->ac
.i32
;
2166 interp
= LLVMGetUndef(type
);
2168 for (unsigned i
= 0; i
< attrib_count
; ++i
)
2169 ctx
->inputs
[ac_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
2171 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
2172 /* Do not account for the number of components inside the array
2173 * of clip/cull distances because this might wrongly set other
2174 * bits like primitive ID or layer.
2176 mask
= 1ull << VARYING_SLOT_CLIP_DIST0
;
2179 ctx
->input_mask
|= mask
;
2183 handle_vs_inputs(struct radv_shader_context
*ctx
,
2184 struct nir_shader
*nir
) {
2185 nir_foreach_variable(variable
, &nir
->inputs
)
2186 handle_vs_input_decl(ctx
, variable
);
2190 prepare_interp_optimize(struct radv_shader_context
*ctx
,
2191 struct nir_shader
*nir
)
2193 bool uses_center
= false;
2194 bool uses_centroid
= false;
2195 nir_foreach_variable(variable
, &nir
->inputs
) {
2196 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
2197 variable
->data
.sample
)
2200 if (variable
->data
.centroid
)
2201 uses_centroid
= true;
2206 if (uses_center
&& uses_centroid
) {
2207 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
, ctx
->abi
.prim_mask
, ctx
->ac
.i32_0
, "");
2208 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
2209 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
2214 handle_fs_inputs(struct radv_shader_context
*ctx
,
2215 struct nir_shader
*nir
)
2217 prepare_interp_optimize(ctx
, nir
);
2219 nir_foreach_variable(variable
, &nir
->inputs
)
2220 handle_fs_input_decl(ctx
, variable
);
2224 if (ctx
->shader_info
->info
.ps
.uses_input_attachments
||
2225 ctx
->shader_info
->info
.needs_multiview_view_index
) {
2226 ctx
->input_mask
|= 1ull << VARYING_SLOT_LAYER
;
2227 ctx
->inputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)] = LLVMGetUndef(ctx
->ac
.i32
);
2230 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
2231 LLVMValueRef interp_param
;
2232 LLVMValueRef
*inputs
= ctx
->inputs
+ac_llvm_reg_index_soa(i
, 0);
2234 if (!(ctx
->input_mask
& (1ull << i
)))
2237 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
2238 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
2239 interp_param
= *inputs
;
2240 interp_fs_input(ctx
, index
, interp_param
, ctx
->abi
.prim_mask
,
2243 if (LLVMIsUndef(interp_param
))
2244 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
2246 } else if (i
== VARYING_SLOT_CLIP_DIST0
) {
2247 int length
= ctx
->shader_info
->info
.ps
.num_input_clips_culls
;
2249 for (unsigned j
= 0; j
< length
; j
+= 4) {
2250 inputs
= ctx
->inputs
+ ac_llvm_reg_index_soa(i
, j
);
2252 interp_param
= *inputs
;
2253 interp_fs_input(ctx
, index
, interp_param
,
2254 ctx
->abi
.prim_mask
, inputs
);
2257 } else if (i
== VARYING_SLOT_POS
) {
2258 for(int i
= 0; i
< 3; ++i
)
2259 inputs
[i
] = ctx
->abi
.frag_pos
[i
];
2261 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
2262 ctx
->abi
.frag_pos
[3]);
2265 ctx
->shader_info
->fs
.num_interp
= index
;
2266 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
2268 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
2269 ctx
->abi
.view_index
= ctx
->inputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2273 scan_shader_output_decl(struct radv_shader_context
*ctx
,
2274 struct nir_variable
*variable
,
2275 struct nir_shader
*shader
,
2276 gl_shader_stage stage
)
2278 int idx
= variable
->data
.location
+ variable
->data
.index
;
2279 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
2280 uint64_t mask_attribs
;
2282 variable
->data
.driver_location
= idx
* 4;
2284 /* tess ctrl has it's own load/store paths for outputs */
2285 if (stage
== MESA_SHADER_TESS_CTRL
)
2288 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
2289 if (stage
== MESA_SHADER_VERTEX
||
2290 stage
== MESA_SHADER_TESS_EVAL
||
2291 stage
== MESA_SHADER_GEOMETRY
) {
2292 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
2293 if (stage
== MESA_SHADER_VERTEX
) {
2294 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2295 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2296 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
<<= shader
->info
.clip_distance_array_size
;
2298 if (stage
== MESA_SHADER_TESS_EVAL
) {
2299 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2300 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2301 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
<<= shader
->info
.clip_distance_array_size
;
2304 mask_attribs
= 1ull << idx
;
2308 ctx
->output_mask
|= mask_attribs
;
2312 /* Initialize arguments for the shader export intrinsic */
2314 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
2315 LLVMValueRef
*values
,
2316 unsigned enabled_channels
,
2318 struct ac_export_args
*args
)
2320 /* Specify the channels that are enabled. */
2321 args
->enabled_channels
= enabled_channels
;
2323 /* Specify whether the EXEC mask represents the valid mask */
2324 args
->valid_mask
= 0;
2326 /* Specify whether this is the last export */
2329 /* Specify the target we are exporting */
2330 args
->target
= target
;
2332 args
->compr
= false;
2333 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
2334 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
2335 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
2336 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
2341 bool is_16bit
= ac_get_type_size(LLVMTypeOf(values
[0])) == 2;
2342 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2343 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
2344 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
2345 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
2346 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
2349 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
2350 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
2351 unsigned bits
, bool hi
) = NULL
;
2353 switch(col_format
) {
2354 case V_028714_SPI_SHADER_ZERO
:
2355 args
->enabled_channels
= 0; /* writemask */
2356 args
->target
= V_008DFC_SQ_EXP_NULL
;
2359 case V_028714_SPI_SHADER_32_R
:
2360 args
->enabled_channels
= 1;
2361 args
->out
[0] = values
[0];
2364 case V_028714_SPI_SHADER_32_GR
:
2365 args
->enabled_channels
= 0x3;
2366 args
->out
[0] = values
[0];
2367 args
->out
[1] = values
[1];
2370 case V_028714_SPI_SHADER_32_AR
:
2371 args
->enabled_channels
= 0x9;
2372 args
->out
[0] = values
[0];
2373 args
->out
[3] = values
[3];
2376 case V_028714_SPI_SHADER_FP16_ABGR
:
2377 args
->enabled_channels
= 0x5;
2378 packf
= ac_build_cvt_pkrtz_f16
;
2380 for (unsigned chan
= 0; chan
< 4; chan
++)
2381 values
[chan
] = LLVMBuildFPExt(ctx
->ac
.builder
,
2387 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2388 args
->enabled_channels
= 0x5;
2389 packf
= ac_build_cvt_pknorm_u16
;
2392 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2393 args
->enabled_channels
= 0x5;
2394 packf
= ac_build_cvt_pknorm_i16
;
2397 case V_028714_SPI_SHADER_UINT16_ABGR
:
2398 args
->enabled_channels
= 0x5;
2399 packi
= ac_build_cvt_pk_u16
;
2401 for (unsigned chan
= 0; chan
< 4; chan
++)
2402 values
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
,
2408 case V_028714_SPI_SHADER_SINT16_ABGR
:
2409 args
->enabled_channels
= 0x5;
2410 packi
= ac_build_cvt_pk_i16
;
2412 for (unsigned chan
= 0; chan
< 4; chan
++)
2413 values
[chan
] = LLVMBuildSExt(ctx
->ac
.builder
,
2420 case V_028714_SPI_SHADER_32_ABGR
:
2421 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2425 /* Pack f16 or norm_i16/u16. */
2427 for (chan
= 0; chan
< 2; chan
++) {
2428 LLVMValueRef pack_args
[2] = {
2430 values
[2 * chan
+ 1]
2432 LLVMValueRef packed
;
2434 packed
= packf(&ctx
->ac
, pack_args
);
2435 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2437 args
->compr
= 1; /* COMPR flag */
2442 for (chan
= 0; chan
< 2; chan
++) {
2443 LLVMValueRef pack_args
[2] = {
2444 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
2445 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
2447 LLVMValueRef packed
;
2449 packed
= packi(&ctx
->ac
, pack_args
,
2450 is_int8
? 8 : is_int10
? 10 : 16,
2452 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2454 args
->compr
= 1; /* COMPR flag */
2460 for (unsigned chan
= 0; chan
< 4; chan
++) {
2461 values
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i16
, "");
2462 args
->out
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i32
, "");
2465 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2467 for (unsigned i
= 0; i
< 4; ++i
) {
2468 if (!(args
->enabled_channels
& (1 << i
)))
2471 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
2476 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
2477 LLVMValueRef
*values
, unsigned enabled_channels
)
2479 struct ac_export_args args
;
2481 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
2482 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
2483 ac_build_export(&ctx
->ac
, &args
);
2487 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
2489 LLVMValueRef output
=
2490 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(index
, chan
)];
2492 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
2496 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
2497 bool export_prim_id
, bool export_layer_id
,
2498 struct radv_vs_output_info
*outinfo
)
2500 uint32_t param_count
= 0;
2502 unsigned pos_idx
, num_pos_exports
= 0;
2503 struct ac_export_args args
, pos_args
[4] = {};
2504 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
2507 if (ctx
->options
->key
.has_multiview_view_index
) {
2508 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2510 for(unsigned i
= 0; i
< 4; ++i
)
2511 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
2512 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
2515 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
), *tmp_out
);
2516 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
2519 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
2520 sizeof(outinfo
->vs_output_param_offset
));
2522 if (ctx
->output_mask
& (1ull << VARYING_SLOT_CLIP_DIST0
)) {
2523 unsigned output_usage_mask
, length
;
2524 LLVMValueRef slots
[8];
2527 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2528 !ctx
->is_gs_copy_shader
) {
2530 ctx
->shader_info
->info
.vs
.output_usage_mask
[VARYING_SLOT_CLIP_DIST0
];
2531 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2533 ctx
->shader_info
->info
.tes
.output_usage_mask
[VARYING_SLOT_CLIP_DIST0
];
2535 assert(ctx
->is_gs_copy_shader
);
2537 ctx
->shader_info
->info
.gs
.output_usage_mask
[VARYING_SLOT_CLIP_DIST0
];
2540 length
= util_last_bit(output_usage_mask
);
2542 i
= VARYING_SLOT_CLIP_DIST0
;
2543 for (j
= 0; j
< length
; j
++)
2544 slots
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2546 for (i
= length
; i
< 8; i
++)
2547 slots
[i
] = LLVMGetUndef(ctx
->ac
.f32
);
2550 target
= V_008DFC_SQ_EXP_POS
+ 3;
2551 si_llvm_init_export_args(ctx
, &slots
[4], 0xf, target
, &args
);
2552 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
2553 &args
, sizeof(args
));
2556 target
= V_008DFC_SQ_EXP_POS
+ 2;
2557 si_llvm_init_export_args(ctx
, &slots
[0], 0xf, target
, &args
);
2558 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
2559 &args
, sizeof(args
));
2561 /* Export the clip/cull distances values to the next stage. */
2562 radv_export_param(ctx
, param_count
, &slots
[0], 0xf);
2563 outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
] = param_count
++;
2565 radv_export_param(ctx
, param_count
, &slots
[4], 0xf);
2566 outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
] = param_count
++;
2570 LLVMValueRef pos_values
[4] = {ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_1
};
2571 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
2572 for (unsigned j
= 0; j
< 4; j
++)
2573 pos_values
[j
] = radv_load_output(ctx
, VARYING_SLOT_POS
, j
);
2575 si_llvm_init_export_args(ctx
, pos_values
, 0xf, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
2577 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
2578 outinfo
->writes_pointsize
= true;
2579 psize_value
= radv_load_output(ctx
, VARYING_SLOT_PSIZ
, 0);
2582 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
2583 outinfo
->writes_layer
= true;
2584 layer_value
= radv_load_output(ctx
, VARYING_SLOT_LAYER
, 0);
2587 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
2588 outinfo
->writes_viewport_index
= true;
2589 viewport_index_value
= radv_load_output(ctx
, VARYING_SLOT_VIEWPORT
, 0);
2592 if (outinfo
->writes_pointsize
||
2593 outinfo
->writes_layer
||
2594 outinfo
->writes_viewport_index
) {
2595 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
2596 (outinfo
->writes_layer
== true ? 4 : 0));
2597 pos_args
[1].valid_mask
= 0;
2598 pos_args
[1].done
= 0;
2599 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
2600 pos_args
[1].compr
= 0;
2601 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
2602 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
2603 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
2604 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
2606 if (outinfo
->writes_pointsize
== true)
2607 pos_args
[1].out
[0] = psize_value
;
2608 if (outinfo
->writes_layer
== true)
2609 pos_args
[1].out
[2] = layer_value
;
2610 if (outinfo
->writes_viewport_index
== true) {
2611 if (ctx
->options
->chip_class
>= GFX9
) {
2612 /* GFX9 has the layer in out.z[10:0] and the viewport
2613 * index in out.z[19:16].
2615 LLVMValueRef v
= viewport_index_value
;
2616 v
= ac_to_integer(&ctx
->ac
, v
);
2617 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
2618 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2620 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
2621 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
2623 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
2624 pos_args
[1].enabled_channels
|= 1 << 2;
2626 pos_args
[1].out
[3] = viewport_index_value
;
2627 pos_args
[1].enabled_channels
|= 1 << 3;
2631 for (i
= 0; i
< 4; i
++) {
2632 if (pos_args
[i
].out
[0])
2637 for (i
= 0; i
< 4; i
++) {
2638 if (!pos_args
[i
].out
[0])
2641 /* Specify the target we are exporting */
2642 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
2643 if (pos_idx
== num_pos_exports
)
2644 pos_args
[i
].done
= 1;
2645 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
2648 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2649 LLVMValueRef values
[4];
2650 if (!(ctx
->output_mask
& (1ull << i
)))
2653 if (i
!= VARYING_SLOT_LAYER
&&
2654 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
2655 i
< VARYING_SLOT_VAR0
)
2658 for (unsigned j
= 0; j
< 4; j
++)
2659 values
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2661 unsigned output_usage_mask
;
2663 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2664 !ctx
->is_gs_copy_shader
) {
2666 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
2667 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2669 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
2671 assert(ctx
->is_gs_copy_shader
);
2673 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
2676 radv_export_param(ctx
, param_count
, values
, output_usage_mask
);
2678 outinfo
->vs_output_param_offset
[i
] = param_count
++;
2681 if (export_prim_id
) {
2682 LLVMValueRef values
[4];
2684 values
[0] = ctx
->vs_prim_id
;
2685 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(2,
2686 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
2687 for (unsigned j
= 1; j
< 4; j
++)
2688 values
[j
] = ctx
->ac
.f32_0
;
2690 radv_export_param(ctx
, param_count
, values
, 0x1);
2692 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
2693 outinfo
->export_prim_id
= true;
2696 if (export_layer_id
&& layer_value
) {
2697 LLVMValueRef values
[4];
2699 values
[0] = layer_value
;
2700 for (unsigned j
= 1; j
< 4; j
++)
2701 values
[j
] = ctx
->ac
.f32_0
;
2703 radv_export_param(ctx
, param_count
, values
, 0x1);
2705 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = param_count
++;
2708 outinfo
->pos_exports
= num_pos_exports
;
2709 outinfo
->param_exports
= param_count
;
2713 handle_es_outputs_post(struct radv_shader_context
*ctx
,
2714 struct radv_es_output_info
*outinfo
)
2717 uint64_t max_output_written
= 0;
2718 LLVMValueRef lds_base
= NULL
;
2720 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2721 unsigned output_usage_mask
;
2725 if (!(ctx
->output_mask
& (1ull << i
)))
2728 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2730 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
2732 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2734 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
2737 if (i
== VARYING_SLOT_CLIP_DIST0
)
2738 length
= util_last_bit(output_usage_mask
);
2740 param_index
= shader_io_get_unique_index(i
);
2742 max_output_written
= MAX2(param_index
+ (length
> 4), max_output_written
);
2745 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
2747 if (ctx
->ac
.chip_class
>= GFX9
) {
2748 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
2749 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
2750 LLVMValueRef wave_idx
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 24, 4);
2751 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
2752 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
2753 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
2754 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
2755 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
2758 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2759 LLVMValueRef dw_addr
= NULL
;
2760 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2761 unsigned output_usage_mask
;
2765 if (!(ctx
->output_mask
& (1ull << i
)))
2768 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2770 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
2772 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2774 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
2777 if (i
== VARYING_SLOT_CLIP_DIST0
)
2778 length
= util_last_bit(output_usage_mask
);
2780 param_index
= shader_io_get_unique_index(i
);
2783 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2784 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
2788 for (j
= 0; j
< length
; j
++) {
2789 if (!(output_usage_mask
& (1 << j
)))
2792 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2793 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
2794 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
2796 if (ctx
->ac
.chip_class
>= GFX9
) {
2797 LLVMValueRef dw_addr_offset
=
2798 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2799 LLVMConstInt(ctx
->ac
.i32
,
2802 ac_lds_store(&ctx
->ac
, dw_addr_offset
, out_val
);
2804 ac_build_buffer_store_dword(&ctx
->ac
,
2807 NULL
, ctx
->es2gs_offset
,
2808 (4 * param_index
+ j
) * 4,
2816 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
2818 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
2819 uint32_t num_tcs_inputs
= util_last_bit64(ctx
->shader_info
->info
.vs
.ls_outputs_written
);
2820 LLVMValueRef vertex_dw_stride
= LLVMConstInt(ctx
->ac
.i32
, num_tcs_inputs
* 4, false);
2821 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
2822 vertex_dw_stride
, "");
2824 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2825 unsigned output_usage_mask
=
2826 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
2827 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2830 if (!(ctx
->output_mask
& (1ull << i
)))
2833 if (i
== VARYING_SLOT_CLIP_DIST0
)
2834 length
= util_last_bit(output_usage_mask
);
2836 int param
= shader_io_get_unique_index(i
);
2837 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
2838 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
2840 for (unsigned j
= 0; j
< length
; j
++) {
2841 LLVMValueRef value
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2842 value
= ac_to_integer(&ctx
->ac
, value
);
2843 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
2844 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
2845 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
2851 write_tess_factors(struct radv_shader_context
*ctx
)
2853 unsigned stride
, outer_comps
, inner_comps
;
2854 struct ac_build_if_state if_ctx
, inner_if_ctx
;
2855 LLVMValueRef invocation_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
2856 LLVMValueRef rel_patch_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
2857 unsigned tess_inner_index
= 0, tess_outer_index
;
2858 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
2859 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
2861 ac_emit_barrier(&ctx
->ac
, ctx
->stage
);
2863 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
2883 ac_nir_build_if(&if_ctx
, ctx
,
2884 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
2885 invocation_id
, ctx
->ac
.i32_0
, ""));
2887 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
2890 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
2891 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2892 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
2895 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
2896 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2897 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
2899 for (i
= 0; i
< 4; i
++) {
2900 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
2901 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
2905 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
2906 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
2907 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
2909 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
2911 for (i
= 0; i
< outer_comps
; i
++) {
2913 ac_lds_load(&ctx
->ac
, lds_outer
);
2914 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
2917 for (i
= 0; i
< inner_comps
; i
++) {
2918 inner
[i
] = out
[outer_comps
+i
] =
2919 ac_lds_load(&ctx
->ac
, lds_inner
);
2920 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
2925 /* Convert the outputs to vectors for stores. */
2926 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
2930 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
2933 buffer
= ctx
->hs_ring_tess_factor
;
2934 tf_base
= ctx
->tess_factor_offset
;
2935 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
2936 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
2937 unsigned tf_offset
= 0;
2939 if (ctx
->options
->chip_class
<= VI
) {
2940 ac_nir_build_if(&inner_if_ctx
, ctx
,
2941 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
2942 rel_patch_id
, ctx
->ac
.i32_0
, ""));
2944 /* Store the dynamic HS control word. */
2945 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
2946 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
2947 1, ctx
->ac
.i32_0
, tf_base
,
2948 0, 1, 0, true, false);
2951 ac_nir_build_endif(&inner_if_ctx
);
2954 /* Store the tessellation factors. */
2955 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
2956 MIN2(stride
, 4), byteoffset
, tf_base
,
2957 tf_offset
, 1, 0, true, false);
2959 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
2960 stride
- 4, byteoffset
, tf_base
,
2961 16 + tf_offset
, 1, 0, true, false);
2963 //store to offchip for TES to read - only if TES reads them
2964 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
2965 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
2966 LLVMValueRef tf_inner_offset
;
2967 unsigned param_outer
, param_inner
;
2969 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
2970 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
2971 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
2973 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
2974 util_next_power_of_two(outer_comps
));
2976 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
2977 outer_comps
, tf_outer_offset
,
2978 ctx
->oc_lds
, 0, 1, 0, true, false);
2980 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
2981 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
2982 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
2984 inner_vec
= inner_comps
== 1 ? inner
[0] :
2985 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
2986 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
2987 inner_comps
, tf_inner_offset
,
2988 ctx
->oc_lds
, 0, 1, 0, true, false);
2991 ac_nir_build_endif(&if_ctx
);
2995 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
2997 write_tess_factors(ctx
);
3001 si_export_mrt_color(struct radv_shader_context
*ctx
,
3002 LLVMValueRef
*color
, unsigned index
,
3003 struct ac_export_args
*args
)
3006 si_llvm_init_export_args(ctx
, color
, 0xf,
3007 V_008DFC_SQ_EXP_MRT
+ index
, args
);
3008 if (!args
->enabled_channels
)
3009 return false; /* unnecessary NULL export */
3015 radv_export_mrt_z(struct radv_shader_context
*ctx
,
3016 LLVMValueRef depth
, LLVMValueRef stencil
,
3017 LLVMValueRef samplemask
)
3019 struct ac_export_args args
;
3021 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
3023 ac_build_export(&ctx
->ac
, &args
);
3027 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
3030 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3031 struct ac_export_args color_args
[8];
3033 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3034 LLVMValueRef values
[4];
3036 if (!(ctx
->output_mask
& (1ull << i
)))
3039 if (i
< FRAG_RESULT_DATA0
)
3042 for (unsigned j
= 0; j
< 4; j
++)
3043 values
[j
] = ac_to_float(&ctx
->ac
,
3044 radv_load_output(ctx
, i
, j
));
3046 bool ret
= si_export_mrt_color(ctx
, values
,
3047 i
- FRAG_RESULT_DATA0
,
3048 &color_args
[index
]);
3053 /* Process depth, stencil, samplemask. */
3054 if (ctx
->shader_info
->info
.ps
.writes_z
) {
3055 depth
= ac_to_float(&ctx
->ac
,
3056 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
3058 if (ctx
->shader_info
->info
.ps
.writes_stencil
) {
3059 stencil
= ac_to_float(&ctx
->ac
,
3060 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
3062 if (ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
3063 samplemask
= ac_to_float(&ctx
->ac
,
3064 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
3067 /* Set the DONE bit on last non-null color export only if Z isn't
3071 !ctx
->shader_info
->info
.ps
.writes_z
&&
3072 !ctx
->shader_info
->info
.ps
.writes_stencil
&&
3073 !ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
3074 unsigned last
= index
- 1;
3076 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
3077 color_args
[last
].done
= 1; /* DONE bit */
3080 /* Export PS outputs. */
3081 for (unsigned i
= 0; i
< index
; i
++)
3082 ac_build_export(&ctx
->ac
, &color_args
[i
]);
3084 if (depth
|| stencil
|| samplemask
)
3085 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
3087 ac_build_export_null(&ctx
->ac
);
3091 emit_gs_epilogue(struct radv_shader_context
*ctx
)
3093 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
3097 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
3098 LLVMValueRef
*addrs
)
3100 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
3102 switch (ctx
->stage
) {
3103 case MESA_SHADER_VERTEX
:
3104 if (ctx
->options
->key
.vs
.as_ls
)
3105 handle_ls_outputs_post(ctx
);
3106 else if (ctx
->options
->key
.vs
.as_es
)
3107 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
3109 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.export_prim_id
,
3110 ctx
->options
->key
.vs
.export_layer_id
,
3111 &ctx
->shader_info
->vs
.outinfo
);
3113 case MESA_SHADER_FRAGMENT
:
3114 handle_fs_outputs_post(ctx
);
3116 case MESA_SHADER_GEOMETRY
:
3117 emit_gs_epilogue(ctx
);
3119 case MESA_SHADER_TESS_CTRL
:
3120 handle_tcs_outputs_post(ctx
);
3122 case MESA_SHADER_TESS_EVAL
:
3123 if (ctx
->options
->key
.tes
.as_es
)
3124 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
3126 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.export_prim_id
,
3127 ctx
->options
->key
.tes
.export_layer_id
,
3128 &ctx
->shader_info
->tes
.outinfo
);
3135 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
,
3136 LLVMPassManagerRef passmgr
,
3137 const struct radv_nir_compiler_options
*options
)
3139 LLVMRunPassManager(passmgr
, ctx
->ac
.module
);
3140 LLVMDisposeBuilder(ctx
->ac
.builder
);
3142 ac_llvm_context_dispose(&ctx
->ac
);
3146 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
3148 struct radv_vs_output_info
*outinfo
;
3150 switch (ctx
->stage
) {
3151 case MESA_SHADER_FRAGMENT
:
3152 case MESA_SHADER_COMPUTE
:
3153 case MESA_SHADER_TESS_CTRL
:
3154 case MESA_SHADER_GEOMETRY
:
3156 case MESA_SHADER_VERTEX
:
3157 if (ctx
->options
->key
.vs
.as_ls
||
3158 ctx
->options
->key
.vs
.as_es
)
3160 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
3162 case MESA_SHADER_TESS_EVAL
:
3163 if (ctx
->options
->key
.vs
.as_es
)
3165 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
3168 unreachable("Unhandled shader type");
3171 ac_optimize_vs_outputs(&ctx
->ac
,
3173 outinfo
->vs_output_param_offset
,
3175 &outinfo
->param_exports
);
3179 ac_setup_rings(struct radv_shader_context
*ctx
)
3181 if (ctx
->options
->chip_class
<= VI
&&
3182 (ctx
->stage
== MESA_SHADER_GEOMETRY
||
3183 ctx
->options
->key
.vs
.as_es
|| ctx
->options
->key
.tes
.as_es
)) {
3184 unsigned ring
= ctx
->stage
== MESA_SHADER_GEOMETRY
? RING_ESGS_GS
3186 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, ring
, false);
3188 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
,
3193 if (ctx
->is_gs_copy_shader
) {
3195 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3196 LLVMConstInt(ctx
->ac
.i32
,
3197 RING_GSVS_VS
, false));
3200 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3201 /* The conceptual layout of the GSVS ring is
3202 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3203 * but the real memory layout is swizzled across
3205 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3207 * Override the buffer descriptor accordingly.
3209 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->ac
.i64
, 2);
3210 uint64_t stream_offset
= 0;
3211 unsigned num_records
= 64;
3212 LLVMValueRef base_ring
;
3215 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3216 LLVMConstInt(ctx
->ac
.i32
,
3217 RING_GSVS_GS
, false));
3219 for (unsigned stream
= 0; stream
< 4; stream
++) {
3220 unsigned num_components
, stride
;
3221 LLVMValueRef ring
, tmp
;
3224 ctx
->shader_info
->info
.gs
.num_stream_output_components
[stream
];
3226 if (!num_components
)
3229 stride
= 4 * num_components
* ctx
->gs_max_out_vertices
;
3231 /* Limit on the stride field for <= CIK. */
3232 assert(stride
< (1 << 14));
3234 ring
= LLVMBuildBitCast(ctx
->ac
.builder
,
3235 base_ring
, v2i64
, "");
3236 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
3237 ring
, ctx
->ac
.i32_0
, "");
3238 tmp
= LLVMBuildAdd(ctx
->ac
.builder
, tmp
,
3239 LLVMConstInt(ctx
->ac
.i64
,
3240 stream_offset
, 0), "");
3241 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
,
3242 ring
, tmp
, ctx
->ac
.i32_0
, "");
3244 stream_offset
+= stride
* 64;
3246 ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ring
,
3249 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ring
,
3251 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
,
3252 LLVMConstInt(ctx
->ac
.i32
,
3253 S_008F04_STRIDE(stride
), false), "");
3254 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
, tmp
,
3257 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
,
3258 LLVMConstInt(ctx
->ac
.i32
,
3259 num_records
, false),
3260 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
3262 ctx
->gsvs_ring
[stream
] = ring
;
3266 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3267 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3268 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
3269 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
3274 ac_nir_get_max_workgroup_size(enum chip_class chip_class
,
3275 const struct nir_shader
*nir
)
3277 switch (nir
->info
.stage
) {
3278 case MESA_SHADER_TESS_CTRL
:
3279 return chip_class
>= CIK
? 128 : 64;
3280 case MESA_SHADER_GEOMETRY
:
3281 return chip_class
>= GFX9
? 128 : 64;
3282 case MESA_SHADER_COMPUTE
:
3288 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
3289 nir
->info
.cs
.local_size
[1] *
3290 nir
->info
.cs
.local_size
[2];
3291 return max_workgroup_size
;
3294 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3295 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
3297 LLVMValueRef count
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 8, 8);
3298 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
3300 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
3301 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
3302 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
3305 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
)
3307 for(int i
= 5; i
>= 0; --i
) {
3308 ctx
->gs_vtx_offset
[i
] = ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
3312 ctx
->gs_wave_id
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 16, 8);
3317 LLVMModuleRef
ac_translate_nir_to_llvm(struct ac_llvm_compiler
*ac_llvm
,
3318 struct nir_shader
*const *shaders
,
3320 struct radv_shader_variant_info
*shader_info
,
3321 const struct radv_nir_compiler_options
*options
)
3323 struct radv_shader_context ctx
= {0};
3325 ctx
.options
= options
;
3326 ctx
.shader_info
= shader_info
;
3328 ac_llvm_context_init(&ctx
.ac
, options
->chip_class
, options
->family
);
3329 ctx
.context
= ctx
.ac
.context
;
3330 ctx
.ac
.module
= ac_create_module(ac_llvm
->tm
, ctx
.context
);
3332 enum ac_float_mode float_mode
=
3333 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
3334 AC_FLOAT_MODE_DEFAULT
;
3336 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
3338 memset(shader_info
, 0, sizeof(*shader_info
));
3340 for(int i
= 0; i
< shader_count
; ++i
)
3341 radv_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
3343 for (i
= 0; i
< RADV_UD_MAX_SETS
; i
++)
3344 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
3345 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
3346 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
3348 ctx
.max_workgroup_size
= 0;
3349 for (int i
= 0; i
< shader_count
; ++i
) {
3350 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
3351 ac_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
3355 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
3356 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
3358 ctx
.abi
.inputs
= &ctx
.inputs
[0];
3359 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
3360 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
3361 ctx
.abi
.load_ubo
= radv_load_ubo
;
3362 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
3363 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
3364 ctx
.abi
.load_resource
= radv_load_resource
;
3365 ctx
.abi
.clamp_shadow_reference
= false;
3366 ctx
.abi
.gfx9_stride_size_workaround
= ctx
.ac
.chip_class
== GFX9
;
3368 if (shader_count
>= 2)
3369 ac_init_exec_full_mask(&ctx
.ac
);
3371 if (ctx
.ac
.chip_class
== GFX9
&&
3372 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
3373 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
3375 for(int i
= 0; i
< shader_count
; ++i
) {
3376 ctx
.stage
= shaders
[i
]->info
.stage
;
3377 ctx
.output_mask
= 0;
3379 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3380 for (int i
= 0; i
< 4; i
++) {
3381 ctx
.gs_next_vertex
[i
] =
3382 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
3384 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
3385 ctx
.abi
.load_inputs
= load_gs_input
;
3386 ctx
.abi
.emit_primitive
= visit_end_primitive
;
3387 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3388 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
3389 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
3390 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
3391 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
3392 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
3393 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
3394 if (shader_count
== 1)
3395 ctx
.tcs_num_inputs
= ctx
.options
->key
.tcs
.num_inputs
;
3397 ctx
.tcs_num_inputs
= util_last_bit64(shader_info
->info
.vs
.ls_outputs_written
);
3398 ctx
.tcs_num_patches
= get_tcs_num_patches(&ctx
);
3399 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
3400 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
3401 ctx
.abi
.load_tess_varyings
= load_tes_input
;
3402 ctx
.abi
.load_tess_coord
= load_tess_coord
;
3403 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
3404 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
3405 ctx
.tcs_num_patches
= ctx
.options
->key
.tes
.num_patches
;
3406 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
3407 if (shader_info
->info
.vs
.needs_instance_id
) {
3408 if (ctx
.options
->key
.vs
.as_ls
) {
3409 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
3410 MAX2(2, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
3412 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
3413 MAX2(1, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
3416 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
3417 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
3418 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
3419 ctx
.abi
.lookup_interp_param
= lookup_interp_param
;
3420 ctx
.abi
.load_sample_position
= load_sample_position
;
3421 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
3422 ctx
.abi
.emit_kill
= radv_emit_kill
;
3426 ac_emit_barrier(&ctx
.ac
, ctx
.stage
);
3428 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
3429 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
3431 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3432 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
3433 shaders
[i
]->info
.cull_distance_array_size
> 4;
3434 ctx
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
3435 ctx
.max_gsvs_emit_size
= ctx
.gsvs_vertex_size
*
3436 shaders
[i
]->info
.gs
.vertices_out
;
3439 ac_setup_rings(&ctx
);
3441 LLVMBasicBlockRef merge_block
;
3442 if (shader_count
>= 2) {
3443 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
3444 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
3445 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
3447 LLVMValueRef count
= ac_unpack_param(&ctx
.ac
, ctx
.merged_wave_info
, 8 * i
, 8);
3448 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
3449 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
3450 thread_id
, count
, "");
3451 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
3453 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
3456 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
3457 handle_fs_inputs(&ctx
, shaders
[i
]);
3458 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
3459 handle_vs_inputs(&ctx
, shaders
[i
]);
3460 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
3461 prepare_gs_input_vgprs(&ctx
);
3463 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
]);
3465 if (shader_count
>= 2) {
3466 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
3467 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
3470 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3471 shader_info
->gs
.gsvs_vertex_size
= ctx
.gsvs_vertex_size
;
3472 shader_info
->gs
.max_gsvs_emit_size
= ctx
.max_gsvs_emit_size
;
3473 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3474 shader_info
->tcs
.num_patches
= ctx
.tcs_num_patches
;
3475 shader_info
->tcs
.lds_size
= calculate_tess_lds_size(&ctx
);
3479 LLVMBuildRetVoid(ctx
.ac
.builder
);
3481 if (options
->dump_preoptir
)
3482 ac_dump_module(ctx
.ac
.module
);
3484 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
3486 if (shader_count
== 1)
3487 ac_nir_eliminate_const_vs_outputs(&ctx
);
3489 if (options
->dump_shader
) {
3490 ctx
.shader_info
->private_mem_vgprs
=
3491 ac_count_scratch_private_memory(ctx
.main_function
);
3494 return ctx
.ac
.module
;
3497 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
3499 unsigned *retval
= (unsigned *)context
;
3500 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
3501 char *description
= LLVMGetDiagInfoDescription(di
);
3503 if (severity
== LLVMDSError
) {
3505 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
3509 LLVMDisposeMessage(description
);
3512 static unsigned ac_llvm_compile(LLVMModuleRef M
,
3513 struct ac_shader_binary
*binary
,
3514 struct ac_llvm_compiler
*ac_llvm
)
3516 unsigned retval
= 0;
3517 LLVMContextRef llvm_ctx
;
3519 /* Setup Diagnostic Handler*/
3520 llvm_ctx
= LLVMGetModuleContext(M
);
3522 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
3526 if (!radv_compile_to_binary(ac_llvm
, M
, binary
))
3531 static void ac_compile_llvm_module(struct ac_llvm_compiler
*ac_llvm
,
3532 LLVMModuleRef llvm_module
,
3533 struct ac_shader_binary
*binary
,
3534 struct ac_shader_config
*config
,
3535 struct radv_shader_variant_info
*shader_info
,
3536 gl_shader_stage stage
,
3537 const struct radv_nir_compiler_options
*options
)
3539 if (options
->dump_shader
)
3540 ac_dump_module(llvm_module
);
3542 memset(binary
, 0, sizeof(*binary
));
3544 if (options
->record_llvm_ir
) {
3545 char *llvm_ir
= LLVMPrintModuleToString(llvm_module
);
3546 binary
->llvm_ir_string
= strdup(llvm_ir
);
3547 LLVMDisposeMessage(llvm_ir
);
3550 int v
= ac_llvm_compile(llvm_module
, binary
, ac_llvm
);
3552 fprintf(stderr
, "compile failed\n");
3555 if (options
->dump_shader
)
3556 fprintf(stderr
, "disasm:\n%s\n", binary
->disasm_string
);
3558 ac_shader_binary_read_config(binary
, config
, 0, options
->supports_spill
);
3560 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
3561 LLVMDisposeModule(llvm_module
);
3562 LLVMContextDispose(ctx
);
3564 if (stage
== MESA_SHADER_FRAGMENT
) {
3565 shader_info
->num_input_vgprs
= 0;
3566 if (G_0286CC_PERSP_SAMPLE_ENA(config
->spi_ps_input_addr
))
3567 shader_info
->num_input_vgprs
+= 2;
3568 if (G_0286CC_PERSP_CENTER_ENA(config
->spi_ps_input_addr
))
3569 shader_info
->num_input_vgprs
+= 2;
3570 if (G_0286CC_PERSP_CENTROID_ENA(config
->spi_ps_input_addr
))
3571 shader_info
->num_input_vgprs
+= 2;
3572 if (G_0286CC_PERSP_PULL_MODEL_ENA(config
->spi_ps_input_addr
))
3573 shader_info
->num_input_vgprs
+= 3;
3574 if (G_0286CC_LINEAR_SAMPLE_ENA(config
->spi_ps_input_addr
))
3575 shader_info
->num_input_vgprs
+= 2;
3576 if (G_0286CC_LINEAR_CENTER_ENA(config
->spi_ps_input_addr
))
3577 shader_info
->num_input_vgprs
+= 2;
3578 if (G_0286CC_LINEAR_CENTROID_ENA(config
->spi_ps_input_addr
))
3579 shader_info
->num_input_vgprs
+= 2;
3580 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config
->spi_ps_input_addr
))
3581 shader_info
->num_input_vgprs
+= 1;
3582 if (G_0286CC_POS_X_FLOAT_ENA(config
->spi_ps_input_addr
))
3583 shader_info
->num_input_vgprs
+= 1;
3584 if (G_0286CC_POS_Y_FLOAT_ENA(config
->spi_ps_input_addr
))
3585 shader_info
->num_input_vgprs
+= 1;
3586 if (G_0286CC_POS_Z_FLOAT_ENA(config
->spi_ps_input_addr
))
3587 shader_info
->num_input_vgprs
+= 1;
3588 if (G_0286CC_POS_W_FLOAT_ENA(config
->spi_ps_input_addr
))
3589 shader_info
->num_input_vgprs
+= 1;
3590 if (G_0286CC_FRONT_FACE_ENA(config
->spi_ps_input_addr
))
3591 shader_info
->num_input_vgprs
+= 1;
3592 if (G_0286CC_ANCILLARY_ENA(config
->spi_ps_input_addr
))
3593 shader_info
->num_input_vgprs
+= 1;
3594 if (G_0286CC_SAMPLE_COVERAGE_ENA(config
->spi_ps_input_addr
))
3595 shader_info
->num_input_vgprs
+= 1;
3596 if (G_0286CC_POS_FIXED_PT_ENA(config
->spi_ps_input_addr
))
3597 shader_info
->num_input_vgprs
+= 1;
3599 config
->num_vgprs
= MAX2(config
->num_vgprs
, shader_info
->num_input_vgprs
);
3601 /* +3 for scratch wave offset and VCC */
3602 config
->num_sgprs
= MAX2(config
->num_sgprs
,
3603 shader_info
->num_input_sgprs
+ 3);
3605 /* Enable 64-bit and 16-bit denormals, because there is no performance
3608 * If denormals are enabled, all floating-point output modifiers are
3611 * Don't enable denormals for 32-bit floats, because:
3612 * - Floating-point output modifiers would be ignored by the hw.
3613 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3614 * have to stop using those.
3615 * - SI & CI would be very slow.
3617 config
->float_mode
|= V_00B028_FP_64_DENORMS
;
3621 ac_fill_shader_info(struct radv_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct radv_nir_compiler_options
*options
)
3623 switch (nir
->info
.stage
) {
3624 case MESA_SHADER_COMPUTE
:
3625 for (int i
= 0; i
< 3; ++i
)
3626 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
3628 case MESA_SHADER_FRAGMENT
:
3629 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
3631 case MESA_SHADER_GEOMETRY
:
3632 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
3633 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
3634 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
3635 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
3637 case MESA_SHADER_TESS_EVAL
:
3638 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
3639 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
3640 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
3641 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
3642 shader_info
->tes
.as_es
= options
->key
.tes
.as_es
;
3644 case MESA_SHADER_TESS_CTRL
:
3645 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
3647 case MESA_SHADER_VERTEX
:
3648 shader_info
->vs
.as_es
= options
->key
.vs
.as_es
;
3649 shader_info
->vs
.as_ls
= options
->key
.vs
.as_ls
;
3650 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3651 if (options
->key
.vs
.as_ls
)
3652 shader_info
->vs
.vgpr_comp_cnt
= MAX2(1, shader_info
->vs
.vgpr_comp_cnt
);
3660 radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
3661 struct ac_shader_binary
*binary
,
3662 struct ac_shader_config
*config
,
3663 struct radv_shader_variant_info
*shader_info
,
3664 struct nir_shader
*const *nir
,
3666 const struct radv_nir_compiler_options
*options
)
3669 LLVMModuleRef llvm_module
;
3671 llvm_module
= ac_translate_nir_to_llvm(ac_llvm
, nir
, nir_count
, shader_info
,
3674 ac_compile_llvm_module(ac_llvm
, llvm_module
, binary
, config
, shader_info
,
3675 nir
[0]->info
.stage
, options
);
3677 for (int i
= 0; i
< nir_count
; ++i
)
3678 ac_fill_shader_info(shader_info
, nir
[i
], options
);
3680 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3681 if (options
->chip_class
== GFX9
) {
3682 if (nir_count
== 2 &&
3683 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3684 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
3690 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
3692 LLVMValueRef vtx_offset
=
3693 LLVMBuildMul(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
3694 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3695 unsigned offset
= 0;
3697 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3698 unsigned output_usage_mask
=
3699 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
3700 int length
= util_last_bit(output_usage_mask
);
3702 if (!(ctx
->output_mask
& (1ull << i
)))
3705 for (unsigned j
= 0; j
< length
; j
++) {
3706 LLVMValueRef value
, soffset
;
3708 if (!(output_usage_mask
& (1 << j
)))
3711 soffset
= LLVMConstInt(ctx
->ac
.i32
,
3713 ctx
->gs_max_out_vertices
* 16 * 4, false);
3717 value
= ac_build_buffer_load(&ctx
->ac
,
3720 vtx_offset
, soffset
,
3721 0, 1, 1, true, false);
3723 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
3724 if (ac_get_type_size(type
) == 2) {
3725 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
3726 value
= LLVMBuildTrunc(ctx
->ac
.builder
, value
, ctx
->ac
.i16
, "");
3729 LLVMBuildStore(ctx
->ac
.builder
,
3730 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
3733 handle_vs_outputs_post(ctx
, false, false, &ctx
->shader_info
->vs
.outinfo
);
3737 radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
3738 struct nir_shader
*geom_shader
,
3739 struct ac_shader_binary
*binary
,
3740 struct ac_shader_config
*config
,
3741 struct radv_shader_variant_info
*shader_info
,
3742 const struct radv_nir_compiler_options
*options
)
3744 struct radv_shader_context ctx
= {0};
3745 ctx
.options
= options
;
3746 ctx
.shader_info
= shader_info
;
3748 ac_llvm_context_init(&ctx
.ac
, options
->chip_class
, options
->family
);
3749 ctx
.context
= ctx
.ac
.context
;
3750 ctx
.ac
.module
= ac_create_module(ac_llvm
->tm
, ctx
.context
);
3752 ctx
.is_gs_copy_shader
= true;
3754 enum ac_float_mode float_mode
=
3755 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
3756 AC_FLOAT_MODE_DEFAULT
;
3758 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
3759 ctx
.stage
= MESA_SHADER_VERTEX
;
3761 radv_nir_shader_info_pass(geom_shader
, options
, &shader_info
->info
);
3763 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
3765 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
3766 ac_setup_rings(&ctx
);
3768 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
3769 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
3770 ac_handle_shader_output_decl(&ctx
.ac
, &ctx
.abi
, geom_shader
,
3771 variable
, MESA_SHADER_VERTEX
);
3774 ac_gs_copy_shader_emit(&ctx
);
3776 LLVMBuildRetVoid(ctx
.ac
.builder
);
3778 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
3780 ac_compile_llvm_module(ac_llvm
, ctx
.ac
.module
, binary
, config
, shader_info
,
3781 MESA_SHADER_VERTEX
, options
);