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radv: add dump_shader to the NIR compiler options
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "nir/nir.h"
31
32 #include <llvm-c/Core.h>
33 #include <llvm-c/TargetMachine.h>
34 #include <llvm-c/Transforms/Scalar.h>
35
36 #include "sid.h"
37 #include "gfx9d.h"
38 #include "ac_binary.h"
39 #include "ac_llvm_util.h"
40 #include "ac_llvm_build.h"
41 #include "ac_shader_abi.h"
42 #include "ac_shader_util.h"
43 #include "ac_exp_param.h"
44
45 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
46
47 struct radv_shader_context {
48 struct ac_llvm_context ac;
49 const struct radv_nir_compiler_options *options;
50 struct radv_shader_variant_info *shader_info;
51 struct ac_shader_abi abi;
52
53 unsigned max_workgroup_size;
54 LLVMContextRef context;
55 LLVMValueRef main_function;
56
57 LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
58 LLVMValueRef ring_offsets;
59
60 LLVMValueRef vertex_buffers;
61 LLVMValueRef rel_auto_id;
62 LLVMValueRef vs_prim_id;
63 LLVMValueRef ls_out_layout;
64 LLVMValueRef es2gs_offset;
65
66 LLVMValueRef tcs_offchip_layout;
67 LLVMValueRef tcs_out_offsets;
68 LLVMValueRef tcs_out_layout;
69 LLVMValueRef tcs_in_layout;
70 LLVMValueRef oc_lds;
71 LLVMValueRef merged_wave_info;
72 LLVMValueRef tess_factor_offset;
73 LLVMValueRef tes_rel_patch_id;
74 LLVMValueRef tes_u;
75 LLVMValueRef tes_v;
76
77 LLVMValueRef gsvs_ring_stride;
78 LLVMValueRef gsvs_num_entries;
79 LLVMValueRef gs2vs_offset;
80 LLVMValueRef gs_wave_id;
81 LLVMValueRef gs_vtx_offset[6];
82
83 LLVMValueRef esgs_ring;
84 LLVMValueRef gsvs_ring;
85 LLVMValueRef hs_ring_tess_offchip;
86 LLVMValueRef hs_ring_tess_factor;
87
88 LLVMValueRef sample_pos_offset;
89 LLVMValueRef persp_sample, persp_center, persp_centroid;
90 LLVMValueRef linear_sample, linear_center, linear_centroid;
91
92 gl_shader_stage stage;
93
94 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
95
96 uint64_t input_mask;
97 uint64_t output_mask;
98 uint8_t num_output_clips;
99 uint8_t num_output_culls;
100
101 bool is_gs_copy_shader;
102 LLVMValueRef gs_next_vertex;
103 unsigned gs_max_out_vertices;
104
105 unsigned tes_primitive_mode;
106 uint64_t tess_outputs_written;
107 uint64_t tess_patch_outputs_written;
108
109 uint32_t tcs_patch_outputs_read;
110 uint64_t tcs_outputs_read;
111 uint32_t tcs_vertices_per_patch;
112 };
113
114 enum radeon_llvm_calling_convention {
115 RADEON_LLVM_AMDGPU_VS = 87,
116 RADEON_LLVM_AMDGPU_GS = 88,
117 RADEON_LLVM_AMDGPU_PS = 89,
118 RADEON_LLVM_AMDGPU_CS = 90,
119 RADEON_LLVM_AMDGPU_HS = 93,
120 };
121
122 static inline struct radv_shader_context *
123 radv_shader_context_from_abi(struct ac_shader_abi *abi)
124 {
125 struct radv_shader_context *ctx = NULL;
126 return container_of(abi, ctx, abi);
127 }
128
129 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
130 {
131 switch (ctx->stage) {
132 case MESA_SHADER_TESS_CTRL:
133 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
134 case MESA_SHADER_TESS_EVAL:
135 return ctx->tes_rel_patch_id;
136 break;
137 default:
138 unreachable("Illegal stage");
139 }
140 }
141
142 /* Tessellation shaders pass outputs to the next shader using LDS.
143 *
144 * LS outputs = TCS inputs
145 * TCS outputs = TES inputs
146 *
147 * The LDS layout is:
148 * - TCS inputs for patch 0
149 * - TCS inputs for patch 1
150 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
151 * - ...
152 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
153 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
154 * - TCS outputs for patch 1
155 * - Per-patch TCS outputs for patch 1
156 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
157 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
158 * - ...
159 *
160 * All three shaders VS(LS), TCS, TES share the same LDS space.
161 */
162 static LLVMValueRef
163 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
164 {
165 if (ctx->stage == MESA_SHADER_VERTEX)
166 return ac_unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
167 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
168 return ac_unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
169 else {
170 assert(0);
171 return NULL;
172 }
173 }
174
175 static LLVMValueRef
176 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
177 {
178 return ac_unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
179 }
180
181 static LLVMValueRef
182 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
183 {
184 return ac_unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
185 }
186
187 static LLVMValueRef
188 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
189 {
190 return LLVMBuildMul(ctx->ac.builder,
191 ac_unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
192 LLVMConstInt(ctx->ac.i32, 4, false), "");
193 }
194
195 static LLVMValueRef
196 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
197 {
198 return LLVMBuildMul(ctx->ac.builder,
199 ac_unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
200 LLVMConstInt(ctx->ac.i32, 4, false), "");
201 }
202
203 static LLVMValueRef
204 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
205 {
206 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
207 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
208
209 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
210 }
211
212 static LLVMValueRef
213 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
214 {
215 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
216 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
217 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
218
219 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
220 LLVMBuildMul(ctx->ac.builder, patch_stride,
221 rel_patch_id, ""),
222 "");
223 }
224
225 static LLVMValueRef
226 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
227 {
228 LLVMValueRef patch0_patch_data_offset =
229 get_tcs_out_patch0_patch_data_offset(ctx);
230 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
231 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
232
233 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
234 LLVMBuildMul(ctx->ac.builder, patch_stride,
235 rel_patch_id, ""),
236 "");
237 }
238
239 #define MAX_ARGS 23
240 struct arg_info {
241 LLVMTypeRef types[MAX_ARGS];
242 LLVMValueRef *assign[MAX_ARGS];
243 unsigned array_params_mask;
244 uint8_t count;
245 uint8_t sgpr_count;
246 uint8_t num_sgprs_used;
247 uint8_t num_vgprs_used;
248 };
249
250 enum ac_arg_regfile {
251 ARG_SGPR,
252 ARG_VGPR,
253 };
254
255 static void
256 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
257 LLVMValueRef *param_ptr)
258 {
259 assert(info->count < MAX_ARGS);
260
261 info->assign[info->count] = param_ptr;
262 info->types[info->count] = type;
263 info->count++;
264
265 if (regfile == ARG_SGPR) {
266 info->num_sgprs_used += ac_get_type_size(type) / 4;
267 info->sgpr_count++;
268 } else {
269 assert(regfile == ARG_VGPR);
270 info->num_vgprs_used += ac_get_type_size(type) / 4;
271 }
272 }
273
274 static inline void
275 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
276 {
277 info->array_params_mask |= (1 << info->count);
278 add_arg(info, ARG_SGPR, type, param_ptr);
279 }
280
281 static void assign_arguments(LLVMValueRef main_function,
282 struct arg_info *info)
283 {
284 unsigned i;
285 for (i = 0; i < info->count; i++) {
286 if (info->assign[i])
287 *info->assign[i] = LLVMGetParam(main_function, i);
288 }
289 }
290
291 static LLVMValueRef
292 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
293 LLVMBuilderRef builder, LLVMTypeRef *return_types,
294 unsigned num_return_elems,
295 struct arg_info *args,
296 unsigned max_workgroup_size,
297 bool unsafe_math)
298 {
299 LLVMTypeRef main_function_type, ret_type;
300 LLVMBasicBlockRef main_function_body;
301
302 if (num_return_elems)
303 ret_type = LLVMStructTypeInContext(ctx, return_types,
304 num_return_elems, true);
305 else
306 ret_type = LLVMVoidTypeInContext(ctx);
307
308 /* Setup the function */
309 main_function_type =
310 LLVMFunctionType(ret_type, args->types, args->count, 0);
311 LLVMValueRef main_function =
312 LLVMAddFunction(module, "main", main_function_type);
313 main_function_body =
314 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
315 LLVMPositionBuilderAtEnd(builder, main_function_body);
316
317 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
318 for (unsigned i = 0; i < args->sgpr_count; ++i) {
319 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
320
321 if (args->array_params_mask & (1 << i)) {
322 LLVMValueRef P = LLVMGetParam(main_function, i);
323 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
324 ac_add_attr_dereferenceable(P, UINT64_MAX);
325 }
326 }
327
328 if (max_workgroup_size) {
329 ac_llvm_add_target_dep_function_attr(main_function,
330 "amdgpu-max-work-group-size",
331 max_workgroup_size);
332 }
333 if (unsafe_math) {
334 /* These were copied from some LLVM test. */
335 LLVMAddTargetDependentFunctionAttr(main_function,
336 "less-precise-fpmad",
337 "true");
338 LLVMAddTargetDependentFunctionAttr(main_function,
339 "no-infs-fp-math",
340 "true");
341 LLVMAddTargetDependentFunctionAttr(main_function,
342 "no-nans-fp-math",
343 "true");
344 LLVMAddTargetDependentFunctionAttr(main_function,
345 "unsafe-fp-math",
346 "true");
347 LLVMAddTargetDependentFunctionAttr(main_function,
348 "no-signed-zeros-fp-math",
349 "true");
350 }
351 return main_function;
352 }
353
354
355 static void
356 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
357 uint32_t indirect_offset)
358 {
359 ud_info->sgpr_idx = *sgpr_idx;
360 ud_info->num_sgprs = num_sgprs;
361 ud_info->indirect = indirect_offset > 0;
362 ud_info->indirect_offset = indirect_offset;
363 *sgpr_idx += num_sgprs;
364 }
365
366 static void
367 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
368 uint8_t num_sgprs)
369 {
370 struct radv_userdata_info *ud_info =
371 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
372 assert(ud_info);
373
374 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
375 }
376
377 static void
378 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
379 uint32_t indirect_offset)
380 {
381 struct radv_userdata_info *ud_info =
382 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
383 assert(ud_info);
384
385 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
386 }
387
388 struct user_sgpr_info {
389 bool need_ring_offsets;
390 uint8_t sgpr_count;
391 bool indirect_all_descriptor_sets;
392 };
393
394 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
395 gl_shader_stage stage)
396 {
397 switch (stage) {
398 case MESA_SHADER_VERTEX:
399 if (ctx->shader_info->info.needs_multiview_view_index ||
400 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
401 return true;
402 break;
403 case MESA_SHADER_TESS_EVAL:
404 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
405 return true;
406 break;
407 case MESA_SHADER_GEOMETRY:
408 case MESA_SHADER_TESS_CTRL:
409 if (ctx->shader_info->info.needs_multiview_view_index)
410 return true;
411 break;
412 default:
413 break;
414 }
415 return false;
416 }
417
418 static uint8_t
419 count_vs_user_sgprs(struct radv_shader_context *ctx)
420 {
421 uint8_t count = 0;
422
423 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
424 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
425
426 return count;
427 }
428
429 static void allocate_user_sgprs(struct radv_shader_context *ctx,
430 gl_shader_stage stage,
431 bool has_previous_stage,
432 gl_shader_stage previous_stage,
433 bool needs_view_index,
434 struct user_sgpr_info *user_sgpr_info)
435 {
436 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
437
438 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
439 if (stage == MESA_SHADER_GEOMETRY ||
440 stage == MESA_SHADER_VERTEX ||
441 stage == MESA_SHADER_TESS_CTRL ||
442 stage == MESA_SHADER_TESS_EVAL ||
443 ctx->is_gs_copy_shader)
444 user_sgpr_info->need_ring_offsets = true;
445
446 if (stage == MESA_SHADER_FRAGMENT &&
447 ctx->shader_info->info.ps.needs_sample_positions)
448 user_sgpr_info->need_ring_offsets = true;
449
450 /* 2 user sgprs will nearly always be allocated for scratch/rings */
451 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
452 user_sgpr_info->sgpr_count += 2;
453 }
454
455 switch (stage) {
456 case MESA_SHADER_COMPUTE:
457 if (ctx->shader_info->info.cs.uses_grid_size)
458 user_sgpr_info->sgpr_count += 3;
459 break;
460 case MESA_SHADER_FRAGMENT:
461 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
462 break;
463 case MESA_SHADER_VERTEX:
464 if (!ctx->is_gs_copy_shader)
465 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
466 if (ctx->options->key.vs.as_ls)
467 user_sgpr_info->sgpr_count++;
468 break;
469 case MESA_SHADER_TESS_CTRL:
470 if (has_previous_stage) {
471 if (previous_stage == MESA_SHADER_VERTEX)
472 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
473 user_sgpr_info->sgpr_count++;
474 }
475 user_sgpr_info->sgpr_count += 4;
476 break;
477 case MESA_SHADER_TESS_EVAL:
478 user_sgpr_info->sgpr_count += 1;
479 break;
480 case MESA_SHADER_GEOMETRY:
481 if (has_previous_stage) {
482 if (previous_stage == MESA_SHADER_VERTEX) {
483 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
484 } else {
485 user_sgpr_info->sgpr_count++;
486 }
487 }
488 user_sgpr_info->sgpr_count += 2;
489 break;
490 default:
491 break;
492 }
493
494 if (needs_view_index)
495 user_sgpr_info->sgpr_count++;
496
497 if (ctx->shader_info->info.loads_push_constants)
498 user_sgpr_info->sgpr_count += 2;
499
500 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
501 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
502
503 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
504 user_sgpr_info->sgpr_count += 2;
505 user_sgpr_info->indirect_all_descriptor_sets = true;
506 } else {
507 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
508 }
509 }
510
511 static void
512 declare_global_input_sgprs(struct radv_shader_context *ctx,
513 gl_shader_stage stage,
514 bool has_previous_stage,
515 gl_shader_stage previous_stage,
516 const struct user_sgpr_info *user_sgpr_info,
517 struct arg_info *args,
518 LLVMValueRef *desc_sets)
519 {
520 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
521 unsigned num_sets = ctx->options->layout ?
522 ctx->options->layout->num_sets : 0;
523 unsigned stage_mask = 1 << stage;
524
525 if (has_previous_stage)
526 stage_mask |= 1 << previous_stage;
527
528 /* 1 for each descriptor set */
529 if (!user_sgpr_info->indirect_all_descriptor_sets) {
530 for (unsigned i = 0; i < num_sets; ++i) {
531 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
532 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
533 add_array_arg(args, type,
534 &ctx->descriptor_sets[i]);
535 }
536 }
537 } else {
538 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
539 }
540
541 if (ctx->shader_info->info.loads_push_constants) {
542 /* 1 for push constants and dynamic descriptors */
543 add_array_arg(args, type, &ctx->abi.push_constants);
544 }
545 }
546
547 static void
548 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
549 gl_shader_stage stage,
550 bool has_previous_stage,
551 gl_shader_stage previous_stage,
552 struct arg_info *args)
553 {
554 if (!ctx->is_gs_copy_shader &&
555 (stage == MESA_SHADER_VERTEX ||
556 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
557 if (ctx->shader_info->info.vs.has_vertex_buffers) {
558 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
559 &ctx->vertex_buffers);
560 }
561 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
562 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
563 if (ctx->shader_info->info.vs.needs_draw_id) {
564 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
565 }
566 }
567 }
568
569 static void
570 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
571 {
572 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
573 if (!ctx->is_gs_copy_shader) {
574 if (ctx->options->key.vs.as_ls) {
575 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
576 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
577 } else {
578 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
579 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
580 }
581 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
582 }
583 }
584
585 static void
586 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
587 {
588 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
589 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
590 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
591 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
592 }
593
594 static void
595 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
596 bool has_previous_stage, gl_shader_stage previous_stage,
597 const struct user_sgpr_info *user_sgpr_info,
598 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
599 {
600 unsigned num_sets = ctx->options->layout ?
601 ctx->options->layout->num_sets : 0;
602 unsigned stage_mask = 1 << stage;
603
604 if (has_previous_stage)
605 stage_mask |= 1 << previous_stage;
606
607 if (!user_sgpr_info->indirect_all_descriptor_sets) {
608 for (unsigned i = 0; i < num_sets; ++i) {
609 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
610 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
611 set_loc_desc(ctx, i, user_sgpr_idx, 0);
612 } else
613 ctx->descriptor_sets[i] = NULL;
614 }
615 } else {
616 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
617 user_sgpr_idx, 2);
618
619 for (unsigned i = 0; i < num_sets; ++i) {
620 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
621 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
622 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
623 ctx->descriptor_sets[i] =
624 ac_build_load_to_sgpr(&ctx->ac,
625 desc_sets,
626 LLVMConstInt(ctx->ac.i32, i, false));
627
628 } else
629 ctx->descriptor_sets[i] = NULL;
630 }
631 ctx->shader_info->need_indirect_descriptor_sets = true;
632 }
633
634 if (ctx->shader_info->info.loads_push_constants) {
635 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
636 }
637 }
638
639 static void
640 set_vs_specific_input_locs(struct radv_shader_context *ctx,
641 gl_shader_stage stage, bool has_previous_stage,
642 gl_shader_stage previous_stage,
643 uint8_t *user_sgpr_idx)
644 {
645 if (!ctx->is_gs_copy_shader &&
646 (stage == MESA_SHADER_VERTEX ||
647 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
648 if (ctx->shader_info->info.vs.has_vertex_buffers) {
649 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
650 user_sgpr_idx, 2);
651 }
652
653 unsigned vs_num = 2;
654 if (ctx->shader_info->info.vs.needs_draw_id)
655 vs_num++;
656
657 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
658 user_sgpr_idx, vs_num);
659 }
660 }
661
662 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
663 {
664 /* handle patch indices separate */
665 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
666 return 0;
667 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
668 return 1;
669 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
670 return 2 + (slot - VARYING_SLOT_PATCH0);
671
672 if (slot == VARYING_SLOT_POS)
673 return 0;
674 if (slot == VARYING_SLOT_PSIZ)
675 return 1;
676 if (slot == VARYING_SLOT_CLIP_DIST0)
677 return 2;
678 /* 3 is reserved for clip dist as well */
679 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
680 return 4 + (slot - VARYING_SLOT_VAR0);
681 unreachable("illegal slot in get unique index\n");
682 }
683
684 static void set_llvm_calling_convention(LLVMValueRef func,
685 gl_shader_stage stage)
686 {
687 enum radeon_llvm_calling_convention calling_conv;
688
689 switch (stage) {
690 case MESA_SHADER_VERTEX:
691 case MESA_SHADER_TESS_EVAL:
692 calling_conv = RADEON_LLVM_AMDGPU_VS;
693 break;
694 case MESA_SHADER_GEOMETRY:
695 calling_conv = RADEON_LLVM_AMDGPU_GS;
696 break;
697 case MESA_SHADER_TESS_CTRL:
698 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
699 break;
700 case MESA_SHADER_FRAGMENT:
701 calling_conv = RADEON_LLVM_AMDGPU_PS;
702 break;
703 case MESA_SHADER_COMPUTE:
704 calling_conv = RADEON_LLVM_AMDGPU_CS;
705 break;
706 default:
707 unreachable("Unhandle shader type");
708 }
709
710 LLVMSetFunctionCallConv(func, calling_conv);
711 }
712
713 static void create_function(struct radv_shader_context *ctx,
714 gl_shader_stage stage,
715 bool has_previous_stage,
716 gl_shader_stage previous_stage)
717 {
718 uint8_t user_sgpr_idx;
719 struct user_sgpr_info user_sgpr_info;
720 struct arg_info args = {};
721 LLVMValueRef desc_sets;
722 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
723 allocate_user_sgprs(ctx, stage, has_previous_stage,
724 previous_stage, needs_view_index, &user_sgpr_info);
725
726 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
727 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
728 &ctx->ring_offsets);
729 }
730
731 switch (stage) {
732 case MESA_SHADER_COMPUTE:
733 declare_global_input_sgprs(ctx, stage, has_previous_stage,
734 previous_stage, &user_sgpr_info,
735 &args, &desc_sets);
736
737 if (ctx->shader_info->info.cs.uses_grid_size) {
738 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
739 &ctx->abi.num_work_groups);
740 }
741
742 for (int i = 0; i < 3; i++) {
743 ctx->abi.workgroup_ids[i] = NULL;
744 if (ctx->shader_info->info.cs.uses_block_id[i]) {
745 add_arg(&args, ARG_SGPR, ctx->ac.i32,
746 &ctx->abi.workgroup_ids[i]);
747 }
748 }
749
750 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
751 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
752 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
753 &ctx->abi.local_invocation_ids);
754 break;
755 case MESA_SHADER_VERTEX:
756 declare_global_input_sgprs(ctx, stage, has_previous_stage,
757 previous_stage, &user_sgpr_info,
758 &args, &desc_sets);
759 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
760 previous_stage, &args);
761
762 if (needs_view_index)
763 add_arg(&args, ARG_SGPR, ctx->ac.i32,
764 &ctx->abi.view_index);
765 if (ctx->options->key.vs.as_es)
766 add_arg(&args, ARG_SGPR, ctx->ac.i32,
767 &ctx->es2gs_offset);
768 else if (ctx->options->key.vs.as_ls)
769 add_arg(&args, ARG_SGPR, ctx->ac.i32,
770 &ctx->ls_out_layout);
771
772 declare_vs_input_vgprs(ctx, &args);
773 break;
774 case MESA_SHADER_TESS_CTRL:
775 if (has_previous_stage) {
776 // First 6 system regs
777 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
778 add_arg(&args, ARG_SGPR, ctx->ac.i32,
779 &ctx->merged_wave_info);
780 add_arg(&args, ARG_SGPR, ctx->ac.i32,
781 &ctx->tess_factor_offset);
782
783 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
784 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
785 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
786
787 declare_global_input_sgprs(ctx, stage,
788 has_previous_stage,
789 previous_stage,
790 &user_sgpr_info, &args,
791 &desc_sets);
792 declare_vs_specific_input_sgprs(ctx, stage,
793 has_previous_stage,
794 previous_stage, &args);
795
796 add_arg(&args, ARG_SGPR, ctx->ac.i32,
797 &ctx->ls_out_layout);
798
799 add_arg(&args, ARG_SGPR, ctx->ac.i32,
800 &ctx->tcs_offchip_layout);
801 add_arg(&args, ARG_SGPR, ctx->ac.i32,
802 &ctx->tcs_out_offsets);
803 add_arg(&args, ARG_SGPR, ctx->ac.i32,
804 &ctx->tcs_out_layout);
805 add_arg(&args, ARG_SGPR, ctx->ac.i32,
806 &ctx->tcs_in_layout);
807 if (needs_view_index)
808 add_arg(&args, ARG_SGPR, ctx->ac.i32,
809 &ctx->abi.view_index);
810
811 add_arg(&args, ARG_VGPR, ctx->ac.i32,
812 &ctx->abi.tcs_patch_id);
813 add_arg(&args, ARG_VGPR, ctx->ac.i32,
814 &ctx->abi.tcs_rel_ids);
815
816 declare_vs_input_vgprs(ctx, &args);
817 } else {
818 declare_global_input_sgprs(ctx, stage,
819 has_previous_stage,
820 previous_stage,
821 &user_sgpr_info, &args,
822 &desc_sets);
823
824 add_arg(&args, ARG_SGPR, ctx->ac.i32,
825 &ctx->tcs_offchip_layout);
826 add_arg(&args, ARG_SGPR, ctx->ac.i32,
827 &ctx->tcs_out_offsets);
828 add_arg(&args, ARG_SGPR, ctx->ac.i32,
829 &ctx->tcs_out_layout);
830 add_arg(&args, ARG_SGPR, ctx->ac.i32,
831 &ctx->tcs_in_layout);
832 if (needs_view_index)
833 add_arg(&args, ARG_SGPR, ctx->ac.i32,
834 &ctx->abi.view_index);
835
836 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->tess_factor_offset);
839 add_arg(&args, ARG_VGPR, ctx->ac.i32,
840 &ctx->abi.tcs_patch_id);
841 add_arg(&args, ARG_VGPR, ctx->ac.i32,
842 &ctx->abi.tcs_rel_ids);
843 }
844 break;
845 case MESA_SHADER_TESS_EVAL:
846 declare_global_input_sgprs(ctx, stage, has_previous_stage,
847 previous_stage, &user_sgpr_info,
848 &args, &desc_sets);
849
850 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
851 if (needs_view_index)
852 add_arg(&args, ARG_SGPR, ctx->ac.i32,
853 &ctx->abi.view_index);
854
855 if (ctx->options->key.tes.as_es) {
856 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
857 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
858 add_arg(&args, ARG_SGPR, ctx->ac.i32,
859 &ctx->es2gs_offset);
860 } else {
861 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
862 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
863 }
864 declare_tes_input_vgprs(ctx, &args);
865 break;
866 case MESA_SHADER_GEOMETRY:
867 if (has_previous_stage) {
868 // First 6 system regs
869 add_arg(&args, ARG_SGPR, ctx->ac.i32,
870 &ctx->gs2vs_offset);
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->merged_wave_info);
873 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
874
875 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
876 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
877 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
878
879 declare_global_input_sgprs(ctx, stage,
880 has_previous_stage,
881 previous_stage,
882 &user_sgpr_info, &args,
883 &desc_sets);
884
885 if (previous_stage == MESA_SHADER_TESS_EVAL) {
886 add_arg(&args, ARG_SGPR, ctx->ac.i32,
887 &ctx->tcs_offchip_layout);
888 } else {
889 declare_vs_specific_input_sgprs(ctx, stage,
890 has_previous_stage,
891 previous_stage,
892 &args);
893 }
894
895 add_arg(&args, ARG_SGPR, ctx->ac.i32,
896 &ctx->gsvs_ring_stride);
897 add_arg(&args, ARG_SGPR, ctx->ac.i32,
898 &ctx->gsvs_num_entries);
899 if (needs_view_index)
900 add_arg(&args, ARG_SGPR, ctx->ac.i32,
901 &ctx->abi.view_index);
902
903 add_arg(&args, ARG_VGPR, ctx->ac.i32,
904 &ctx->gs_vtx_offset[0]);
905 add_arg(&args, ARG_VGPR, ctx->ac.i32,
906 &ctx->gs_vtx_offset[2]);
907 add_arg(&args, ARG_VGPR, ctx->ac.i32,
908 &ctx->abi.gs_prim_id);
909 add_arg(&args, ARG_VGPR, ctx->ac.i32,
910 &ctx->abi.gs_invocation_id);
911 add_arg(&args, ARG_VGPR, ctx->ac.i32,
912 &ctx->gs_vtx_offset[4]);
913
914 if (previous_stage == MESA_SHADER_VERTEX) {
915 declare_vs_input_vgprs(ctx, &args);
916 } else {
917 declare_tes_input_vgprs(ctx, &args);
918 }
919 } else {
920 declare_global_input_sgprs(ctx, stage,
921 has_previous_stage,
922 previous_stage,
923 &user_sgpr_info, &args,
924 &desc_sets);
925
926 add_arg(&args, ARG_SGPR, ctx->ac.i32,
927 &ctx->gsvs_ring_stride);
928 add_arg(&args, ARG_SGPR, ctx->ac.i32,
929 &ctx->gsvs_num_entries);
930 if (needs_view_index)
931 add_arg(&args, ARG_SGPR, ctx->ac.i32,
932 &ctx->abi.view_index);
933
934 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
935 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
936 add_arg(&args, ARG_VGPR, ctx->ac.i32,
937 &ctx->gs_vtx_offset[0]);
938 add_arg(&args, ARG_VGPR, ctx->ac.i32,
939 &ctx->gs_vtx_offset[1]);
940 add_arg(&args, ARG_VGPR, ctx->ac.i32,
941 &ctx->abi.gs_prim_id);
942 add_arg(&args, ARG_VGPR, ctx->ac.i32,
943 &ctx->gs_vtx_offset[2]);
944 add_arg(&args, ARG_VGPR, ctx->ac.i32,
945 &ctx->gs_vtx_offset[3]);
946 add_arg(&args, ARG_VGPR, ctx->ac.i32,
947 &ctx->gs_vtx_offset[4]);
948 add_arg(&args, ARG_VGPR, ctx->ac.i32,
949 &ctx->gs_vtx_offset[5]);
950 add_arg(&args, ARG_VGPR, ctx->ac.i32,
951 &ctx->abi.gs_invocation_id);
952 }
953 break;
954 case MESA_SHADER_FRAGMENT:
955 declare_global_input_sgprs(ctx, stage, has_previous_stage,
956 previous_stage, &user_sgpr_info,
957 &args, &desc_sets);
958
959 if (ctx->shader_info->info.ps.needs_sample_positions)
960 add_arg(&args, ARG_SGPR, ctx->ac.i32,
961 &ctx->sample_pos_offset);
962
963 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
964 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
965 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
966 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
967 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
968 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
969 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
970 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
971 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
972 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
973 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
974 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
975 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
977 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
979 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
980 break;
981 default:
982 unreachable("Shader stage not implemented");
983 }
984
985 ctx->main_function = create_llvm_function(
986 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
987 ctx->max_workgroup_size,
988 ctx->options->unsafe_math);
989 set_llvm_calling_convention(ctx->main_function, stage);
990
991
992 ctx->shader_info->num_input_vgprs = 0;
993 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
994
995 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
996
997 if (ctx->stage != MESA_SHADER_FRAGMENT)
998 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
999
1000 assign_arguments(ctx->main_function, &args);
1001
1002 user_sgpr_idx = 0;
1003
1004 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1005 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1006 &user_sgpr_idx, 2);
1007 if (ctx->options->supports_spill) {
1008 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1009 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1010 NULL, 0, AC_FUNC_ATTR_READNONE);
1011 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1012 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1013 }
1014 }
1015
1016 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1017 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1018 if (has_previous_stage)
1019 user_sgpr_idx = 0;
1020
1021 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1022 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1023
1024 switch (stage) {
1025 case MESA_SHADER_COMPUTE:
1026 if (ctx->shader_info->info.cs.uses_grid_size) {
1027 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1028 &user_sgpr_idx, 3);
1029 }
1030 break;
1031 case MESA_SHADER_VERTEX:
1032 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1033 previous_stage, &user_sgpr_idx);
1034 if (ctx->abi.view_index)
1035 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1036 if (ctx->options->key.vs.as_ls) {
1037 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1038 &user_sgpr_idx, 1);
1039 }
1040 break;
1041 case MESA_SHADER_TESS_CTRL:
1042 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1043 previous_stage, &user_sgpr_idx);
1044 if (has_previous_stage)
1045 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1046 &user_sgpr_idx, 1);
1047 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1048 if (ctx->abi.view_index)
1049 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1050 break;
1051 case MESA_SHADER_TESS_EVAL:
1052 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1053 if (ctx->abi.view_index)
1054 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1055 break;
1056 case MESA_SHADER_GEOMETRY:
1057 if (has_previous_stage) {
1058 if (previous_stage == MESA_SHADER_VERTEX)
1059 set_vs_specific_input_locs(ctx, stage,
1060 has_previous_stage,
1061 previous_stage,
1062 &user_sgpr_idx);
1063 else
1064 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1065 &user_sgpr_idx, 1);
1066 }
1067 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1068 &user_sgpr_idx, 2);
1069 if (ctx->abi.view_index)
1070 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1071 break;
1072 case MESA_SHADER_FRAGMENT:
1073 if (ctx->shader_info->info.ps.needs_sample_positions) {
1074 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1075 &user_sgpr_idx, 1);
1076 }
1077 break;
1078 default:
1079 unreachable("Shader stage not implemented");
1080 }
1081
1082 if (stage == MESA_SHADER_TESS_CTRL ||
1083 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1084 /* GFX9 has the ESGS ring buffer in LDS. */
1085 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1086 ac_declare_lds_as_pointer(&ctx->ac);
1087 }
1088
1089 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1090 }
1091
1092
1093 static LLVMValueRef
1094 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1095 unsigned desc_set, unsigned binding)
1096 {
1097 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1098 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1099 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1100 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1101 unsigned base_offset = layout->binding[binding].offset;
1102 LLVMValueRef offset, stride;
1103
1104 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1105 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1106 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1107 layout->binding[binding].dynamic_offset_offset;
1108 desc_ptr = ctx->abi.push_constants;
1109 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1110 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1111 } else
1112 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1113
1114 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
1115 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
1116 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
1117
1118 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1119 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1120 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1121
1122 return desc_ptr;
1123 }
1124
1125
1126 /* The offchip buffer layout for TCS->TES is
1127 *
1128 * - attribute 0 of patch 0 vertex 0
1129 * - attribute 0 of patch 0 vertex 1
1130 * - attribute 0 of patch 0 vertex 2
1131 * ...
1132 * - attribute 0 of patch 1 vertex 0
1133 * - attribute 0 of patch 1 vertex 1
1134 * ...
1135 * - attribute 1 of patch 0 vertex 0
1136 * - attribute 1 of patch 0 vertex 1
1137 * ...
1138 * - per patch attribute 0 of patch 0
1139 * - per patch attribute 0 of patch 1
1140 * ...
1141 *
1142 * Note that every attribute has 4 components.
1143 */
1144 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1145 LLVMValueRef vertex_index,
1146 LLVMValueRef param_index)
1147 {
1148 LLVMValueRef base_addr, vertices_per_patch, num_patches;
1149 LLVMValueRef param_stride, constant16;
1150 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1151
1152 vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
1153 num_patches = ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
1154
1155 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1156 if (vertex_index) {
1157 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
1158 vertices_per_patch, "");
1159
1160 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1161 vertex_index, "");
1162
1163 param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
1164 num_patches, "");
1165 } else {
1166 base_addr = rel_patch_id;
1167 param_stride = num_patches;
1168 }
1169
1170 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1171 LLVMBuildMul(ctx->ac.builder, param_index,
1172 param_stride, ""), "");
1173
1174 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1175
1176 if (!vertex_index) {
1177 LLVMValueRef patch_data_offset =
1178 ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
1179
1180 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1181 patch_data_offset, "");
1182 }
1183 return base_addr;
1184 }
1185
1186 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1187 unsigned param,
1188 unsigned const_index,
1189 bool is_compact,
1190 LLVMValueRef vertex_index,
1191 LLVMValueRef indir_index)
1192 {
1193 LLVMValueRef param_index;
1194
1195 if (indir_index)
1196 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1197 indir_index, "");
1198 else {
1199 if (const_index && !is_compact)
1200 param += const_index;
1201 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1202 }
1203 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1204 }
1205
1206 static void
1207 mark_tess_output(struct radv_shader_context *ctx,
1208 bool is_patch, uint32_t param, int num_slots)
1209
1210 {
1211 uint64_t slot_mask = (1ull << num_slots) - 1;
1212 if (is_patch) {
1213 ctx->tess_patch_outputs_written |= (slot_mask << param);
1214 } else
1215 ctx->tess_outputs_written |= (slot_mask << param);
1216 }
1217
1218 static LLVMValueRef
1219 get_dw_address(struct radv_shader_context *ctx,
1220 LLVMValueRef dw_addr,
1221 unsigned param,
1222 unsigned const_index,
1223 bool compact_const_index,
1224 LLVMValueRef vertex_index,
1225 LLVMValueRef stride,
1226 LLVMValueRef indir_index)
1227
1228 {
1229
1230 if (vertex_index) {
1231 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1232 LLVMBuildMul(ctx->ac.builder,
1233 vertex_index,
1234 stride, ""), "");
1235 }
1236
1237 if (indir_index)
1238 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1239 LLVMBuildMul(ctx->ac.builder, indir_index,
1240 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1241 else if (const_index && !compact_const_index)
1242 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1243 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1244
1245 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1246 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1247
1248 if (const_index && compact_const_index)
1249 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1250 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1251 return dw_addr;
1252 }
1253
1254 static LLVMValueRef
1255 load_tcs_varyings(struct ac_shader_abi *abi,
1256 LLVMTypeRef type,
1257 LLVMValueRef vertex_index,
1258 LLVMValueRef indir_index,
1259 unsigned const_index,
1260 unsigned location,
1261 unsigned driver_location,
1262 unsigned component,
1263 unsigned num_components,
1264 bool is_patch,
1265 bool is_compact,
1266 bool load_input)
1267 {
1268 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1269 LLVMValueRef dw_addr, stride;
1270 LLVMValueRef value[4], result;
1271 unsigned param = shader_io_get_unique_index(location);
1272
1273 if (load_input) {
1274 stride = ac_unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
1275 dw_addr = get_tcs_in_current_patch_offset(ctx);
1276 } else {
1277 if (!is_patch) {
1278 stride = get_tcs_out_vertex_stride(ctx);
1279 dw_addr = get_tcs_out_current_patch_offset(ctx);
1280 } else {
1281 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1282 stride = NULL;
1283 }
1284 }
1285
1286 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1287 indir_index);
1288
1289 for (unsigned i = 0; i < num_components + component; i++) {
1290 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1291 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1292 ctx->ac.i32_1, "");
1293 }
1294 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1295 return result;
1296 }
1297
1298 static void
1299 store_tcs_output(struct ac_shader_abi *abi,
1300 const nir_variable *var,
1301 LLVMValueRef vertex_index,
1302 LLVMValueRef param_index,
1303 unsigned const_index,
1304 LLVMValueRef src,
1305 unsigned writemask)
1306 {
1307 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1308 const unsigned location = var->data.location;
1309 const unsigned component = var->data.location_frac;
1310 const bool is_patch = var->data.patch;
1311 const bool is_compact = var->data.compact;
1312 const unsigned count = glsl_count_attribute_slots(var->type, false);
1313 LLVMValueRef dw_addr;
1314 LLVMValueRef stride = NULL;
1315 LLVMValueRef buf_addr = NULL;
1316 unsigned param;
1317 bool store_lds = true;
1318
1319 if (is_patch) {
1320 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1321 store_lds = false;
1322 } else {
1323 if (!(ctx->tcs_outputs_read & (1ULL << location)))
1324 store_lds = false;
1325 }
1326
1327 param = shader_io_get_unique_index(location);
1328 if (location == VARYING_SLOT_CLIP_DIST0 &&
1329 is_compact && const_index > 3) {
1330 const_index -= 3;
1331 param++;
1332 }
1333
1334 if (!is_patch) {
1335 stride = get_tcs_out_vertex_stride(ctx);
1336 dw_addr = get_tcs_out_current_patch_offset(ctx);
1337 } else {
1338 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1339 }
1340
1341 if (param_index)
1342 mark_tess_output(ctx, is_patch, param, count);
1343 else
1344 mark_tess_output(ctx, is_patch, param, 1);
1345
1346 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1347 param_index);
1348 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1349 vertex_index, param_index);
1350
1351 bool is_tess_factor = false;
1352 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1353 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1354 is_tess_factor = true;
1355
1356 unsigned base = is_compact ? const_index : 0;
1357 for (unsigned chan = 0; chan < 8; chan++) {
1358 if (!(writemask & (1 << chan)))
1359 continue;
1360 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1361
1362 if (store_lds || is_tess_factor) {
1363 LLVMValueRef dw_addr_chan =
1364 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1365 LLVMConstInt(ctx->ac.i32, chan, false), "");
1366 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1367 }
1368
1369 if (!is_tess_factor && writemask != 0xF)
1370 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1371 buf_addr, ctx->oc_lds,
1372 4 * (base + chan), 1, 0, true, false);
1373 }
1374
1375 if (writemask == 0xF) {
1376 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1377 buf_addr, ctx->oc_lds,
1378 (base * 4), 1, 0, true, false);
1379 }
1380 }
1381
1382 static LLVMValueRef
1383 load_tes_input(struct ac_shader_abi *abi,
1384 LLVMTypeRef type,
1385 LLVMValueRef vertex_index,
1386 LLVMValueRef param_index,
1387 unsigned const_index,
1388 unsigned location,
1389 unsigned driver_location,
1390 unsigned component,
1391 unsigned num_components,
1392 bool is_patch,
1393 bool is_compact,
1394 bool load_input)
1395 {
1396 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1397 LLVMValueRef buf_addr;
1398 LLVMValueRef result;
1399 unsigned param = shader_io_get_unique_index(location);
1400
1401 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
1402 const_index -= 3;
1403 param++;
1404 }
1405
1406 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1407 is_compact, vertex_index, param_index);
1408
1409 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1410 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1411
1412 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1413 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
1414 result = ac_trim_vector(&ctx->ac, result, num_components);
1415 return result;
1416 }
1417
1418 static LLVMValueRef
1419 load_gs_input(struct ac_shader_abi *abi,
1420 unsigned location,
1421 unsigned driver_location,
1422 unsigned component,
1423 unsigned num_components,
1424 unsigned vertex_index,
1425 unsigned const_index,
1426 LLVMTypeRef type)
1427 {
1428 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1429 LLVMValueRef vtx_offset;
1430 unsigned param, vtx_offset_param;
1431 LLVMValueRef value[4], result;
1432
1433 vtx_offset_param = vertex_index;
1434 assert(vtx_offset_param < 6);
1435 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1436 LLVMConstInt(ctx->ac.i32, 4, false), "");
1437
1438 param = shader_io_get_unique_index(location);
1439
1440 for (unsigned i = component; i < num_components + component; i++) {
1441 if (ctx->ac.chip_class >= GFX9) {
1442 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1443 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1444 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1445 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1446 } else {
1447 LLVMValueRef soffset =
1448 LLVMConstInt(ctx->ac.i32,
1449 (param * 4 + i + const_index) * 256,
1450 false);
1451
1452 value[i] = ac_build_buffer_load(&ctx->ac,
1453 ctx->esgs_ring, 1,
1454 ctx->ac.i32_0,
1455 vtx_offset, soffset,
1456 0, 1, 0, true, false);
1457
1458 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
1459 type, "");
1460 }
1461 }
1462 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1463 result = ac_to_integer(&ctx->ac, result);
1464 return result;
1465 }
1466
1467
1468 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1469 {
1470 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1471 ac_build_kill_if_false(&ctx->ac, visible);
1472 }
1473
1474 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
1475 enum glsl_interp_mode interp, unsigned location)
1476 {
1477 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1478
1479 switch (interp) {
1480 case INTERP_MODE_FLAT:
1481 default:
1482 return NULL;
1483 case INTERP_MODE_SMOOTH:
1484 case INTERP_MODE_NONE:
1485 if (location == INTERP_CENTER)
1486 return ctx->persp_center;
1487 else if (location == INTERP_CENTROID)
1488 return ctx->persp_centroid;
1489 else if (location == INTERP_SAMPLE)
1490 return ctx->persp_sample;
1491 break;
1492 case INTERP_MODE_NOPERSPECTIVE:
1493 if (location == INTERP_CENTER)
1494 return ctx->linear_center;
1495 else if (location == INTERP_CENTROID)
1496 return ctx->linear_centroid;
1497 else if (location == INTERP_SAMPLE)
1498 return ctx->linear_sample;
1499 break;
1500 }
1501 return NULL;
1502 }
1503
1504 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1505 LLVMValueRef sample_id)
1506 {
1507 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1508
1509 LLVMValueRef result;
1510 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
1511
1512 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1513 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1514
1515 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
1516 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1517
1518 return result;
1519 }
1520
1521
1522 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1523 {
1524 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1525 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
1526 ctx->options->key.fs.log2_num_samples :
1527 ctx->options->key.fs.log2_ps_iter_samples;
1528
1529 /* The bit pattern matches that used by fixed function fragment
1530 * processing. */
1531 static const uint16_t ps_iter_masks[] = {
1532 0xffff, /* not used */
1533 0x5555,
1534 0x1111,
1535 0x0101,
1536 0x0001,
1537 };
1538 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1539
1540 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1541
1542 LLVMValueRef result, sample_id;
1543 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1544 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1545 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1546 return result;
1547 }
1548
1549
1550 static void
1551 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1552 {
1553 LLVMValueRef gs_next_vertex;
1554 LLVMValueRef can_emit;
1555 int idx;
1556 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1557
1558 assert(stream == 0);
1559
1560 /* Write vertex attribute values to GSVS ring */
1561 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1562 ctx->gs_next_vertex,
1563 "");
1564
1565 /* If this thread has already emitted the declared maximum number of
1566 * vertices, kill it: excessive vertex emissions are not supposed to
1567 * have any effect, and GS threads have no externally observable
1568 * effects other than emitting vertices.
1569 */
1570 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1571 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
1572 ac_build_kill_if_false(&ctx->ac, can_emit);
1573
1574 /* loop num outputs */
1575 idx = 0;
1576 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1577 LLVMValueRef *out_ptr = &addrs[i * 4];
1578 int length = 4;
1579 int slot = idx;
1580 int slot_inc = 1;
1581
1582 if (!(ctx->output_mask & (1ull << i)))
1583 continue;
1584
1585 if (i == VARYING_SLOT_CLIP_DIST0) {
1586 /* pack clip and cull into a single set of slots */
1587 length = ctx->num_output_clips + ctx->num_output_culls;
1588 if (length > 4)
1589 slot_inc = 2;
1590 }
1591 for (unsigned j = 0; j < length; j++) {
1592 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1593 out_ptr[j], "");
1594 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
1595 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1596 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1597
1598 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1599
1600 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
1601 out_val, 1,
1602 voffset, ctx->gs2vs_offset, 0,
1603 1, 1, true, true);
1604 }
1605 idx += slot_inc;
1606 }
1607
1608 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1609 ctx->ac.i32_1, "");
1610 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
1611
1612 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
1613 }
1614
1615 static void
1616 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1617 {
1618 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1619 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1620 }
1621
1622 static LLVMValueRef
1623 load_tess_coord(struct ac_shader_abi *abi)
1624 {
1625 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1626
1627 LLVMValueRef coord[4] = {
1628 ctx->tes_u,
1629 ctx->tes_v,
1630 ctx->ac.f32_0,
1631 ctx->ac.f32_0,
1632 };
1633
1634 if (ctx->tes_primitive_mode == GL_TRIANGLES)
1635 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1636 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1637
1638 return ac_build_gather_values(&ctx->ac, coord, 3);
1639 }
1640
1641 static LLVMValueRef
1642 load_patch_vertices_in(struct ac_shader_abi *abi)
1643 {
1644 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1645 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1646 }
1647
1648
1649 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1650 {
1651 return abi->base_vertex;
1652 }
1653
1654 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1655 LLVMValueRef buffer_ptr, bool write)
1656 {
1657 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1658 LLVMValueRef result;
1659
1660 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1661
1662 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1663 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1664
1665 return result;
1666 }
1667
1668 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1669 {
1670 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1671 LLVMValueRef result;
1672
1673 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1674
1675 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1676 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1677
1678 return result;
1679 }
1680
1681 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1682 unsigned descriptor_set,
1683 unsigned base_index,
1684 unsigned constant_index,
1685 LLVMValueRef index,
1686 enum ac_descriptor_type desc_type,
1687 bool image, bool write)
1688 {
1689 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1690 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1691 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1692 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1693 unsigned offset = binding->offset;
1694 unsigned stride = binding->size;
1695 unsigned type_size;
1696 LLVMBuilderRef builder = ctx->ac.builder;
1697 LLVMTypeRef type;
1698
1699 assert(base_index < layout->binding_count);
1700
1701 switch (desc_type) {
1702 case AC_DESC_IMAGE:
1703 type = ctx->ac.v8i32;
1704 type_size = 32;
1705 break;
1706 case AC_DESC_FMASK:
1707 type = ctx->ac.v8i32;
1708 offset += 32;
1709 type_size = 32;
1710 break;
1711 case AC_DESC_SAMPLER:
1712 type = ctx->ac.v4i32;
1713 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
1714 offset += 64;
1715
1716 type_size = 16;
1717 break;
1718 case AC_DESC_BUFFER:
1719 type = ctx->ac.v4i32;
1720 type_size = 16;
1721 break;
1722 default:
1723 unreachable("invalid desc_type\n");
1724 }
1725
1726 offset += constant_index * stride;
1727
1728 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1729 (!index || binding->immutable_samplers_equal)) {
1730 if (binding->immutable_samplers_equal)
1731 constant_index = 0;
1732
1733 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1734
1735 LLVMValueRef constants[] = {
1736 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1737 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1738 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1739 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1740 };
1741 return ac_build_gather_values(&ctx->ac, constants, 4);
1742 }
1743
1744 assert(stride % type_size == 0);
1745
1746 if (!index)
1747 index = ctx->ac.i32_0;
1748
1749 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1750
1751 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
1752 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
1753
1754 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1755 }
1756
1757
1758 static void
1759 handle_vs_input_decl(struct radv_shader_context *ctx,
1760 struct nir_variable *variable)
1761 {
1762 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
1763 LLVMValueRef t_offset;
1764 LLVMValueRef t_list;
1765 LLVMValueRef input;
1766 LLVMValueRef buffer_index;
1767 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
1768 int idx = variable->data.location;
1769 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1770 uint8_t input_usage_mask =
1771 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
1772 unsigned num_channels = util_last_bit(input_usage_mask);
1773
1774 variable->data.driver_location = idx * 4;
1775
1776 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
1777 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
1778 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
1779 ctx->abi.start_instance, "");
1780 if (ctx->options->key.vs.as_ls) {
1781 ctx->shader_info->vs.vgpr_comp_cnt =
1782 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
1783 } else {
1784 ctx->shader_info->vs.vgpr_comp_cnt =
1785 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
1786 }
1787 } else
1788 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
1789 ctx->abi.base_vertex, "");
1790 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
1791
1792 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1793
1794 input = ac_build_buffer_load_format(&ctx->ac, t_list,
1795 buffer_index,
1796 ctx->ac.i32_0,
1797 num_channels, false, true);
1798
1799 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
1800
1801 for (unsigned chan = 0; chan < 4; chan++) {
1802 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1803 ctx->inputs[ac_llvm_reg_index_soa(idx, chan)] =
1804 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
1805 input, llvm_chan, ""));
1806 }
1807 }
1808 }
1809
1810 static void interp_fs_input(struct radv_shader_context *ctx,
1811 unsigned attr,
1812 LLVMValueRef interp_param,
1813 LLVMValueRef prim_mask,
1814 LLVMValueRef result[4])
1815 {
1816 LLVMValueRef attr_number;
1817 unsigned chan;
1818 LLVMValueRef i, j;
1819 bool interp = interp_param != NULL;
1820
1821 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
1822
1823 /* fs.constant returns the param from the middle vertex, so it's not
1824 * really useful for flat shading. It's meant to be used for custom
1825 * interpolation (but the intrinsic can't fetch from the other two
1826 * vertices).
1827 *
1828 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1829 * to do the right thing. The only reason we use fs.constant is that
1830 * fs.interp cannot be used on integers, because they can be equal
1831 * to NaN.
1832 */
1833 if (interp) {
1834 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1835 ctx->ac.v2f32, "");
1836
1837 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1838 ctx->ac.i32_0, "");
1839 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1840 ctx->ac.i32_1, "");
1841 }
1842
1843 for (chan = 0; chan < 4; chan++) {
1844 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1845
1846 if (interp) {
1847 result[chan] = ac_build_fs_interp(&ctx->ac,
1848 llvm_chan,
1849 attr_number,
1850 prim_mask, i, j);
1851 } else {
1852 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
1853 LLVMConstInt(ctx->ac.i32, 2, false),
1854 llvm_chan,
1855 attr_number,
1856 prim_mask);
1857 }
1858 }
1859 }
1860
1861 static void
1862 handle_fs_input_decl(struct radv_shader_context *ctx,
1863 struct nir_variable *variable)
1864 {
1865 int idx = variable->data.location;
1866 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1867 LLVMValueRef interp;
1868
1869 variable->data.driver_location = idx * 4;
1870 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
1871
1872 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
1873 unsigned interp_type;
1874 if (variable->data.sample)
1875 interp_type = INTERP_SAMPLE;
1876 else if (variable->data.centroid)
1877 interp_type = INTERP_CENTROID;
1878 else
1879 interp_type = INTERP_CENTER;
1880
1881 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
1882 } else
1883 interp = NULL;
1884
1885 for (unsigned i = 0; i < attrib_count; ++i)
1886 ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
1887
1888 }
1889
1890 static void
1891 handle_vs_inputs(struct radv_shader_context *ctx,
1892 struct nir_shader *nir) {
1893 nir_foreach_variable(variable, &nir->inputs)
1894 handle_vs_input_decl(ctx, variable);
1895 }
1896
1897 static void
1898 prepare_interp_optimize(struct radv_shader_context *ctx,
1899 struct nir_shader *nir)
1900 {
1901 if (!ctx->options->key.fs.multisample)
1902 return;
1903
1904 bool uses_center = false;
1905 bool uses_centroid = false;
1906 nir_foreach_variable(variable, &nir->inputs) {
1907 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
1908 variable->data.sample)
1909 continue;
1910
1911 if (variable->data.centroid)
1912 uses_centroid = true;
1913 else
1914 uses_center = true;
1915 }
1916
1917 if (uses_center && uses_centroid) {
1918 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
1919 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
1920 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
1921 }
1922 }
1923
1924 static void
1925 handle_fs_inputs(struct radv_shader_context *ctx,
1926 struct nir_shader *nir)
1927 {
1928 prepare_interp_optimize(ctx, nir);
1929
1930 nir_foreach_variable(variable, &nir->inputs)
1931 handle_fs_input_decl(ctx, variable);
1932
1933 unsigned index = 0;
1934
1935 if (ctx->shader_info->info.ps.uses_input_attachments ||
1936 ctx->shader_info->info.needs_multiview_view_index)
1937 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
1938
1939 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
1940 LLVMValueRef interp_param;
1941 LLVMValueRef *inputs = ctx->inputs +ac_llvm_reg_index_soa(i, 0);
1942
1943 if (!(ctx->input_mask & (1ull << i)))
1944 continue;
1945
1946 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
1947 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
1948 interp_param = *inputs;
1949 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
1950 inputs);
1951
1952 if (!interp_param)
1953 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
1954 ++index;
1955 } else if (i == VARYING_SLOT_POS) {
1956 for(int i = 0; i < 3; ++i)
1957 inputs[i] = ctx->abi.frag_pos[i];
1958
1959 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
1960 ctx->abi.frag_pos[3]);
1961 }
1962 }
1963 ctx->shader_info->fs.num_interp = index;
1964 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
1965
1966 if (ctx->shader_info->info.needs_multiview_view_index)
1967 ctx->abi.view_index = ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
1968 }
1969
1970 static void
1971 scan_shader_output_decl(struct radv_shader_context *ctx,
1972 struct nir_variable *variable,
1973 struct nir_shader *shader,
1974 gl_shader_stage stage)
1975 {
1976 int idx = variable->data.location + variable->data.index;
1977 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1978 uint64_t mask_attribs;
1979
1980 variable->data.driver_location = idx * 4;
1981
1982 /* tess ctrl has it's own load/store paths for outputs */
1983 if (stage == MESA_SHADER_TESS_CTRL)
1984 return;
1985
1986 mask_attribs = ((1ull << attrib_count) - 1) << idx;
1987 if (stage == MESA_SHADER_VERTEX ||
1988 stage == MESA_SHADER_TESS_EVAL ||
1989 stage == MESA_SHADER_GEOMETRY) {
1990 if (idx == VARYING_SLOT_CLIP_DIST0) {
1991 int length = shader->info.clip_distance_array_size +
1992 shader->info.cull_distance_array_size;
1993 if (stage == MESA_SHADER_VERTEX) {
1994 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
1995 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
1996 }
1997 if (stage == MESA_SHADER_TESS_EVAL) {
1998 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
1999 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2000 }
2001
2002 if (length > 4)
2003 attrib_count = 2;
2004 else
2005 attrib_count = 1;
2006 mask_attribs = 1ull << idx;
2007 }
2008 }
2009
2010 ctx->output_mask |= mask_attribs;
2011 }
2012
2013
2014 /* Initialize arguments for the shader export intrinsic */
2015 static void
2016 si_llvm_init_export_args(struct radv_shader_context *ctx,
2017 LLVMValueRef *values,
2018 unsigned enabled_channels,
2019 unsigned target,
2020 struct ac_export_args *args)
2021 {
2022 /* Specify the channels that are enabled. */
2023 args->enabled_channels = enabled_channels;
2024
2025 /* Specify whether the EXEC mask represents the valid mask */
2026 args->valid_mask = 0;
2027
2028 /* Specify whether this is the last export */
2029 args->done = 0;
2030
2031 /* Specify the target we are exporting */
2032 args->target = target;
2033
2034 args->compr = false;
2035 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2036 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2037 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2038 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2039
2040 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
2041 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2042 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2043 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2044 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2045 unsigned chan;
2046
2047 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2048 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2049 unsigned bits, bool hi) = NULL;
2050
2051 switch(col_format) {
2052 case V_028714_SPI_SHADER_ZERO:
2053 args->enabled_channels = 0; /* writemask */
2054 args->target = V_008DFC_SQ_EXP_NULL;
2055 break;
2056
2057 case V_028714_SPI_SHADER_32_R:
2058 args->enabled_channels = 1;
2059 args->out[0] = values[0];
2060 break;
2061
2062 case V_028714_SPI_SHADER_32_GR:
2063 args->enabled_channels = 0x3;
2064 args->out[0] = values[0];
2065 args->out[1] = values[1];
2066 break;
2067
2068 case V_028714_SPI_SHADER_32_AR:
2069 args->enabled_channels = 0x9;
2070 args->out[0] = values[0];
2071 args->out[3] = values[3];
2072 break;
2073
2074 case V_028714_SPI_SHADER_FP16_ABGR:
2075 args->enabled_channels = 0x5;
2076 packf = ac_build_cvt_pkrtz_f16;
2077 break;
2078
2079 case V_028714_SPI_SHADER_UNORM16_ABGR:
2080 args->enabled_channels = 0x5;
2081 packf = ac_build_cvt_pknorm_u16;
2082 break;
2083
2084 case V_028714_SPI_SHADER_SNORM16_ABGR:
2085 args->enabled_channels = 0x5;
2086 packf = ac_build_cvt_pknorm_i16;
2087 break;
2088
2089 case V_028714_SPI_SHADER_UINT16_ABGR:
2090 args->enabled_channels = 0x5;
2091 packi = ac_build_cvt_pk_u16;
2092 break;
2093
2094 case V_028714_SPI_SHADER_SINT16_ABGR:
2095 args->enabled_channels = 0x5;
2096 packi = ac_build_cvt_pk_i16;
2097 break;
2098
2099 default:
2100 case V_028714_SPI_SHADER_32_ABGR:
2101 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2102 break;
2103 }
2104
2105 /* Pack f16 or norm_i16/u16. */
2106 if (packf) {
2107 for (chan = 0; chan < 2; chan++) {
2108 LLVMValueRef pack_args[2] = {
2109 values[2 * chan],
2110 values[2 * chan + 1]
2111 };
2112 LLVMValueRef packed;
2113
2114 packed = packf(&ctx->ac, pack_args);
2115 args->out[chan] = ac_to_float(&ctx->ac, packed);
2116 }
2117 args->compr = 1; /* COMPR flag */
2118 }
2119
2120 /* Pack i16/u16. */
2121 if (packi) {
2122 for (chan = 0; chan < 2; chan++) {
2123 LLVMValueRef pack_args[2] = {
2124 ac_to_integer(&ctx->ac, values[2 * chan]),
2125 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2126 };
2127 LLVMValueRef packed;
2128
2129 packed = packi(&ctx->ac, pack_args,
2130 is_int8 ? 8 : is_int10 ? 10 : 16,
2131 chan == 1);
2132 args->out[chan] = ac_to_float(&ctx->ac, packed);
2133 }
2134 args->compr = 1; /* COMPR flag */
2135 }
2136 return;
2137 }
2138
2139 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2140
2141 for (unsigned i = 0; i < 4; ++i) {
2142 if (!(args->enabled_channels & (1 << i)))
2143 continue;
2144
2145 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2146 }
2147 }
2148
2149 static void
2150 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2151 LLVMValueRef *values, unsigned enabled_channels)
2152 {
2153 struct ac_export_args args;
2154
2155 si_llvm_init_export_args(ctx, values, enabled_channels,
2156 V_008DFC_SQ_EXP_PARAM + index, &args);
2157 ac_build_export(&ctx->ac, &args);
2158 }
2159
2160 static LLVMValueRef
2161 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2162 {
2163 LLVMValueRef output =
2164 ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2165
2166 return LLVMBuildLoad(ctx->ac.builder, output, "");
2167 }
2168
2169 static void
2170 handle_vs_outputs_post(struct radv_shader_context *ctx,
2171 bool export_prim_id,
2172 struct radv_vs_output_info *outinfo)
2173 {
2174 uint32_t param_count = 0;
2175 unsigned target;
2176 unsigned pos_idx, num_pos_exports = 0;
2177 struct ac_export_args args, pos_args[4] = {};
2178 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2179 int i;
2180
2181 if (ctx->options->key.has_multiview_view_index) {
2182 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2183 if(!*tmp_out) {
2184 for(unsigned i = 0; i < 4; ++i)
2185 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2186 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2187 }
2188
2189 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2190 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2191 }
2192
2193 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2194 sizeof(outinfo->vs_output_param_offset));
2195
2196 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
2197 LLVMValueRef slots[8];
2198 unsigned j;
2199
2200 if (outinfo->cull_dist_mask)
2201 outinfo->cull_dist_mask <<= ctx->num_output_clips;
2202
2203 i = VARYING_SLOT_CLIP_DIST0;
2204 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
2205 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2206
2207 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
2208 slots[i] = LLVMGetUndef(ctx->ac.f32);
2209
2210 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
2211 target = V_008DFC_SQ_EXP_POS + 3;
2212 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
2213 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2214 &args, sizeof(args));
2215 }
2216
2217 target = V_008DFC_SQ_EXP_POS + 2;
2218 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
2219 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2220 &args, sizeof(args));
2221
2222 }
2223
2224 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
2225 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
2226 for (unsigned j = 0; j < 4; j++)
2227 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
2228 }
2229 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
2230
2231 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
2232 outinfo->writes_pointsize = true;
2233 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
2234 }
2235
2236 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
2237 outinfo->writes_layer = true;
2238 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
2239 }
2240
2241 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
2242 outinfo->writes_viewport_index = true;
2243 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
2244 }
2245
2246 if (outinfo->writes_pointsize ||
2247 outinfo->writes_layer ||
2248 outinfo->writes_viewport_index) {
2249 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2250 (outinfo->writes_layer == true ? 4 : 0));
2251 pos_args[1].valid_mask = 0;
2252 pos_args[1].done = 0;
2253 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2254 pos_args[1].compr = 0;
2255 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2256 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2257 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2258 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2259
2260 if (outinfo->writes_pointsize == true)
2261 pos_args[1].out[0] = psize_value;
2262 if (outinfo->writes_layer == true)
2263 pos_args[1].out[2] = layer_value;
2264 if (outinfo->writes_viewport_index == true) {
2265 if (ctx->options->chip_class >= GFX9) {
2266 /* GFX9 has the layer in out.z[10:0] and the viewport
2267 * index in out.z[19:16].
2268 */
2269 LLVMValueRef v = viewport_index_value;
2270 v = ac_to_integer(&ctx->ac, v);
2271 v = LLVMBuildShl(ctx->ac.builder, v,
2272 LLVMConstInt(ctx->ac.i32, 16, false),
2273 "");
2274 v = LLVMBuildOr(ctx->ac.builder, v,
2275 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2276
2277 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2278 pos_args[1].enabled_channels |= 1 << 2;
2279 } else {
2280 pos_args[1].out[3] = viewport_index_value;
2281 pos_args[1].enabled_channels |= 1 << 3;
2282 }
2283 }
2284 }
2285 for (i = 0; i < 4; i++) {
2286 if (pos_args[i].out[0])
2287 num_pos_exports++;
2288 }
2289
2290 pos_idx = 0;
2291 for (i = 0; i < 4; i++) {
2292 if (!pos_args[i].out[0])
2293 continue;
2294
2295 /* Specify the target we are exporting */
2296 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2297 if (pos_idx == num_pos_exports)
2298 pos_args[i].done = 1;
2299 ac_build_export(&ctx->ac, &pos_args[i]);
2300 }
2301
2302 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2303 LLVMValueRef values[4];
2304 if (!(ctx->output_mask & (1ull << i)))
2305 continue;
2306
2307 if (i != VARYING_SLOT_LAYER &&
2308 i != VARYING_SLOT_PRIMITIVE_ID &&
2309 i < VARYING_SLOT_VAR0)
2310 continue;
2311
2312 for (unsigned j = 0; j < 4; j++)
2313 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2314
2315 unsigned output_usage_mask;
2316
2317 if (ctx->stage == MESA_SHADER_VERTEX &&
2318 !ctx->is_gs_copy_shader) {
2319 output_usage_mask =
2320 ctx->shader_info->info.vs.output_usage_mask[i];
2321 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2322 output_usage_mask =
2323 ctx->shader_info->info.tes.output_usage_mask[i];
2324 } else {
2325 /* Enable all channels for the GS copy shader because
2326 * we don't know the output usage mask currently.
2327 */
2328 output_usage_mask = 0xf;
2329 }
2330
2331 radv_export_param(ctx, param_count, values, output_usage_mask);
2332
2333 outinfo->vs_output_param_offset[i] = param_count++;
2334 }
2335
2336 if (export_prim_id) {
2337 LLVMValueRef values[4];
2338
2339 values[0] = ctx->vs_prim_id;
2340 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
2341 ctx->shader_info->vs.vgpr_comp_cnt);
2342 for (unsigned j = 1; j < 4; j++)
2343 values[j] = ctx->ac.f32_0;
2344
2345 radv_export_param(ctx, param_count, values, 0xf);
2346
2347 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2348 outinfo->export_prim_id = true;
2349 }
2350
2351 outinfo->pos_exports = num_pos_exports;
2352 outinfo->param_exports = param_count;
2353 }
2354
2355 static void
2356 handle_es_outputs_post(struct radv_shader_context *ctx,
2357 struct radv_es_output_info *outinfo)
2358 {
2359 int j;
2360 uint64_t max_output_written = 0;
2361 LLVMValueRef lds_base = NULL;
2362
2363 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2364 int param_index;
2365 int length = 4;
2366
2367 if (!(ctx->output_mask & (1ull << i)))
2368 continue;
2369
2370 if (i == VARYING_SLOT_CLIP_DIST0)
2371 length = ctx->num_output_clips + ctx->num_output_culls;
2372
2373 param_index = shader_io_get_unique_index(i);
2374
2375 max_output_written = MAX2(param_index + (length > 4), max_output_written);
2376 }
2377
2378 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
2379
2380 if (ctx->ac.chip_class >= GFX9) {
2381 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2382 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2383 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2384 LLVMConstInt(ctx->ac.i32, 24, false),
2385 LLVMConstInt(ctx->ac.i32, 4, false), false);
2386 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2387 LLVMBuildMul(ctx->ac.builder, wave_idx,
2388 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
2389 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2390 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2391 }
2392
2393 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2394 LLVMValueRef dw_addr = NULL;
2395 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2396 int param_index;
2397 int length = 4;
2398
2399 if (!(ctx->output_mask & (1ull << i)))
2400 continue;
2401
2402 if (i == VARYING_SLOT_CLIP_DIST0)
2403 length = ctx->num_output_clips + ctx->num_output_culls;
2404
2405 param_index = shader_io_get_unique_index(i);
2406
2407 if (lds_base) {
2408 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2409 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2410 "");
2411 }
2412 for (j = 0; j < length; j++) {
2413 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2414 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2415
2416 if (ctx->ac.chip_class >= GFX9) {
2417 ac_lds_store(&ctx->ac, dw_addr,
2418 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2419 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2420 } else {
2421 ac_build_buffer_store_dword(&ctx->ac,
2422 ctx->esgs_ring,
2423 out_val, 1,
2424 NULL, ctx->es2gs_offset,
2425 (4 * param_index + j) * 4,
2426 1, 1, true, true);
2427 }
2428 }
2429 }
2430 }
2431
2432 static void
2433 handle_ls_outputs_post(struct radv_shader_context *ctx)
2434 {
2435 LLVMValueRef vertex_id = ctx->rel_auto_id;
2436 LLVMValueRef vertex_dw_stride = ac_unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
2437 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2438 vertex_dw_stride, "");
2439
2440 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2441 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2442 int length = 4;
2443
2444 if (!(ctx->output_mask & (1ull << i)))
2445 continue;
2446
2447 if (i == VARYING_SLOT_CLIP_DIST0)
2448 length = ctx->num_output_clips + ctx->num_output_culls;
2449 int param = shader_io_get_unique_index(i);
2450 mark_tess_output(ctx, false, param, 1);
2451 if (length > 4)
2452 mark_tess_output(ctx, false, param + 1, 1);
2453 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2454 LLVMConstInt(ctx->ac.i32, param * 4, false),
2455 "");
2456 for (unsigned j = 0; j < length; j++) {
2457 ac_lds_store(&ctx->ac, dw_addr,
2458 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2459 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2460 }
2461 }
2462 }
2463
2464 struct ac_build_if_state
2465 {
2466 struct radv_shader_context *ctx;
2467 LLVMValueRef condition;
2468 LLVMBasicBlockRef entry_block;
2469 LLVMBasicBlockRef true_block;
2470 LLVMBasicBlockRef false_block;
2471 LLVMBasicBlockRef merge_block;
2472 };
2473
2474 static LLVMBasicBlockRef
2475 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
2476 {
2477 LLVMBasicBlockRef current_block;
2478 LLVMBasicBlockRef next_block;
2479 LLVMBasicBlockRef new_block;
2480
2481 /* get current basic block */
2482 current_block = LLVMGetInsertBlock(ctx->ac.builder);
2483
2484 /* chqeck if there's another block after this one */
2485 next_block = LLVMGetNextBasicBlock(current_block);
2486 if (next_block) {
2487 /* insert the new block before the next block */
2488 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
2489 }
2490 else {
2491 /* append new block after current block */
2492 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
2493 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
2494 }
2495 return new_block;
2496 }
2497
2498 static void
2499 ac_nir_build_if(struct ac_build_if_state *ifthen,
2500 struct radv_shader_context *ctx,
2501 LLVMValueRef condition)
2502 {
2503 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
2504
2505 memset(ifthen, 0, sizeof *ifthen);
2506 ifthen->ctx = ctx;
2507 ifthen->condition = condition;
2508 ifthen->entry_block = block;
2509
2510 /* create endif/merge basic block for the phi functions */
2511 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
2512
2513 /* create/insert true_block before merge_block */
2514 ifthen->true_block =
2515 LLVMInsertBasicBlockInContext(ctx->context,
2516 ifthen->merge_block,
2517 "if-true-block");
2518
2519 /* successive code goes into the true block */
2520 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
2521 }
2522
2523 /**
2524 * End a conditional.
2525 */
2526 static void
2527 ac_nir_build_endif(struct ac_build_if_state *ifthen)
2528 {
2529 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
2530
2531 /* Insert branch to the merge block from current block */
2532 LLVMBuildBr(builder, ifthen->merge_block);
2533
2534 /*
2535 * Now patch in the various branch instructions.
2536 */
2537
2538 /* Insert the conditional branch instruction at the end of entry_block */
2539 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
2540 if (ifthen->false_block) {
2541 /* we have an else clause */
2542 LLVMBuildCondBr(builder, ifthen->condition,
2543 ifthen->true_block, ifthen->false_block);
2544 }
2545 else {
2546 /* no else clause */
2547 LLVMBuildCondBr(builder, ifthen->condition,
2548 ifthen->true_block, ifthen->merge_block);
2549 }
2550
2551 /* Resume building code at end of the ifthen->merge_block */
2552 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
2553 }
2554
2555 static void
2556 write_tess_factors(struct radv_shader_context *ctx)
2557 {
2558 unsigned stride, outer_comps, inner_comps;
2559 struct ac_build_if_state if_ctx, inner_if_ctx;
2560 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
2561 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
2562 unsigned tess_inner_index = 0, tess_outer_index;
2563 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
2564 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2565 int i;
2566 ac_emit_barrier(&ctx->ac, ctx->stage);
2567
2568 switch (ctx->options->key.tcs.primitive_mode) {
2569 case GL_ISOLINES:
2570 stride = 2;
2571 outer_comps = 2;
2572 inner_comps = 0;
2573 break;
2574 case GL_TRIANGLES:
2575 stride = 4;
2576 outer_comps = 3;
2577 inner_comps = 1;
2578 break;
2579 case GL_QUADS:
2580 stride = 6;
2581 outer_comps = 4;
2582 inner_comps = 2;
2583 break;
2584 default:
2585 return;
2586 }
2587
2588 ac_nir_build_if(&if_ctx, ctx,
2589 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2590 invocation_id, ctx->ac.i32_0, ""));
2591
2592 lds_base = get_tcs_out_current_patch_data_offset(ctx);
2593
2594 if (inner_comps) {
2595 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2596 mark_tess_output(ctx, true, tess_inner_index, 1);
2597 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2598 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
2599 }
2600
2601 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2602 mark_tess_output(ctx, true, tess_outer_index, 1);
2603 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2604 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
2605
2606 for (i = 0; i < 4; i++) {
2607 inner[i] = LLVMGetUndef(ctx->ac.i32);
2608 outer[i] = LLVMGetUndef(ctx->ac.i32);
2609 }
2610
2611 // LINES reverseal
2612 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
2613 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
2614 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2615 ctx->ac.i32_1, "");
2616 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
2617 } else {
2618 for (i = 0; i < outer_comps; i++) {
2619 outer[i] = out[i] =
2620 ac_lds_load(&ctx->ac, lds_outer);
2621 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2622 ctx->ac.i32_1, "");
2623 }
2624 for (i = 0; i < inner_comps; i++) {
2625 inner[i] = out[outer_comps+i] =
2626 ac_lds_load(&ctx->ac, lds_inner);
2627 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
2628 ctx->ac.i32_1, "");
2629 }
2630 }
2631
2632 /* Convert the outputs to vectors for stores. */
2633 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
2634 vec1 = NULL;
2635
2636 if (stride > 4)
2637 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
2638
2639
2640 buffer = ctx->hs_ring_tess_factor;
2641 tf_base = ctx->tess_factor_offset;
2642 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2643 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
2644 unsigned tf_offset = 0;
2645
2646 if (ctx->options->chip_class <= VI) {
2647 ac_nir_build_if(&inner_if_ctx, ctx,
2648 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2649 rel_patch_id, ctx->ac.i32_0, ""));
2650
2651 /* Store the dynamic HS control word. */
2652 ac_build_buffer_store_dword(&ctx->ac, buffer,
2653 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
2654 1, ctx->ac.i32_0, tf_base,
2655 0, 1, 0, true, false);
2656 tf_offset += 4;
2657
2658 ac_nir_build_endif(&inner_if_ctx);
2659 }
2660
2661 /* Store the tessellation factors. */
2662 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2663 MIN2(stride, 4), byteoffset, tf_base,
2664 tf_offset, 1, 0, true, false);
2665 if (vec1)
2666 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2667 stride - 4, byteoffset, tf_base,
2668 16 + tf_offset, 1, 0, true, false);
2669
2670 //store to offchip for TES to read - only if TES reads them
2671 if (ctx->options->key.tcs.tes_reads_tess_factors) {
2672 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
2673 LLVMValueRef tf_inner_offset;
2674 unsigned param_outer, param_inner;
2675
2676 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2677 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
2678 LLVMConstInt(ctx->ac.i32, param_outer, 0));
2679
2680 outer_vec = ac_build_gather_values(&ctx->ac, outer,
2681 util_next_power_of_two(outer_comps));
2682
2683 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
2684 outer_comps, tf_outer_offset,
2685 ctx->oc_lds, 0, 1, 0, true, false);
2686 if (inner_comps) {
2687 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2688 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
2689 LLVMConstInt(ctx->ac.i32, param_inner, 0));
2690
2691 inner_vec = inner_comps == 1 ? inner[0] :
2692 ac_build_gather_values(&ctx->ac, inner, inner_comps);
2693 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
2694 inner_comps, tf_inner_offset,
2695 ctx->oc_lds, 0, 1, 0, true, false);
2696 }
2697 }
2698 ac_nir_build_endif(&if_ctx);
2699 }
2700
2701 static void
2702 handle_tcs_outputs_post(struct radv_shader_context *ctx)
2703 {
2704 write_tess_factors(ctx);
2705 }
2706
2707 static bool
2708 si_export_mrt_color(struct radv_shader_context *ctx,
2709 LLVMValueRef *color, unsigned index,
2710 struct ac_export_args *args)
2711 {
2712 /* Export */
2713 si_llvm_init_export_args(ctx, color, 0xf,
2714 V_008DFC_SQ_EXP_MRT + index, args);
2715 if (!args->enabled_channels)
2716 return false; /* unnecessary NULL export */
2717
2718 return true;
2719 }
2720
2721 static void
2722 radv_export_mrt_z(struct radv_shader_context *ctx,
2723 LLVMValueRef depth, LLVMValueRef stencil,
2724 LLVMValueRef samplemask)
2725 {
2726 struct ac_export_args args;
2727
2728 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
2729
2730 ac_build_export(&ctx->ac, &args);
2731 }
2732
2733 static void
2734 handle_fs_outputs_post(struct radv_shader_context *ctx)
2735 {
2736 unsigned index = 0;
2737 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2738 struct ac_export_args color_args[8];
2739
2740 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2741 LLVMValueRef values[4];
2742
2743 if (!(ctx->output_mask & (1ull << i)))
2744 continue;
2745
2746 if (i < FRAG_RESULT_DATA0)
2747 continue;
2748
2749 for (unsigned j = 0; j < 4; j++)
2750 values[j] = ac_to_float(&ctx->ac,
2751 radv_load_output(ctx, i, j));
2752
2753 bool ret = si_export_mrt_color(ctx, values,
2754 i - FRAG_RESULT_DATA0,
2755 &color_args[index]);
2756 if (ret)
2757 index++;
2758 }
2759
2760 /* Process depth, stencil, samplemask. */
2761 if (ctx->shader_info->info.ps.writes_z) {
2762 depth = ac_to_float(&ctx->ac,
2763 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
2764 }
2765 if (ctx->shader_info->info.ps.writes_stencil) {
2766 stencil = ac_to_float(&ctx->ac,
2767 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
2768 }
2769 if (ctx->shader_info->info.ps.writes_sample_mask) {
2770 samplemask = ac_to_float(&ctx->ac,
2771 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
2772 }
2773
2774 /* Set the DONE bit on last non-null color export only if Z isn't
2775 * exported.
2776 */
2777 if (index > 0 &&
2778 !ctx->shader_info->info.ps.writes_z &&
2779 !ctx->shader_info->info.ps.writes_stencil &&
2780 !ctx->shader_info->info.ps.writes_sample_mask) {
2781 unsigned last = index - 1;
2782
2783 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
2784 color_args[last].done = 1; /* DONE bit */
2785 }
2786
2787 /* Export PS outputs. */
2788 for (unsigned i = 0; i < index; i++)
2789 ac_build_export(&ctx->ac, &color_args[i]);
2790
2791 if (depth || stencil || samplemask)
2792 radv_export_mrt_z(ctx, depth, stencil, samplemask);
2793 else if (!index)
2794 ac_build_export_null(&ctx->ac);
2795 }
2796
2797 static void
2798 emit_gs_epilogue(struct radv_shader_context *ctx)
2799 {
2800 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
2801 }
2802
2803 static void
2804 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
2805 LLVMValueRef *addrs)
2806 {
2807 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2808
2809 switch (ctx->stage) {
2810 case MESA_SHADER_VERTEX:
2811 if (ctx->options->key.vs.as_ls)
2812 handle_ls_outputs_post(ctx);
2813 else if (ctx->options->key.vs.as_es)
2814 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
2815 else
2816 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
2817 &ctx->shader_info->vs.outinfo);
2818 break;
2819 case MESA_SHADER_FRAGMENT:
2820 handle_fs_outputs_post(ctx);
2821 break;
2822 case MESA_SHADER_GEOMETRY:
2823 emit_gs_epilogue(ctx);
2824 break;
2825 case MESA_SHADER_TESS_CTRL:
2826 handle_tcs_outputs_post(ctx);
2827 break;
2828 case MESA_SHADER_TESS_EVAL:
2829 if (ctx->options->key.tes.as_es)
2830 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
2831 else
2832 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
2833 &ctx->shader_info->tes.outinfo);
2834 break;
2835 default:
2836 break;
2837 }
2838 }
2839
2840 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
2841 {
2842 LLVMPassManagerRef passmgr;
2843 /* Create the pass manager */
2844 passmgr = LLVMCreateFunctionPassManagerForModule(
2845 ctx->ac.module);
2846
2847 /* This pass should eliminate all the load and store instructions */
2848 LLVMAddPromoteMemoryToRegisterPass(passmgr);
2849
2850 /* Add some optimization passes */
2851 LLVMAddScalarReplAggregatesPass(passmgr);
2852 LLVMAddLICMPass(passmgr);
2853 LLVMAddAggressiveDCEPass(passmgr);
2854 LLVMAddCFGSimplificationPass(passmgr);
2855 LLVMAddInstructionCombiningPass(passmgr);
2856
2857 /* Run the pass */
2858 LLVMInitializeFunctionPassManager(passmgr);
2859 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
2860 LLVMFinalizeFunctionPassManager(passmgr);
2861
2862 LLVMDisposeBuilder(ctx->ac.builder);
2863 LLVMDisposePassManager(passmgr);
2864
2865 ac_llvm_context_dispose(&ctx->ac);
2866 }
2867
2868 static void
2869 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
2870 {
2871 struct radv_vs_output_info *outinfo;
2872
2873 switch (ctx->stage) {
2874 case MESA_SHADER_FRAGMENT:
2875 case MESA_SHADER_COMPUTE:
2876 case MESA_SHADER_TESS_CTRL:
2877 case MESA_SHADER_GEOMETRY:
2878 return;
2879 case MESA_SHADER_VERTEX:
2880 if (ctx->options->key.vs.as_ls ||
2881 ctx->options->key.vs.as_es)
2882 return;
2883 outinfo = &ctx->shader_info->vs.outinfo;
2884 break;
2885 case MESA_SHADER_TESS_EVAL:
2886 if (ctx->options->key.vs.as_es)
2887 return;
2888 outinfo = &ctx->shader_info->tes.outinfo;
2889 break;
2890 default:
2891 unreachable("Unhandled shader type");
2892 }
2893
2894 ac_optimize_vs_outputs(&ctx->ac,
2895 ctx->main_function,
2896 outinfo->vs_output_param_offset,
2897 VARYING_SLOT_MAX,
2898 &outinfo->param_exports);
2899 }
2900
2901 static void
2902 ac_setup_rings(struct radv_shader_context *ctx)
2903 {
2904 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
2905 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
2906 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
2907 }
2908
2909 if (ctx->is_gs_copy_shader) {
2910 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
2911 }
2912 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2913 LLVMValueRef tmp;
2914 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
2915 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
2916
2917 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
2918
2919 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
2920 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
2921 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
2922 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
2923 }
2924
2925 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
2926 ctx->stage == MESA_SHADER_TESS_EVAL) {
2927 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
2928 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
2929 }
2930 }
2931
2932 static unsigned
2933 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
2934 const struct nir_shader *nir)
2935 {
2936 switch (nir->info.stage) {
2937 case MESA_SHADER_TESS_CTRL:
2938 return chip_class >= CIK ? 128 : 64;
2939 case MESA_SHADER_GEOMETRY:
2940 return chip_class >= GFX9 ? 128 : 64;
2941 case MESA_SHADER_COMPUTE:
2942 break;
2943 default:
2944 return 0;
2945 }
2946
2947 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
2948 nir->info.cs.local_size[1] *
2949 nir->info.cs.local_size[2];
2950 return max_workgroup_size;
2951 }
2952
2953 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
2954 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
2955 {
2956 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2957 LLVMConstInt(ctx->ac.i32, 8, false),
2958 LLVMConstInt(ctx->ac.i32, 8, false), false);
2959 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
2960 ctx->ac.i32_0, "");
2961 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
2962 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
2963 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
2964 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
2965 }
2966
2967 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
2968 {
2969 for(int i = 5; i >= 0; --i) {
2970 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
2971 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
2972 LLVMConstInt(ctx->ac.i32, 16, false), false);
2973 }
2974
2975 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2976 LLVMConstInt(ctx->ac.i32, 16, false),
2977 LLVMConstInt(ctx->ac.i32, 8, false), false);
2978 }
2979
2980
2981 static
2982 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
2983 struct nir_shader *const *shaders,
2984 int shader_count,
2985 struct radv_shader_variant_info *shader_info,
2986 const struct radv_nir_compiler_options *options)
2987 {
2988 struct radv_shader_context ctx = {0};
2989 unsigned i;
2990 ctx.options = options;
2991 ctx.shader_info = shader_info;
2992 ctx.context = LLVMContextCreate();
2993
2994 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
2995 options->family);
2996 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
2997 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
2998
2999 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
3000 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
3001 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
3002 LLVMDisposeTargetData(data_layout);
3003 LLVMDisposeMessage(data_layout_str);
3004
3005 enum ac_float_mode float_mode =
3006 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3007 AC_FLOAT_MODE_DEFAULT;
3008
3009 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3010
3011 memset(shader_info, 0, sizeof(*shader_info));
3012
3013 for(int i = 0; i < shader_count; ++i)
3014 radv_nir_shader_info_pass(shaders[i], options, &shader_info->info);
3015
3016 for (i = 0; i < RADV_UD_MAX_SETS; i++)
3017 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
3018 for (i = 0; i < AC_UD_MAX_UD; i++)
3019 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
3020
3021 ctx.max_workgroup_size = 0;
3022 for (int i = 0; i < shader_count; ++i) {
3023 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3024 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
3025 shaders[i]));
3026 }
3027
3028 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
3029 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
3030
3031 ctx.abi.inputs = &ctx.inputs[0];
3032 ctx.abi.emit_outputs = handle_shader_outputs_post;
3033 ctx.abi.emit_vertex = visit_emit_vertex;
3034 ctx.abi.load_ubo = radv_load_ubo;
3035 ctx.abi.load_ssbo = radv_load_ssbo;
3036 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3037 ctx.abi.load_resource = radv_load_resource;
3038 ctx.abi.clamp_shadow_reference = false;
3039
3040 if (shader_count >= 2)
3041 ac_init_exec_full_mask(&ctx.ac);
3042
3043 if (ctx.ac.chip_class == GFX9 &&
3044 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3045 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3046
3047 for(int i = 0; i < shader_count; ++i) {
3048 ctx.stage = shaders[i]->info.stage;
3049 ctx.output_mask = 0;
3050 ctx.tess_outputs_written = 0;
3051 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
3052 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
3053
3054 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3055 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
3056 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
3057 ctx.abi.load_inputs = load_gs_input;
3058 ctx.abi.emit_primitive = visit_end_primitive;
3059 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3060 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
3061 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
3062 ctx.abi.load_tess_varyings = load_tcs_varyings;
3063 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3064 ctx.abi.store_tcs_outputs = store_tcs_output;
3065 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3066 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
3067 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
3068 ctx.abi.load_tess_varyings = load_tes_input;
3069 ctx.abi.load_tess_coord = load_tess_coord;
3070 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3071 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3072 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
3073 if (shader_info->info.vs.needs_instance_id) {
3074 if (ctx.options->key.vs.as_ls) {
3075 ctx.shader_info->vs.vgpr_comp_cnt =
3076 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
3077 } else {
3078 ctx.shader_info->vs.vgpr_comp_cnt =
3079 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
3080 }
3081 }
3082 ctx.abi.load_base_vertex = radv_load_base_vertex;
3083 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
3084 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
3085 ctx.abi.lookup_interp_param = lookup_interp_param;
3086 ctx.abi.load_sample_position = load_sample_position;
3087 ctx.abi.load_sample_mask_in = load_sample_mask_in;
3088 ctx.abi.emit_kill = radv_emit_kill;
3089 }
3090
3091 if (i)
3092 ac_emit_barrier(&ctx.ac, ctx.stage);
3093
3094 ac_setup_rings(&ctx);
3095
3096 LLVMBasicBlockRef merge_block;
3097 if (shader_count >= 2) {
3098 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
3099 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3100 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3101
3102 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
3103 LLVMConstInt(ctx.ac.i32, 8 * i, false),
3104 LLVMConstInt(ctx.ac.i32, 8, false), false);
3105 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
3106 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
3107 thread_id, count, "");
3108 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
3109
3110 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
3111 }
3112
3113 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
3114 handle_fs_inputs(&ctx, shaders[i]);
3115 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
3116 handle_vs_inputs(&ctx, shaders[i]);
3117 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
3118 prepare_gs_input_vgprs(&ctx);
3119
3120 nir_foreach_variable(variable, &shaders[i]->outputs)
3121 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
3122
3123 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
3124
3125 if (shader_count >= 2) {
3126 LLVMBuildBr(ctx.ac.builder, merge_block);
3127 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
3128 }
3129
3130 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3131 unsigned addclip = shaders[i]->info.clip_distance_array_size +
3132 shaders[i]->info.cull_distance_array_size > 4;
3133 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
3134 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
3135 shaders[i]->info.gs.vertices_out;
3136 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3137 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
3138 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
3139 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
3140 shader_info->vs.outputs_written = ctx.tess_outputs_written;
3141 }
3142 }
3143
3144 LLVMBuildRetVoid(ctx.ac.builder);
3145
3146 if (options->dump_preoptir)
3147 ac_dump_module(ctx.ac.module);
3148
3149 ac_llvm_finalize_module(&ctx);
3150
3151 if (shader_count == 1)
3152 ac_nir_eliminate_const_vs_outputs(&ctx);
3153
3154 if (options->dump_shader) {
3155 ctx.shader_info->private_mem_vgprs =
3156 ac_count_scratch_private_memory(ctx.main_function);
3157 }
3158
3159 return ctx.ac.module;
3160 }
3161
3162 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
3163 {
3164 unsigned *retval = (unsigned *)context;
3165 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
3166 char *description = LLVMGetDiagInfoDescription(di);
3167
3168 if (severity == LLVMDSError) {
3169 *retval = 1;
3170 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
3171 description);
3172 }
3173
3174 LLVMDisposeMessage(description);
3175 }
3176
3177 static unsigned ac_llvm_compile(LLVMModuleRef M,
3178 struct ac_shader_binary *binary,
3179 LLVMTargetMachineRef tm)
3180 {
3181 unsigned retval = 0;
3182 char *err;
3183 LLVMContextRef llvm_ctx;
3184 LLVMMemoryBufferRef out_buffer;
3185 unsigned buffer_size;
3186 const char *buffer_data;
3187 LLVMBool mem_err;
3188
3189 /* Setup Diagnostic Handler*/
3190 llvm_ctx = LLVMGetModuleContext(M);
3191
3192 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
3193 &retval);
3194
3195 /* Compile IR*/
3196 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
3197 &err, &out_buffer);
3198
3199 /* Process Errors/Warnings */
3200 if (mem_err) {
3201 fprintf(stderr, "%s: %s", __FUNCTION__, err);
3202 free(err);
3203 retval = 1;
3204 goto out;
3205 }
3206
3207 /* Extract Shader Code*/
3208 buffer_size = LLVMGetBufferSize(out_buffer);
3209 buffer_data = LLVMGetBufferStart(out_buffer);
3210
3211 ac_elf_read(buffer_data, buffer_size, binary);
3212
3213 /* Clean up */
3214 LLVMDisposeMemoryBuffer(out_buffer);
3215
3216 out:
3217 return retval;
3218 }
3219
3220 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
3221 LLVMModuleRef llvm_module,
3222 struct ac_shader_binary *binary,
3223 struct ac_shader_config *config,
3224 struct radv_shader_variant_info *shader_info,
3225 gl_shader_stage stage,
3226 const struct radv_nir_compiler_options *options)
3227 {
3228 if (options->dump_shader)
3229 ac_dump_module(llvm_module);
3230
3231 memset(binary, 0, sizeof(*binary));
3232 int v = ac_llvm_compile(llvm_module, binary, tm);
3233 if (v) {
3234 fprintf(stderr, "compile failed\n");
3235 }
3236
3237 if (options->dump_shader)
3238 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
3239
3240 ac_shader_binary_read_config(binary, config, 0, options->supports_spill);
3241
3242 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
3243 LLVMDisposeModule(llvm_module);
3244 LLVMContextDispose(ctx);
3245
3246 if (stage == MESA_SHADER_FRAGMENT) {
3247 shader_info->num_input_vgprs = 0;
3248 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
3249 shader_info->num_input_vgprs += 2;
3250 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
3251 shader_info->num_input_vgprs += 2;
3252 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
3253 shader_info->num_input_vgprs += 2;
3254 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
3255 shader_info->num_input_vgprs += 3;
3256 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
3257 shader_info->num_input_vgprs += 2;
3258 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
3259 shader_info->num_input_vgprs += 2;
3260 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
3261 shader_info->num_input_vgprs += 2;
3262 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
3263 shader_info->num_input_vgprs += 1;
3264 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
3265 shader_info->num_input_vgprs += 1;
3266 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
3267 shader_info->num_input_vgprs += 1;
3268 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
3269 shader_info->num_input_vgprs += 1;
3270 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
3271 shader_info->num_input_vgprs += 1;
3272 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
3273 shader_info->num_input_vgprs += 1;
3274 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
3275 shader_info->num_input_vgprs += 1;
3276 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
3277 shader_info->num_input_vgprs += 1;
3278 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
3279 shader_info->num_input_vgprs += 1;
3280 }
3281 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
3282
3283 /* +3 for scratch wave offset and VCC */
3284 config->num_sgprs = MAX2(config->num_sgprs,
3285 shader_info->num_input_sgprs + 3);
3286
3287 /* Enable 64-bit and 16-bit denormals, because there is no performance
3288 * cost.
3289 *
3290 * If denormals are enabled, all floating-point output modifiers are
3291 * ignored.
3292 *
3293 * Don't enable denormals for 32-bit floats, because:
3294 * - Floating-point output modifiers would be ignored by the hw.
3295 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3296 * have to stop using those.
3297 * - SI & CI would be very slow.
3298 */
3299 config->float_mode |= V_00B028_FP_64_DENORMS;
3300 }
3301
3302 static void
3303 ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct radv_nir_compiler_options *options)
3304 {
3305 switch (nir->info.stage) {
3306 case MESA_SHADER_COMPUTE:
3307 for (int i = 0; i < 3; ++i)
3308 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
3309 break;
3310 case MESA_SHADER_FRAGMENT:
3311 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
3312 break;
3313 case MESA_SHADER_GEOMETRY:
3314 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
3315 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
3316 shader_info->gs.output_prim = nir->info.gs.output_primitive;
3317 shader_info->gs.invocations = nir->info.gs.invocations;
3318 break;
3319 case MESA_SHADER_TESS_EVAL:
3320 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
3321 shader_info->tes.spacing = nir->info.tess.spacing;
3322 shader_info->tes.ccw = nir->info.tess.ccw;
3323 shader_info->tes.point_mode = nir->info.tess.point_mode;
3324 shader_info->tes.as_es = options->key.tes.as_es;
3325 break;
3326 case MESA_SHADER_TESS_CTRL:
3327 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
3328 break;
3329 case MESA_SHADER_VERTEX:
3330 shader_info->vs.as_es = options->key.vs.as_es;
3331 shader_info->vs.as_ls = options->key.vs.as_ls;
3332 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3333 if (options->key.vs.as_ls)
3334 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
3335 break;
3336 default:
3337 break;
3338 }
3339 }
3340
3341 void
3342 radv_compile_nir_shader(LLVMTargetMachineRef tm,
3343 struct ac_shader_binary *binary,
3344 struct ac_shader_config *config,
3345 struct radv_shader_variant_info *shader_info,
3346 struct nir_shader *const *nir,
3347 int nir_count,
3348 const struct radv_nir_compiler_options *options)
3349 {
3350
3351 LLVMModuleRef llvm_module;
3352
3353 llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
3354 options);
3355
3356 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info,
3357 nir[0]->info.stage, options);
3358
3359 for (int i = 0; i < nir_count; ++i)
3360 ac_fill_shader_info(shader_info, nir[i], options);
3361
3362 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3363 if (options->chip_class == GFX9) {
3364 if (nir_count == 2 &&
3365 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
3366 shader_info->gs.es_type = nir[0]->info.stage;
3367 }
3368 }
3369 }
3370
3371 static void
3372 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
3373 {
3374 LLVMValueRef vtx_offset =
3375 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
3376 LLVMConstInt(ctx->ac.i32, 4, false), "");
3377 int idx = 0;
3378
3379 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3380 int length = 4;
3381 int slot = idx;
3382 int slot_inc = 1;
3383 if (!(ctx->output_mask & (1ull << i)))
3384 continue;
3385
3386 if (i == VARYING_SLOT_CLIP_DIST0) {
3387 /* unpack clip and cull from a single set of slots */
3388 length = ctx->num_output_clips + ctx->num_output_culls;
3389 if (length > 4)
3390 slot_inc = 2;
3391 }
3392
3393 for (unsigned j = 0; j < length; j++) {
3394 LLVMValueRef value, soffset;
3395
3396 soffset = LLVMConstInt(ctx->ac.i32,
3397 (slot * 4 + j) *
3398 ctx->gs_max_out_vertices * 16 * 4, false);
3399
3400 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
3401 1, ctx->ac.i32_0,
3402 vtx_offset, soffset,
3403 0, 1, 1, true, false);
3404
3405 LLVMBuildStore(ctx->ac.builder,
3406 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3407 }
3408 idx += slot_inc;
3409 }
3410 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
3411 }
3412
3413 void
3414 radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
3415 struct nir_shader *geom_shader,
3416 struct ac_shader_binary *binary,
3417 struct ac_shader_config *config,
3418 struct radv_shader_variant_info *shader_info,
3419 const struct radv_nir_compiler_options *options)
3420 {
3421 struct radv_shader_context ctx = {0};
3422 ctx.context = LLVMContextCreate();
3423 ctx.options = options;
3424 ctx.shader_info = shader_info;
3425
3426 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3427 options->family);
3428 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3429
3430 ctx.is_gs_copy_shader = true;
3431 LLVMSetTarget(ctx.ac.module, "amdgcn--");
3432
3433 enum ac_float_mode float_mode =
3434 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3435 AC_FLOAT_MODE_DEFAULT;
3436
3437 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3438 ctx.stage = MESA_SHADER_VERTEX;
3439
3440 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
3441
3442 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
3443 ac_setup_rings(&ctx);
3444
3445 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
3446 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
3447
3448 nir_foreach_variable(variable, &geom_shader->outputs) {
3449 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
3450 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
3451 variable, MESA_SHADER_VERTEX);
3452 }
3453
3454 ac_gs_copy_shader_emit(&ctx);
3455
3456 LLVMBuildRetVoid(ctx.ac.builder);
3457
3458 ac_llvm_finalize_module(&ctx);
3459
3460 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
3461 MESA_SHADER_VERTEX, options);
3462 }