2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "radv_shader_args.h"
32 #include "radv_debug.h"
36 #include "ac_binary.h"
37 #include "ac_llvm_util.h"
38 #include "ac_llvm_build.h"
39 #include "ac_shader_abi.h"
40 #include "ac_shader_util.h"
41 #include "ac_exp_param.h"
43 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 struct radv_shader_context
{
46 struct ac_llvm_context ac
;
47 const struct nir_shader
*shader
;
48 struct ac_shader_abi abi
;
49 const struct radv_shader_args
*args
;
51 gl_shader_stage stage
;
53 unsigned max_workgroup_size
;
54 LLVMContextRef context
;
55 LLVMValueRef main_function
;
57 LLVMValueRef descriptor_sets
[MAX_SETS
];
59 LLVMValueRef ring_offsets
;
61 LLVMValueRef rel_auto_id
;
63 LLVMValueRef gs_wave_id
;
64 LLVMValueRef gs_vtx_offset
[6];
66 LLVMValueRef esgs_ring
;
67 LLVMValueRef gsvs_ring
[4];
68 LLVMValueRef hs_ring_tess_offchip
;
69 LLVMValueRef hs_ring_tess_factor
;
71 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
75 LLVMValueRef gs_next_vertex
[4];
76 LLVMValueRef gs_curprim_verts
[4];
77 LLVMValueRef gs_generated_prims
[4];
78 LLVMValueRef gs_ngg_emit
;
79 LLVMValueRef gs_ngg_scratch
;
81 uint32_t tcs_num_inputs
;
82 uint32_t tcs_num_patches
;
84 LLVMValueRef vertexptr
; /* GFX10 only */
87 struct radv_shader_output_values
{
88 LLVMValueRef values
[4];
94 static inline struct radv_shader_context
*
95 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
97 struct radv_shader_context
*ctx
= NULL
;
98 return container_of(abi
, ctx
, abi
);
101 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
103 switch (ctx
->stage
) {
104 case MESA_SHADER_TESS_CTRL
:
105 return ac_unpack_param(&ctx
->ac
,
106 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_rel_ids
),
108 case MESA_SHADER_TESS_EVAL
:
109 return ac_get_arg(&ctx
->ac
, ctx
->args
->tes_rel_patch_id
);
112 unreachable("Illegal stage");
116 /* Tessellation shaders pass outputs to the next shader using LDS.
118 * LS outputs = TCS inputs
119 * TCS outputs = TES inputs
122 * - TCS inputs for patch 0
123 * - TCS inputs for patch 1
124 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
126 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
127 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
128 * - TCS outputs for patch 1
129 * - Per-patch TCS outputs for patch 1
130 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
131 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
134 * All three shaders VS(LS), TCS, TES share the same LDS space.
137 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
139 assert(ctx
->stage
== MESA_SHADER_TESS_CTRL
);
140 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
141 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
143 input_patch_size
/= 4;
144 return LLVMConstInt(ctx
->ac
.i32
, input_patch_size
, false);
148 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
150 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
151 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
152 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
153 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
154 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
155 output_patch_size
/= 4;
156 return LLVMConstInt(ctx
->ac
.i32
, output_patch_size
, false);
160 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
162 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
163 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
164 output_vertex_size
/= 4;
165 return LLVMConstInt(ctx
->ac
.i32
, output_vertex_size
, false);
169 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
171 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
172 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
173 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
174 uint32_t output_patch0_offset
= input_patch_size
;
175 unsigned num_patches
= ctx
->tcs_num_patches
;
177 output_patch0_offset
*= num_patches
;
178 output_patch0_offset
/= 4;
179 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
183 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
185 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
186 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
187 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
188 uint32_t output_patch0_offset
= input_patch_size
;
190 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
191 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
192 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
193 unsigned num_patches
= ctx
->tcs_num_patches
;
195 output_patch0_offset
*= num_patches
;
196 output_patch0_offset
+= pervertex_output_patch_size
;
197 output_patch0_offset
/= 4;
198 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
202 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
204 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
205 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
207 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
211 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
213 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
214 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
215 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
217 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
222 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
224 LLVMValueRef patch0_patch_data_offset
=
225 get_tcs_out_patch0_patch_data_offset(ctx
);
226 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
227 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
229 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
230 patch0_patch_data_offset
);
234 create_llvm_function(struct ac_llvm_context
*ctx
, LLVMModuleRef module
,
235 LLVMBuilderRef builder
,
236 const struct ac_shader_args
*args
,
237 enum ac_llvm_calling_convention convention
,
238 unsigned max_workgroup_size
,
239 const struct radv_nir_compiler_options
*options
)
241 LLVMValueRef main_function
=
242 ac_build_main(args
, ctx
, convention
, "main", ctx
->voidt
, module
);
244 if (options
->address32_hi
) {
245 ac_llvm_add_target_dep_function_attr(main_function
,
246 "amdgpu-32bit-address-high-bits",
247 options
->address32_hi
);
250 ac_llvm_set_workgroup_size(main_function
, max_workgroup_size
);
252 return main_function
;
256 load_descriptor_sets(struct radv_shader_context
*ctx
)
258 uint32_t mask
= ctx
->args
->shader_info
->desc_set_used_mask
;
259 if (ctx
->args
->shader_info
->need_indirect_descriptor_sets
) {
260 LLVMValueRef desc_sets
=
261 ac_get_arg(&ctx
->ac
, ctx
->args
->descriptor_sets
[0]);
263 int i
= u_bit_scan(&mask
);
265 ctx
->descriptor_sets
[i
] =
266 ac_build_load_to_sgpr(&ctx
->ac
, desc_sets
,
267 LLVMConstInt(ctx
->ac
.i32
, i
, false));
272 int i
= u_bit_scan(&mask
);
274 ctx
->descriptor_sets
[i
] =
275 ac_get_arg(&ctx
->ac
, ctx
->args
->descriptor_sets
[i
]);
280 static enum ac_llvm_calling_convention
281 get_llvm_calling_convention(LLVMValueRef func
, gl_shader_stage stage
)
284 case MESA_SHADER_VERTEX
:
285 case MESA_SHADER_TESS_EVAL
:
286 return AC_LLVM_AMDGPU_VS
;
288 case MESA_SHADER_GEOMETRY
:
289 return AC_LLVM_AMDGPU_GS
;
291 case MESA_SHADER_TESS_CTRL
:
292 return AC_LLVM_AMDGPU_HS
;
294 case MESA_SHADER_FRAGMENT
:
295 return AC_LLVM_AMDGPU_PS
;
297 case MESA_SHADER_COMPUTE
:
298 return AC_LLVM_AMDGPU_CS
;
301 unreachable("Unhandle shader type");
305 /* Returns whether the stage is a stage that can be directly before the GS */
306 static bool is_pre_gs_stage(gl_shader_stage stage
)
308 return stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_TESS_EVAL
;
311 static void create_function(struct radv_shader_context
*ctx
,
312 gl_shader_stage stage
,
313 bool has_previous_stage
)
315 if (ctx
->ac
.chip_class
>= GFX10
) {
316 if (is_pre_gs_stage(stage
) && ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
317 /* On GFX10, VS is merged into GS for NGG. */
318 stage
= MESA_SHADER_GEOMETRY
;
319 has_previous_stage
= true;
323 ctx
->main_function
= create_llvm_function(
324 &ctx
->ac
, ctx
->ac
.module
, ctx
->ac
.builder
, &ctx
->args
->ac
,
325 get_llvm_calling_convention(ctx
->main_function
, stage
),
326 ctx
->max_workgroup_size
,
329 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
330 LLVMPointerType(ctx
->ac
.i8
, AC_ADDR_SPACE_CONST
),
331 NULL
, 0, AC_FUNC_ATTR_READNONE
);
332 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
333 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
335 load_descriptor_sets(ctx
);
337 if (stage
== MESA_SHADER_TESS_CTRL
||
338 (stage
== MESA_SHADER_VERTEX
&& ctx
->args
->options
->key
.vs_common_out
.as_ls
) ||
339 /* GFX9 has the ESGS ring buffer in LDS. */
340 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
341 ac_declare_lds_as_pointer(&ctx
->ac
);
348 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
349 unsigned desc_set
, unsigned binding
)
351 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
352 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
353 struct radv_pipeline_layout
*pipeline_layout
= ctx
->args
->options
->layout
;
354 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
355 unsigned base_offset
= layout
->binding
[binding
].offset
;
356 LLVMValueRef offset
, stride
;
358 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
359 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
360 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
361 layout
->binding
[binding
].dynamic_offset_offset
;
362 desc_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.push_constants
);
363 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
364 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
366 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
368 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
370 if (layout
->binding
[binding
].type
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
371 offset
= ac_build_imad(&ctx
->ac
, index
, stride
, offset
);
374 desc_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, desc_ptr
, &offset
, 1, "");
375 desc_ptr
= ac_cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
376 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
378 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
379 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
380 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
381 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
382 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
384 if (ctx
->ac
.chip_class
>= GFX10
) {
385 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
386 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
387 S_008F0C_RESOURCE_LEVEL(1);
389 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
390 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
393 LLVMValueRef desc_components
[4] = {
394 LLVMBuildPtrToInt(ctx
->ac
.builder
, desc_ptr
, ctx
->ac
.intptr
, ""),
395 LLVMConstInt(ctx
->ac
.i32
, S_008F04_BASE_ADDRESS_HI(ctx
->args
->options
->address32_hi
), false),
396 /* High limit to support variable sizes. */
397 LLVMConstInt(ctx
->ac
.i32
, 0xffffffff, false),
398 LLVMConstInt(ctx
->ac
.i32
, desc_type
, false),
401 return ac_build_gather_values(&ctx
->ac
, desc_components
, 4);
408 /* The offchip buffer layout for TCS->TES is
410 * - attribute 0 of patch 0 vertex 0
411 * - attribute 0 of patch 0 vertex 1
412 * - attribute 0 of patch 0 vertex 2
414 * - attribute 0 of patch 1 vertex 0
415 * - attribute 0 of patch 1 vertex 1
417 * - attribute 1 of patch 0 vertex 0
418 * - attribute 1 of patch 0 vertex 1
420 * - per patch attribute 0 of patch 0
421 * - per patch attribute 0 of patch 1
424 * Note that every attribute has 4 components.
426 static LLVMValueRef
get_non_vertex_index_offset(struct radv_shader_context
*ctx
)
428 uint32_t num_patches
= ctx
->tcs_num_patches
;
429 uint32_t num_tcs_outputs
;
430 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
431 num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
433 num_tcs_outputs
= ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
435 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
436 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
438 return LLVMConstInt(ctx
->ac
.i32
, pervertex_output_patch_size
* num_patches
, false);
441 static LLVMValueRef
calc_param_stride(struct radv_shader_context
*ctx
,
442 LLVMValueRef vertex_index
)
444 LLVMValueRef param_stride
;
446 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.tess
.tcs_vertices_out
* ctx
->tcs_num_patches
, false);
448 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_num_patches
, false);
452 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
453 LLVMValueRef vertex_index
,
454 LLVMValueRef param_index
)
456 LLVMValueRef base_addr
;
457 LLVMValueRef param_stride
, constant16
;
458 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
459 LLVMValueRef vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.tess
.tcs_vertices_out
, false);
460 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
461 param_stride
= calc_param_stride(ctx
, vertex_index
);
463 base_addr
= ac_build_imad(&ctx
->ac
, rel_patch_id
,
464 vertices_per_patch
, vertex_index
);
466 base_addr
= rel_patch_id
;
469 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
470 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
471 param_stride
, ""), "");
473 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
476 LLVMValueRef patch_data_offset
= get_non_vertex_index_offset(ctx
);
478 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
479 patch_data_offset
, "");
484 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
486 unsigned const_index
,
488 LLVMValueRef vertex_index
,
489 LLVMValueRef indir_index
)
491 LLVMValueRef param_index
;
494 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
497 if (const_index
&& !is_compact
)
498 param
+= const_index
;
499 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
501 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
505 get_dw_address(struct radv_shader_context
*ctx
,
506 LLVMValueRef dw_addr
,
508 unsigned const_index
,
509 bool compact_const_index
,
510 LLVMValueRef vertex_index
,
512 LLVMValueRef indir_index
)
517 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
518 LLVMBuildMul(ctx
->ac
.builder
,
524 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
525 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
526 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
527 else if (const_index
&& !compact_const_index
)
528 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
529 LLVMConstInt(ctx
->ac
.i32
, const_index
* 4, false), "");
531 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
532 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
534 if (const_index
&& compact_const_index
)
535 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
536 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
541 load_tcs_varyings(struct ac_shader_abi
*abi
,
543 LLVMValueRef vertex_index
,
544 LLVMValueRef indir_index
,
545 unsigned const_index
,
547 unsigned driver_location
,
549 unsigned num_components
,
554 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
555 LLVMValueRef dw_addr
, stride
;
556 LLVMValueRef value
[4], result
;
557 unsigned param
= shader_io_get_unique_index(location
);
560 uint32_t input_vertex_size
= (ctx
->tcs_num_inputs
* 16) / 4;
561 stride
= LLVMConstInt(ctx
->ac
.i32
, input_vertex_size
, false);
562 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
565 stride
= get_tcs_out_vertex_stride(ctx
);
566 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
568 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
573 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
576 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
577 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
578 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
581 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
586 store_tcs_output(struct ac_shader_abi
*abi
,
587 const nir_variable
*var
,
588 LLVMValueRef vertex_index
,
589 LLVMValueRef param_index
,
590 unsigned const_index
,
594 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
595 const unsigned location
= var
->data
.location
;
596 unsigned component
= var
->data
.location_frac
;
597 const bool is_patch
= var
->data
.patch
;
598 const bool is_compact
= var
->data
.compact
;
599 LLVMValueRef dw_addr
;
600 LLVMValueRef stride
= NULL
;
601 LLVMValueRef buf_addr
= NULL
;
602 LLVMValueRef oc_lds
= ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
);
604 bool store_lds
= true;
607 if (!(ctx
->shader
->info
.patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
610 if (!(ctx
->shader
->info
.outputs_read
& (1ULL << location
)))
614 param
= shader_io_get_unique_index(location
);
615 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
616 const_index
+= component
;
619 if (const_index
>= 4) {
626 stride
= get_tcs_out_vertex_stride(ctx
);
627 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
629 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
632 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
634 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
635 vertex_index
, param_index
);
637 bool is_tess_factor
= false;
638 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
639 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
640 is_tess_factor
= true;
642 unsigned base
= is_compact
? const_index
: 0;
643 for (unsigned chan
= 0; chan
< 8; chan
++) {
644 if (!(writemask
& (1 << chan
)))
646 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
647 value
= ac_to_integer(&ctx
->ac
, value
);
648 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
650 if (store_lds
|| is_tess_factor
) {
651 LLVMValueRef dw_addr_chan
=
652 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
653 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
654 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
657 if (!is_tess_factor
&& writemask
!= 0xF)
658 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
660 4 * (base
+ chan
), ac_glc
);
663 if (writemask
== 0xF) {
664 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
671 load_tes_input(struct ac_shader_abi
*abi
,
673 LLVMValueRef vertex_index
,
674 LLVMValueRef param_index
,
675 unsigned const_index
,
677 unsigned driver_location
,
679 unsigned num_components
,
684 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
685 LLVMValueRef buf_addr
;
687 LLVMValueRef oc_lds
= ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
);
688 unsigned param
= shader_io_get_unique_index(location
);
690 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
691 const_index
+= component
;
693 if (const_index
>= 4) {
699 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
700 is_compact
, vertex_index
, param_index
);
702 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
703 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
705 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
706 buf_addr
, oc_lds
, is_compact
? (4 * const_index
) : 0, ac_glc
, true, false);
707 result
= ac_trim_vector(&ctx
->ac
, result
, num_components
);
712 radv_emit_fetch_64bit(struct radv_shader_context
*ctx
,
713 LLVMTypeRef type
, LLVMValueRef a
, LLVMValueRef b
)
715 LLVMValueRef values
[2] = {
716 ac_to_integer(&ctx
->ac
, a
),
717 ac_to_integer(&ctx
->ac
, b
),
719 LLVMValueRef result
= ac_build_gather_values(&ctx
->ac
, values
, 2);
720 return LLVMBuildBitCast(ctx
->ac
.builder
, result
, type
, "");
724 load_gs_input(struct ac_shader_abi
*abi
,
726 unsigned driver_location
,
728 unsigned num_components
,
729 unsigned vertex_index
,
730 unsigned const_index
,
733 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
734 LLVMValueRef vtx_offset
;
735 unsigned param
, vtx_offset_param
;
736 LLVMValueRef value
[4], result
;
738 vtx_offset_param
= vertex_index
;
739 assert(vtx_offset_param
< 6);
740 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
741 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
743 param
= shader_io_get_unique_index(location
);
745 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
746 if (ctx
->ac
.chip_class
>= GFX9
) {
747 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
748 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
749 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
750 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
752 if (ac_get_type_size(type
) == 8) {
753 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
754 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
+ 1, 0), "");
755 LLVMValueRef tmp
= ac_lds_load(&ctx
->ac
, dw_addr
);
757 value
[i
] = radv_emit_fetch_64bit(ctx
, type
, value
[i
], tmp
);
760 LLVMValueRef soffset
=
761 LLVMConstInt(ctx
->ac
.i32
,
762 (param
* 4 + i
+ const_index
) * 256,
765 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
769 0, ac_glc
, true, false);
771 if (ac_get_type_size(type
) == 8) {
772 soffset
= LLVMConstInt(ctx
->ac
.i32
,
773 (param
* 4 + i
+ const_index
+ 1) * 256,
777 ac_build_buffer_load(&ctx
->ac
,
781 0, ac_glc
, true, false);
783 value
[i
] = radv_emit_fetch_64bit(ctx
, type
, value
[i
], tmp
);
787 if (ac_get_type_size(type
) == 2) {
788 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i32
, "");
789 value
[i
] = LLVMBuildTrunc(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i16
, "");
791 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], type
, "");
793 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
794 result
= ac_to_integer(&ctx
->ac
, result
);
799 radv_get_sample_pos_offset(uint32_t num_samples
)
801 uint32_t sample_pos_offset
= 0;
803 switch (num_samples
) {
805 sample_pos_offset
= 1;
808 sample_pos_offset
= 3;
811 sample_pos_offset
= 7;
816 return sample_pos_offset
;
819 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
820 LLVMValueRef sample_id
)
822 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
825 LLVMValueRef index
= LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false);
826 LLVMValueRef ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ctx
->ring_offsets
, &index
, 1, "");
828 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
829 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
831 uint32_t sample_pos_offset
=
832 radv_get_sample_pos_offset(ctx
->args
->options
->key
.fs
.num_samples
);
835 LLVMBuildAdd(ctx
->ac
.builder
, sample_id
,
836 LLVMConstInt(ctx
->ac
.i32
, sample_pos_offset
, false), "");
837 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
843 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
845 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
846 uint8_t log2_ps_iter_samples
;
848 if (ctx
->args
->shader_info
->ps
.force_persample
) {
849 log2_ps_iter_samples
=
850 util_logbase2(ctx
->args
->options
->key
.fs
.num_samples
);
852 log2_ps_iter_samples
= ctx
->args
->options
->key
.fs
.log2_ps_iter_samples
;
855 /* The bit pattern matches that used by fixed function fragment
857 static const uint16_t ps_iter_masks
[] = {
858 0xffff, /* not used */
864 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
866 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
868 LLVMValueRef result
, sample_id
;
869 sample_id
= ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.ancillary
), 8, 4);
870 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
871 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
,
872 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.sample_coverage
), "");
877 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
879 LLVMValueRef vertexidx
,
880 LLVMValueRef
*addrs
);
883 visit_emit_vertex_with_counter(struct ac_shader_abi
*abi
, unsigned stream
,
884 LLVMValueRef vertexidx
, LLVMValueRef
*addrs
)
887 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
889 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
890 gfx10_ngg_gs_emit_vertex(ctx
, stream
, vertexidx
, addrs
);
894 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
895 unsigned output_usage_mask
=
896 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
897 uint8_t output_stream
=
898 ctx
->args
->shader_info
->gs
.output_streams
[i
];
899 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
900 int length
= util_last_bit(output_usage_mask
);
902 if (!(ctx
->output_mask
& (1ull << i
)) ||
903 output_stream
!= stream
)
906 for (unsigned j
= 0; j
< length
; j
++) {
907 if (!(output_usage_mask
& (1 << j
)))
910 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
912 LLVMValueRef voffset
=
913 LLVMConstInt(ctx
->ac
.i32
, offset
*
914 ctx
->shader
->info
.gs
.vertices_out
, false);
918 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, vertexidx
, "");
919 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
921 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
922 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
924 ac_build_buffer_store_dword(&ctx
->ac
,
925 ctx
->gsvs_ring
[stream
],
929 ctx
->args
->gs2vs_offset
),
930 0, ac_glc
| ac_slc
| ac_swizzled
);
934 ac_build_sendmsg(&ctx
->ac
,
935 AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
940 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
942 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
944 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
945 LLVMBuildStore(ctx
->ac
.builder
, ctx
->ac
.i32_0
, ctx
->gs_curprim_verts
[stream
]);
949 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
953 load_tess_coord(struct ac_shader_abi
*abi
)
955 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
957 LLVMValueRef coord
[4] = {
958 ac_get_arg(&ctx
->ac
, ctx
->args
->tes_u
),
959 ac_get_arg(&ctx
->ac
, ctx
->args
->tes_v
),
964 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
)
965 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
966 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
968 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
972 load_patch_vertices_in(struct ac_shader_abi
*abi
)
974 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
975 return LLVMConstInt(ctx
->ac
.i32
, ctx
->args
->options
->key
.tcs
.input_vertices
, false);
979 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
981 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
982 return ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.base_vertex
);
985 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
986 LLVMValueRef buffer_ptr
, bool write
)
988 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
991 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
993 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
994 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
999 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
1001 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1002 LLVMValueRef result
;
1004 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr
)) != LLVMPointerTypeKind
) {
1005 /* Do not load the descriptor for inlined uniform blocks. */
1009 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1011 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1012 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1017 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
1018 unsigned descriptor_set
,
1019 unsigned base_index
,
1020 unsigned constant_index
,
1022 enum ac_descriptor_type desc_type
,
1023 bool image
, bool write
,
1026 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1027 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
1028 struct radv_descriptor_set_layout
*layout
= ctx
->args
->options
->layout
->set
[descriptor_set
].layout
;
1029 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
1030 unsigned offset
= binding
->offset
;
1031 unsigned stride
= binding
->size
;
1033 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1036 assert(base_index
< layout
->binding_count
);
1038 switch (desc_type
) {
1040 type
= ctx
->ac
.v8i32
;
1044 type
= ctx
->ac
.v8i32
;
1048 case AC_DESC_SAMPLER
:
1049 type
= ctx
->ac
.v4i32
;
1050 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
) {
1051 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
1056 case AC_DESC_BUFFER
:
1057 type
= ctx
->ac
.v4i32
;
1060 case AC_DESC_PLANE_0
:
1061 case AC_DESC_PLANE_1
:
1062 case AC_DESC_PLANE_2
:
1063 type
= ctx
->ac
.v8i32
;
1065 offset
+= 32 * (desc_type
- AC_DESC_PLANE_0
);
1068 unreachable("invalid desc_type\n");
1071 offset
+= constant_index
* stride
;
1073 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
1074 (!index
|| binding
->immutable_samplers_equal
)) {
1075 if (binding
->immutable_samplers_equal
)
1078 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
1080 LLVMValueRef constants
[] = {
1081 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
1082 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
1083 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
1084 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
1086 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
1089 assert(stride
% type_size
== 0);
1091 LLVMValueRef adjusted_index
= index
;
1092 if (!adjusted_index
)
1093 adjusted_index
= ctx
->ac
.i32_0
;
1095 adjusted_index
= LLVMBuildMul(builder
, adjusted_index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
1097 LLVMValueRef val_offset
= LLVMConstInt(ctx
->ac
.i32
, offset
, 0);
1098 list
= LLVMBuildGEP(builder
, list
, &val_offset
, 1, "");
1099 list
= LLVMBuildPointerCast(builder
, list
,
1100 ac_array_in_const32_addr_space(type
), "");
1102 LLVMValueRef descriptor
= ac_build_load_to_sgpr(&ctx
->ac
, list
, adjusted_index
);
1104 /* 3 plane formats always have same size and format for plane 1 & 2, so
1105 * use the tail from plane 1 so that we can store only the first 16 bytes
1106 * of the last plane. */
1107 if (desc_type
== AC_DESC_PLANE_2
) {
1108 LLVMValueRef descriptor2
= radv_get_sampler_desc(abi
, descriptor_set
, base_index
, constant_index
, index
, AC_DESC_PLANE_1
,image
, write
, bindless
);
1110 LLVMValueRef components
[8];
1111 for (unsigned i
= 0; i
< 4; ++i
)
1112 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor
, i
);
1114 for (unsigned i
= 4; i
< 8; ++i
)
1115 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor2
, i
);
1116 descriptor
= ac_build_gather_values(&ctx
->ac
, components
, 8);
1122 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1123 * so we may need to fix it up. */
1125 adjust_vertex_fetch_alpha(struct radv_shader_context
*ctx
,
1126 unsigned adjustment
,
1129 if (adjustment
== RADV_ALPHA_ADJUST_NONE
)
1132 LLVMValueRef c30
= LLVMConstInt(ctx
->ac
.i32
, 30, 0);
1134 alpha
= LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1136 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
1137 alpha
= LLVMBuildFPToUI(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
1139 alpha
= ac_to_integer(&ctx
->ac
, alpha
);
1141 /* For the integer-like cases, do a natural sign extension.
1143 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1144 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1147 alpha
= LLVMBuildShl(ctx
->ac
.builder
, alpha
,
1148 adjustment
== RADV_ALPHA_ADJUST_SNORM
?
1149 LLVMConstInt(ctx
->ac
.i32
, 7, 0) : c30
, "");
1150 alpha
= LLVMBuildAShr(ctx
->ac
.builder
, alpha
, c30
, "");
1152 /* Convert back to the right type. */
1153 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
1155 LLVMValueRef neg_one
= LLVMConstReal(ctx
->ac
.f32
, -1.0);
1156 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1157 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, alpha
, neg_one
, "");
1158 alpha
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, alpha
, "");
1159 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
1160 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1163 return LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
1167 radv_fixup_vertex_input_fetches(struct radv_shader_context
*ctx
,
1169 unsigned num_channels
,
1172 LLVMValueRef zero
= is_float
? ctx
->ac
.f32_0
: ctx
->ac
.i32_0
;
1173 LLVMValueRef one
= is_float
? ctx
->ac
.f32_1
: ctx
->ac
.i32_1
;
1174 LLVMValueRef chan
[4];
1176 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMVectorTypeKind
) {
1177 unsigned vec_size
= LLVMGetVectorSize(LLVMTypeOf(value
));
1179 if (num_channels
== 4 && num_channels
== vec_size
)
1182 num_channels
= MIN2(num_channels
, vec_size
);
1184 for (unsigned i
= 0; i
< num_channels
; i
++)
1185 chan
[i
] = ac_llvm_extract_elem(&ctx
->ac
, value
, i
);
1187 assert(num_channels
== 1);
1191 for (unsigned i
= num_channels
; i
< 4; i
++) {
1192 chan
[i
] = i
== 3 ? one
: zero
;
1193 chan
[i
] = ac_to_integer(&ctx
->ac
, chan
[i
]);
1196 return ac_build_gather_values(&ctx
->ac
, chan
, 4);
1200 handle_vs_input_decl(struct radv_shader_context
*ctx
,
1201 struct nir_variable
*variable
)
1203 LLVMValueRef t_list_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->vertex_buffers
);
1204 LLVMValueRef t_offset
;
1205 LLVMValueRef t_list
;
1207 LLVMValueRef buffer_index
;
1208 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
1209 uint8_t input_usage_mask
=
1210 ctx
->args
->shader_info
->vs
.input_usage_mask
[variable
->data
.location
];
1211 unsigned num_input_channels
= util_last_bit(input_usage_mask
);
1213 variable
->data
.driver_location
= variable
->data
.location
* 4;
1215 enum glsl_base_type type
= glsl_get_base_type(variable
->type
);
1216 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
1217 LLVMValueRef output
[4];
1218 unsigned attrib_index
= variable
->data
.location
+ i
- VERT_ATTRIB_GENERIC0
;
1219 unsigned attrib_format
= ctx
->args
->options
->key
.vs
.vertex_attribute_formats
[attrib_index
];
1220 unsigned data_format
= attrib_format
& 0x0f;
1221 unsigned num_format
= (attrib_format
>> 4) & 0x07;
1222 bool is_float
= num_format
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
1223 num_format
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
1225 if (ctx
->args
->options
->key
.vs
.instance_rate_inputs
& (1u << attrib_index
)) {
1226 uint32_t divisor
= ctx
->args
->options
->key
.vs
.instance_rate_divisors
[attrib_index
];
1229 buffer_index
= ctx
->abi
.instance_id
;
1232 buffer_index
= LLVMBuildUDiv(ctx
->ac
.builder
, buffer_index
,
1233 LLVMConstInt(ctx
->ac
.i32
, divisor
, 0), "");
1236 buffer_index
= ctx
->ac
.i32_0
;
1239 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
1240 ac_get_arg(&ctx
->ac
,
1241 ctx
->args
->ac
.start_instance
),\
1244 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
1246 ac_get_arg(&ctx
->ac
,
1247 ctx
->args
->ac
.base_vertex
), "");
1250 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(data_format
);
1252 /* Adjust the number of channels to load based on the vertex
1255 unsigned num_channels
= MIN2(num_input_channels
, vtx_info
->num_channels
);
1256 unsigned attrib_binding
= ctx
->args
->options
->key
.vs
.vertex_attribute_bindings
[attrib_index
];
1257 unsigned attrib_offset
= ctx
->args
->options
->key
.vs
.vertex_attribute_offsets
[attrib_index
];
1258 unsigned attrib_stride
= ctx
->args
->options
->key
.vs
.vertex_attribute_strides
[attrib_index
];
1260 if (ctx
->args
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
1261 /* Always load, at least, 3 channels for formats that
1262 * need to be shuffled because X<->Z.
1264 num_channels
= MAX2(num_channels
, 3);
1267 t_offset
= LLVMConstInt(ctx
->ac
.i32
, attrib_binding
, false);
1268 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
1270 /* Perform per-channel vertex fetch operations if unaligned
1271 * access are detected. Only GFX6 and GFX10 are affected.
1273 bool unaligned_vertex_fetches
= false;
1274 if ((ctx
->ac
.chip_class
== GFX6
|| ctx
->ac
.chip_class
== GFX10
) &&
1275 vtx_info
->chan_format
!= data_format
&&
1276 ((attrib_offset
% vtx_info
->element_size
) ||
1277 (attrib_stride
% vtx_info
->element_size
)))
1278 unaligned_vertex_fetches
= true;
1280 if (unaligned_vertex_fetches
) {
1281 unsigned chan_format
= vtx_info
->chan_format
;
1282 LLVMValueRef values
[4];
1284 assert(ctx
->ac
.chip_class
== GFX6
||
1285 ctx
->ac
.chip_class
== GFX10
);
1287 for (unsigned chan
= 0; chan
< num_channels
; chan
++) {
1288 unsigned chan_offset
= attrib_offset
+ chan
* vtx_info
->chan_byte_size
;
1289 LLVMValueRef chan_index
= buffer_index
;
1291 if (attrib_stride
!= 0 && chan_offset
> attrib_stride
) {
1292 LLVMValueRef buffer_offset
=
1293 LLVMConstInt(ctx
->ac
.i32
,
1294 chan_offset
/ attrib_stride
, false);
1296 chan_index
= LLVMBuildAdd(ctx
->ac
.builder
,
1300 chan_offset
= chan_offset
% attrib_stride
;
1303 values
[chan
] = ac_build_struct_tbuffer_load(&ctx
->ac
, t_list
,
1305 LLVMConstInt(ctx
->ac
.i32
, chan_offset
, false),
1306 ctx
->ac
.i32_0
, ctx
->ac
.i32_0
, 1,
1307 chan_format
, num_format
, 0, true);
1310 input
= ac_build_gather_values(&ctx
->ac
, values
, num_channels
);
1312 if (attrib_stride
!= 0 && attrib_offset
> attrib_stride
) {
1313 LLVMValueRef buffer_offset
=
1314 LLVMConstInt(ctx
->ac
.i32
,
1315 attrib_offset
/ attrib_stride
, false);
1317 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
1321 attrib_offset
= attrib_offset
% attrib_stride
;
1324 input
= ac_build_struct_tbuffer_load(&ctx
->ac
, t_list
,
1326 LLVMConstInt(ctx
->ac
.i32
, attrib_offset
, false),
1327 ctx
->ac
.i32_0
, ctx
->ac
.i32_0
,
1329 data_format
, num_format
, 0, true);
1332 if (ctx
->args
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
1334 c
[0] = ac_llvm_extract_elem(&ctx
->ac
, input
, 2);
1335 c
[1] = ac_llvm_extract_elem(&ctx
->ac
, input
, 1);
1336 c
[2] = ac_llvm_extract_elem(&ctx
->ac
, input
, 0);
1337 c
[3] = ac_llvm_extract_elem(&ctx
->ac
, input
, 3);
1339 input
= ac_build_gather_values(&ctx
->ac
, c
, 4);
1342 input
= radv_fixup_vertex_input_fetches(ctx
, input
, num_channels
,
1345 for (unsigned chan
= 0; chan
< 4; chan
++) {
1346 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
1347 output
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
, input
, llvm_chan
, "");
1348 if (type
== GLSL_TYPE_FLOAT16
) {
1349 output
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f32
, "");
1350 output
[chan
] = LLVMBuildFPTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f16
, "");
1354 unsigned alpha_adjust
= (ctx
->args
->options
->key
.vs
.alpha_adjust
>> (attrib_index
* 2)) & 3;
1355 output
[3] = adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, output
[3]);
1357 for (unsigned chan
= 0; chan
< 4; chan
++) {
1358 output
[chan
] = ac_to_integer(&ctx
->ac
, output
[chan
]);
1359 if (type
== GLSL_TYPE_UINT16
|| type
== GLSL_TYPE_INT16
)
1360 output
[chan
] = LLVMBuildTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.i16
, "");
1362 ctx
->inputs
[ac_llvm_reg_index_soa(variable
->data
.location
+ i
, chan
)] = output
[chan
];
1368 handle_vs_inputs(struct radv_shader_context
*ctx
,
1369 struct nir_shader
*nir
) {
1370 nir_foreach_variable(variable
, &nir
->inputs
)
1371 handle_vs_input_decl(ctx
, variable
);
1375 prepare_interp_optimize(struct radv_shader_context
*ctx
,
1376 struct nir_shader
*nir
)
1378 bool uses_center
= false;
1379 bool uses_centroid
= false;
1380 nir_foreach_variable(variable
, &nir
->inputs
) {
1381 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
1382 variable
->data
.sample
)
1385 if (variable
->data
.centroid
)
1386 uses_centroid
= true;
1391 ctx
->abi
.persp_centroid
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.persp_centroid
);
1392 ctx
->abi
.linear_centroid
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.linear_centroid
);
1394 if (uses_center
&& uses_centroid
) {
1395 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
,
1396 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.prim_mask
),
1398 ctx
->abi
.persp_centroid
=
1399 LLVMBuildSelect(ctx
->ac
.builder
, sel
,
1400 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.persp_center
),
1401 ctx
->abi
.persp_centroid
, "");
1402 ctx
->abi
.linear_centroid
=
1403 LLVMBuildSelect(ctx
->ac
.builder
, sel
,
1404 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.linear_center
),
1405 ctx
->abi
.linear_centroid
, "");
1410 scan_shader_output_decl(struct radv_shader_context
*ctx
,
1411 struct nir_variable
*variable
,
1412 struct nir_shader
*shader
,
1413 gl_shader_stage stage
)
1415 int idx
= variable
->data
.location
+ variable
->data
.index
;
1416 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
1417 uint64_t mask_attribs
;
1419 variable
->data
.driver_location
= idx
* 4;
1421 /* tess ctrl has it's own load/store paths for outputs */
1422 if (stage
== MESA_SHADER_TESS_CTRL
)
1425 if (variable
->data
.compact
) {
1426 unsigned component_count
= variable
->data
.location_frac
+
1427 glsl_get_length(variable
->type
);
1428 attrib_count
= (component_count
+ 3) / 4;
1431 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
1433 ctx
->output_mask
|= mask_attribs
;
1437 /* Initialize arguments for the shader export intrinsic */
1439 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
1440 LLVMValueRef
*values
,
1441 unsigned enabled_channels
,
1443 struct ac_export_args
*args
)
1445 /* Specify the channels that are enabled. */
1446 args
->enabled_channels
= enabled_channels
;
1448 /* Specify whether the EXEC mask represents the valid mask */
1449 args
->valid_mask
= 0;
1451 /* Specify whether this is the last export */
1454 /* Specify the target we are exporting */
1455 args
->target
= target
;
1457 args
->compr
= false;
1458 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
1459 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
1460 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
1461 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
1466 bool is_16bit
= ac_get_type_size(LLVMTypeOf(values
[0])) == 2;
1467 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1468 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
1469 unsigned col_format
= (ctx
->args
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
1470 bool is_int8
= (ctx
->args
->options
->key
.fs
.is_int8
>> index
) & 1;
1471 bool is_int10
= (ctx
->args
->options
->key
.fs
.is_int10
>> index
) & 1;
1474 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
1475 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
1476 unsigned bits
, bool hi
) = NULL
;
1478 switch(col_format
) {
1479 case V_028714_SPI_SHADER_ZERO
:
1480 args
->enabled_channels
= 0; /* writemask */
1481 args
->target
= V_008DFC_SQ_EXP_NULL
;
1484 case V_028714_SPI_SHADER_32_R
:
1485 args
->enabled_channels
= 1;
1486 args
->out
[0] = values
[0];
1489 case V_028714_SPI_SHADER_32_GR
:
1490 args
->enabled_channels
= 0x3;
1491 args
->out
[0] = values
[0];
1492 args
->out
[1] = values
[1];
1495 case V_028714_SPI_SHADER_32_AR
:
1496 if (ctx
->ac
.chip_class
>= GFX10
) {
1497 args
->enabled_channels
= 0x3;
1498 args
->out
[0] = values
[0];
1499 args
->out
[1] = values
[3];
1501 args
->enabled_channels
= 0x9;
1502 args
->out
[0] = values
[0];
1503 args
->out
[3] = values
[3];
1507 case V_028714_SPI_SHADER_FP16_ABGR
:
1508 args
->enabled_channels
= 0x5;
1509 packf
= ac_build_cvt_pkrtz_f16
;
1511 for (unsigned chan
= 0; chan
< 4; chan
++)
1512 values
[chan
] = LLVMBuildFPExt(ctx
->ac
.builder
,
1518 case V_028714_SPI_SHADER_UNORM16_ABGR
:
1519 args
->enabled_channels
= 0x5;
1520 packf
= ac_build_cvt_pknorm_u16
;
1523 case V_028714_SPI_SHADER_SNORM16_ABGR
:
1524 args
->enabled_channels
= 0x5;
1525 packf
= ac_build_cvt_pknorm_i16
;
1528 case V_028714_SPI_SHADER_UINT16_ABGR
:
1529 args
->enabled_channels
= 0x5;
1530 packi
= ac_build_cvt_pk_u16
;
1532 for (unsigned chan
= 0; chan
< 4; chan
++)
1533 values
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
,
1534 ac_to_integer(&ctx
->ac
, values
[chan
]),
1539 case V_028714_SPI_SHADER_SINT16_ABGR
:
1540 args
->enabled_channels
= 0x5;
1541 packi
= ac_build_cvt_pk_i16
;
1543 for (unsigned chan
= 0; chan
< 4; chan
++)
1544 values
[chan
] = LLVMBuildSExt(ctx
->ac
.builder
,
1545 ac_to_integer(&ctx
->ac
, values
[chan
]),
1551 case V_028714_SPI_SHADER_32_ABGR
:
1552 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
1556 /* Pack f16 or norm_i16/u16. */
1558 for (chan
= 0; chan
< 2; chan
++) {
1559 LLVMValueRef pack_args
[2] = {
1561 values
[2 * chan
+ 1]
1563 LLVMValueRef packed
;
1565 packed
= packf(&ctx
->ac
, pack_args
);
1566 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
1568 args
->compr
= 1; /* COMPR flag */
1573 for (chan
= 0; chan
< 2; chan
++) {
1574 LLVMValueRef pack_args
[2] = {
1575 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
1576 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
1578 LLVMValueRef packed
;
1580 packed
= packi(&ctx
->ac
, pack_args
,
1581 is_int8
? 8 : is_int10
? 10 : 16,
1583 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
1585 args
->compr
= 1; /* COMPR flag */
1591 for (unsigned chan
= 0; chan
< 4; chan
++) {
1592 values
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i16
, "");
1593 args
->out
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i32
, "");
1596 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
1598 for (unsigned i
= 0; i
< 4; ++i
)
1599 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
1603 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
1604 LLVMValueRef
*values
, unsigned enabled_channels
)
1606 struct ac_export_args args
;
1608 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
1609 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
1610 ac_build_export(&ctx
->ac
, &args
);
1614 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
1616 LLVMValueRef output
= ctx
->abi
.outputs
[ac_llvm_reg_index_soa(index
, chan
)];
1617 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
1621 radv_emit_stream_output(struct radv_shader_context
*ctx
,
1622 LLVMValueRef
const *so_buffers
,
1623 LLVMValueRef
const *so_write_offsets
,
1624 const struct radv_stream_output
*output
,
1625 struct radv_shader_output_values
*shader_out
)
1627 unsigned num_comps
= util_bitcount(output
->component_mask
);
1628 unsigned buf
= output
->buffer
;
1629 unsigned offset
= output
->offset
;
1631 LLVMValueRef out
[4];
1633 assert(num_comps
&& num_comps
<= 4);
1634 if (!num_comps
|| num_comps
> 4)
1637 /* Get the first component. */
1638 start
= ffs(output
->component_mask
) - 1;
1640 /* Load the output as int. */
1641 for (int i
= 0; i
< num_comps
; i
++) {
1642 out
[i
] = ac_to_integer(&ctx
->ac
, shader_out
->values
[start
+ i
]);
1645 /* Pack the output. */
1646 LLVMValueRef vdata
= NULL
;
1648 switch (num_comps
) {
1649 case 1: /* as i32 */
1652 case 2: /* as v2i32 */
1653 case 3: /* as v4i32 (aligned to 4) */
1654 out
[3] = LLVMGetUndef(ctx
->ac
.i32
);
1656 case 4: /* as v4i32 */
1657 vdata
= ac_build_gather_values(&ctx
->ac
, out
,
1658 !ac_has_vec3_support(ctx
->ac
.chip_class
, false) ?
1659 util_next_power_of_two(num_comps
) :
1664 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf
],
1665 vdata
, num_comps
, so_write_offsets
[buf
],
1666 ctx
->ac
.i32_0
, offset
,
1671 radv_emit_streamout(struct radv_shader_context
*ctx
, unsigned stream
)
1675 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1676 assert(ctx
->args
->streamout_config
.used
);
1677 LLVMValueRef so_vtx_count
=
1678 ac_build_bfe(&ctx
->ac
,
1679 ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_config
),
1680 LLVMConstInt(ctx
->ac
.i32
, 16, false),
1681 LLVMConstInt(ctx
->ac
.i32
, 7, false), false);
1683 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
1685 /* can_emit = tid < so_vtx_count; */
1686 LLVMValueRef can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
1687 tid
, so_vtx_count
, "");
1689 /* Emit the streamout code conditionally. This actually avoids
1690 * out-of-bounds buffer access. The hw tells us via the SGPR
1691 * (so_vtx_count) which threads are allowed to emit streamout data.
1693 ac_build_ifcc(&ctx
->ac
, can_emit
, 6501);
1695 /* The buffer offset is computed as follows:
1696 * ByteOffset = streamout_offset[buffer_id]*4 +
1697 * (streamout_write_index + thread_id)*stride[buffer_id] +
1700 LLVMValueRef so_write_index
=
1701 ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_write_idx
);
1703 /* Compute (streamout_write_index + thread_id). */
1705 LLVMBuildAdd(ctx
->ac
.builder
, so_write_index
, tid
, "");
1707 /* Load the descriptor and compute the write offset for each
1710 LLVMValueRef so_write_offset
[4] = {};
1711 LLVMValueRef so_buffers
[4] = {};
1712 LLVMValueRef buf_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_buffers
);
1714 for (i
= 0; i
< 4; i
++) {
1715 uint16_t stride
= ctx
->args
->shader_info
->so
.strides
[i
];
1720 LLVMValueRef offset
=
1721 LLVMConstInt(ctx
->ac
.i32
, i
, false);
1723 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
,
1726 LLVMValueRef so_offset
=
1727 ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_offset
[i
]);
1729 so_offset
= LLVMBuildMul(ctx
->ac
.builder
, so_offset
,
1730 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1732 so_write_offset
[i
] =
1733 ac_build_imad(&ctx
->ac
, so_write_index
,
1734 LLVMConstInt(ctx
->ac
.i32
,
1739 /* Write streamout data. */
1740 for (i
= 0; i
< ctx
->args
->shader_info
->so
.num_outputs
; i
++) {
1741 struct radv_shader_output_values shader_out
= {};
1742 struct radv_stream_output
*output
=
1743 &ctx
->args
->shader_info
->so
.outputs
[i
];
1745 if (stream
!= output
->stream
)
1748 for (int j
= 0; j
< 4; j
++) {
1749 shader_out
.values
[j
] =
1750 radv_load_output(ctx
, output
->location
, j
);
1753 radv_emit_stream_output(ctx
, so_buffers
,so_write_offset
,
1754 output
, &shader_out
);
1757 ac_build_endif(&ctx
->ac
, 6501);
1761 radv_build_param_exports(struct radv_shader_context
*ctx
,
1762 struct radv_shader_output_values
*outputs
,
1764 struct radv_vs_output_info
*outinfo
,
1765 bool export_clip_dists
)
1767 unsigned param_count
= 0;
1769 for (unsigned i
= 0; i
< noutput
; i
++) {
1770 unsigned slot_name
= outputs
[i
].slot_name
;
1771 unsigned usage_mask
= outputs
[i
].usage_mask
;
1773 if (slot_name
!= VARYING_SLOT_LAYER
&&
1774 slot_name
!= VARYING_SLOT_PRIMITIVE_ID
&&
1775 slot_name
!= VARYING_SLOT_VIEWPORT
&&
1776 slot_name
!= VARYING_SLOT_CLIP_DIST0
&&
1777 slot_name
!= VARYING_SLOT_CLIP_DIST1
&&
1778 slot_name
< VARYING_SLOT_VAR0
)
1781 if ((slot_name
== VARYING_SLOT_CLIP_DIST0
||
1782 slot_name
== VARYING_SLOT_CLIP_DIST1
) && !export_clip_dists
)
1785 radv_export_param(ctx
, param_count
, outputs
[i
].values
, usage_mask
);
1787 assert(i
< ARRAY_SIZE(outinfo
->vs_output_param_offset
));
1788 outinfo
->vs_output_param_offset
[slot_name
] = param_count
++;
1791 outinfo
->param_exports
= param_count
;
1794 /* Generate export instructions for hardware VS shader stage or NGG GS stage
1795 * (position and parameter data only).
1798 radv_llvm_export_vs(struct radv_shader_context
*ctx
,
1799 struct radv_shader_output_values
*outputs
,
1801 struct radv_vs_output_info
*outinfo
,
1802 bool export_clip_dists
)
1804 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_value
= NULL
;
1805 struct ac_export_args pos_args
[4] = {};
1806 unsigned pos_idx
, index
;
1809 /* Build position exports */
1810 for (i
= 0; i
< noutput
; i
++) {
1811 switch (outputs
[i
].slot_name
) {
1812 case VARYING_SLOT_POS
:
1813 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
1814 V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
1816 case VARYING_SLOT_PSIZ
:
1817 psize_value
= outputs
[i
].values
[0];
1819 case VARYING_SLOT_LAYER
:
1820 layer_value
= outputs
[i
].values
[0];
1822 case VARYING_SLOT_VIEWPORT
:
1823 viewport_value
= outputs
[i
].values
[0];
1825 case VARYING_SLOT_CLIP_DIST0
:
1826 case VARYING_SLOT_CLIP_DIST1
:
1827 index
= 2 + outputs
[i
].slot_index
;
1828 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
1829 V_008DFC_SQ_EXP_POS
+ index
,
1837 /* We need to add the position output manually if it's missing. */
1838 if (!pos_args
[0].out
[0]) {
1839 pos_args
[0].enabled_channels
= 0xf; /* writemask */
1840 pos_args
[0].valid_mask
= 0; /* EXEC mask */
1841 pos_args
[0].done
= 0; /* last export? */
1842 pos_args
[0].target
= V_008DFC_SQ_EXP_POS
;
1843 pos_args
[0].compr
= 0; /* COMPR flag */
1844 pos_args
[0].out
[0] = ctx
->ac
.f32_0
; /* X */
1845 pos_args
[0].out
[1] = ctx
->ac
.f32_0
; /* Y */
1846 pos_args
[0].out
[2] = ctx
->ac
.f32_0
; /* Z */
1847 pos_args
[0].out
[3] = ctx
->ac
.f32_1
; /* W */
1850 if (outinfo
->writes_pointsize
||
1851 outinfo
->writes_layer
||
1852 outinfo
->writes_viewport_index
) {
1853 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
1854 (outinfo
->writes_layer
== true ? 4 : 0));
1855 pos_args
[1].valid_mask
= 0;
1856 pos_args
[1].done
= 0;
1857 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
1858 pos_args
[1].compr
= 0;
1859 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
1860 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
1861 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
1862 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
1864 if (outinfo
->writes_pointsize
== true)
1865 pos_args
[1].out
[0] = psize_value
;
1866 if (outinfo
->writes_layer
== true)
1867 pos_args
[1].out
[2] = layer_value
;
1868 if (outinfo
->writes_viewport_index
== true) {
1869 if (ctx
->args
->options
->chip_class
>= GFX9
) {
1870 /* GFX9 has the layer in out.z[10:0] and the viewport
1871 * index in out.z[19:16].
1873 LLVMValueRef v
= viewport_value
;
1874 v
= ac_to_integer(&ctx
->ac
, v
);
1875 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
1876 LLVMConstInt(ctx
->ac
.i32
, 16, false),
1878 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
1879 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
1881 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
1882 pos_args
[1].enabled_channels
|= 1 << 2;
1884 pos_args
[1].out
[3] = viewport_value
;
1885 pos_args
[1].enabled_channels
|= 1 << 3;
1890 for (i
= 0; i
< 4; i
++) {
1891 if (pos_args
[i
].out
[0])
1892 outinfo
->pos_exports
++;
1895 /* GFX10 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
1896 * Setting valid_mask=1 prevents it and has no other effect.
1898 if (ctx
->ac
.chip_class
== GFX10
)
1899 pos_args
[0].valid_mask
= 1;
1902 for (i
= 0; i
< 4; i
++) {
1903 if (!pos_args
[i
].out
[0])
1906 /* Specify the target we are exporting */
1907 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
1909 if (pos_idx
== outinfo
->pos_exports
)
1910 /* Specify that this is the last export */
1911 pos_args
[i
].done
= 1;
1913 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
1916 /* Build parameter exports */
1917 radv_build_param_exports(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
1921 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
1922 bool export_prim_id
,
1923 bool export_clip_dists
,
1924 struct radv_vs_output_info
*outinfo
)
1926 struct radv_shader_output_values
*outputs
;
1927 unsigned noutput
= 0;
1929 if (ctx
->args
->options
->key
.has_multiview_view_index
) {
1930 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
1932 for(unsigned i
= 0; i
< 4; ++i
)
1933 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
1934 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
1937 LLVMValueRef view_index
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.view_index
);
1938 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, view_index
), *tmp_out
);
1939 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
1942 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
1943 sizeof(outinfo
->vs_output_param_offset
));
1944 outinfo
->pos_exports
= 0;
1946 if (!ctx
->args
->options
->use_ngg_streamout
&&
1947 ctx
->args
->shader_info
->so
.num_outputs
&&
1948 !ctx
->args
->is_gs_copy_shader
) {
1949 /* The GS copy shader emission already emits streamout. */
1950 radv_emit_streamout(ctx
, 0);
1953 /* Allocate a temporary array for the output values. */
1954 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_prim_id
;
1955 outputs
= malloc(num_outputs
* sizeof(outputs
[0]));
1957 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
1958 if (!(ctx
->output_mask
& (1ull << i
)))
1961 outputs
[noutput
].slot_name
= i
;
1962 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
1964 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
1965 !ctx
->args
->is_gs_copy_shader
) {
1966 outputs
[noutput
].usage_mask
=
1967 ctx
->args
->shader_info
->vs
.output_usage_mask
[i
];
1968 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
1969 outputs
[noutput
].usage_mask
=
1970 ctx
->args
->shader_info
->tes
.output_usage_mask
[i
];
1972 assert(ctx
->args
->is_gs_copy_shader
);
1973 outputs
[noutput
].usage_mask
=
1974 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
1977 for (unsigned j
= 0; j
< 4; j
++) {
1978 outputs
[noutput
].values
[j
] =
1979 ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
1985 /* Export PrimitiveID. */
1986 if (export_prim_id
) {
1987 outputs
[noutput
].slot_name
= VARYING_SLOT_PRIMITIVE_ID
;
1988 outputs
[noutput
].slot_index
= 0;
1989 outputs
[noutput
].usage_mask
= 0x1;
1990 outputs
[noutput
].values
[0] =
1991 ac_get_arg(&ctx
->ac
, ctx
->args
->vs_prim_id
);
1992 for (unsigned j
= 1; j
< 4; j
++)
1993 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
1997 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
2003 handle_es_outputs_post(struct radv_shader_context
*ctx
,
2004 struct radv_es_output_info
*outinfo
)
2007 LLVMValueRef lds_base
= NULL
;
2009 if (ctx
->ac
.chip_class
>= GFX9
) {
2010 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
2011 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
2012 LLVMValueRef wave_idx
=
2013 ac_unpack_param(&ctx
->ac
,
2014 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 24, 4);
2015 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
2016 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
2017 LLVMConstInt(ctx
->ac
.i32
,
2018 ctx
->ac
.wave_size
, false), ""), "");
2019 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
2020 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
2023 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2024 LLVMValueRef dw_addr
= NULL
;
2025 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2026 unsigned output_usage_mask
;
2029 if (!(ctx
->output_mask
& (1ull << i
)))
2032 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2034 ctx
->args
->shader_info
->vs
.output_usage_mask
[i
];
2036 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2038 ctx
->args
->shader_info
->tes
.output_usage_mask
[i
];
2041 param_index
= shader_io_get_unique_index(i
);
2044 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2045 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
2049 for (j
= 0; j
< 4; j
++) {
2050 if (!(output_usage_mask
& (1 << j
)))
2053 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2054 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
2055 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
2057 if (ctx
->ac
.chip_class
>= GFX9
) {
2058 LLVMValueRef dw_addr_offset
=
2059 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2060 LLVMConstInt(ctx
->ac
.i32
,
2063 ac_lds_store(&ctx
->ac
, dw_addr_offset
, out_val
);
2065 ac_build_buffer_store_dword(&ctx
->ac
,
2069 ac_get_arg(&ctx
->ac
, ctx
->args
->es2gs_offset
),
2070 (4 * param_index
+ j
) * 4,
2071 ac_glc
| ac_slc
| ac_swizzled
);
2078 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
2080 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
2081 uint32_t num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
2082 LLVMValueRef vertex_dw_stride
= LLVMConstInt(ctx
->ac
.i32
, num_tcs_inputs
* 4, false);
2083 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
2084 vertex_dw_stride
, "");
2086 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2087 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2089 if (!(ctx
->output_mask
& (1ull << i
)))
2092 int param
= shader_io_get_unique_index(i
);
2093 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
2094 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
2096 for (unsigned j
= 0; j
< 4; j
++) {
2097 LLVMValueRef value
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2098 value
= ac_to_integer(&ctx
->ac
, value
);
2099 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
2100 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
2101 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
2106 static LLVMValueRef
get_wave_id_in_tg(struct radv_shader_context
*ctx
)
2108 return ac_unpack_param(&ctx
->ac
,
2109 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 24, 4);
2112 static LLVMValueRef
get_tgsize(struct radv_shader_context
*ctx
)
2114 return ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 28, 4);
2117 static LLVMValueRef
get_thread_id_in_tg(struct radv_shader_context
*ctx
)
2119 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2121 tmp
= LLVMBuildMul(builder
, get_wave_id_in_tg(ctx
),
2122 LLVMConstInt(ctx
->ac
.i32
, ctx
->ac
.wave_size
, false), "");
2123 return LLVMBuildAdd(builder
, tmp
, ac_get_thread_id(&ctx
->ac
), "");
2126 static LLVMValueRef
ngg_get_vtx_cnt(struct radv_shader_context
*ctx
)
2128 return ac_build_bfe(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_tg_info
),
2129 LLVMConstInt(ctx
->ac
.i32
, 12, false),
2130 LLVMConstInt(ctx
->ac
.i32
, 9, false),
2134 static LLVMValueRef
ngg_get_prim_cnt(struct radv_shader_context
*ctx
)
2136 return ac_build_bfe(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_tg_info
),
2137 LLVMConstInt(ctx
->ac
.i32
, 22, false),
2138 LLVMConstInt(ctx
->ac
.i32
, 9, false),
2142 static LLVMValueRef
ngg_get_ordered_id(struct radv_shader_context
*ctx
)
2144 return ac_build_bfe(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_tg_info
),
2146 LLVMConstInt(ctx
->ac
.i32
, 12, false),
2151 ngg_gs_get_vertex_storage(struct radv_shader_context
*ctx
)
2153 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
);
2155 if (ctx
->args
->options
->key
.has_multiview_view_index
)
2158 LLVMTypeRef elements
[2] = {
2159 LLVMArrayType(ctx
->ac
.i32
, 4 * num_outputs
),
2160 LLVMArrayType(ctx
->ac
.i8
, 4),
2162 LLVMTypeRef type
= LLVMStructTypeInContext(ctx
->ac
.context
, elements
, 2, false);
2163 type
= LLVMPointerType(LLVMArrayType(type
, 0), AC_ADDR_SPACE_LDS
);
2164 return LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->gs_ngg_emit
, type
, "");
2168 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
2169 * is in emit order; that is:
2170 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
2171 * - during vertex emit, i.e. while the API GS shader invocation is running,
2172 * N = threadidx * gs_max_out_vertices + emitidx
2174 * Goals of the LDS memory layout:
2175 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
2176 * in uniform control flow
2177 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
2179 * 3. Agnostic to the number of waves (since we don't know it before compiling)
2180 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
2181 * 5. Avoid wasting memory.
2183 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
2184 * layout, elimination of bank conflicts requires that each vertex occupy an
2185 * odd number of dwords. We use the additional dword to store the output stream
2186 * index as well as a flag to indicate whether this vertex ends a primitive
2187 * for rasterization.
2189 * Swizzling is required to satisfy points 1 and 2 simultaneously.
2191 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
2192 * Indices are swizzled in groups of 32, which ensures point 1 without
2193 * disturbing point 2.
2195 * \return an LDS pointer to type {[N x i32], [4 x i8]}
2198 ngg_gs_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef vertexidx
)
2200 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2201 LLVMValueRef storage
= ngg_gs_get_vertex_storage(ctx
);
2203 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
2204 unsigned write_stride_2exp
= ffs(ctx
->shader
->info
.gs
.vertices_out
) - 1;
2205 if (write_stride_2exp
) {
2207 LLVMBuildLShr(builder
, vertexidx
,
2208 LLVMConstInt(ctx
->ac
.i32
, 5, false), "");
2209 LLVMValueRef swizzle
=
2210 LLVMBuildAnd(builder
, row
,
2211 LLVMConstInt(ctx
->ac
.i32
, (1u << write_stride_2exp
) - 1,
2213 vertexidx
= LLVMBuildXor(builder
, vertexidx
, swizzle
, "");
2216 return ac_build_gep0(&ctx
->ac
, storage
, vertexidx
);
2220 ngg_gs_emit_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef gsthread
,
2221 LLVMValueRef emitidx
)
2223 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2226 tmp
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false);
2227 tmp
= LLVMBuildMul(builder
, tmp
, gsthread
, "");
2228 const LLVMValueRef vertexidx
= LLVMBuildAdd(builder
, tmp
, emitidx
, "");
2229 return ngg_gs_vertex_ptr(ctx
, vertexidx
);
2233 ngg_gs_get_emit_output_ptr(struct radv_shader_context
*ctx
, LLVMValueRef vertexptr
,
2236 LLVMValueRef gep_idx
[3] = {
2237 ctx
->ac
.i32_0
, /* implied C-style array */
2238 ctx
->ac
.i32_0
, /* first struct entry */
2239 LLVMConstInt(ctx
->ac
.i32
, out_idx
, false),
2241 return LLVMBuildGEP(ctx
->ac
.builder
, vertexptr
, gep_idx
, 3, "");
2245 ngg_gs_get_emit_primflag_ptr(struct radv_shader_context
*ctx
, LLVMValueRef vertexptr
,
2248 LLVMValueRef gep_idx
[3] = {
2249 ctx
->ac
.i32_0
, /* implied C-style array */
2250 ctx
->ac
.i32_1
, /* second struct entry */
2251 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
2253 return LLVMBuildGEP(ctx
->ac
.builder
, vertexptr
, gep_idx
, 3, "");
2256 static struct radv_stream_output
*
2257 radv_get_stream_output_by_loc(struct radv_streamout_info
*so
, unsigned location
)
2259 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
2260 if (so
->outputs
[i
].location
== location
)
2261 return &so
->outputs
[i
];
2267 static void build_streamout_vertex(struct radv_shader_context
*ctx
,
2268 LLVMValueRef
*so_buffer
, LLVMValueRef
*wg_offset_dw
,
2269 unsigned stream
, LLVMValueRef offset_vtx
,
2270 LLVMValueRef vertexptr
)
2272 struct radv_streamout_info
*so
= &ctx
->args
->shader_info
->so
;
2273 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2274 LLVMValueRef offset
[4] = {};
2277 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2278 if (!wg_offset_dw
[buffer
])
2281 tmp
= LLVMBuildMul(builder
, offset_vtx
,
2282 LLVMConstInt(ctx
->ac
.i32
, so
->strides
[buffer
], false), "");
2283 tmp
= LLVMBuildAdd(builder
, wg_offset_dw
[buffer
], tmp
, "");
2284 offset
[buffer
] = LLVMBuildShl(builder
, tmp
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
2287 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
2288 struct radv_shader_output_values outputs
[AC_LLVM_MAX_OUTPUTS
];
2289 unsigned noutput
= 0;
2290 unsigned out_idx
= 0;
2292 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2293 unsigned output_usage_mask
=
2294 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
2295 uint8_t output_stream
= ctx
->args
->shader_info
->gs
.output_streams
[i
];
2297 if (!(ctx
->output_mask
& (1ull << i
)) ||
2298 output_stream
!= stream
)
2301 outputs
[noutput
].slot_name
= i
;
2302 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
2303 outputs
[noutput
].usage_mask
= output_usage_mask
;
2305 int length
= util_last_bit(output_usage_mask
);
2307 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
2308 if (!(output_usage_mask
& (1 << j
)))
2311 tmp
= ac_build_gep0(&ctx
->ac
, vertexptr
,
2312 LLVMConstInt(ctx
->ac
.i32
, out_idx
, false));
2313 outputs
[noutput
].values
[j
] = LLVMBuildLoad(builder
, tmp
, "");
2316 for (unsigned j
= length
; j
< 4; j
++)
2317 outputs
[noutput
].values
[j
] = LLVMGetUndef(ctx
->ac
.f32
);
2322 for (unsigned i
= 0; i
< noutput
; i
++) {
2323 struct radv_stream_output
*output
=
2324 radv_get_stream_output_by_loc(so
, outputs
[i
].slot_name
);
2327 output
->stream
!= stream
)
2330 struct radv_shader_output_values out
= {};
2332 for (unsigned j
= 0; j
< 4; j
++) {
2333 out
.values
[j
] = outputs
[i
].values
[j
];
2336 radv_emit_stream_output(ctx
, so_buffer
, offset
, output
, &out
);
2339 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
2340 struct radv_stream_output
*output
=
2341 &ctx
->args
->shader_info
->so
.outputs
[i
];
2343 if (stream
!= output
->stream
)
2346 struct radv_shader_output_values out
= {};
2348 for (unsigned comp
= 0; comp
< 4; comp
++) {
2349 if (!(output
->component_mask
& (1 << comp
)))
2352 tmp
= ac_build_gep0(&ctx
->ac
, vertexptr
,
2353 LLVMConstInt(ctx
->ac
.i32
, 4 * i
+ comp
, false));
2354 out
.values
[comp
] = LLVMBuildLoad(builder
, tmp
, "");
2357 radv_emit_stream_output(ctx
, so_buffer
, offset
, output
, &out
);
2362 struct ngg_streamout
{
2363 LLVMValueRef num_vertices
;
2365 /* per-thread data */
2366 LLVMValueRef prim_enable
[4]; /* i1 per stream */
2367 LLVMValueRef vertices
[3]; /* [N x i32] addrspace(LDS)* */
2370 LLVMValueRef emit
[4]; /* per-stream emitted primitives (only valid for used streams) */
2374 * Build streamout logic.
2376 * Implies a barrier.
2378 * Writes number of emitted primitives to gs_ngg_scratch[4:7].
2380 * Clobbers gs_ngg_scratch[8:].
2382 static void build_streamout(struct radv_shader_context
*ctx
,
2383 struct ngg_streamout
*nggso
)
2385 struct radv_streamout_info
*so
= &ctx
->args
->shader_info
->so
;
2386 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2387 LLVMValueRef buf_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_buffers
);
2388 LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
2389 LLVMValueRef cond
, tmp
, tmp2
;
2390 LLVMValueRef i32_2
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
2391 LLVMValueRef i32_4
= LLVMConstInt(ctx
->ac
.i32
, 4, false);
2392 LLVMValueRef i32_8
= LLVMConstInt(ctx
->ac
.i32
, 8, false);
2393 LLVMValueRef so_buffer
[4] = {};
2394 unsigned max_num_vertices
= 1 + (nggso
->vertices
[1] ? 1 : 0) +
2395 (nggso
->vertices
[2] ? 1 : 0);
2396 LLVMValueRef prim_stride_dw
[4] = {};
2397 LLVMValueRef prim_stride_dw_vgpr
= LLVMGetUndef(ctx
->ac
.i32
);
2398 int stream_for_buffer
[4] = { -1, -1, -1, -1 };
2399 unsigned bufmask_for_stream
[4] = {};
2400 bool isgs
= ctx
->stage
== MESA_SHADER_GEOMETRY
;
2401 unsigned scratch_emit_base
= isgs
? 4 : 0;
2402 LLVMValueRef scratch_emit_basev
= isgs
? i32_4
: ctx
->ac
.i32_0
;
2403 unsigned scratch_offset_base
= isgs
? 8 : 4;
2404 LLVMValueRef scratch_offset_basev
= isgs
? i32_8
: i32_4
;
2406 ac_llvm_add_target_dep_function_attr(ctx
->main_function
,
2407 "amdgpu-gds-size", 256);
2409 /* Determine the mapping of streamout buffers to vertex streams. */
2410 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
2411 unsigned buf
= so
->outputs
[i
].buffer
;
2412 unsigned stream
= so
->outputs
[i
].stream
;
2413 assert(stream_for_buffer
[buf
] < 0 || stream_for_buffer
[buf
] == stream
);
2414 stream_for_buffer
[buf
] = stream
;
2415 bufmask_for_stream
[stream
] |= 1 << buf
;
2418 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2419 if (stream_for_buffer
[buffer
] == -1)
2422 assert(so
->strides
[buffer
]);
2424 LLVMValueRef stride_for_buffer
=
2425 LLVMConstInt(ctx
->ac
.i32
, so
->strides
[buffer
], false);
2426 prim_stride_dw
[buffer
] =
2427 LLVMBuildMul(builder
, stride_for_buffer
,
2428 nggso
->num_vertices
, "");
2429 prim_stride_dw_vgpr
= ac_build_writelane(
2430 &ctx
->ac
, prim_stride_dw_vgpr
, prim_stride_dw
[buffer
],
2431 LLVMConstInt(ctx
->ac
.i32
, buffer
, false));
2433 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, buffer
, false);
2434 so_buffer
[buffer
] = ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
,
2438 cond
= LLVMBuildICmp(builder
, LLVMIntEQ
, get_wave_id_in_tg(ctx
), ctx
->ac
.i32_0
, "");
2439 ac_build_ifcc(&ctx
->ac
, cond
, 5200);
2441 LLVMTypeRef gdsptr
= LLVMPointerType(ctx
->ac
.i32
, AC_ADDR_SPACE_GDS
);
2442 LLVMValueRef gdsbase
= LLVMBuildIntToPtr(builder
, ctx
->ac
.i32_0
, gdsptr
, "");
2444 /* Advance the streamout offsets in GDS. */
2445 LLVMValueRef offsets_vgpr
= ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.i32
, "");
2446 LLVMValueRef generated_by_stream_vgpr
= ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.i32
, "");
2448 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, ac_get_thread_id(&ctx
->ac
), i32_4
, "");
2449 ac_build_ifcc(&ctx
->ac
, cond
, 5210);
2451 /* Fetch the number of generated primitives and store
2452 * it in GDS for later use.
2455 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tid
);
2456 tmp
= LLVMBuildLoad(builder
, tmp
, "");
2458 tmp
= ac_build_writelane(&ctx
->ac
, ctx
->ac
.i32_0
,
2459 ngg_get_prim_cnt(ctx
), ctx
->ac
.i32_0
);
2461 LLVMBuildStore(builder
, tmp
, generated_by_stream_vgpr
);
2463 unsigned swizzle
[4];
2464 int unused_stream
= -1;
2465 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2466 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
]) {
2467 unused_stream
= stream
;
2471 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2472 if (stream_for_buffer
[buffer
] >= 0) {
2473 swizzle
[buffer
] = stream_for_buffer
[buffer
];
2475 assert(unused_stream
>= 0);
2476 swizzle
[buffer
] = unused_stream
;
2480 tmp
= ac_build_quad_swizzle(&ctx
->ac
, tmp
,
2481 swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2482 tmp
= LLVMBuildMul(builder
, tmp
, prim_stride_dw_vgpr
, "");
2484 LLVMValueRef args
[] = {
2485 LLVMBuildIntToPtr(builder
, ngg_get_ordered_id(ctx
), gdsptr
, ""),
2487 ctx
->ac
.i32_0
, // ordering
2488 ctx
->ac
.i32_0
, // scope
2489 ctx
->ac
.i1false
, // isVolatile
2490 LLVMConstInt(ctx
->ac
.i32
, 4 << 24, false), // OA index
2491 ctx
->ac
.i1true
, // wave release
2492 ctx
->ac
.i1true
, // wave done
2495 tmp
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.ds.ordered.add",
2496 ctx
->ac
.i32
, args
, ARRAY_SIZE(args
), 0);
2498 /* Keep offsets in a VGPR for quick retrieval via readlane by
2499 * the first wave for bounds checking, and also store in LDS
2500 * for retrieval by all waves later. */
2501 LLVMBuildStore(builder
, tmp
, offsets_vgpr
);
2503 tmp2
= LLVMBuildAdd(builder
, ac_get_thread_id(&ctx
->ac
),
2504 scratch_offset_basev
, "");
2505 tmp2
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tmp2
);
2506 LLVMBuildStore(builder
, tmp
, tmp2
);
2508 ac_build_endif(&ctx
->ac
, 5210);
2510 /* Determine the max emit per buffer. This is done via the SALU, in part
2511 * because LLVM can't generate divide-by-multiply if we try to do this
2512 * via VALU with one lane per buffer.
2514 LLVMValueRef max_emit
[4] = {};
2515 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2516 if (stream_for_buffer
[buffer
] == -1)
2519 /* Compute the streamout buffer size in DWORD. */
2520 LLVMValueRef bufsize_dw
=
2521 LLVMBuildLShr(builder
,
2522 LLVMBuildExtractElement(builder
, so_buffer
[buffer
], i32_2
, ""),
2525 /* Load the streamout buffer offset from GDS. */
2526 tmp
= LLVMBuildLoad(builder
, offsets_vgpr
, "");
2527 LLVMValueRef offset_dw
=
2528 ac_build_readlane(&ctx
->ac
, tmp
,
2529 LLVMConstInt(ctx
->ac
.i32
, buffer
, false));
2531 /* Compute the remaining size to emit. */
2532 LLVMValueRef remaining_dw
=
2533 LLVMBuildSub(builder
, bufsize_dw
, offset_dw
, "");
2534 tmp
= LLVMBuildUDiv(builder
, remaining_dw
,
2535 prim_stride_dw
[buffer
], "");
2537 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
2538 bufsize_dw
, offset_dw
, "");
2539 max_emit
[buffer
] = LLVMBuildSelect(builder
, cond
,
2540 ctx
->ac
.i32_0
, tmp
, "");
2543 /* Determine the number of emitted primitives per stream and fixup the
2544 * GDS counter if necessary.
2546 * This is complicated by the fact that a single stream can emit to
2547 * multiple buffers (but luckily not vice versa).
2549 LLVMValueRef emit_vgpr
= ctx
->ac
.i32_0
;
2551 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2552 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
2555 /* Load the number of generated primitives from GDS and
2556 * determine that number for the given stream.
2558 tmp
= LLVMBuildLoad(builder
, generated_by_stream_vgpr
, "");
2559 LLVMValueRef generated
=
2560 ac_build_readlane(&ctx
->ac
, tmp
,
2561 LLVMConstInt(ctx
->ac
.i32
, stream
, false));
2564 /* Compute the number of emitted primitives. */
2565 LLVMValueRef emit
= generated
;
2566 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2567 if (stream_for_buffer
[buffer
] == stream
)
2568 emit
= ac_build_umin(&ctx
->ac
, emit
, max_emit
[buffer
]);
2571 /* Store the number of emitted primitives for that
2574 emit_vgpr
= ac_build_writelane(&ctx
->ac
, emit_vgpr
, emit
,
2575 LLVMConstInt(ctx
->ac
.i32
, stream
, false));
2577 /* Fixup the offset using a plain GDS atomic if we overflowed. */
2578 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, emit
, generated
, "");
2579 ac_build_ifcc(&ctx
->ac
, cond
, 5221); /* scalar branch */
2580 tmp
= LLVMBuildLShr(builder
,
2581 LLVMConstInt(ctx
->ac
.i32
, bufmask_for_stream
[stream
], false),
2582 ac_get_thread_id(&ctx
->ac
), "");
2583 tmp
= LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
2584 ac_build_ifcc(&ctx
->ac
, tmp
, 5222);
2586 tmp
= LLVMBuildSub(builder
, generated
, emit
, "");
2587 tmp
= LLVMBuildMul(builder
, tmp
, prim_stride_dw_vgpr
, "");
2588 tmp2
= LLVMBuildGEP(builder
, gdsbase
, &tid
, 1, "");
2589 LLVMBuildAtomicRMW(builder
, LLVMAtomicRMWBinOpSub
, tmp2
, tmp
,
2590 LLVMAtomicOrderingMonotonic
, false);
2592 ac_build_endif(&ctx
->ac
, 5222);
2593 ac_build_endif(&ctx
->ac
, 5221);
2596 /* Store the number of emitted primitives to LDS for later use. */
2597 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, ac_get_thread_id(&ctx
->ac
), i32_4
, "");
2598 ac_build_ifcc(&ctx
->ac
, cond
, 5225);
2600 tmp
= LLVMBuildAdd(builder
, ac_get_thread_id(&ctx
->ac
),
2601 scratch_emit_basev
, "");
2602 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tmp
);
2603 LLVMBuildStore(builder
, emit_vgpr
, tmp
);
2605 ac_build_endif(&ctx
->ac
, 5225);
2607 ac_build_endif(&ctx
->ac
, 5200);
2609 /* Determine the workgroup-relative per-thread / primitive offset into
2610 * the streamout buffers */
2611 struct ac_wg_scan primemit_scan
[4] = {};
2614 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2615 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
2618 primemit_scan
[stream
].enable_exclusive
= true;
2619 primemit_scan
[stream
].op
= nir_op_iadd
;
2620 primemit_scan
[stream
].src
= nggso
->prim_enable
[stream
];
2621 primemit_scan
[stream
].scratch
=
2622 ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
,
2623 LLVMConstInt(ctx
->ac
.i32
, 12 + 8 * stream
, false));
2624 primemit_scan
[stream
].waveidx
= get_wave_id_in_tg(ctx
);
2625 primemit_scan
[stream
].numwaves
= get_tgsize(ctx
);
2626 primemit_scan
[stream
].maxwaves
= 8;
2627 ac_build_wg_scan_top(&ctx
->ac
, &primemit_scan
[stream
]);
2631 ac_build_s_barrier(&ctx
->ac
);
2633 /* Fetch the per-buffer offsets and per-stream emit counts in all waves. */
2634 LLVMValueRef wgoffset_dw
[4] = {};
2637 LLVMValueRef scratch_vgpr
;
2639 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, ac_get_thread_id(&ctx
->ac
));
2640 scratch_vgpr
= LLVMBuildLoad(builder
, tmp
, "");
2642 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2643 if (stream_for_buffer
[buffer
] >= 0) {
2644 wgoffset_dw
[buffer
] = ac_build_readlane(
2645 &ctx
->ac
, scratch_vgpr
,
2646 LLVMConstInt(ctx
->ac
.i32
, scratch_offset_base
+ buffer
, false));
2650 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2651 if (ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
]) {
2652 nggso
->emit
[stream
] = ac_build_readlane(
2653 &ctx
->ac
, scratch_vgpr
,
2654 LLVMConstInt(ctx
->ac
.i32
, scratch_emit_base
+ stream
, false));
2659 /* Write out primitive data */
2660 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2661 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
2665 ac_build_wg_scan_bottom(&ctx
->ac
, &primemit_scan
[stream
]);
2667 primemit_scan
[stream
].result_exclusive
= tid
;
2670 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
2671 primemit_scan
[stream
].result_exclusive
,
2672 nggso
->emit
[stream
], "");
2673 cond
= LLVMBuildAnd(builder
, cond
, nggso
->prim_enable
[stream
], "");
2674 ac_build_ifcc(&ctx
->ac
, cond
, 5240);
2676 LLVMValueRef offset_vtx
=
2677 LLVMBuildMul(builder
, primemit_scan
[stream
].result_exclusive
,
2678 nggso
->num_vertices
, "");
2680 for (unsigned i
= 0; i
< max_num_vertices
; ++i
) {
2681 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
2682 LLVMConstInt(ctx
->ac
.i32
, i
, false),
2683 nggso
->num_vertices
, "");
2684 ac_build_ifcc(&ctx
->ac
, cond
, 5241);
2685 build_streamout_vertex(ctx
, so_buffer
, wgoffset_dw
,
2686 stream
, offset_vtx
, nggso
->vertices
[i
]);
2687 ac_build_endif(&ctx
->ac
, 5241);
2688 offset_vtx
= LLVMBuildAdd(builder
, offset_vtx
, ctx
->ac
.i32_1
, "");
2691 ac_build_endif(&ctx
->ac
, 5240);
2695 static unsigned ngg_nogs_vertex_size(struct radv_shader_context
*ctx
)
2697 unsigned lds_vertex_size
= 0;
2699 if (ctx
->args
->shader_info
->so
.num_outputs
)
2700 lds_vertex_size
= 4 * ctx
->args
->shader_info
->so
.num_outputs
+ 1;
2702 return lds_vertex_size
;
2706 * Returns an `[N x i32] addrspace(LDS)*` pointing at contiguous LDS storage
2707 * for the vertex outputs.
2709 static LLVMValueRef
ngg_nogs_vertex_ptr(struct radv_shader_context
*ctx
,
2712 /* The extra dword is used to avoid LDS bank conflicts. */
2713 unsigned vertex_size
= ngg_nogs_vertex_size(ctx
);
2714 LLVMTypeRef ai32
= LLVMArrayType(ctx
->ac
.i32
, vertex_size
);
2715 LLVMTypeRef pai32
= LLVMPointerType(ai32
, AC_ADDR_SPACE_LDS
);
2716 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->esgs_ring
, pai32
, "");
2717 return LLVMBuildGEP(ctx
->ac
.builder
, tmp
, &vtxid
, 1, "");
2721 handle_ngg_outputs_post_1(struct radv_shader_context
*ctx
)
2723 struct radv_streamout_info
*so
= &ctx
->args
->shader_info
->so
;
2724 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2725 LLVMValueRef vertex_ptr
= NULL
;
2726 LLVMValueRef tmp
, tmp2
;
2728 assert((ctx
->stage
== MESA_SHADER_VERTEX
||
2729 ctx
->stage
== MESA_SHADER_TESS_EVAL
) && !ctx
->args
->is_gs_copy_shader
);
2731 if (!ctx
->args
->shader_info
->so
.num_outputs
)
2734 vertex_ptr
= ngg_nogs_vertex_ptr(ctx
, get_thread_id_in_tg(ctx
));
2736 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
2737 struct radv_stream_output
*output
=
2738 &ctx
->args
->shader_info
->so
.outputs
[i
];
2740 unsigned loc
= output
->location
;
2742 for (unsigned comp
= 0; comp
< 4; comp
++) {
2743 if (!(output
->component_mask
& (1 << comp
)))
2746 tmp
= ac_build_gep0(&ctx
->ac
, vertex_ptr
,
2747 LLVMConstInt(ctx
->ac
.i32
, 4 * i
+ comp
, false));
2748 tmp2
= LLVMBuildLoad(builder
,
2749 ctx
->abi
.outputs
[4 * loc
+ comp
], "");
2750 tmp2
= ac_to_integer(&ctx
->ac
, tmp2
);
2751 LLVMBuildStore(builder
, tmp2
, tmp
);
2757 handle_ngg_outputs_post_2(struct radv_shader_context
*ctx
)
2759 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2762 assert((ctx
->stage
== MESA_SHADER_VERTEX
||
2763 ctx
->stage
== MESA_SHADER_TESS_EVAL
) && !ctx
->args
->is_gs_copy_shader
);
2765 LLVMValueRef prims_in_wave
= ac_unpack_param(&ctx
->ac
,
2766 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 8, 8);
2767 LLVMValueRef vtx_in_wave
= ac_unpack_param(&ctx
->ac
,
2768 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 0, 8);
2769 LLVMValueRef is_gs_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
2770 ac_get_thread_id(&ctx
->ac
), prims_in_wave
, "");
2771 LLVMValueRef is_es_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
2772 ac_get_thread_id(&ctx
->ac
), vtx_in_wave
, "");
2773 LLVMValueRef vtxindex
[] = {
2774 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[0]), 0, 16),
2775 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[0]), 16, 16),
2776 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[2]), 0, 16),
2779 /* Determine the number of vertices per primitive. */
2780 unsigned num_vertices
;
2781 LLVMValueRef num_vertices_val
;
2783 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2784 LLVMValueRef outprim_val
=
2785 LLVMConstInt(ctx
->ac
.i32
,
2786 ctx
->args
->options
->key
.vs
.outprim
, false);
2787 num_vertices_val
= LLVMBuildAdd(builder
, outprim_val
,
2789 num_vertices
= 3; /* TODO: optimize for points & lines */
2791 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2793 if (ctx
->shader
->info
.tess
.point_mode
)
2795 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
2800 num_vertices_val
= LLVMConstInt(ctx
->ac
.i32
, num_vertices
, false);
2804 if (ctx
->args
->shader_info
->so
.num_outputs
) {
2805 struct ngg_streamout nggso
= {};
2807 nggso
.num_vertices
= num_vertices_val
;
2808 nggso
.prim_enable
[0] = is_gs_thread
;
2810 for (unsigned i
= 0; i
< num_vertices
; ++i
)
2811 nggso
.vertices
[i
] = ngg_nogs_vertex_ptr(ctx
, vtxindex
[i
]);
2813 build_streamout(ctx
, &nggso
);
2816 /* Copy Primitive IDs from GS threads to the LDS address corresponding
2817 * to the ES thread of the provoking vertex.
2819 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2820 ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
2821 if (ctx
->args
->shader_info
->so
.num_outputs
)
2822 ac_build_s_barrier(&ctx
->ac
);
2824 ac_build_ifcc(&ctx
->ac
, is_gs_thread
, 5400);
2825 /* Extract the PROVOKING_VTX_INDEX field. */
2826 LLVMValueRef provoking_vtx_in_prim
=
2827 LLVMConstInt(ctx
->ac
.i32
, 0, false);
2829 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
2830 LLVMValueRef indices
= ac_build_gather_values(&ctx
->ac
, vtxindex
, 3);
2831 LLVMValueRef provoking_vtx_index
=
2832 LLVMBuildExtractElement(builder
, indices
, provoking_vtx_in_prim
, "");
2834 LLVMBuildStore(builder
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.gs_prim_id
),
2835 ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
, provoking_vtx_index
));
2836 ac_build_endif(&ctx
->ac
, 5400);
2839 /* TODO: primitive culling */
2841 ac_build_sendmsg_gs_alloc_req(&ctx
->ac
, get_wave_id_in_tg(ctx
),
2842 ngg_get_vtx_cnt(ctx
), ngg_get_prim_cnt(ctx
));
2844 /* TODO: streamout queries */
2845 /* Export primitive data to the index buffer.
2847 * For the first version, we will always build up all three indices
2848 * independent of the primitive type. The additional garbage data
2851 * TODO: culling depends on the primitive type, so can have some
2854 ac_build_ifcc(&ctx
->ac
, is_gs_thread
, 6001);
2856 struct ac_ngg_prim prim
= {};
2858 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
2859 prim
.passthrough
= ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[0]);
2861 prim
.num_vertices
= num_vertices
;
2862 prim
.isnull
= ctx
->ac
.i1false
;
2863 memcpy(prim
.index
, vtxindex
, sizeof(vtxindex
[0]) * 3);
2865 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
2866 tmp
= LLVMBuildLShr(builder
,
2867 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.gs_invocation_id
),
2868 LLVMConstInt(ctx
->ac
.i32
, 8 + i
, false), "");
2869 prim
.edgeflag
[i
] = LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
2873 ac_build_export_prim(&ctx
->ac
, &prim
);
2875 ac_build_endif(&ctx
->ac
, 6001);
2877 /* Export per-vertex data (positions and parameters). */
2878 ac_build_ifcc(&ctx
->ac
, is_es_thread
, 6002);
2880 struct radv_vs_output_info
*outinfo
=
2881 ctx
->stage
== MESA_SHADER_TESS_EVAL
?
2882 &ctx
->args
->shader_info
->tes
.outinfo
: &ctx
->args
->shader_info
->vs
.outinfo
;
2884 /* Exporting the primitive ID is handled below. */
2885 /* TODO: use the new VS export path */
2886 handle_vs_outputs_post(ctx
, false,
2887 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
,
2890 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
2891 unsigned param_count
= outinfo
->param_exports
;
2892 LLVMValueRef values
[4];
2894 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2895 /* Wait for GS stores to finish. */
2896 ac_build_s_barrier(&ctx
->ac
);
2898 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
,
2899 get_thread_id_in_tg(ctx
));
2900 values
[0] = LLVMBuildLoad(builder
, tmp
, "");
2902 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2903 values
[0] = ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tes_patch_id
);
2906 values
[0] = ac_to_float(&ctx
->ac
, values
[0]);
2907 for (unsigned j
= 1; j
< 4; j
++)
2908 values
[j
] = ctx
->ac
.f32_0
;
2910 radv_export_param(ctx
, param_count
, values
, 0x1);
2912 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
2913 outinfo
->param_exports
= param_count
;
2916 ac_build_endif(&ctx
->ac
, 6002);
2919 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context
*ctx
)
2921 /* Zero out the part of LDS scratch that is used to accumulate the
2922 * per-stream generated primitive count.
2924 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2925 LLVMValueRef scratchptr
= ctx
->gs_ngg_scratch
;
2926 LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
2927 LLVMBasicBlockRef merge_block
;
2930 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
2931 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
2932 merge_block
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
2934 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
2935 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, then_block
, merge_block
);
2936 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, then_block
);
2938 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, scratchptr
, tid
);
2939 LLVMBuildStore(builder
, ctx
->ac
.i32_0
, ptr
);
2941 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
2942 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
2944 ac_build_s_barrier(&ctx
->ac
);
2947 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context
*ctx
)
2949 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2950 LLVMValueRef i8_0
= LLVMConstInt(ctx
->ac
.i8
, 0, false);
2953 /* Zero out remaining (non-emitted) primitive flags.
2955 * Note: Alternatively, we could pass the relevant gs_next_vertex to
2956 * the emit threads via LDS. This is likely worse in the expected
2957 * typical case where each GS thread emits the full set of
2960 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2961 unsigned num_components
;
2964 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
2965 if (!num_components
)
2968 const LLVMValueRef gsthread
= get_thread_id_in_tg(ctx
);
2970 ac_build_bgnloop(&ctx
->ac
, 5100);
2972 const LLVMValueRef vertexidx
=
2973 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
2974 tmp
= LLVMBuildICmp(builder
, LLVMIntUGE
, vertexidx
,
2975 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
2976 ac_build_ifcc(&ctx
->ac
, tmp
, 5101);
2977 ac_build_break(&ctx
->ac
);
2978 ac_build_endif(&ctx
->ac
, 5101);
2980 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
2981 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
2983 tmp
= ngg_gs_emit_vertex_ptr(ctx
, gsthread
, vertexidx
);
2984 LLVMBuildStore(builder
, i8_0
,
2985 ngg_gs_get_emit_primflag_ptr(ctx
, tmp
, stream
));
2987 ac_build_endloop(&ctx
->ac
, 5100);
2990 /* Accumulate generated primitives counts across the entire threadgroup. */
2991 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2992 unsigned num_components
;
2995 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
2996 if (!num_components
)
2999 LLVMValueRef numprims
=
3000 LLVMBuildLoad(builder
, ctx
->gs_generated_prims
[stream
], "");
3001 numprims
= ac_build_reduce(&ctx
->ac
, numprims
, nir_op_iadd
, ctx
->ac
.wave_size
);
3003 tmp
= LLVMBuildICmp(builder
, LLVMIntEQ
, ac_get_thread_id(&ctx
->ac
), ctx
->ac
.i32_0
, "");
3004 ac_build_ifcc(&ctx
->ac
, tmp
, 5105);
3006 LLVMBuildAtomicRMW(builder
, LLVMAtomicRMWBinOpAdd
,
3007 ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
,
3008 LLVMConstInt(ctx
->ac
.i32
, stream
, false)),
3009 numprims
, LLVMAtomicOrderingMonotonic
, false);
3011 ac_build_endif(&ctx
->ac
, 5105);
3015 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context
*ctx
)
3017 const unsigned verts_per_prim
= si_conv_gl_prim_to_vertices(ctx
->shader
->info
.gs
.output_primitive
);
3018 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3019 LLVMValueRef tmp
, tmp2
;
3021 ac_build_s_barrier(&ctx
->ac
);
3023 const LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3024 LLVMValueRef num_emit_threads
= ngg_get_prim_cnt(ctx
);
3027 if (ctx
->args
->shader_info
->so
.num_outputs
) {
3028 struct ngg_streamout nggso
= {};
3030 nggso
.num_vertices
= LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
, false);
3032 LLVMValueRef vertexptr
= ngg_gs_vertex_ptr(ctx
, tid
);
3033 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3034 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
3037 tmp
= LLVMBuildLoad(builder
,
3038 ngg_gs_get_emit_primflag_ptr(ctx
, vertexptr
, stream
), "");
3039 tmp
= LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3040 tmp2
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3041 nggso
.prim_enable
[stream
] = LLVMBuildAnd(builder
, tmp
, tmp2
, "");
3044 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3045 tmp
= LLVMBuildSub(builder
, tid
,
3046 LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
- i
- 1, false), "");
3047 tmp
= ngg_gs_vertex_ptr(ctx
, tmp
);
3048 nggso
.vertices
[i
] = ac_build_gep0(&ctx
->ac
, tmp
, ctx
->ac
.i32_0
);
3051 build_streamout(ctx
, &nggso
);
3054 /* Write shader query data. */
3055 tmp
= ac_get_arg(&ctx
->ac
, ctx
->args
->ngg_gs_state
);
3056 tmp
= LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3057 ac_build_ifcc(&ctx
->ac
, tmp
, 5109);
3058 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
,
3059 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3060 ac_build_ifcc(&ctx
->ac
, tmp
, 5110);
3062 tmp
= LLVMBuildLoad(builder
, ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tid
), "");
3064 ac_llvm_add_target_dep_function_attr(ctx
->main_function
,
3065 "amdgpu-gds-size", 256);
3067 LLVMTypeRef gdsptr
= LLVMPointerType(ctx
->ac
.i32
, AC_ADDR_SPACE_GDS
);
3068 LLVMValueRef gdsbase
= LLVMBuildIntToPtr(builder
, ctx
->ac
.i32_0
, gdsptr
, "");
3070 const char *sync_scope
= LLVM_VERSION_MAJOR
>= 9 ? "workgroup-one-as" : "workgroup";
3072 /* Use a plain GDS atomic to accumulate the number of generated
3075 ac_build_atomic_rmw(&ctx
->ac
, LLVMAtomicRMWBinOpAdd
, gdsbase
,
3078 ac_build_endif(&ctx
->ac
, 5110);
3079 ac_build_endif(&ctx
->ac
, 5109);
3083 /* Determine vertex liveness. */
3084 LLVMValueRef vertliveptr
= ac_build_alloca(&ctx
->ac
, ctx
->ac
.i1
, "vertexlive");
3086 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3087 ac_build_ifcc(&ctx
->ac
, tmp
, 5120);
3089 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3090 const LLVMValueRef primidx
=
3091 LLVMBuildAdd(builder
, tid
,
3092 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
3095 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, primidx
, num_emit_threads
, "");
3096 ac_build_ifcc(&ctx
->ac
, tmp
, 5121 + i
);
3099 /* Load primitive liveness */
3100 tmp
= ngg_gs_vertex_ptr(ctx
, primidx
);
3101 tmp
= LLVMBuildLoad(builder
,
3102 ngg_gs_get_emit_primflag_ptr(ctx
, tmp
, 0), "");
3103 const LLVMValueRef primlive
=
3104 LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3106 tmp
= LLVMBuildLoad(builder
, vertliveptr
, "");
3107 tmp
= LLVMBuildOr(builder
, tmp
, primlive
, ""),
3108 LLVMBuildStore(builder
, tmp
, vertliveptr
);
3111 ac_build_endif(&ctx
->ac
, 5121 + i
);
3114 ac_build_endif(&ctx
->ac
, 5120);
3116 /* Inclusive scan addition across the current wave. */
3117 LLVMValueRef vertlive
= LLVMBuildLoad(builder
, vertliveptr
, "");
3118 struct ac_wg_scan vertlive_scan
= {};
3119 vertlive_scan
.op
= nir_op_iadd
;
3120 vertlive_scan
.enable_reduce
= true;
3121 vertlive_scan
.enable_exclusive
= true;
3122 vertlive_scan
.src
= vertlive
;
3123 vertlive_scan
.scratch
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, ctx
->ac
.i32_0
);
3124 vertlive_scan
.waveidx
= get_wave_id_in_tg(ctx
);
3125 vertlive_scan
.numwaves
= get_tgsize(ctx
);
3126 vertlive_scan
.maxwaves
= 8;
3128 ac_build_wg_scan(&ctx
->ac
, &vertlive_scan
);
3130 /* Skip all exports (including index exports) when possible. At least on
3131 * early gfx10 revisions this is also to avoid hangs.
3133 LLVMValueRef have_exports
=
3134 LLVMBuildICmp(builder
, LLVMIntNE
, vertlive_scan
.result_reduce
, ctx
->ac
.i32_0
, "");
3136 LLVMBuildSelect(builder
, have_exports
, num_emit_threads
, ctx
->ac
.i32_0
, "");
3138 /* Allocate export space. Send this message as early as possible, to
3139 * hide the latency of the SQ <-> SPI roundtrip.
3141 * Note: We could consider compacting primitives for export as well.
3142 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3143 * prim data per clock and skips null primitives at no additional
3144 * cost. So compacting primitives can only be beneficial when
3145 * there are 4 or more contiguous null primitives in the export
3146 * (in the common case of single-dword prim exports).
3148 ac_build_sendmsg_gs_alloc_req(&ctx
->ac
, get_wave_id_in_tg(ctx
),
3149 vertlive_scan
.result_reduce
, num_emit_threads
);
3151 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3152 * of the primitive liveness flags, relying on the fact that each
3153 * threadgroup can have at most 256 threads. */
3154 ac_build_ifcc(&ctx
->ac
, vertlive
, 5130);
3156 tmp
= ngg_gs_vertex_ptr(ctx
, vertlive_scan
.result_exclusive
);
3157 tmp2
= LLVMBuildTrunc(builder
, tid
, ctx
->ac
.i8
, "");
3158 LLVMBuildStore(builder
, tmp2
,
3159 ngg_gs_get_emit_primflag_ptr(ctx
, tmp
, 1));
3161 ac_build_endif(&ctx
->ac
, 5130);
3163 ac_build_s_barrier(&ctx
->ac
);
3165 /* Export primitive data */
3166 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3167 ac_build_ifcc(&ctx
->ac
, tmp
, 5140);
3170 struct ac_ngg_prim prim
= {};
3171 prim
.num_vertices
= verts_per_prim
;
3173 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
3174 flags
= LLVMBuildLoad(builder
,
3175 ngg_gs_get_emit_primflag_ptr(ctx
, tmp
, 0), "");
3176 prim
.isnull
= LLVMBuildNot(builder
, LLVMBuildTrunc(builder
, flags
, ctx
->ac
.i1
, ""), "");
3178 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3179 prim
.index
[i
] = LLVMBuildSub(builder
, vertlive_scan
.result_exclusive
,
3180 LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
- i
- 1, false), "");
3181 prim
.edgeflag
[i
] = ctx
->ac
.i1false
;
3184 /* Geometry shaders output triangle strips, but NGG expects
3185 * triangles. We need to change the vertex order for odd
3186 * triangles to get correct front/back facing by swapping 2
3187 * vertex indices, but we also have to keep the provoking
3188 * vertex in the same place.
3190 if (verts_per_prim
== 3) {
3191 LLVMValueRef is_odd
= LLVMBuildLShr(builder
, flags
, ctx
->ac
.i8_1
, "");
3192 is_odd
= LLVMBuildTrunc(builder
, is_odd
, ctx
->ac
.i1
, "");
3194 struct ac_ngg_prim in
= prim
;
3195 prim
.index
[0] = in
.index
[0];
3196 prim
.index
[1] = LLVMBuildSelect(builder
, is_odd
,
3197 in
.index
[2], in
.index
[1], "");
3198 prim
.index
[2] = LLVMBuildSelect(builder
, is_odd
,
3199 in
.index
[1], in
.index
[2], "");
3202 ac_build_export_prim(&ctx
->ac
, &prim
);
3204 ac_build_endif(&ctx
->ac
, 5140);
3206 /* Export position and parameter data */
3207 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, vertlive_scan
.result_reduce
, "");
3208 ac_build_ifcc(&ctx
->ac
, tmp
, 5145);
3210 struct radv_vs_output_info
*outinfo
= &ctx
->args
->shader_info
->vs
.outinfo
;
3211 bool export_view_index
= ctx
->args
->options
->key
.has_multiview_view_index
;
3212 struct radv_shader_output_values
*outputs
;
3213 unsigned noutput
= 0;
3215 /* Allocate a temporary array for the output values. */
3216 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_view_index
;
3217 outputs
= calloc(num_outputs
, sizeof(outputs
[0]));
3219 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
3220 sizeof(outinfo
->vs_output_param_offset
));
3221 outinfo
->pos_exports
= 0;
3223 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
3224 tmp
= LLVMBuildLoad(builder
,
3225 ngg_gs_get_emit_primflag_ptr(ctx
, tmp
, 1), "");
3226 tmp
= LLVMBuildZExt(builder
, tmp
, ctx
->ac
.i32
, "");
3227 const LLVMValueRef vertexptr
= ngg_gs_vertex_ptr(ctx
, tmp
);
3229 unsigned out_idx
= 0;
3230 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3231 unsigned output_usage_mask
=
3232 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
3233 int length
= util_last_bit(output_usage_mask
);
3235 if (!(ctx
->output_mask
& (1ull << i
)))
3238 outputs
[noutput
].slot_name
= i
;
3239 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
3240 outputs
[noutput
].usage_mask
= output_usage_mask
;
3242 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
3243 if (!(output_usage_mask
& (1 << j
)))
3246 tmp
= ngg_gs_get_emit_output_ptr(ctx
, vertexptr
, out_idx
);
3247 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3249 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
3250 if (ac_get_type_size(type
) == 2) {
3251 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
3252 tmp
= LLVMBuildTrunc(ctx
->ac
.builder
, tmp
, ctx
->ac
.i16
, "");
3255 outputs
[noutput
].values
[j
] = ac_to_float(&ctx
->ac
, tmp
);
3258 for (unsigned j
= length
; j
< 4; j
++)
3259 outputs
[noutput
].values
[j
] = LLVMGetUndef(ctx
->ac
.f32
);
3264 /* Export ViewIndex. */
3265 if (export_view_index
) {
3266 outputs
[noutput
].slot_name
= VARYING_SLOT_LAYER
;
3267 outputs
[noutput
].slot_index
= 0;
3268 outputs
[noutput
].usage_mask
= 0x1;
3269 outputs
[noutput
].values
[0] =
3270 ac_to_float(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.view_index
));
3271 for (unsigned j
= 1; j
< 4; j
++)
3272 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
3276 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
,
3277 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
);
3280 ac_build_endif(&ctx
->ac
, 5145);
3283 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
3285 LLVMValueRef vertexidx
,
3286 LLVMValueRef
*addrs
)
3288 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3291 const LLVMValueRef vertexptr
=
3292 ngg_gs_emit_vertex_ptr(ctx
, get_thread_id_in_tg(ctx
), vertexidx
);
3293 unsigned out_idx
= 0;
3294 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3295 unsigned output_usage_mask
=
3296 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
3297 uint8_t output_stream
=
3298 ctx
->args
->shader_info
->gs
.output_streams
[i
];
3299 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
3300 int length
= util_last_bit(output_usage_mask
);
3302 if (!(ctx
->output_mask
& (1ull << i
)) ||
3303 output_stream
!= stream
)
3306 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
3307 if (!(output_usage_mask
& (1 << j
)))
3310 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
3312 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
3313 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
3315 LLVMBuildStore(builder
, out_val
,
3316 ngg_gs_get_emit_output_ptr(ctx
, vertexptr
, out_idx
));
3319 assert(out_idx
* 4 <= ctx
->args
->shader_info
->gs
.gsvs_vertex_size
);
3321 /* Store the current number of emitted vertices to zero out remaining
3322 * primitive flags in case the geometry shader doesn't emit the maximum
3323 * number of vertices.
3325 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
3326 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
3328 /* Determine and store whether this vertex completed a primitive. */
3329 const LLVMValueRef curverts
= LLVMBuildLoad(builder
, ctx
->gs_curprim_verts
[stream
], "");
3331 tmp
= LLVMConstInt(ctx
->ac
.i32
, si_conv_gl_prim_to_vertices(ctx
->shader
->info
.gs
.output_primitive
) - 1, false);
3332 const LLVMValueRef iscompleteprim
=
3333 LLVMBuildICmp(builder
, LLVMIntUGE
, curverts
, tmp
, "");
3335 /* Since the geometry shader emits triangle strips, we need to
3336 * track which primitive is odd and swap vertex indices to get
3337 * the correct vertex order.
3339 LLVMValueRef is_odd
= ctx
->ac
.i1false
;
3341 si_conv_gl_prim_to_vertices(ctx
->shader
->info
.gs
.output_primitive
) == 3) {
3342 tmp
= LLVMBuildAnd(builder
, curverts
, ctx
->ac
.i32_1
, "");
3343 is_odd
= LLVMBuildICmp(builder
, LLVMIntEQ
, tmp
, ctx
->ac
.i32_1
, "");
3346 tmp
= LLVMBuildAdd(builder
, curverts
, ctx
->ac
.i32_1
, "");
3347 LLVMBuildStore(builder
, tmp
, ctx
->gs_curprim_verts
[stream
]);
3349 /* The per-vertex primitive flag encoding:
3350 * bit 0: whether this vertex finishes a primitive
3351 * bit 1: whether the primitive is odd (if we are emitting triangle strips)
3353 tmp
= LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i8
, "");
3354 tmp
= LLVMBuildOr(builder
, tmp
,
3355 LLVMBuildShl(builder
,
3356 LLVMBuildZExt(builder
, is_odd
, ctx
->ac
.i8
, ""),
3357 ctx
->ac
.i8_1
, ""), "");
3358 LLVMBuildStore(builder
, tmp
,
3359 ngg_gs_get_emit_primflag_ptr(ctx
, vertexptr
, stream
));
3361 tmp
= LLVMBuildLoad(builder
, ctx
->gs_generated_prims
[stream
], "");
3362 tmp
= LLVMBuildAdd(builder
, tmp
, LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i32
, ""), "");
3363 LLVMBuildStore(builder
, tmp
, ctx
->gs_generated_prims
[stream
]);
3367 write_tess_factors(struct radv_shader_context
*ctx
)
3369 unsigned stride
, outer_comps
, inner_comps
;
3370 LLVMValueRef tcs_rel_ids
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_rel_ids
);
3371 LLVMValueRef invocation_id
= ac_unpack_param(&ctx
->ac
, tcs_rel_ids
, 8, 5);
3372 LLVMValueRef rel_patch_id
= ac_unpack_param(&ctx
->ac
, tcs_rel_ids
, 0, 8);
3373 unsigned tess_inner_index
= 0, tess_outer_index
;
3374 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
3375 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
3377 ac_emit_barrier(&ctx
->ac
, ctx
->stage
);
3379 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
3399 ac_build_ifcc(&ctx
->ac
,
3400 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3401 invocation_id
, ctx
->ac
.i32_0
, ""), 6503);
3403 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
3406 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3407 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3408 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
3411 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3412 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3413 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
3415 for (i
= 0; i
< 4; i
++) {
3416 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3417 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3421 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
3422 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
3423 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3425 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
3427 for (i
= 0; i
< outer_comps
; i
++) {
3429 ac_lds_load(&ctx
->ac
, lds_outer
);
3430 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3433 for (i
= 0; i
< inner_comps
; i
++) {
3434 inner
[i
] = out
[outer_comps
+i
] =
3435 ac_lds_load(&ctx
->ac
, lds_inner
);
3436 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
3441 /* Convert the outputs to vectors for stores. */
3442 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
3446 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
3449 buffer
= ctx
->hs_ring_tess_factor
;
3450 tf_base
= ac_get_arg(&ctx
->ac
, ctx
->args
->tess_factor_offset
);
3451 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
3452 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
3453 unsigned tf_offset
= 0;
3455 if (ctx
->ac
.chip_class
<= GFX8
) {
3456 ac_build_ifcc(&ctx
->ac
,
3457 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3458 rel_patch_id
, ctx
->ac
.i32_0
, ""), 6504);
3460 /* Store the dynamic HS control word. */
3461 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
3462 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
3463 1, ctx
->ac
.i32_0
, tf_base
,
3467 ac_build_endif(&ctx
->ac
, 6504);
3470 /* Store the tessellation factors. */
3471 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
3472 MIN2(stride
, 4), byteoffset
, tf_base
,
3475 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
3476 stride
- 4, byteoffset
, tf_base
,
3477 16 + tf_offset
, ac_glc
);
3479 //store to offchip for TES to read - only if TES reads them
3480 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
3481 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
3482 LLVMValueRef tf_inner_offset
;
3483 unsigned param_outer
, param_inner
;
3485 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3486 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3487 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
3489 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
3490 util_next_power_of_two(outer_comps
));
3492 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
3493 outer_comps
, tf_outer_offset
,
3494 ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
),
3497 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3498 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3499 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
3501 inner_vec
= inner_comps
== 1 ? inner
[0] :
3502 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
3503 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
3504 inner_comps
, tf_inner_offset
,
3505 ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
),
3510 ac_build_endif(&ctx
->ac
, 6503);
3514 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
3516 write_tess_factors(ctx
);
3520 si_export_mrt_color(struct radv_shader_context
*ctx
,
3521 LLVMValueRef
*color
, unsigned index
,
3522 struct ac_export_args
*args
)
3525 si_llvm_init_export_args(ctx
, color
, 0xf,
3526 V_008DFC_SQ_EXP_MRT
+ index
, args
);
3527 if (!args
->enabled_channels
)
3528 return false; /* unnecessary NULL export */
3534 radv_export_mrt_z(struct radv_shader_context
*ctx
,
3535 LLVMValueRef depth
, LLVMValueRef stencil
,
3536 LLVMValueRef samplemask
)
3538 struct ac_export_args args
;
3540 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
3542 ac_build_export(&ctx
->ac
, &args
);
3546 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
3549 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3550 struct ac_export_args color_args
[8];
3552 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3553 LLVMValueRef values
[4];
3555 if (!(ctx
->output_mask
& (1ull << i
)))
3558 if (i
< FRAG_RESULT_DATA0
)
3561 for (unsigned j
= 0; j
< 4; j
++)
3562 values
[j
] = ac_to_float(&ctx
->ac
,
3563 radv_load_output(ctx
, i
, j
));
3565 bool ret
= si_export_mrt_color(ctx
, values
,
3566 i
- FRAG_RESULT_DATA0
,
3567 &color_args
[index
]);
3572 /* Process depth, stencil, samplemask. */
3573 if (ctx
->args
->shader_info
->ps
.writes_z
) {
3574 depth
= ac_to_float(&ctx
->ac
,
3575 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
3577 if (ctx
->args
->shader_info
->ps
.writes_stencil
) {
3578 stencil
= ac_to_float(&ctx
->ac
,
3579 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
3581 if (ctx
->args
->shader_info
->ps
.writes_sample_mask
) {
3582 samplemask
= ac_to_float(&ctx
->ac
,
3583 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
3586 /* Set the DONE bit on last non-null color export only if Z isn't
3590 !ctx
->args
->shader_info
->ps
.writes_z
&&
3591 !ctx
->args
->shader_info
->ps
.writes_stencil
&&
3592 !ctx
->args
->shader_info
->ps
.writes_sample_mask
) {
3593 unsigned last
= index
- 1;
3595 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
3596 color_args
[last
].done
= 1; /* DONE bit */
3599 /* Export PS outputs. */
3600 for (unsigned i
= 0; i
< index
; i
++)
3601 ac_build_export(&ctx
->ac
, &color_args
[i
]);
3603 if (depth
|| stencil
|| samplemask
)
3604 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
3606 ac_build_export_null(&ctx
->ac
);
3610 emit_gs_epilogue(struct radv_shader_context
*ctx
)
3612 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
3613 gfx10_ngg_gs_emit_epilogue_1(ctx
);
3617 if (ctx
->ac
.chip_class
>= GFX10
)
3618 LLVMBuildFence(ctx
->ac
.builder
, LLVMAtomicOrderingRelease
, false, "");
3620 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
3624 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
3625 LLVMValueRef
*addrs
)
3627 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
3629 switch (ctx
->stage
) {
3630 case MESA_SHADER_VERTEX
:
3631 if (ctx
->args
->options
->key
.vs_common_out
.as_ls
)
3632 handle_ls_outputs_post(ctx
);
3633 else if (ctx
->args
->options
->key
.vs_common_out
.as_es
)
3634 handle_es_outputs_post(ctx
, &ctx
->args
->shader_info
->vs
.es_info
);
3635 else if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
)
3636 handle_ngg_outputs_post_1(ctx
);
3638 handle_vs_outputs_post(ctx
, ctx
->args
->options
->key
.vs_common_out
.export_prim_id
,
3639 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
,
3640 &ctx
->args
->shader_info
->vs
.outinfo
);
3642 case MESA_SHADER_FRAGMENT
:
3643 handle_fs_outputs_post(ctx
);
3645 case MESA_SHADER_GEOMETRY
:
3646 emit_gs_epilogue(ctx
);
3648 case MESA_SHADER_TESS_CTRL
:
3649 handle_tcs_outputs_post(ctx
);
3651 case MESA_SHADER_TESS_EVAL
:
3652 if (ctx
->args
->options
->key
.vs_common_out
.as_es
)
3653 handle_es_outputs_post(ctx
, &ctx
->args
->shader_info
->tes
.es_info
);
3654 else if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
)
3655 handle_ngg_outputs_post_1(ctx
);
3657 handle_vs_outputs_post(ctx
, ctx
->args
->options
->key
.vs_common_out
.export_prim_id
,
3658 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
,
3659 &ctx
->args
->shader_info
->tes
.outinfo
);
3666 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
,
3667 LLVMPassManagerRef passmgr
,
3668 const struct radv_nir_compiler_options
*options
)
3670 LLVMRunPassManager(passmgr
, ctx
->ac
.module
);
3671 LLVMDisposeBuilder(ctx
->ac
.builder
);
3673 ac_llvm_context_dispose(&ctx
->ac
);
3677 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
3679 struct radv_vs_output_info
*outinfo
;
3681 switch (ctx
->stage
) {
3682 case MESA_SHADER_FRAGMENT
:
3683 case MESA_SHADER_COMPUTE
:
3684 case MESA_SHADER_TESS_CTRL
:
3685 case MESA_SHADER_GEOMETRY
:
3687 case MESA_SHADER_VERTEX
:
3688 if (ctx
->args
->options
->key
.vs_common_out
.as_ls
||
3689 ctx
->args
->options
->key
.vs_common_out
.as_es
)
3691 outinfo
= &ctx
->args
->shader_info
->vs
.outinfo
;
3693 case MESA_SHADER_TESS_EVAL
:
3694 if (ctx
->args
->options
->key
.vs_common_out
.as_es
)
3696 outinfo
= &ctx
->args
->shader_info
->tes
.outinfo
;
3699 unreachable("Unhandled shader type");
3702 ac_optimize_vs_outputs(&ctx
->ac
,
3704 outinfo
->vs_output_param_offset
,
3705 VARYING_SLOT_MAX
, 0,
3706 &outinfo
->param_exports
);
3710 ac_setup_rings(struct radv_shader_context
*ctx
)
3712 if (ctx
->args
->options
->chip_class
<= GFX8
&&
3713 (ctx
->stage
== MESA_SHADER_GEOMETRY
||
3714 ctx
->args
->options
->key
.vs_common_out
.as_es
)) {
3715 unsigned ring
= ctx
->stage
== MESA_SHADER_GEOMETRY
? RING_ESGS_GS
3717 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, ring
, false);
3719 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
,
3724 if (ctx
->args
->is_gs_copy_shader
) {
3726 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3727 LLVMConstInt(ctx
->ac
.i32
,
3728 RING_GSVS_VS
, false));
3731 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3732 /* The conceptual layout of the GSVS ring is
3733 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3734 * but the real memory layout is swizzled across
3736 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3738 * Override the buffer descriptor accordingly.
3740 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->ac
.i64
, 2);
3741 uint64_t stream_offset
= 0;
3742 unsigned num_records
= ctx
->ac
.wave_size
;
3743 LLVMValueRef base_ring
;
3746 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3747 LLVMConstInt(ctx
->ac
.i32
,
3748 RING_GSVS_GS
, false));
3750 for (unsigned stream
= 0; stream
< 4; stream
++) {
3751 unsigned num_components
, stride
;
3752 LLVMValueRef ring
, tmp
;
3755 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
3757 if (!num_components
)
3760 stride
= 4 * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
3762 /* Limit on the stride field for <= GFX7. */
3763 assert(stride
< (1 << 14));
3765 ring
= LLVMBuildBitCast(ctx
->ac
.builder
,
3766 base_ring
, v2i64
, "");
3767 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
3768 ring
, ctx
->ac
.i32_0
, "");
3769 tmp
= LLVMBuildAdd(ctx
->ac
.builder
, tmp
,
3770 LLVMConstInt(ctx
->ac
.i64
,
3771 stream_offset
, 0), "");
3772 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
,
3773 ring
, tmp
, ctx
->ac
.i32_0
, "");
3775 stream_offset
+= stride
* ctx
->ac
.wave_size
;
3777 ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ring
,
3780 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ring
,
3782 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
,
3783 LLVMConstInt(ctx
->ac
.i32
,
3784 S_008F04_STRIDE(stride
), false), "");
3785 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
, tmp
,
3788 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
,
3789 LLVMConstInt(ctx
->ac
.i32
,
3790 num_records
, false),
3791 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
3793 ctx
->gsvs_ring
[stream
] = ring
;
3797 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3798 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3799 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
3800 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
3805 radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
3806 gl_shader_stage stage
,
3807 const struct nir_shader
*nir
)
3809 const unsigned backup_sizes
[] = {chip_class
>= GFX9
? 128 : 64, 1, 1};
3811 for (unsigned i
= 0; i
< 3; i
++)
3812 sizes
[i
] = nir
? nir
->info
.cs
.local_size
[i
] : backup_sizes
[i
];
3813 return radv_get_max_workgroup_size(chip_class
, stage
, sizes
);
3816 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3817 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
3819 LLVMValueRef count
=
3820 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 8, 8);
3821 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
3823 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
,
3824 ac_get_arg(&ctx
->ac
, ctx
->args
->rel_auto_id
),
3825 ctx
->abi
.instance_id
, "");
3826 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
,
3827 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_rel_ids
),
3830 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
,
3831 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_patch_id
),
3832 ctx
->abi
.vertex_id
, "");
3835 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
, bool merged
)
3838 for(int i
= 5; i
>= 0; --i
) {
3839 ctx
->gs_vtx_offset
[i
] =
3840 ac_unpack_param(&ctx
->ac
,
3841 ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[i
& ~1]),
3845 ctx
->gs_wave_id
= ac_unpack_param(&ctx
->ac
,
3846 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
),
3849 for (int i
= 0; i
< 6; i
++)
3850 ctx
->gs_vtx_offset
[i
] = ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[i
]);
3851 ctx
->gs_wave_id
= ac_get_arg(&ctx
->ac
, ctx
->args
->gs_wave_id
);
3855 /* Ensure that the esgs ring is declared.
3857 * We declare it with 64KB alignment as a hint that the
3858 * pointer value will always be 0.
3860 static void declare_esgs_ring(struct radv_shader_context
*ctx
)
3865 assert(!LLVMGetNamedGlobal(ctx
->ac
.module
, "esgs_ring"));
3867 ctx
->esgs_ring
= LLVMAddGlobalInAddressSpace(
3868 ctx
->ac
.module
, LLVMArrayType(ctx
->ac
.i32
, 0),
3871 LLVMSetLinkage(ctx
->esgs_ring
, LLVMExternalLinkage
);
3872 LLVMSetAlignment(ctx
->esgs_ring
, 64 * 1024);
3876 LLVMModuleRef
ac_translate_nir_to_llvm(struct ac_llvm_compiler
*ac_llvm
,
3877 struct nir_shader
*const *shaders
,
3879 const struct radv_shader_args
*args
)
3881 struct radv_shader_context ctx
= {0};
3884 enum ac_float_mode float_mode
= AC_FLOAT_MODE_DEFAULT
;
3886 if (args
->shader_info
->float_controls_mode
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
) {
3887 float_mode
= AC_FLOAT_MODE_DENORM_FLUSH_TO_ZERO
;
3890 ac_llvm_context_init(&ctx
.ac
, ac_llvm
, args
->options
->chip_class
,
3891 args
->options
->family
, float_mode
,
3892 args
->shader_info
->wave_size
,
3893 args
->shader_info
->ballot_bit_size
);
3894 ctx
.context
= ctx
.ac
.context
;
3896 ctx
.max_workgroup_size
= 0;
3897 for (int i
= 0; i
< shader_count
; ++i
) {
3898 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
3899 radv_nir_get_max_workgroup_size(args
->options
->chip_class
,
3900 shaders
[i
]->info
.stage
,
3904 if (ctx
.ac
.chip_class
>= GFX10
) {
3905 if (is_pre_gs_stage(shaders
[0]->info
.stage
) &&
3906 args
->options
->key
.vs_common_out
.as_ngg
) {
3907 ctx
.max_workgroup_size
= 128;
3911 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2);
3913 ctx
.abi
.inputs
= &ctx
.inputs
[0];
3914 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
3915 ctx
.abi
.emit_vertex_with_counter
= visit_emit_vertex_with_counter
;
3916 ctx
.abi
.load_ubo
= radv_load_ubo
;
3917 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
3918 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
3919 ctx
.abi
.load_resource
= radv_load_resource
;
3920 ctx
.abi
.clamp_shadow_reference
= false;
3921 ctx
.abi
.robust_buffer_access
= args
->options
->robust_buffer_access
;
3923 bool is_ngg
= is_pre_gs_stage(shaders
[0]->info
.stage
) && args
->options
->key
.vs_common_out
.as_ngg
;
3924 if (shader_count
>= 2 || is_ngg
)
3925 ac_init_exec_full_mask(&ctx
.ac
);
3927 if (args
->ac
.vertex_id
.used
)
3928 ctx
.abi
.vertex_id
= ac_get_arg(&ctx
.ac
, args
->ac
.vertex_id
);
3929 if (args
->rel_auto_id
.used
)
3930 ctx
.rel_auto_id
= ac_get_arg(&ctx
.ac
, args
->rel_auto_id
);
3931 if (args
->ac
.instance_id
.used
)
3932 ctx
.abi
.instance_id
= ac_get_arg(&ctx
.ac
, args
->ac
.instance_id
);
3934 if (args
->options
->has_ls_vgpr_init_bug
&&
3935 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
3936 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
3939 /* Declare scratch space base for streamout and vertex
3940 * compaction. Whether space is actually allocated is
3941 * determined during linking / PM4 creation.
3943 * Add an extra dword per vertex to ensure an odd stride, which
3944 * avoids bank conflicts for SoA accesses.
3946 if (!args
->options
->key
.vs_common_out
.as_ngg_passthrough
)
3947 declare_esgs_ring(&ctx
);
3949 /* This is really only needed when streamout and / or vertex
3950 * compaction is enabled.
3952 if (args
->shader_info
->so
.num_outputs
) {
3953 LLVMTypeRef asi32
= LLVMArrayType(ctx
.ac
.i32
, 8);
3954 ctx
.gs_ngg_scratch
= LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
3955 asi32
, "ngg_scratch", AC_ADDR_SPACE_LDS
);
3956 LLVMSetInitializer(ctx
.gs_ngg_scratch
, LLVMGetUndef(asi32
));
3957 LLVMSetAlignment(ctx
.gs_ngg_scratch
, 4);
3961 for(int i
= 0; i
< shader_count
; ++i
) {
3962 ctx
.stage
= shaders
[i
]->info
.stage
;
3963 ctx
.shader
= shaders
[i
];
3964 ctx
.output_mask
= 0;
3966 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
3967 for (int i
= 0; i
< 4; i
++) {
3968 ctx
.gs_next_vertex
[i
] =
3969 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
3971 if (args
->options
->key
.vs_common_out
.as_ngg
) {
3972 for (unsigned i
= 0; i
< 4; ++i
) {
3973 ctx
.gs_curprim_verts
[i
] =
3974 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
3975 ctx
.gs_generated_prims
[i
] =
3976 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
3979 unsigned scratch_size
= 8;
3980 if (args
->shader_info
->so
.num_outputs
)
3983 LLVMTypeRef ai32
= LLVMArrayType(ctx
.ac
.i32
, scratch_size
);
3984 ctx
.gs_ngg_scratch
=
3985 LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
3986 ai32
, "ngg_scratch", AC_ADDR_SPACE_LDS
);
3987 LLVMSetInitializer(ctx
.gs_ngg_scratch
, LLVMGetUndef(ai32
));
3988 LLVMSetAlignment(ctx
.gs_ngg_scratch
, 4);
3990 ctx
.gs_ngg_emit
= LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
3991 LLVMArrayType(ctx
.ac
.i32
, 0), "ngg_emit", AC_ADDR_SPACE_LDS
);
3992 LLVMSetLinkage(ctx
.gs_ngg_emit
, LLVMExternalLinkage
);
3993 LLVMSetAlignment(ctx
.gs_ngg_emit
, 4);
3996 ctx
.abi
.load_inputs
= load_gs_input
;
3997 ctx
.abi
.emit_primitive
= visit_end_primitive
;
3998 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3999 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
4000 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4001 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
4002 if (shader_count
== 1)
4003 ctx
.tcs_num_inputs
= args
->options
->key
.tcs
.num_inputs
;
4005 ctx
.tcs_num_inputs
= util_last_bit64(args
->shader_info
->vs
.ls_outputs_written
);
4006 unsigned tcs_num_outputs
= util_last_bit64(ctx
.args
->shader_info
->tcs
.outputs_written
);
4007 unsigned tcs_num_patch_outputs
= util_last_bit64(ctx
.args
->shader_info
->tcs
.patch_outputs_written
);
4008 ctx
.tcs_num_patches
=
4009 get_tcs_num_patches(
4010 ctx
.args
->options
->key
.tcs
.input_vertices
,
4011 ctx
.shader
->info
.tess
.tcs_vertices_out
,
4014 tcs_num_patch_outputs
,
4015 ctx
.args
->options
->tess_offchip_block_dw_size
,
4016 ctx
.args
->options
->chip_class
,
4017 ctx
.args
->options
->family
);
4018 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4019 ctx
.abi
.load_tess_varyings
= load_tes_input
;
4020 ctx
.abi
.load_tess_coord
= load_tess_coord
;
4021 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4022 ctx
.tcs_num_patches
= args
->options
->key
.tes
.num_patches
;
4023 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
4024 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
4025 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
4026 ctx
.abi
.load_sample_position
= load_sample_position
;
4027 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
4030 if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&&
4031 args
->options
->key
.vs_common_out
.as_ngg
&&
4032 args
->options
->key
.vs_common_out
.export_prim_id
) {
4033 declare_esgs_ring(&ctx
);
4036 bool nested_barrier
= false;
4039 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4040 args
->options
->key
.vs_common_out
.as_ngg
) {
4041 gfx10_ngg_gs_emit_prologue(&ctx
);
4042 nested_barrier
= false;
4044 nested_barrier
= true;
4048 if (nested_barrier
) {
4049 /* Execute a barrier before the second shader in
4052 * Execute the barrier inside the conditional block,
4053 * so that empty waves can jump directly to s_endpgm,
4054 * which will also signal the barrier.
4056 * This is possible in gfx9, because an empty wave
4057 * for the second shader does not participate in
4058 * the epilogue. With NGG, empty waves may still
4059 * be required to export data (e.g. GS output vertices),
4060 * so we cannot let them exit early.
4062 * If the shader is TCS and the TCS epilog is present
4063 * and contains a barrier, it will wait there and then
4066 ac_emit_barrier(&ctx
.ac
, ctx
.stage
);
4069 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
4070 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
4072 ac_setup_rings(&ctx
);
4074 LLVMBasicBlockRef merge_block
= NULL
;
4075 if (shader_count
>= 2 || is_ngg
) {
4076 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
4077 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4078 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4080 LLVMValueRef count
=
4081 ac_unpack_param(&ctx
.ac
,
4082 ac_get_arg(&ctx
.ac
, args
->merged_wave_info
),
4084 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
4085 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
4086 thread_id
, count
, "");
4087 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
4089 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
4092 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
4093 prepare_interp_optimize(&ctx
, shaders
[i
]);
4094 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
4095 handle_vs_inputs(&ctx
, shaders
[i
]);
4096 else if(shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
4097 prepare_gs_input_vgprs(&ctx
, shader_count
>= 2);
4099 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, &args
->ac
, shaders
[i
]);
4101 if (shader_count
>= 2 || is_ngg
) {
4102 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
4103 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
4106 /* This needs to be outside the if wrapping the shader body, as sometimes
4107 * the HW generates waves with 0 es/vs threads. */
4108 if (is_pre_gs_stage(shaders
[i
]->info
.stage
) &&
4109 args
->options
->key
.vs_common_out
.as_ngg
&&
4110 i
== shader_count
- 1) {
4111 handle_ngg_outputs_post_2(&ctx
);
4112 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4113 args
->options
->key
.vs_common_out
.as_ngg
) {
4114 gfx10_ngg_gs_emit_epilogue_2(&ctx
);
4117 if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4118 unsigned tcs_num_outputs
= util_last_bit64(ctx
.args
->shader_info
->tcs
.outputs_written
);
4119 unsigned tcs_num_patch_outputs
= util_last_bit64(ctx
.args
->shader_info
->tcs
.patch_outputs_written
);
4120 args
->shader_info
->tcs
.num_patches
= ctx
.tcs_num_patches
;
4121 args
->shader_info
->tcs
.lds_size
=
4122 calculate_tess_lds_size(
4123 ctx
.args
->options
->key
.tcs
.input_vertices
,
4124 ctx
.shader
->info
.tess
.tcs_vertices_out
,
4126 ctx
.tcs_num_patches
,
4128 tcs_num_patch_outputs
);
4132 LLVMBuildRetVoid(ctx
.ac
.builder
);
4134 if (args
->options
->dump_preoptir
) {
4135 fprintf(stderr
, "%s LLVM IR:\n\n",
4136 radv_get_shader_name(args
->shader_info
,
4137 shaders
[shader_count
- 1]->info
.stage
));
4138 ac_dump_module(ctx
.ac
.module
);
4139 fprintf(stderr
, "\n");
4142 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, args
->options
);
4144 if (shader_count
== 1)
4145 ac_nir_eliminate_const_vs_outputs(&ctx
);
4147 if (args
->options
->dump_shader
) {
4148 args
->shader_info
->private_mem_vgprs
=
4149 ac_count_scratch_private_memory(ctx
.main_function
);
4152 return ctx
.ac
.module
;
4155 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
4157 unsigned *retval
= (unsigned *)context
;
4158 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
4159 char *description
= LLVMGetDiagInfoDescription(di
);
4161 if (severity
== LLVMDSError
) {
4163 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
4167 LLVMDisposeMessage(description
);
4170 static unsigned radv_llvm_compile(LLVMModuleRef M
,
4171 char **pelf_buffer
, size_t *pelf_size
,
4172 struct ac_llvm_compiler
*ac_llvm
)
4174 unsigned retval
= 0;
4175 LLVMContextRef llvm_ctx
;
4177 /* Setup Diagnostic Handler*/
4178 llvm_ctx
= LLVMGetModuleContext(M
);
4180 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
4184 if (!radv_compile_to_elf(ac_llvm
, M
, pelf_buffer
, pelf_size
))
4189 static void ac_compile_llvm_module(struct ac_llvm_compiler
*ac_llvm
,
4190 LLVMModuleRef llvm_module
,
4191 struct radv_shader_binary
**rbinary
,
4192 gl_shader_stage stage
,
4194 const struct radv_nir_compiler_options
*options
)
4196 char *elf_buffer
= NULL
;
4197 size_t elf_size
= 0;
4198 char *llvm_ir_string
= NULL
;
4200 if (options
->dump_shader
) {
4201 fprintf(stderr
, "%s LLVM IR:\n\n", name
);
4202 ac_dump_module(llvm_module
);
4203 fprintf(stderr
, "\n");
4206 if (options
->record_ir
) {
4207 char *llvm_ir
= LLVMPrintModuleToString(llvm_module
);
4208 llvm_ir_string
= strdup(llvm_ir
);
4209 LLVMDisposeMessage(llvm_ir
);
4212 int v
= radv_llvm_compile(llvm_module
, &elf_buffer
, &elf_size
, ac_llvm
);
4214 fprintf(stderr
, "compile failed\n");
4217 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
4218 LLVMDisposeModule(llvm_module
);
4219 LLVMContextDispose(ctx
);
4221 size_t llvm_ir_size
= llvm_ir_string
? strlen(llvm_ir_string
) : 0;
4222 size_t alloc_size
= sizeof(struct radv_shader_binary_rtld
) + elf_size
+ llvm_ir_size
+ 1;
4223 struct radv_shader_binary_rtld
*rbin
= calloc(1, alloc_size
);
4224 memcpy(rbin
->data
, elf_buffer
, elf_size
);
4226 memcpy(rbin
->data
+ elf_size
, llvm_ir_string
, llvm_ir_size
+ 1);
4228 rbin
->base
.type
= RADV_BINARY_TYPE_RTLD
;
4229 rbin
->base
.stage
= stage
;
4230 rbin
->base
.total_size
= alloc_size
;
4231 rbin
->elf_size
= elf_size
;
4232 rbin
->llvm_ir_size
= llvm_ir_size
;
4233 *rbinary
= &rbin
->base
;
4235 free(llvm_ir_string
);
4240 radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
4241 struct radv_shader_binary
**rbinary
,
4242 const struct radv_shader_args
*args
,
4243 struct nir_shader
*const *nir
,
4247 LLVMModuleRef llvm_module
;
4249 llvm_module
= ac_translate_nir_to_llvm(ac_llvm
, nir
, nir_count
, args
);
4251 ac_compile_llvm_module(ac_llvm
, llvm_module
, rbinary
,
4252 nir
[nir_count
- 1]->info
.stage
,
4253 radv_get_shader_name(args
->shader_info
,
4254 nir
[nir_count
- 1]->info
.stage
),
4257 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4258 if (args
->options
->chip_class
>= GFX9
) {
4259 if (nir_count
== 2 &&
4260 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4261 args
->shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
4267 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
4269 LLVMValueRef vtx_offset
=
4270 LLVMBuildMul(ctx
->ac
.builder
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.vertex_id
),
4271 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4272 LLVMValueRef stream_id
;
4274 /* Fetch the vertex stream ID. */
4275 if (!ctx
->args
->options
->use_ngg_streamout
&&
4276 ctx
->args
->shader_info
->so
.num_outputs
) {
4278 ac_unpack_param(&ctx
->ac
,
4279 ac_get_arg(&ctx
->ac
,
4280 ctx
->args
->streamout_config
),
4283 stream_id
= ctx
->ac
.i32_0
;
4286 LLVMBasicBlockRef end_bb
;
4287 LLVMValueRef switch_inst
;
4289 end_bb
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
,
4290 ctx
->main_function
, "end");
4291 switch_inst
= LLVMBuildSwitch(ctx
->ac
.builder
, stream_id
, end_bb
, 4);
4293 for (unsigned stream
= 0; stream
< 4; stream
++) {
4294 unsigned num_components
=
4295 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
4296 LLVMBasicBlockRef bb
;
4299 if (stream
> 0 && !num_components
)
4302 if (stream
> 0 && !ctx
->args
->shader_info
->so
.num_outputs
)
4305 bb
= LLVMInsertBasicBlockInContext(ctx
->ac
.context
, end_bb
, "out");
4306 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
->ac
.i32
, stream
, 0), bb
);
4307 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, bb
);
4310 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4311 unsigned output_usage_mask
=
4312 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
4313 unsigned output_stream
=
4314 ctx
->args
->shader_info
->gs
.output_streams
[i
];
4315 int length
= util_last_bit(output_usage_mask
);
4317 if (!(ctx
->output_mask
& (1ull << i
)) ||
4318 output_stream
!= stream
)
4321 for (unsigned j
= 0; j
< length
; j
++) {
4322 LLVMValueRef value
, soffset
;
4324 if (!(output_usage_mask
& (1 << j
)))
4327 soffset
= LLVMConstInt(ctx
->ac
.i32
,
4329 ctx
->shader
->info
.gs
.vertices_out
* 16 * 4, false);
4333 value
= ac_build_buffer_load(&ctx
->ac
,
4336 vtx_offset
, soffset
,
4337 0, ac_glc
| ac_slc
, true, false);
4339 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4340 if (ac_get_type_size(type
) == 2) {
4341 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
4342 value
= LLVMBuildTrunc(ctx
->ac
.builder
, value
, ctx
->ac
.i16
, "");
4345 LLVMBuildStore(ctx
->ac
.builder
,
4346 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4350 if (!ctx
->args
->options
->use_ngg_streamout
&&
4351 ctx
->args
->shader_info
->so
.num_outputs
)
4352 radv_emit_streamout(ctx
, stream
);
4355 handle_vs_outputs_post(ctx
, false, true,
4356 &ctx
->args
->shader_info
->vs
.outinfo
);
4359 LLVMBuildBr(ctx
->ac
.builder
, end_bb
);
4362 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, end_bb
);
4366 radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
4367 struct nir_shader
*geom_shader
,
4368 struct radv_shader_binary
**rbinary
,
4369 const struct radv_shader_args
*args
)
4371 struct radv_shader_context ctx
= {0};
4374 assert(args
->is_gs_copy_shader
);
4376 ac_llvm_context_init(&ctx
.ac
, ac_llvm
, args
->options
->chip_class
,
4377 args
->options
->family
, AC_FLOAT_MODE_DEFAULT
, 64, 64);
4378 ctx
.context
= ctx
.ac
.context
;
4380 ctx
.stage
= MESA_SHADER_VERTEX
;
4381 ctx
.shader
= geom_shader
;
4383 create_function(&ctx
, MESA_SHADER_VERTEX
, false);
4385 ac_setup_rings(&ctx
);
4387 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
4388 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
4389 ac_handle_shader_output_decl(&ctx
.ac
, &ctx
.abi
, geom_shader
,
4390 variable
, MESA_SHADER_VERTEX
);
4393 ac_gs_copy_shader_emit(&ctx
);
4395 LLVMBuildRetVoid(ctx
.ac
.builder
);
4397 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, args
->options
);
4399 ac_compile_llvm_module(ac_llvm
, ctx
.ac
.module
, rbinary
,
4400 MESA_SHADER_VERTEX
, "GS Copy Shader", args
->options
);
4401 (*rbinary
)->is_gs_copy_shader
= true;
4406 llvm_compile_shader(struct radv_device
*device
,
4407 unsigned shader_count
,
4408 struct nir_shader
*const *shaders
,
4409 struct radv_shader_binary
**binary
,
4410 struct radv_shader_args
*args
)
4412 enum ac_target_machine_options tm_options
= 0;
4413 struct ac_llvm_compiler ac_llvm
;
4414 bool thread_compiler
;
4416 tm_options
|= AC_TM_SUPPORTS_SPILL
;
4417 if (args
->options
->check_ir
)
4418 tm_options
|= AC_TM_CHECK_IR
;
4419 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_LOAD_STORE_OPT
)
4420 tm_options
|= AC_TM_NO_LOAD_STORE_OPT
;
4422 thread_compiler
= !(device
->instance
->debug_flags
& RADV_DEBUG_NOTHREADLLVM
);
4424 radv_init_llvm_compiler(&ac_llvm
, thread_compiler
,
4425 args
->options
->family
, tm_options
,
4426 args
->shader_info
->wave_size
);
4428 if (args
->is_gs_copy_shader
) {
4429 radv_compile_gs_copy_shader(&ac_llvm
, *shaders
, binary
, args
);
4431 radv_compile_nir_shader(&ac_llvm
, binary
, args
,
4432 shaders
, shader_count
);
4435 radv_destroy_llvm_compiler(&ac_llvm
, thread_compiler
);