2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "radv_shader_args.h"
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36 #include <llvm-c/Transforms/Scalar.h>
37 #include <llvm-c/Transforms/Utils.h>
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_llvm_build.h"
43 #include "ac_shader_abi.h"
44 #include "ac_shader_util.h"
45 #include "ac_exp_param.h"
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49 struct radv_shader_context
{
50 struct ac_llvm_context ac
;
51 const struct nir_shader
*shader
;
52 struct ac_shader_abi abi
;
53 const struct radv_shader_args
*args
;
55 gl_shader_stage stage
;
57 unsigned max_workgroup_size
;
58 LLVMContextRef context
;
59 LLVMValueRef main_function
;
61 LLVMValueRef descriptor_sets
[MAX_SETS
];
63 LLVMValueRef ring_offsets
;
65 LLVMValueRef rel_auto_id
;
67 LLVMValueRef gs_wave_id
;
68 LLVMValueRef gs_vtx_offset
[6];
70 LLVMValueRef esgs_ring
;
71 LLVMValueRef gsvs_ring
[4];
72 LLVMValueRef hs_ring_tess_offchip
;
73 LLVMValueRef hs_ring_tess_factor
;
75 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
79 LLVMValueRef gs_next_vertex
[4];
80 LLVMValueRef gs_curprim_verts
[4];
81 LLVMValueRef gs_generated_prims
[4];
82 LLVMValueRef gs_ngg_emit
;
83 LLVMValueRef gs_ngg_scratch
;
85 uint32_t tcs_num_inputs
;
86 uint32_t tcs_num_patches
;
88 LLVMValueRef vertexptr
; /* GFX10 only */
91 struct radv_shader_output_values
{
92 LLVMValueRef values
[4];
98 static inline struct radv_shader_context
*
99 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
101 struct radv_shader_context
*ctx
= NULL
;
102 return container_of(abi
, ctx
, abi
);
105 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
107 switch (ctx
->stage
) {
108 case MESA_SHADER_TESS_CTRL
:
109 return ac_unpack_param(&ctx
->ac
,
110 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_rel_ids
),
112 case MESA_SHADER_TESS_EVAL
:
113 return ac_get_arg(&ctx
->ac
, ctx
->args
->tes_rel_patch_id
);
116 unreachable("Illegal stage");
121 get_tcs_num_patches(struct radv_shader_context
*ctx
)
123 unsigned num_tcs_input_cp
= ctx
->args
->options
->key
.tcs
.input_vertices
;
124 unsigned num_tcs_output_cp
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
125 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
126 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
127 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
128 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
129 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
130 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
131 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
132 unsigned num_patches
;
133 unsigned hardware_lds_size
;
135 /* Ensure that we only need one wave per SIMD so we don't need to check
136 * resource usage. Also ensures that the number of tcs in and out
137 * vertices per threadgroup are at most 256.
139 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
140 /* Make sure that the data fits in LDS. This assumes the shaders only
141 * use LDS for the inputs and outputs.
143 hardware_lds_size
= 32768;
145 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
146 * threadgroup, even though there is more than 32 KiB LDS.
148 * Test: dEQP-VK.tessellation.shader_input_output.barrier
150 if (ctx
->args
->options
->chip_class
>= GFX7
&& ctx
->args
->options
->family
!= CHIP_STONEY
)
151 hardware_lds_size
= 65536;
153 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
154 /* Make sure the output data fits in the offchip buffer */
155 num_patches
= MIN2(num_patches
, (ctx
->args
->options
->tess_offchip_block_dw_size
* 4) / output_patch_size
);
156 /* Not necessary for correctness, but improves performance. The
157 * specific value is taken from the proprietary driver.
159 num_patches
= MIN2(num_patches
, 40);
161 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
162 if (ctx
->args
->options
->chip_class
== GFX6
) {
163 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
164 num_patches
= MIN2(num_patches
, one_wave
);
170 calculate_tess_lds_size(struct radv_shader_context
*ctx
)
172 unsigned num_tcs_input_cp
= ctx
->args
->options
->key
.tcs
.input_vertices
;
173 unsigned num_tcs_output_cp
;
174 unsigned num_tcs_outputs
, num_tcs_patch_outputs
;
175 unsigned input_vertex_size
, output_vertex_size
;
176 unsigned input_patch_size
, output_patch_size
;
177 unsigned pervertex_output_patch_size
;
178 unsigned output_patch0_offset
;
179 unsigned num_patches
;
182 num_tcs_output_cp
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
183 num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
184 num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
186 input_vertex_size
= ctx
->tcs_num_inputs
* 16;
187 output_vertex_size
= num_tcs_outputs
* 16;
189 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
191 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
192 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
194 num_patches
= ctx
->tcs_num_patches
;
195 output_patch0_offset
= input_patch_size
* num_patches
;
197 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
201 /* Tessellation shaders pass outputs to the next shader using LDS.
203 * LS outputs = TCS inputs
204 * TCS outputs = TES inputs
207 * - TCS inputs for patch 0
208 * - TCS inputs for patch 1
209 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
211 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
212 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
213 * - TCS outputs for patch 1
214 * - Per-patch TCS outputs for patch 1
215 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
216 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
219 * All three shaders VS(LS), TCS, TES share the same LDS space.
222 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
224 assert(ctx
->stage
== MESA_SHADER_TESS_CTRL
);
225 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
226 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
228 input_patch_size
/= 4;
229 return LLVMConstInt(ctx
->ac
.i32
, input_patch_size
, false);
233 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
235 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
236 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
237 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
238 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
239 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
240 output_patch_size
/= 4;
241 return LLVMConstInt(ctx
->ac
.i32
, output_patch_size
, false);
245 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
247 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
248 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
249 output_vertex_size
/= 4;
250 return LLVMConstInt(ctx
->ac
.i32
, output_vertex_size
, false);
254 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
256 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
257 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
258 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
259 uint32_t output_patch0_offset
= input_patch_size
;
260 unsigned num_patches
= ctx
->tcs_num_patches
;
262 output_patch0_offset
*= num_patches
;
263 output_patch0_offset
/= 4;
264 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
268 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
270 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
271 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
272 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
273 uint32_t output_patch0_offset
= input_patch_size
;
275 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
276 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
277 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
278 unsigned num_patches
= ctx
->tcs_num_patches
;
280 output_patch0_offset
*= num_patches
;
281 output_patch0_offset
+= pervertex_output_patch_size
;
282 output_patch0_offset
/= 4;
283 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
287 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
289 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
290 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
292 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
296 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
298 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
299 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
300 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
302 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
307 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
309 LLVMValueRef patch0_patch_data_offset
=
310 get_tcs_out_patch0_patch_data_offset(ctx
);
311 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
312 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
314 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
315 patch0_patch_data_offset
);
319 create_llvm_function(struct ac_llvm_context
*ctx
, LLVMModuleRef module
,
320 LLVMBuilderRef builder
,
321 const struct ac_shader_args
*args
,
322 enum ac_llvm_calling_convention convention
,
323 unsigned max_workgroup_size
,
324 const struct radv_nir_compiler_options
*options
)
326 LLVMValueRef main_function
=
327 ac_build_main(args
, ctx
, convention
, "main", ctx
->voidt
, module
);
329 if (options
->address32_hi
) {
330 ac_llvm_add_target_dep_function_attr(main_function
,
331 "amdgpu-32bit-address-high-bits",
332 options
->address32_hi
);
335 ac_llvm_set_workgroup_size(main_function
, max_workgroup_size
);
337 return main_function
;
341 load_descriptor_sets(struct radv_shader_context
*ctx
)
343 uint32_t mask
= ctx
->args
->shader_info
->desc_set_used_mask
;
344 if (ctx
->args
->shader_info
->need_indirect_descriptor_sets
) {
345 LLVMValueRef desc_sets
=
346 ac_get_arg(&ctx
->ac
, ctx
->args
->descriptor_sets
[0]);
348 int i
= u_bit_scan(&mask
);
350 ctx
->descriptor_sets
[i
] =
351 ac_build_load_to_sgpr(&ctx
->ac
, desc_sets
,
352 LLVMConstInt(ctx
->ac
.i32
, i
, false));
357 int i
= u_bit_scan(&mask
);
359 ctx
->descriptor_sets
[i
] =
360 ac_get_arg(&ctx
->ac
, ctx
->args
->descriptor_sets
[i
]);
365 static enum ac_llvm_calling_convention
366 get_llvm_calling_convention(LLVMValueRef func
, gl_shader_stage stage
)
369 case MESA_SHADER_VERTEX
:
370 case MESA_SHADER_TESS_EVAL
:
371 return AC_LLVM_AMDGPU_VS
;
373 case MESA_SHADER_GEOMETRY
:
374 return AC_LLVM_AMDGPU_GS
;
376 case MESA_SHADER_TESS_CTRL
:
377 return AC_LLVM_AMDGPU_HS
;
379 case MESA_SHADER_FRAGMENT
:
380 return AC_LLVM_AMDGPU_PS
;
382 case MESA_SHADER_COMPUTE
:
383 return AC_LLVM_AMDGPU_CS
;
386 unreachable("Unhandle shader type");
390 /* Returns whether the stage is a stage that can be directly before the GS */
391 static bool is_pre_gs_stage(gl_shader_stage stage
)
393 return stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_TESS_EVAL
;
396 static void create_function(struct radv_shader_context
*ctx
,
397 gl_shader_stage stage
,
398 bool has_previous_stage
)
400 if (ctx
->ac
.chip_class
>= GFX10
) {
401 if (is_pre_gs_stage(stage
) && ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
402 /* On GFX10, VS is merged into GS for NGG. */
403 stage
= MESA_SHADER_GEOMETRY
;
404 has_previous_stage
= true;
408 ctx
->main_function
= create_llvm_function(
409 &ctx
->ac
, ctx
->ac
.module
, ctx
->ac
.builder
, &ctx
->args
->ac
,
410 get_llvm_calling_convention(ctx
->main_function
, stage
),
411 ctx
->max_workgroup_size
,
414 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
415 LLVMPointerType(ctx
->ac
.i8
, AC_ADDR_SPACE_CONST
),
416 NULL
, 0, AC_FUNC_ATTR_READNONE
);
417 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
418 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
420 load_descriptor_sets(ctx
);
422 if (stage
== MESA_SHADER_TESS_CTRL
||
423 (stage
== MESA_SHADER_VERTEX
&& ctx
->args
->options
->key
.vs_common_out
.as_ls
) ||
424 /* GFX9 has the ESGS ring buffer in LDS. */
425 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
426 ac_declare_lds_as_pointer(&ctx
->ac
);
433 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
434 unsigned desc_set
, unsigned binding
)
436 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
437 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
438 struct radv_pipeline_layout
*pipeline_layout
= ctx
->args
->options
->layout
;
439 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
440 unsigned base_offset
= layout
->binding
[binding
].offset
;
441 LLVMValueRef offset
, stride
;
443 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
444 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
445 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
446 layout
->binding
[binding
].dynamic_offset_offset
;
447 desc_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.push_constants
);
448 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
449 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
451 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
453 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
455 if (layout
->binding
[binding
].type
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
456 offset
= ac_build_imad(&ctx
->ac
, index
, stride
, offset
);
459 desc_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, desc_ptr
, &offset
, 1, "");
460 desc_ptr
= ac_cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
461 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
463 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
464 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
465 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
466 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
467 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
469 if (ctx
->ac
.chip_class
>= GFX10
) {
470 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
471 S_008F0C_OOB_SELECT(3) |
472 S_008F0C_RESOURCE_LEVEL(1);
474 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
475 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
478 LLVMValueRef desc_components
[4] = {
479 LLVMBuildPtrToInt(ctx
->ac
.builder
, desc_ptr
, ctx
->ac
.intptr
, ""),
480 LLVMConstInt(ctx
->ac
.i32
, S_008F04_BASE_ADDRESS_HI(ctx
->args
->options
->address32_hi
), false),
481 /* High limit to support variable sizes. */
482 LLVMConstInt(ctx
->ac
.i32
, 0xffffffff, false),
483 LLVMConstInt(ctx
->ac
.i32
, desc_type
, false),
486 return ac_build_gather_values(&ctx
->ac
, desc_components
, 4);
493 /* The offchip buffer layout for TCS->TES is
495 * - attribute 0 of patch 0 vertex 0
496 * - attribute 0 of patch 0 vertex 1
497 * - attribute 0 of patch 0 vertex 2
499 * - attribute 0 of patch 1 vertex 0
500 * - attribute 0 of patch 1 vertex 1
502 * - attribute 1 of patch 0 vertex 0
503 * - attribute 1 of patch 0 vertex 1
505 * - per patch attribute 0 of patch 0
506 * - per patch attribute 0 of patch 1
509 * Note that every attribute has 4 components.
511 static LLVMValueRef
get_non_vertex_index_offset(struct radv_shader_context
*ctx
)
513 uint32_t num_patches
= ctx
->tcs_num_patches
;
514 uint32_t num_tcs_outputs
;
515 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
516 num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
518 num_tcs_outputs
= ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
520 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
521 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
523 return LLVMConstInt(ctx
->ac
.i32
, pervertex_output_patch_size
* num_patches
, false);
526 static LLVMValueRef
calc_param_stride(struct radv_shader_context
*ctx
,
527 LLVMValueRef vertex_index
)
529 LLVMValueRef param_stride
;
531 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.tess
.tcs_vertices_out
* ctx
->tcs_num_patches
, false);
533 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_num_patches
, false);
537 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
538 LLVMValueRef vertex_index
,
539 LLVMValueRef param_index
)
541 LLVMValueRef base_addr
;
542 LLVMValueRef param_stride
, constant16
;
543 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
544 LLVMValueRef vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.tess
.tcs_vertices_out
, false);
545 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
546 param_stride
= calc_param_stride(ctx
, vertex_index
);
548 base_addr
= ac_build_imad(&ctx
->ac
, rel_patch_id
,
549 vertices_per_patch
, vertex_index
);
551 base_addr
= rel_patch_id
;
554 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
555 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
556 param_stride
, ""), "");
558 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
561 LLVMValueRef patch_data_offset
= get_non_vertex_index_offset(ctx
);
563 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
564 patch_data_offset
, "");
569 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
571 unsigned const_index
,
573 LLVMValueRef vertex_index
,
574 LLVMValueRef indir_index
)
576 LLVMValueRef param_index
;
579 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
582 if (const_index
&& !is_compact
)
583 param
+= const_index
;
584 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
586 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
590 get_dw_address(struct radv_shader_context
*ctx
,
591 LLVMValueRef dw_addr
,
593 unsigned const_index
,
594 bool compact_const_index
,
595 LLVMValueRef vertex_index
,
597 LLVMValueRef indir_index
)
602 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
603 LLVMBuildMul(ctx
->ac
.builder
,
609 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
610 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
611 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
612 else if (const_index
&& !compact_const_index
)
613 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
614 LLVMConstInt(ctx
->ac
.i32
, const_index
* 4, false), "");
616 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
617 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
619 if (const_index
&& compact_const_index
)
620 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
621 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
626 load_tcs_varyings(struct ac_shader_abi
*abi
,
628 LLVMValueRef vertex_index
,
629 LLVMValueRef indir_index
,
630 unsigned const_index
,
632 unsigned driver_location
,
634 unsigned num_components
,
639 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
640 LLVMValueRef dw_addr
, stride
;
641 LLVMValueRef value
[4], result
;
642 unsigned param
= shader_io_get_unique_index(location
);
645 uint32_t input_vertex_size
= (ctx
->tcs_num_inputs
* 16) / 4;
646 stride
= LLVMConstInt(ctx
->ac
.i32
, input_vertex_size
, false);
647 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
650 stride
= get_tcs_out_vertex_stride(ctx
);
651 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
653 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
658 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
661 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
662 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
663 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
666 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
671 store_tcs_output(struct ac_shader_abi
*abi
,
672 const nir_variable
*var
,
673 LLVMValueRef vertex_index
,
674 LLVMValueRef param_index
,
675 unsigned const_index
,
679 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
680 const unsigned location
= var
->data
.location
;
681 unsigned component
= var
->data
.location_frac
;
682 const bool is_patch
= var
->data
.patch
;
683 const bool is_compact
= var
->data
.compact
;
684 LLVMValueRef dw_addr
;
685 LLVMValueRef stride
= NULL
;
686 LLVMValueRef buf_addr
= NULL
;
687 LLVMValueRef oc_lds
= ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
);
689 bool store_lds
= true;
692 if (!(ctx
->shader
->info
.patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
695 if (!(ctx
->shader
->info
.outputs_read
& (1ULL << location
)))
699 param
= shader_io_get_unique_index(location
);
700 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
701 const_index
+= component
;
704 if (const_index
>= 4) {
711 stride
= get_tcs_out_vertex_stride(ctx
);
712 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
714 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
717 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
719 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
720 vertex_index
, param_index
);
722 bool is_tess_factor
= false;
723 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
724 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
725 is_tess_factor
= true;
727 unsigned base
= is_compact
? const_index
: 0;
728 for (unsigned chan
= 0; chan
< 8; chan
++) {
729 if (!(writemask
& (1 << chan
)))
731 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
732 value
= ac_to_integer(&ctx
->ac
, value
);
733 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
735 if (store_lds
|| is_tess_factor
) {
736 LLVMValueRef dw_addr_chan
=
737 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
738 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
739 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
742 if (!is_tess_factor
&& writemask
!= 0xF)
743 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
745 4 * (base
+ chan
), ac_glc
);
748 if (writemask
== 0xF) {
749 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
756 load_tes_input(struct ac_shader_abi
*abi
,
758 LLVMValueRef vertex_index
,
759 LLVMValueRef param_index
,
760 unsigned const_index
,
762 unsigned driver_location
,
764 unsigned num_components
,
769 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
770 LLVMValueRef buf_addr
;
772 LLVMValueRef oc_lds
= ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
);
773 unsigned param
= shader_io_get_unique_index(location
);
775 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
776 const_index
+= component
;
778 if (const_index
>= 4) {
784 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
785 is_compact
, vertex_index
, param_index
);
787 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
788 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
790 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
791 buf_addr
, oc_lds
, is_compact
? (4 * const_index
) : 0, ac_glc
, true, false);
792 result
= ac_trim_vector(&ctx
->ac
, result
, num_components
);
797 radv_emit_fetch_64bit(struct radv_shader_context
*ctx
,
798 LLVMTypeRef type
, LLVMValueRef a
, LLVMValueRef b
)
800 LLVMValueRef values
[2] = {
801 ac_to_integer(&ctx
->ac
, a
),
802 ac_to_integer(&ctx
->ac
, b
),
804 LLVMValueRef result
= ac_build_gather_values(&ctx
->ac
, values
, 2);
805 return LLVMBuildBitCast(ctx
->ac
.builder
, result
, type
, "");
809 load_gs_input(struct ac_shader_abi
*abi
,
811 unsigned driver_location
,
813 unsigned num_components
,
814 unsigned vertex_index
,
815 unsigned const_index
,
818 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
819 LLVMValueRef vtx_offset
;
820 unsigned param
, vtx_offset_param
;
821 LLVMValueRef value
[4], result
;
823 vtx_offset_param
= vertex_index
;
824 assert(vtx_offset_param
< 6);
825 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
826 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
828 param
= shader_io_get_unique_index(location
);
830 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
831 if (ctx
->ac
.chip_class
>= GFX9
) {
832 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
833 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
834 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
835 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
837 if (ac_get_type_size(type
) == 8) {
838 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
839 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
+ 1, 0), "");
840 LLVMValueRef tmp
= ac_lds_load(&ctx
->ac
, dw_addr
);
842 value
[i
] = radv_emit_fetch_64bit(ctx
, type
, value
[i
], tmp
);
845 LLVMValueRef soffset
=
846 LLVMConstInt(ctx
->ac
.i32
,
847 (param
* 4 + i
+ const_index
) * 256,
850 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
854 0, ac_glc
, true, false);
856 if (ac_get_type_size(type
) == 8) {
857 soffset
= LLVMConstInt(ctx
->ac
.i32
,
858 (param
* 4 + i
+ const_index
+ 1) * 256,
862 ac_build_buffer_load(&ctx
->ac
,
866 0, ac_glc
, true, false);
868 value
[i
] = radv_emit_fetch_64bit(ctx
, type
, value
[i
], tmp
);
872 if (ac_get_type_size(type
) == 2) {
873 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i32
, "");
874 value
[i
] = LLVMBuildTrunc(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i16
, "");
876 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], type
, "");
878 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
879 result
= ac_to_integer(&ctx
->ac
, result
);
884 static void radv_emit_kill(struct ac_shader_abi
*abi
, LLVMValueRef visible
)
886 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
887 ac_build_kill_if_false(&ctx
->ac
, visible
);
891 radv_get_sample_pos_offset(uint32_t num_samples
)
893 uint32_t sample_pos_offset
= 0;
895 switch (num_samples
) {
897 sample_pos_offset
= 1;
900 sample_pos_offset
= 3;
903 sample_pos_offset
= 7;
908 return sample_pos_offset
;
911 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
912 LLVMValueRef sample_id
)
914 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
917 LLVMValueRef index
= LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false);
918 LLVMValueRef ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ctx
->ring_offsets
, &index
, 1, "");
920 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
921 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
923 uint32_t sample_pos_offset
=
924 radv_get_sample_pos_offset(ctx
->args
->options
->key
.fs
.num_samples
);
927 LLVMBuildAdd(ctx
->ac
.builder
, sample_id
,
928 LLVMConstInt(ctx
->ac
.i32
, sample_pos_offset
, false), "");
929 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
935 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
937 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
938 uint8_t log2_ps_iter_samples
;
940 if (ctx
->args
->shader_info
->ps
.force_persample
) {
941 log2_ps_iter_samples
=
942 util_logbase2(ctx
->args
->options
->key
.fs
.num_samples
);
944 log2_ps_iter_samples
= ctx
->args
->options
->key
.fs
.log2_ps_iter_samples
;
947 /* The bit pattern matches that used by fixed function fragment
949 static const uint16_t ps_iter_masks
[] = {
950 0xffff, /* not used */
956 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
958 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
960 LLVMValueRef result
, sample_id
;
961 sample_id
= ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.ancillary
), 8, 4);
962 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
963 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
,
964 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.sample_coverage
), "");
969 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
971 LLVMValueRef
*addrs
);
974 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
976 LLVMValueRef gs_next_vertex
;
977 LLVMValueRef can_emit
;
979 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
981 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
982 gfx10_ngg_gs_emit_vertex(ctx
, stream
, addrs
);
986 /* Write vertex attribute values to GSVS ring */
987 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
988 ctx
->gs_next_vertex
[stream
],
991 /* If this thread has already emitted the declared maximum number of
992 * vertices, don't emit any more: excessive vertex emissions are not
993 * supposed to have any effect.
995 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
996 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
998 bool use_kill
= !ctx
->args
->shader_info
->gs
.writes_memory
;
1000 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
1002 ac_build_ifcc(&ctx
->ac
, can_emit
, 6505);
1004 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
1005 unsigned output_usage_mask
=
1006 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
1007 uint8_t output_stream
=
1008 ctx
->args
->shader_info
->gs
.output_streams
[i
];
1009 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
1010 int length
= util_last_bit(output_usage_mask
);
1012 if (!(ctx
->output_mask
& (1ull << i
)) ||
1013 output_stream
!= stream
)
1016 for (unsigned j
= 0; j
< length
; j
++) {
1017 if (!(output_usage_mask
& (1 << j
)))
1020 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
1022 LLVMValueRef voffset
=
1023 LLVMConstInt(ctx
->ac
.i32
, offset
*
1024 ctx
->shader
->info
.gs
.vertices_out
, false);
1028 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
1029 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1031 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
1032 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
1034 ac_build_buffer_store_dword(&ctx
->ac
,
1035 ctx
->gsvs_ring
[stream
],
1038 ac_get_arg(&ctx
->ac
,
1039 ctx
->args
->gs2vs_offset
),
1040 0, ac_glc
| ac_slc
| ac_swizzled
);
1044 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
1046 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
1048 ac_build_sendmsg(&ctx
->ac
,
1049 AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
1053 ac_build_endif(&ctx
->ac
, 6505);
1057 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
1059 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1061 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
1062 LLVMBuildStore(ctx
->ac
.builder
, ctx
->ac
.i32_0
, ctx
->gs_curprim_verts
[stream
]);
1066 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
1070 load_tess_coord(struct ac_shader_abi
*abi
)
1072 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1074 LLVMValueRef coord
[4] = {
1075 ac_get_arg(&ctx
->ac
, ctx
->args
->tes_u
),
1076 ac_get_arg(&ctx
->ac
, ctx
->args
->tes_v
),
1081 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
)
1082 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
1083 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
1085 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
1089 load_patch_vertices_in(struct ac_shader_abi
*abi
)
1091 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1092 return LLVMConstInt(ctx
->ac
.i32
, ctx
->args
->options
->key
.tcs
.input_vertices
, false);
1096 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
1098 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1099 return ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.base_vertex
);
1102 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
1103 LLVMValueRef buffer_ptr
, bool write
)
1105 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1106 LLVMValueRef result
;
1108 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1110 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1111 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1116 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
1118 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1119 LLVMValueRef result
;
1121 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr
)) != LLVMPointerTypeKind
) {
1122 /* Do not load the descriptor for inlined uniform blocks. */
1126 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1128 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1129 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1134 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
1135 unsigned descriptor_set
,
1136 unsigned base_index
,
1137 unsigned constant_index
,
1139 enum ac_descriptor_type desc_type
,
1140 bool image
, bool write
,
1143 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1144 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
1145 struct radv_descriptor_set_layout
*layout
= ctx
->args
->options
->layout
->set
[descriptor_set
].layout
;
1146 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
1147 unsigned offset
= binding
->offset
;
1148 unsigned stride
= binding
->size
;
1150 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1153 assert(base_index
< layout
->binding_count
);
1155 switch (desc_type
) {
1157 type
= ctx
->ac
.v8i32
;
1161 type
= ctx
->ac
.v8i32
;
1165 case AC_DESC_SAMPLER
:
1166 type
= ctx
->ac
.v4i32
;
1167 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
) {
1168 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
1173 case AC_DESC_BUFFER
:
1174 type
= ctx
->ac
.v4i32
;
1177 case AC_DESC_PLANE_0
:
1178 case AC_DESC_PLANE_1
:
1179 case AC_DESC_PLANE_2
:
1180 type
= ctx
->ac
.v8i32
;
1182 offset
+= 32 * (desc_type
- AC_DESC_PLANE_0
);
1185 unreachable("invalid desc_type\n");
1188 offset
+= constant_index
* stride
;
1190 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
1191 (!index
|| binding
->immutable_samplers_equal
)) {
1192 if (binding
->immutable_samplers_equal
)
1195 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
1197 LLVMValueRef constants
[] = {
1198 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
1199 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
1200 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
1201 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
1203 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
1206 assert(stride
% type_size
== 0);
1208 LLVMValueRef adjusted_index
= index
;
1209 if (!adjusted_index
)
1210 adjusted_index
= ctx
->ac
.i32_0
;
1212 adjusted_index
= LLVMBuildMul(builder
, adjusted_index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
1214 LLVMValueRef val_offset
= LLVMConstInt(ctx
->ac
.i32
, offset
, 0);
1215 list
= LLVMBuildGEP(builder
, list
, &val_offset
, 1, "");
1216 list
= LLVMBuildPointerCast(builder
, list
,
1217 ac_array_in_const32_addr_space(type
), "");
1219 LLVMValueRef descriptor
= ac_build_load_to_sgpr(&ctx
->ac
, list
, adjusted_index
);
1221 /* 3 plane formats always have same size and format for plane 1 & 2, so
1222 * use the tail from plane 1 so that we can store only the first 16 bytes
1223 * of the last plane. */
1224 if (desc_type
== AC_DESC_PLANE_2
) {
1225 LLVMValueRef descriptor2
= radv_get_sampler_desc(abi
, descriptor_set
, base_index
, constant_index
, index
, AC_DESC_PLANE_1
,image
, write
, bindless
);
1227 LLVMValueRef components
[8];
1228 for (unsigned i
= 0; i
< 4; ++i
)
1229 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor
, i
);
1231 for (unsigned i
= 4; i
< 8; ++i
)
1232 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor2
, i
);
1233 descriptor
= ac_build_gather_values(&ctx
->ac
, components
, 8);
1239 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1240 * so we may need to fix it up. */
1242 adjust_vertex_fetch_alpha(struct radv_shader_context
*ctx
,
1243 unsigned adjustment
,
1246 if (adjustment
== RADV_ALPHA_ADJUST_NONE
)
1249 LLVMValueRef c30
= LLVMConstInt(ctx
->ac
.i32
, 30, 0);
1251 alpha
= LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1253 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
1254 alpha
= LLVMBuildFPToUI(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
1256 alpha
= ac_to_integer(&ctx
->ac
, alpha
);
1258 /* For the integer-like cases, do a natural sign extension.
1260 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1261 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1264 alpha
= LLVMBuildShl(ctx
->ac
.builder
, alpha
,
1265 adjustment
== RADV_ALPHA_ADJUST_SNORM
?
1266 LLVMConstInt(ctx
->ac
.i32
, 7, 0) : c30
, "");
1267 alpha
= LLVMBuildAShr(ctx
->ac
.builder
, alpha
, c30
, "");
1269 /* Convert back to the right type. */
1270 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
1272 LLVMValueRef neg_one
= LLVMConstReal(ctx
->ac
.f32
, -1.0);
1273 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1274 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, alpha
, neg_one
, "");
1275 alpha
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, alpha
, "");
1276 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
1277 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1280 return LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
1284 get_num_channels_from_data_format(unsigned data_format
)
1286 switch (data_format
) {
1287 case V_008F0C_BUF_DATA_FORMAT_8
:
1288 case V_008F0C_BUF_DATA_FORMAT_16
:
1289 case V_008F0C_BUF_DATA_FORMAT_32
:
1291 case V_008F0C_BUF_DATA_FORMAT_8_8
:
1292 case V_008F0C_BUF_DATA_FORMAT_16_16
:
1293 case V_008F0C_BUF_DATA_FORMAT_32_32
:
1295 case V_008F0C_BUF_DATA_FORMAT_10_11_11
:
1296 case V_008F0C_BUF_DATA_FORMAT_11_11_10
:
1297 case V_008F0C_BUF_DATA_FORMAT_32_32_32
:
1299 case V_008F0C_BUF_DATA_FORMAT_8_8_8_8
:
1300 case V_008F0C_BUF_DATA_FORMAT_10_10_10_2
:
1301 case V_008F0C_BUF_DATA_FORMAT_2_10_10_10
:
1302 case V_008F0C_BUF_DATA_FORMAT_16_16_16_16
:
1303 case V_008F0C_BUF_DATA_FORMAT_32_32_32_32
:
1313 radv_fixup_vertex_input_fetches(struct radv_shader_context
*ctx
,
1315 unsigned num_channels
,
1318 LLVMValueRef zero
= is_float
? ctx
->ac
.f32_0
: ctx
->ac
.i32_0
;
1319 LLVMValueRef one
= is_float
? ctx
->ac
.f32_1
: ctx
->ac
.i32_1
;
1320 LLVMValueRef chan
[4];
1322 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMVectorTypeKind
) {
1323 unsigned vec_size
= LLVMGetVectorSize(LLVMTypeOf(value
));
1325 if (num_channels
== 4 && num_channels
== vec_size
)
1328 num_channels
= MIN2(num_channels
, vec_size
);
1330 for (unsigned i
= 0; i
< num_channels
; i
++)
1331 chan
[i
] = ac_llvm_extract_elem(&ctx
->ac
, value
, i
);
1334 assert(num_channels
== 1);
1339 for (unsigned i
= num_channels
; i
< 4; i
++) {
1340 chan
[i
] = i
== 3 ? one
: zero
;
1341 chan
[i
] = ac_to_integer(&ctx
->ac
, chan
[i
]);
1344 return ac_build_gather_values(&ctx
->ac
, chan
, 4);
1348 handle_vs_input_decl(struct radv_shader_context
*ctx
,
1349 struct nir_variable
*variable
)
1351 LLVMValueRef t_list_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->vertex_buffers
);
1352 LLVMValueRef t_offset
;
1353 LLVMValueRef t_list
;
1355 LLVMValueRef buffer_index
;
1356 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
1357 uint8_t input_usage_mask
=
1358 ctx
->args
->shader_info
->vs
.input_usage_mask
[variable
->data
.location
];
1359 unsigned num_input_channels
= util_last_bit(input_usage_mask
);
1361 variable
->data
.driver_location
= variable
->data
.location
* 4;
1363 enum glsl_base_type type
= glsl_get_base_type(variable
->type
);
1364 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
1365 LLVMValueRef output
[4];
1366 unsigned attrib_index
= variable
->data
.location
+ i
- VERT_ATTRIB_GENERIC0
;
1367 unsigned attrib_format
= ctx
->args
->options
->key
.vs
.vertex_attribute_formats
[attrib_index
];
1368 unsigned data_format
= attrib_format
& 0x0f;
1369 unsigned num_format
= (attrib_format
>> 4) & 0x07;
1370 bool is_float
= num_format
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
1371 num_format
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
1373 if (ctx
->args
->options
->key
.vs
.instance_rate_inputs
& (1u << attrib_index
)) {
1374 uint32_t divisor
= ctx
->args
->options
->key
.vs
.instance_rate_divisors
[attrib_index
];
1377 buffer_index
= ctx
->abi
.instance_id
;
1380 buffer_index
= LLVMBuildUDiv(ctx
->ac
.builder
, buffer_index
,
1381 LLVMConstInt(ctx
->ac
.i32
, divisor
, 0), "");
1384 buffer_index
= ctx
->ac
.i32_0
;
1387 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
1388 ac_get_arg(&ctx
->ac
,
1389 ctx
->args
->ac
.start_instance
),\
1392 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
1394 ac_get_arg(&ctx
->ac
,
1395 ctx
->args
->ac
.base_vertex
), "");
1398 /* Adjust the number of channels to load based on the vertex
1401 unsigned num_format_channels
= get_num_channels_from_data_format(data_format
);
1402 unsigned num_channels
= MIN2(num_input_channels
, num_format_channels
);
1403 unsigned attrib_binding
= ctx
->args
->options
->key
.vs
.vertex_attribute_bindings
[attrib_index
];
1404 unsigned attrib_offset
= ctx
->args
->options
->key
.vs
.vertex_attribute_offsets
[attrib_index
];
1405 unsigned attrib_stride
= ctx
->args
->options
->key
.vs
.vertex_attribute_strides
[attrib_index
];
1407 if (ctx
->args
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
1408 /* Always load, at least, 3 channels for formats that
1409 * need to be shuffled because X<->Z.
1411 num_channels
= MAX2(num_channels
, 3);
1414 if (attrib_stride
!= 0 && attrib_offset
> attrib_stride
) {
1415 LLVMValueRef buffer_offset
=
1416 LLVMConstInt(ctx
->ac
.i32
,
1417 attrib_offset
/ attrib_stride
, false);
1419 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
1423 attrib_offset
= attrib_offset
% attrib_stride
;
1426 t_offset
= LLVMConstInt(ctx
->ac
.i32
, attrib_binding
, false);
1427 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
1429 input
= ac_build_struct_tbuffer_load(&ctx
->ac
, t_list
,
1431 LLVMConstInt(ctx
->ac
.i32
, attrib_offset
, false),
1432 ctx
->ac
.i32_0
, ctx
->ac
.i32_0
,
1434 data_format
, num_format
, 0, true);
1436 if (ctx
->args
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
1438 c
[0] = ac_llvm_extract_elem(&ctx
->ac
, input
, 2);
1439 c
[1] = ac_llvm_extract_elem(&ctx
->ac
, input
, 1);
1440 c
[2] = ac_llvm_extract_elem(&ctx
->ac
, input
, 0);
1441 c
[3] = ac_llvm_extract_elem(&ctx
->ac
, input
, 3);
1443 input
= ac_build_gather_values(&ctx
->ac
, c
, 4);
1446 input
= radv_fixup_vertex_input_fetches(ctx
, input
, num_channels
,
1449 for (unsigned chan
= 0; chan
< 4; chan
++) {
1450 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
1451 output
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
, input
, llvm_chan
, "");
1452 if (type
== GLSL_TYPE_FLOAT16
) {
1453 output
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f32
, "");
1454 output
[chan
] = LLVMBuildFPTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f16
, "");
1458 unsigned alpha_adjust
= (ctx
->args
->options
->key
.vs
.alpha_adjust
>> (attrib_index
* 2)) & 3;
1459 output
[3] = adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, output
[3]);
1461 for (unsigned chan
= 0; chan
< 4; chan
++) {
1462 output
[chan
] = ac_to_integer(&ctx
->ac
, output
[chan
]);
1463 if (type
== GLSL_TYPE_UINT16
|| type
== GLSL_TYPE_INT16
)
1464 output
[chan
] = LLVMBuildTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.i16
, "");
1466 ctx
->inputs
[ac_llvm_reg_index_soa(variable
->data
.location
+ i
, chan
)] = output
[chan
];
1472 handle_vs_inputs(struct radv_shader_context
*ctx
,
1473 struct nir_shader
*nir
) {
1474 nir_foreach_variable(variable
, &nir
->inputs
)
1475 handle_vs_input_decl(ctx
, variable
);
1479 prepare_interp_optimize(struct radv_shader_context
*ctx
,
1480 struct nir_shader
*nir
)
1482 bool uses_center
= false;
1483 bool uses_centroid
= false;
1484 nir_foreach_variable(variable
, &nir
->inputs
) {
1485 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
1486 variable
->data
.sample
)
1489 if (variable
->data
.centroid
)
1490 uses_centroid
= true;
1495 ctx
->abi
.persp_centroid
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.persp_centroid
);
1496 ctx
->abi
.linear_centroid
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.linear_centroid
);
1498 if (uses_center
&& uses_centroid
) {
1499 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
,
1500 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.prim_mask
),
1502 ctx
->abi
.persp_centroid
=
1503 LLVMBuildSelect(ctx
->ac
.builder
, sel
,
1504 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.persp_center
),
1505 ctx
->abi
.persp_centroid
, "");
1506 ctx
->abi
.linear_centroid
=
1507 LLVMBuildSelect(ctx
->ac
.builder
, sel
,
1508 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.linear_center
),
1509 ctx
->abi
.linear_centroid
, "");
1514 scan_shader_output_decl(struct radv_shader_context
*ctx
,
1515 struct nir_variable
*variable
,
1516 struct nir_shader
*shader
,
1517 gl_shader_stage stage
)
1519 int idx
= variable
->data
.location
+ variable
->data
.index
;
1520 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
1521 uint64_t mask_attribs
;
1523 variable
->data
.driver_location
= idx
* 4;
1525 /* tess ctrl has it's own load/store paths for outputs */
1526 if (stage
== MESA_SHADER_TESS_CTRL
)
1529 if (variable
->data
.compact
) {
1530 unsigned component_count
= variable
->data
.location_frac
+
1531 glsl_get_length(variable
->type
);
1532 attrib_count
= (component_count
+ 3) / 4;
1535 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
1537 ctx
->output_mask
|= mask_attribs
;
1541 /* Initialize arguments for the shader export intrinsic */
1543 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
1544 LLVMValueRef
*values
,
1545 unsigned enabled_channels
,
1547 struct ac_export_args
*args
)
1549 /* Specify the channels that are enabled. */
1550 args
->enabled_channels
= enabled_channels
;
1552 /* Specify whether the EXEC mask represents the valid mask */
1553 args
->valid_mask
= 0;
1555 /* Specify whether this is the last export */
1558 /* Specify the target we are exporting */
1559 args
->target
= target
;
1561 args
->compr
= false;
1562 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
1563 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
1564 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
1565 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
1570 bool is_16bit
= ac_get_type_size(LLVMTypeOf(values
[0])) == 2;
1571 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1572 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
1573 unsigned col_format
= (ctx
->args
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
1574 bool is_int8
= (ctx
->args
->options
->key
.fs
.is_int8
>> index
) & 1;
1575 bool is_int10
= (ctx
->args
->options
->key
.fs
.is_int10
>> index
) & 1;
1578 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
1579 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
1580 unsigned bits
, bool hi
) = NULL
;
1582 switch(col_format
) {
1583 case V_028714_SPI_SHADER_ZERO
:
1584 args
->enabled_channels
= 0; /* writemask */
1585 args
->target
= V_008DFC_SQ_EXP_NULL
;
1588 case V_028714_SPI_SHADER_32_R
:
1589 args
->enabled_channels
= 1;
1590 args
->out
[0] = values
[0];
1593 case V_028714_SPI_SHADER_32_GR
:
1594 args
->enabled_channels
= 0x3;
1595 args
->out
[0] = values
[0];
1596 args
->out
[1] = values
[1];
1599 case V_028714_SPI_SHADER_32_AR
:
1600 if (ctx
->ac
.chip_class
>= GFX10
) {
1601 args
->enabled_channels
= 0x3;
1602 args
->out
[0] = values
[0];
1603 args
->out
[1] = values
[3];
1605 args
->enabled_channels
= 0x9;
1606 args
->out
[0] = values
[0];
1607 args
->out
[3] = values
[3];
1611 case V_028714_SPI_SHADER_FP16_ABGR
:
1612 args
->enabled_channels
= 0x5;
1613 packf
= ac_build_cvt_pkrtz_f16
;
1615 for (unsigned chan
= 0; chan
< 4; chan
++)
1616 values
[chan
] = LLVMBuildFPExt(ctx
->ac
.builder
,
1622 case V_028714_SPI_SHADER_UNORM16_ABGR
:
1623 args
->enabled_channels
= 0x5;
1624 packf
= ac_build_cvt_pknorm_u16
;
1627 case V_028714_SPI_SHADER_SNORM16_ABGR
:
1628 args
->enabled_channels
= 0x5;
1629 packf
= ac_build_cvt_pknorm_i16
;
1632 case V_028714_SPI_SHADER_UINT16_ABGR
:
1633 args
->enabled_channels
= 0x5;
1634 packi
= ac_build_cvt_pk_u16
;
1636 for (unsigned chan
= 0; chan
< 4; chan
++)
1637 values
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
,
1638 ac_to_integer(&ctx
->ac
, values
[chan
]),
1643 case V_028714_SPI_SHADER_SINT16_ABGR
:
1644 args
->enabled_channels
= 0x5;
1645 packi
= ac_build_cvt_pk_i16
;
1647 for (unsigned chan
= 0; chan
< 4; chan
++)
1648 values
[chan
] = LLVMBuildSExt(ctx
->ac
.builder
,
1649 ac_to_integer(&ctx
->ac
, values
[chan
]),
1655 case V_028714_SPI_SHADER_32_ABGR
:
1656 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
1660 /* Pack f16 or norm_i16/u16. */
1662 for (chan
= 0; chan
< 2; chan
++) {
1663 LLVMValueRef pack_args
[2] = {
1665 values
[2 * chan
+ 1]
1667 LLVMValueRef packed
;
1669 packed
= packf(&ctx
->ac
, pack_args
);
1670 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
1672 args
->compr
= 1; /* COMPR flag */
1677 for (chan
= 0; chan
< 2; chan
++) {
1678 LLVMValueRef pack_args
[2] = {
1679 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
1680 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
1682 LLVMValueRef packed
;
1684 packed
= packi(&ctx
->ac
, pack_args
,
1685 is_int8
? 8 : is_int10
? 10 : 16,
1687 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
1689 args
->compr
= 1; /* COMPR flag */
1695 for (unsigned chan
= 0; chan
< 4; chan
++) {
1696 values
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i16
, "");
1697 args
->out
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i32
, "");
1700 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
1702 for (unsigned i
= 0; i
< 4; ++i
)
1703 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
1707 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
1708 LLVMValueRef
*values
, unsigned enabled_channels
)
1710 struct ac_export_args args
;
1712 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
1713 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
1714 ac_build_export(&ctx
->ac
, &args
);
1718 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
1720 LLVMValueRef output
= ctx
->abi
.outputs
[ac_llvm_reg_index_soa(index
, chan
)];
1721 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
1725 radv_emit_stream_output(struct radv_shader_context
*ctx
,
1726 LLVMValueRef
const *so_buffers
,
1727 LLVMValueRef
const *so_write_offsets
,
1728 const struct radv_stream_output
*output
,
1729 struct radv_shader_output_values
*shader_out
)
1731 unsigned num_comps
= util_bitcount(output
->component_mask
);
1732 unsigned buf
= output
->buffer
;
1733 unsigned offset
= output
->offset
;
1735 LLVMValueRef out
[4];
1737 assert(num_comps
&& num_comps
<= 4);
1738 if (!num_comps
|| num_comps
> 4)
1741 /* Get the first component. */
1742 start
= ffs(output
->component_mask
) - 1;
1744 /* Load the output as int. */
1745 for (int i
= 0; i
< num_comps
; i
++) {
1746 out
[i
] = ac_to_integer(&ctx
->ac
, shader_out
->values
[start
+ i
]);
1749 /* Pack the output. */
1750 LLVMValueRef vdata
= NULL
;
1752 switch (num_comps
) {
1753 case 1: /* as i32 */
1756 case 2: /* as v2i32 */
1757 case 3: /* as v4i32 (aligned to 4) */
1758 out
[3] = LLVMGetUndef(ctx
->ac
.i32
);
1760 case 4: /* as v4i32 */
1761 vdata
= ac_build_gather_values(&ctx
->ac
, out
,
1762 !ac_has_vec3_support(ctx
->ac
.chip_class
, false) ?
1763 util_next_power_of_two(num_comps
) :
1768 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf
],
1769 vdata
, num_comps
, so_write_offsets
[buf
],
1770 ctx
->ac
.i32_0
, offset
,
1775 radv_emit_streamout(struct radv_shader_context
*ctx
, unsigned stream
)
1779 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1780 assert(ctx
->args
->streamout_config
.used
);
1781 LLVMValueRef so_vtx_count
=
1782 ac_build_bfe(&ctx
->ac
,
1783 ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_config
),
1784 LLVMConstInt(ctx
->ac
.i32
, 16, false),
1785 LLVMConstInt(ctx
->ac
.i32
, 7, false), false);
1787 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
1789 /* can_emit = tid < so_vtx_count; */
1790 LLVMValueRef can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
1791 tid
, so_vtx_count
, "");
1793 /* Emit the streamout code conditionally. This actually avoids
1794 * out-of-bounds buffer access. The hw tells us via the SGPR
1795 * (so_vtx_count) which threads are allowed to emit streamout data.
1797 ac_build_ifcc(&ctx
->ac
, can_emit
, 6501);
1799 /* The buffer offset is computed as follows:
1800 * ByteOffset = streamout_offset[buffer_id]*4 +
1801 * (streamout_write_index + thread_id)*stride[buffer_id] +
1804 LLVMValueRef so_write_index
=
1805 ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_write_idx
);
1807 /* Compute (streamout_write_index + thread_id). */
1809 LLVMBuildAdd(ctx
->ac
.builder
, so_write_index
, tid
, "");
1811 /* Load the descriptor and compute the write offset for each
1814 LLVMValueRef so_write_offset
[4] = {};
1815 LLVMValueRef so_buffers
[4] = {};
1816 LLVMValueRef buf_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_buffers
);
1818 for (i
= 0; i
< 4; i
++) {
1819 uint16_t stride
= ctx
->args
->shader_info
->so
.strides
[i
];
1824 LLVMValueRef offset
=
1825 LLVMConstInt(ctx
->ac
.i32
, i
, false);
1827 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
,
1830 LLVMValueRef so_offset
=
1831 ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_offset
[i
]);
1833 so_offset
= LLVMBuildMul(ctx
->ac
.builder
, so_offset
,
1834 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1836 so_write_offset
[i
] =
1837 ac_build_imad(&ctx
->ac
, so_write_index
,
1838 LLVMConstInt(ctx
->ac
.i32
,
1843 /* Write streamout data. */
1844 for (i
= 0; i
< ctx
->args
->shader_info
->so
.num_outputs
; i
++) {
1845 struct radv_shader_output_values shader_out
= {};
1846 struct radv_stream_output
*output
=
1847 &ctx
->args
->shader_info
->so
.outputs
[i
];
1849 if (stream
!= output
->stream
)
1852 for (int j
= 0; j
< 4; j
++) {
1853 shader_out
.values
[j
] =
1854 radv_load_output(ctx
, output
->location
, j
);
1857 radv_emit_stream_output(ctx
, so_buffers
,so_write_offset
,
1858 output
, &shader_out
);
1861 ac_build_endif(&ctx
->ac
, 6501);
1865 radv_build_param_exports(struct radv_shader_context
*ctx
,
1866 struct radv_shader_output_values
*outputs
,
1868 struct radv_vs_output_info
*outinfo
,
1869 bool export_clip_dists
)
1871 unsigned param_count
= 0;
1873 for (unsigned i
= 0; i
< noutput
; i
++) {
1874 unsigned slot_name
= outputs
[i
].slot_name
;
1875 unsigned usage_mask
= outputs
[i
].usage_mask
;
1877 if (slot_name
!= VARYING_SLOT_LAYER
&&
1878 slot_name
!= VARYING_SLOT_PRIMITIVE_ID
&&
1879 slot_name
!= VARYING_SLOT_CLIP_DIST0
&&
1880 slot_name
!= VARYING_SLOT_CLIP_DIST1
&&
1881 slot_name
< VARYING_SLOT_VAR0
)
1884 if ((slot_name
== VARYING_SLOT_CLIP_DIST0
||
1885 slot_name
== VARYING_SLOT_CLIP_DIST1
) && !export_clip_dists
)
1888 radv_export_param(ctx
, param_count
, outputs
[i
].values
, usage_mask
);
1890 assert(i
< ARRAY_SIZE(outinfo
->vs_output_param_offset
));
1891 outinfo
->vs_output_param_offset
[slot_name
] = param_count
++;
1894 outinfo
->param_exports
= param_count
;
1897 /* Generate export instructions for hardware VS shader stage or NGG GS stage
1898 * (position and parameter data only).
1901 radv_llvm_export_vs(struct radv_shader_context
*ctx
,
1902 struct radv_shader_output_values
*outputs
,
1904 struct radv_vs_output_info
*outinfo
,
1905 bool export_clip_dists
)
1907 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_value
= NULL
;
1908 struct ac_export_args pos_args
[4] = {};
1909 unsigned pos_idx
, index
;
1912 /* Build position exports */
1913 for (i
= 0; i
< noutput
; i
++) {
1914 switch (outputs
[i
].slot_name
) {
1915 case VARYING_SLOT_POS
:
1916 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
1917 V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
1919 case VARYING_SLOT_PSIZ
:
1920 psize_value
= outputs
[i
].values
[0];
1922 case VARYING_SLOT_LAYER
:
1923 layer_value
= outputs
[i
].values
[0];
1925 case VARYING_SLOT_VIEWPORT
:
1926 viewport_value
= outputs
[i
].values
[0];
1928 case VARYING_SLOT_CLIP_DIST0
:
1929 case VARYING_SLOT_CLIP_DIST1
:
1930 index
= 2 + outputs
[i
].slot_index
;
1931 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
1932 V_008DFC_SQ_EXP_POS
+ index
,
1940 /* We need to add the position output manually if it's missing. */
1941 if (!pos_args
[0].out
[0]) {
1942 pos_args
[0].enabled_channels
= 0xf; /* writemask */
1943 pos_args
[0].valid_mask
= 0; /* EXEC mask */
1944 pos_args
[0].done
= 0; /* last export? */
1945 pos_args
[0].target
= V_008DFC_SQ_EXP_POS
;
1946 pos_args
[0].compr
= 0; /* COMPR flag */
1947 pos_args
[0].out
[0] = ctx
->ac
.f32_0
; /* X */
1948 pos_args
[0].out
[1] = ctx
->ac
.f32_0
; /* Y */
1949 pos_args
[0].out
[2] = ctx
->ac
.f32_0
; /* Z */
1950 pos_args
[0].out
[3] = ctx
->ac
.f32_1
; /* W */
1953 if (outinfo
->writes_pointsize
||
1954 outinfo
->writes_layer
||
1955 outinfo
->writes_viewport_index
) {
1956 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
1957 (outinfo
->writes_layer
== true ? 4 : 0));
1958 pos_args
[1].valid_mask
= 0;
1959 pos_args
[1].done
= 0;
1960 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
1961 pos_args
[1].compr
= 0;
1962 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
1963 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
1964 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
1965 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
1967 if (outinfo
->writes_pointsize
== true)
1968 pos_args
[1].out
[0] = psize_value
;
1969 if (outinfo
->writes_layer
== true)
1970 pos_args
[1].out
[2] = layer_value
;
1971 if (outinfo
->writes_viewport_index
== true) {
1972 if (ctx
->args
->options
->chip_class
>= GFX9
) {
1973 /* GFX9 has the layer in out.z[10:0] and the viewport
1974 * index in out.z[19:16].
1976 LLVMValueRef v
= viewport_value
;
1977 v
= ac_to_integer(&ctx
->ac
, v
);
1978 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
1979 LLVMConstInt(ctx
->ac
.i32
, 16, false),
1981 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
1982 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
1984 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
1985 pos_args
[1].enabled_channels
|= 1 << 2;
1987 pos_args
[1].out
[3] = viewport_value
;
1988 pos_args
[1].enabled_channels
|= 1 << 3;
1993 for (i
= 0; i
< 4; i
++) {
1994 if (pos_args
[i
].out
[0])
1995 outinfo
->pos_exports
++;
1998 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
1999 * Setting valid_mask=1 prevents it and has no other effect.
2001 if (ctx
->ac
.family
== CHIP_NAVI10
||
2002 ctx
->ac
.family
== CHIP_NAVI12
||
2003 ctx
->ac
.family
== CHIP_NAVI14
)
2004 pos_args
[0].valid_mask
= 1;
2007 for (i
= 0; i
< 4; i
++) {
2008 if (!pos_args
[i
].out
[0])
2011 /* Specify the target we are exporting */
2012 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
2014 if (pos_idx
== outinfo
->pos_exports
)
2015 /* Specify that this is the last export */
2016 pos_args
[i
].done
= 1;
2018 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
2021 /* Build parameter exports */
2022 radv_build_param_exports(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
2026 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
2027 bool export_prim_id
,
2028 bool export_clip_dists
,
2029 struct radv_vs_output_info
*outinfo
)
2031 struct radv_shader_output_values
*outputs
;
2032 unsigned noutput
= 0;
2034 if (ctx
->args
->options
->key
.has_multiview_view_index
) {
2035 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2037 for(unsigned i
= 0; i
< 4; ++i
)
2038 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
2039 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
2042 LLVMValueRef view_index
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.view_index
);
2043 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, view_index
), *tmp_out
);
2044 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
2047 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
2048 sizeof(outinfo
->vs_output_param_offset
));
2049 outinfo
->pos_exports
= 0;
2051 if (!ctx
->args
->options
->use_ngg_streamout
&&
2052 ctx
->args
->shader_info
->so
.num_outputs
&&
2053 !ctx
->args
->is_gs_copy_shader
) {
2054 /* The GS copy shader emission already emits streamout. */
2055 radv_emit_streamout(ctx
, 0);
2058 /* Allocate a temporary array for the output values. */
2059 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_prim_id
;
2060 outputs
= malloc(num_outputs
* sizeof(outputs
[0]));
2062 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2063 if (!(ctx
->output_mask
& (1ull << i
)))
2066 outputs
[noutput
].slot_name
= i
;
2067 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
2069 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2070 !ctx
->args
->is_gs_copy_shader
) {
2071 outputs
[noutput
].usage_mask
=
2072 ctx
->args
->shader_info
->vs
.output_usage_mask
[i
];
2073 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2074 outputs
[noutput
].usage_mask
=
2075 ctx
->args
->shader_info
->tes
.output_usage_mask
[i
];
2077 assert(ctx
->args
->is_gs_copy_shader
);
2078 outputs
[noutput
].usage_mask
=
2079 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
2082 for (unsigned j
= 0; j
< 4; j
++) {
2083 outputs
[noutput
].values
[j
] =
2084 ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2090 /* Export PrimitiveID. */
2091 if (export_prim_id
) {
2092 outputs
[noutput
].slot_name
= VARYING_SLOT_PRIMITIVE_ID
;
2093 outputs
[noutput
].slot_index
= 0;
2094 outputs
[noutput
].usage_mask
= 0x1;
2095 outputs
[noutput
].values
[0] =
2096 ac_get_arg(&ctx
->ac
, ctx
->args
->vs_prim_id
);
2097 for (unsigned j
= 1; j
< 4; j
++)
2098 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
2102 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
2108 handle_es_outputs_post(struct radv_shader_context
*ctx
,
2109 struct radv_es_output_info
*outinfo
)
2112 LLVMValueRef lds_base
= NULL
;
2114 if (ctx
->ac
.chip_class
>= GFX9
) {
2115 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
2116 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
2117 LLVMValueRef wave_idx
=
2118 ac_unpack_param(&ctx
->ac
,
2119 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 24, 4);
2120 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
2121 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
2122 LLVMConstInt(ctx
->ac
.i32
,
2123 ctx
->ac
.wave_size
, false), ""), "");
2124 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
2125 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
2128 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2129 LLVMValueRef dw_addr
= NULL
;
2130 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2131 unsigned output_usage_mask
;
2134 if (!(ctx
->output_mask
& (1ull << i
)))
2137 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2139 ctx
->args
->shader_info
->vs
.output_usage_mask
[i
];
2141 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2143 ctx
->args
->shader_info
->tes
.output_usage_mask
[i
];
2146 param_index
= shader_io_get_unique_index(i
);
2149 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2150 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
2154 for (j
= 0; j
< 4; j
++) {
2155 if (!(output_usage_mask
& (1 << j
)))
2158 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2159 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
2160 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
2162 if (ctx
->ac
.chip_class
>= GFX9
) {
2163 LLVMValueRef dw_addr_offset
=
2164 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2165 LLVMConstInt(ctx
->ac
.i32
,
2168 ac_lds_store(&ctx
->ac
, dw_addr_offset
, out_val
);
2170 ac_build_buffer_store_dword(&ctx
->ac
,
2174 ac_get_arg(&ctx
->ac
, ctx
->args
->es2gs_offset
),
2175 (4 * param_index
+ j
) * 4,
2176 ac_glc
| ac_slc
| ac_swizzled
);
2183 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
2185 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
2186 uint32_t num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
2187 LLVMValueRef vertex_dw_stride
= LLVMConstInt(ctx
->ac
.i32
, num_tcs_inputs
* 4, false);
2188 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
2189 vertex_dw_stride
, "");
2191 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2192 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2194 if (!(ctx
->output_mask
& (1ull << i
)))
2197 int param
= shader_io_get_unique_index(i
);
2198 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
2199 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
2201 for (unsigned j
= 0; j
< 4; j
++) {
2202 LLVMValueRef value
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2203 value
= ac_to_integer(&ctx
->ac
, value
);
2204 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
2205 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
2206 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
2211 static LLVMValueRef
get_wave_id_in_tg(struct radv_shader_context
*ctx
)
2213 return ac_unpack_param(&ctx
->ac
,
2214 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 24, 4);
2217 static LLVMValueRef
get_tgsize(struct radv_shader_context
*ctx
)
2219 return ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 28, 4);
2222 static LLVMValueRef
get_thread_id_in_tg(struct radv_shader_context
*ctx
)
2224 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2226 tmp
= LLVMBuildMul(builder
, get_wave_id_in_tg(ctx
),
2227 LLVMConstInt(ctx
->ac
.i32
, ctx
->ac
.wave_size
, false), "");
2228 return LLVMBuildAdd(builder
, tmp
, ac_get_thread_id(&ctx
->ac
), "");
2231 static LLVMValueRef
ngg_get_vtx_cnt(struct radv_shader_context
*ctx
)
2233 return ac_build_bfe(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_tg_info
),
2234 LLVMConstInt(ctx
->ac
.i32
, 12, false),
2235 LLVMConstInt(ctx
->ac
.i32
, 9, false),
2239 static LLVMValueRef
ngg_get_prim_cnt(struct radv_shader_context
*ctx
)
2241 return ac_build_bfe(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_tg_info
),
2242 LLVMConstInt(ctx
->ac
.i32
, 22, false),
2243 LLVMConstInt(ctx
->ac
.i32
, 9, false),
2247 static LLVMValueRef
ngg_get_ordered_id(struct radv_shader_context
*ctx
)
2249 return ac_build_bfe(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_tg_info
),
2251 LLVMConstInt(ctx
->ac
.i32
, 11, false),
2256 ngg_gs_get_vertex_storage(struct radv_shader_context
*ctx
)
2258 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
);
2260 if (ctx
->args
->options
->key
.has_multiview_view_index
)
2263 LLVMTypeRef elements
[2] = {
2264 LLVMArrayType(ctx
->ac
.i32
, 4 * num_outputs
),
2265 LLVMArrayType(ctx
->ac
.i8
, 4),
2267 LLVMTypeRef type
= LLVMStructTypeInContext(ctx
->ac
.context
, elements
, 2, false);
2268 type
= LLVMPointerType(LLVMArrayType(type
, 0), AC_ADDR_SPACE_LDS
);
2269 return LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->gs_ngg_emit
, type
, "");
2273 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
2274 * is in emit order; that is:
2275 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
2276 * - during vertex emit, i.e. while the API GS shader invocation is running,
2277 * N = threadidx * gs_max_out_vertices + emitidx
2279 * Goals of the LDS memory layout:
2280 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
2281 * in uniform control flow
2282 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
2284 * 3. Agnostic to the number of waves (since we don't know it before compiling)
2285 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
2286 * 5. Avoid wasting memory.
2288 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
2289 * layout, elimination of bank conflicts requires that each vertex occupy an
2290 * odd number of dwords. We use the additional dword to store the output stream
2291 * index as well as a flag to indicate whether this vertex ends a primitive
2292 * for rasterization.
2294 * Swizzling is required to satisfy points 1 and 2 simultaneously.
2296 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
2297 * Indices are swizzled in groups of 32, which ensures point 1 without
2298 * disturbing point 2.
2300 * \return an LDS pointer to type {[N x i32], [4 x i8]}
2303 ngg_gs_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef vertexidx
)
2305 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2306 LLVMValueRef storage
= ngg_gs_get_vertex_storage(ctx
);
2308 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
2309 unsigned write_stride_2exp
= ffs(ctx
->shader
->info
.gs
.vertices_out
) - 1;
2310 if (write_stride_2exp
) {
2312 LLVMBuildLShr(builder
, vertexidx
,
2313 LLVMConstInt(ctx
->ac
.i32
, 5, false), "");
2314 LLVMValueRef swizzle
=
2315 LLVMBuildAnd(builder
, row
,
2316 LLVMConstInt(ctx
->ac
.i32
, (1u << write_stride_2exp
) - 1,
2318 vertexidx
= LLVMBuildXor(builder
, vertexidx
, swizzle
, "");
2321 return ac_build_gep0(&ctx
->ac
, storage
, vertexidx
);
2325 ngg_gs_emit_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef gsthread
,
2326 LLVMValueRef emitidx
)
2328 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2331 tmp
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false);
2332 tmp
= LLVMBuildMul(builder
, tmp
, gsthread
, "");
2333 const LLVMValueRef vertexidx
= LLVMBuildAdd(builder
, tmp
, emitidx
, "");
2334 return ngg_gs_vertex_ptr(ctx
, vertexidx
);
2337 /* Send GS Alloc Req message from the first wave of the group to SPI.
2338 * Message payload is:
2339 * - bits 0..10: vertices in group
2340 * - bits 12..22: primitives in group
2342 static void build_sendmsg_gs_alloc_req(struct radv_shader_context
*ctx
,
2343 LLVMValueRef vtx_cnt
,
2344 LLVMValueRef prim_cnt
)
2346 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2349 tmp
= LLVMBuildICmp(builder
, LLVMIntEQ
, get_wave_id_in_tg(ctx
), ctx
->ac
.i32_0
, "");
2350 ac_build_ifcc(&ctx
->ac
, tmp
, 5020);
2352 tmp
= LLVMBuildShl(builder
, prim_cnt
, LLVMConstInt(ctx
->ac
.i32
, 12, false),"");
2353 tmp
= LLVMBuildOr(builder
, tmp
, vtx_cnt
, "");
2354 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_ALLOC_REQ
, tmp
);
2356 ac_build_endif(&ctx
->ac
, 5020);
2360 unsigned num_vertices
;
2361 LLVMValueRef isnull
;
2363 LLVMValueRef index
[3];
2364 LLVMValueRef edgeflag
[3];
2367 static void build_export_prim(struct radv_shader_context
*ctx
,
2368 const struct ngg_prim
*prim
)
2370 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2371 struct ac_export_args args
;
2372 LLVMValueRef vertices
[3];
2373 LLVMValueRef odd
, even
;
2376 tmp
= LLVMBuildZExt(builder
, prim
->isnull
, ctx
->ac
.i32
, "");
2377 args
.out
[0] = LLVMBuildShl(builder
, tmp
, LLVMConstInt(ctx
->ac
.i32
, 31, false), "");
2379 for (unsigned i
= 0; i
< prim
->num_vertices
; ++i
) {
2380 tmp
= LLVMBuildZExt(builder
, prim
->edgeflag
[i
], ctx
->ac
.i32
, "");
2381 tmp
= LLVMBuildShl(builder
, tmp
,
2382 LLVMConstInt(ctx
->ac
.i32
, 9, false), "");
2383 vertices
[i
] = LLVMBuildOr(builder
, prim
->index
[i
], tmp
, "");
2386 switch (prim
->num_vertices
) {
2388 args
.out
[0] = LLVMBuildOr(builder
, args
.out
[0], vertices
[0], "");
2391 tmp
= LLVMBuildShl(builder
, vertices
[1],
2392 LLVMConstInt(ctx
->ac
.i32
, 10, false), "");
2393 tmp
= LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
2394 args
.out
[0] = LLVMBuildOr(builder
, tmp
, vertices
[0], "");
2397 /* Swap vertices if needed to follow drawing order. */
2398 tmp
= LLVMBuildShl(builder
, vertices
[2],
2399 LLVMConstInt(ctx
->ac
.i32
, 20, false), "");
2400 even
= LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
2401 tmp
= LLVMBuildShl(builder
, vertices
[1],
2402 LLVMConstInt(ctx
->ac
.i32
, 10, false), "");
2403 even
= LLVMBuildOr(builder
, even
, tmp
, "");
2404 even
= LLVMBuildOr(builder
, even
, vertices
[0], "");
2406 tmp
= LLVMBuildShl(builder
, vertices
[1],
2407 LLVMConstInt(ctx
->ac
.i32
, 20, false), "");
2408 odd
= LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
2409 tmp
= LLVMBuildShl(builder
, vertices
[2],
2410 LLVMConstInt(ctx
->ac
.i32
, 10, false), "");
2411 odd
= LLVMBuildOr(builder
, odd
, tmp
, "");
2412 odd
= LLVMBuildOr(builder
, odd
, vertices
[0], "");
2414 args
.out
[0] = LLVMBuildSelect(builder
, prim
->swap
, odd
, even
, "");
2417 unreachable("invalid number of vertices");
2420 args
.out
[0] = LLVMBuildBitCast(builder
, args
.out
[0], ctx
->ac
.f32
, "");
2421 args
.out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
2422 args
.out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
2423 args
.out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
2425 args
.target
= V_008DFC_SQ_EXP_PRIM
;
2426 args
.enabled_channels
= 1;
2428 args
.valid_mask
= false;
2431 ac_build_export(&ctx
->ac
, &args
);
2434 static struct radv_stream_output
*
2435 radv_get_stream_output_by_loc(struct radv_streamout_info
*so
, unsigned location
)
2437 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
2438 if (so
->outputs
[i
].location
== location
)
2439 return &so
->outputs
[i
];
2445 static void build_streamout_vertex(struct radv_shader_context
*ctx
,
2446 LLVMValueRef
*so_buffer
, LLVMValueRef
*wg_offset_dw
,
2447 unsigned stream
, LLVMValueRef offset_vtx
,
2448 LLVMValueRef vertexptr
)
2450 struct radv_streamout_info
*so
= &ctx
->args
->shader_info
->so
;
2451 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2452 LLVMValueRef offset
[4] = {};
2455 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2456 if (!wg_offset_dw
[buffer
])
2459 tmp
= LLVMBuildMul(builder
, offset_vtx
,
2460 LLVMConstInt(ctx
->ac
.i32
, so
->strides
[buffer
], false), "");
2461 tmp
= LLVMBuildAdd(builder
, wg_offset_dw
[buffer
], tmp
, "");
2462 offset
[buffer
] = LLVMBuildShl(builder
, tmp
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
2465 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
2466 struct radv_shader_output_values outputs
[AC_LLVM_MAX_OUTPUTS
];
2467 unsigned noutput
= 0;
2468 unsigned out_idx
= 0;
2470 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2471 unsigned output_usage_mask
=
2472 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
2473 uint8_t output_stream
=
2474 output_stream
= ctx
->args
->shader_info
->gs
.output_streams
[i
];
2476 if (!(ctx
->output_mask
& (1ull << i
)) ||
2477 output_stream
!= stream
)
2480 outputs
[noutput
].slot_name
= i
;
2481 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
2482 outputs
[noutput
].usage_mask
= output_usage_mask
;
2484 int length
= util_last_bit(output_usage_mask
);
2486 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
2487 if (!(output_usage_mask
& (1 << j
)))
2490 tmp
= ac_build_gep0(&ctx
->ac
, vertexptr
,
2491 LLVMConstInt(ctx
->ac
.i32
, out_idx
, false));
2492 outputs
[noutput
].values
[j
] = LLVMBuildLoad(builder
, tmp
, "");
2495 for (unsigned j
= length
; j
< 4; j
++)
2496 outputs
[noutput
].values
[j
] = LLVMGetUndef(ctx
->ac
.f32
);
2501 for (unsigned i
= 0; i
< noutput
; i
++) {
2502 struct radv_stream_output
*output
=
2503 radv_get_stream_output_by_loc(so
, outputs
[i
].slot_name
);
2506 output
->stream
!= stream
)
2509 struct radv_shader_output_values out
= {};
2511 for (unsigned j
= 0; j
< 4; j
++) {
2512 out
.values
[j
] = outputs
[i
].values
[j
];
2515 radv_emit_stream_output(ctx
, so_buffer
, offset
, output
, &out
);
2518 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
2519 struct radv_stream_output
*output
=
2520 &ctx
->args
->shader_info
->so
.outputs
[i
];
2522 if (stream
!= output
->stream
)
2525 struct radv_shader_output_values out
= {};
2527 for (unsigned comp
= 0; comp
< 4; comp
++) {
2528 if (!(output
->component_mask
& (1 << comp
)))
2531 tmp
= ac_build_gep0(&ctx
->ac
, vertexptr
,
2532 LLVMConstInt(ctx
->ac
.i32
, 4 * i
+ comp
, false));
2533 out
.values
[comp
] = LLVMBuildLoad(builder
, tmp
, "");
2536 radv_emit_stream_output(ctx
, so_buffer
, offset
, output
, &out
);
2541 struct ngg_streamout
{
2542 LLVMValueRef num_vertices
;
2544 /* per-thread data */
2545 LLVMValueRef prim_enable
[4]; /* i1 per stream */
2546 LLVMValueRef vertices
[3]; /* [N x i32] addrspace(LDS)* */
2549 LLVMValueRef emit
[4]; /* per-stream emitted primitives (only valid for used streams) */
2553 * Build streamout logic.
2555 * Implies a barrier.
2557 * Writes number of emitted primitives to gs_ngg_scratch[4:7].
2559 * Clobbers gs_ngg_scratch[8:].
2561 static void build_streamout(struct radv_shader_context
*ctx
,
2562 struct ngg_streamout
*nggso
)
2564 struct radv_streamout_info
*so
= &ctx
->args
->shader_info
->so
;
2565 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2566 LLVMValueRef buf_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_buffers
);
2567 LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
2568 LLVMValueRef cond
, tmp
, tmp2
;
2569 LLVMValueRef i32_2
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
2570 LLVMValueRef i32_4
= LLVMConstInt(ctx
->ac
.i32
, 4, false);
2571 LLVMValueRef i32_8
= LLVMConstInt(ctx
->ac
.i32
, 8, false);
2572 LLVMValueRef so_buffer
[4] = {};
2573 unsigned max_num_vertices
= 1 + (nggso
->vertices
[1] ? 1 : 0) +
2574 (nggso
->vertices
[2] ? 1 : 0);
2575 LLVMValueRef prim_stride_dw
[4] = {};
2576 LLVMValueRef prim_stride_dw_vgpr
= LLVMGetUndef(ctx
->ac
.i32
);
2577 int stream_for_buffer
[4] = { -1, -1, -1, -1 };
2578 unsigned bufmask_for_stream
[4] = {};
2579 bool isgs
= ctx
->stage
== MESA_SHADER_GEOMETRY
;
2580 unsigned scratch_emit_base
= isgs
? 4 : 0;
2581 LLVMValueRef scratch_emit_basev
= isgs
? i32_4
: ctx
->ac
.i32_0
;
2582 unsigned scratch_offset_base
= isgs
? 8 : 4;
2583 LLVMValueRef scratch_offset_basev
= isgs
? i32_8
: i32_4
;
2585 ac_llvm_add_target_dep_function_attr(ctx
->main_function
,
2586 "amdgpu-gds-size", 256);
2588 /* Determine the mapping of streamout buffers to vertex streams. */
2589 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
2590 unsigned buf
= so
->outputs
[i
].buffer
;
2591 unsigned stream
= so
->outputs
[i
].stream
;
2592 assert(stream_for_buffer
[buf
] < 0 || stream_for_buffer
[buf
] == stream
);
2593 stream_for_buffer
[buf
] = stream
;
2594 bufmask_for_stream
[stream
] |= 1 << buf
;
2597 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2598 if (stream_for_buffer
[buffer
] == -1)
2601 assert(so
->strides
[buffer
]);
2603 LLVMValueRef stride_for_buffer
=
2604 LLVMConstInt(ctx
->ac
.i32
, so
->strides
[buffer
], false);
2605 prim_stride_dw
[buffer
] =
2606 LLVMBuildMul(builder
, stride_for_buffer
,
2607 nggso
->num_vertices
, "");
2608 prim_stride_dw_vgpr
= ac_build_writelane(
2609 &ctx
->ac
, prim_stride_dw_vgpr
, prim_stride_dw
[buffer
],
2610 LLVMConstInt(ctx
->ac
.i32
, buffer
, false));
2612 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, buffer
, false);
2613 so_buffer
[buffer
] = ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
,
2617 cond
= LLVMBuildICmp(builder
, LLVMIntEQ
, get_wave_id_in_tg(ctx
), ctx
->ac
.i32_0
, "");
2618 ac_build_ifcc(&ctx
->ac
, cond
, 5200);
2620 LLVMTypeRef gdsptr
= LLVMPointerType(ctx
->ac
.i32
, AC_ADDR_SPACE_GDS
);
2621 LLVMValueRef gdsbase
= LLVMBuildIntToPtr(builder
, ctx
->ac
.i32_0
, gdsptr
, "");
2623 /* Advance the streamout offsets in GDS. */
2624 LLVMValueRef offsets_vgpr
= ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.i32
, "");
2625 LLVMValueRef generated_by_stream_vgpr
= ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.i32
, "");
2627 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, ac_get_thread_id(&ctx
->ac
), i32_4
, "");
2628 ac_build_ifcc(&ctx
->ac
, cond
, 5210);
2630 /* Fetch the number of generated primitives and store
2631 * it in GDS for later use.
2634 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tid
);
2635 tmp
= LLVMBuildLoad(builder
, tmp
, "");
2637 tmp
= ac_build_writelane(&ctx
->ac
, ctx
->ac
.i32_0
,
2638 ngg_get_prim_cnt(ctx
), ctx
->ac
.i32_0
);
2640 LLVMBuildStore(builder
, tmp
, generated_by_stream_vgpr
);
2642 unsigned swizzle
[4];
2643 int unused_stream
= -1;
2644 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2645 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
]) {
2646 unused_stream
= stream
;
2650 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2651 if (stream_for_buffer
[buffer
] >= 0) {
2652 swizzle
[buffer
] = stream_for_buffer
[buffer
];
2654 assert(unused_stream
>= 0);
2655 swizzle
[buffer
] = unused_stream
;
2659 tmp
= ac_build_quad_swizzle(&ctx
->ac
, tmp
,
2660 swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2661 tmp
= LLVMBuildMul(builder
, tmp
, prim_stride_dw_vgpr
, "");
2663 LLVMValueRef args
[] = {
2664 LLVMBuildIntToPtr(builder
, ngg_get_ordered_id(ctx
), gdsptr
, ""),
2666 ctx
->ac
.i32_0
, // ordering
2667 ctx
->ac
.i32_0
, // scope
2668 ctx
->ac
.i1false
, // isVolatile
2669 LLVMConstInt(ctx
->ac
.i32
, 4 << 24, false), // OA index
2670 ctx
->ac
.i1true
, // wave release
2671 ctx
->ac
.i1true
, // wave done
2674 tmp
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.ds.ordered.add",
2675 ctx
->ac
.i32
, args
, ARRAY_SIZE(args
), 0);
2677 /* Keep offsets in a VGPR for quick retrieval via readlane by
2678 * the first wave for bounds checking, and also store in LDS
2679 * for retrieval by all waves later. */
2680 LLVMBuildStore(builder
, tmp
, offsets_vgpr
);
2682 tmp2
= LLVMBuildAdd(builder
, ac_get_thread_id(&ctx
->ac
),
2683 scratch_offset_basev
, "");
2684 tmp2
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tmp2
);
2685 LLVMBuildStore(builder
, tmp
, tmp2
);
2687 ac_build_endif(&ctx
->ac
, 5210);
2689 /* Determine the max emit per buffer. This is done via the SALU, in part
2690 * because LLVM can't generate divide-by-multiply if we try to do this
2691 * via VALU with one lane per buffer.
2693 LLVMValueRef max_emit
[4] = {};
2694 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2695 if (stream_for_buffer
[buffer
] == -1)
2698 /* Compute the streamout buffer size in DWORD. */
2699 LLVMValueRef bufsize_dw
=
2700 LLVMBuildLShr(builder
,
2701 LLVMBuildExtractElement(builder
, so_buffer
[buffer
], i32_2
, ""),
2704 /* Load the streamout buffer offset from GDS. */
2705 tmp
= LLVMBuildLoad(builder
, offsets_vgpr
, "");
2706 LLVMValueRef offset_dw
=
2707 ac_build_readlane(&ctx
->ac
, tmp
,
2708 LLVMConstInt(ctx
->ac
.i32
, buffer
, false));
2710 /* Compute the remaining size to emit. */
2711 LLVMValueRef remaining_dw
=
2712 LLVMBuildSub(builder
, bufsize_dw
, offset_dw
, "");
2713 tmp
= LLVMBuildUDiv(builder
, remaining_dw
,
2714 prim_stride_dw
[buffer
], "");
2716 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
2717 bufsize_dw
, offset_dw
, "");
2718 max_emit
[buffer
] = LLVMBuildSelect(builder
, cond
,
2719 ctx
->ac
.i32_0
, tmp
, "");
2722 /* Determine the number of emitted primitives per stream and fixup the
2723 * GDS counter if necessary.
2725 * This is complicated by the fact that a single stream can emit to
2726 * multiple buffers (but luckily not vice versa).
2728 LLVMValueRef emit_vgpr
= ctx
->ac
.i32_0
;
2730 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2731 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
2734 /* Load the number of generated primitives from GDS and
2735 * determine that number for the given stream.
2737 tmp
= LLVMBuildLoad(builder
, generated_by_stream_vgpr
, "");
2738 LLVMValueRef generated
=
2739 ac_build_readlane(&ctx
->ac
, tmp
,
2740 LLVMConstInt(ctx
->ac
.i32
, stream
, false));
2743 /* Compute the number of emitted primitives. */
2744 LLVMValueRef emit
= generated
;
2745 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2746 if (stream_for_buffer
[buffer
] == stream
)
2747 emit
= ac_build_umin(&ctx
->ac
, emit
, max_emit
[buffer
]);
2750 /* Store the number of emitted primitives for that
2753 emit_vgpr
= ac_build_writelane(&ctx
->ac
, emit_vgpr
, emit
,
2754 LLVMConstInt(ctx
->ac
.i32
, stream
, false));
2756 /* Fixup the offset using a plain GDS atomic if we overflowed. */
2757 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, emit
, generated
, "");
2758 ac_build_ifcc(&ctx
->ac
, cond
, 5221); /* scalar branch */
2759 tmp
= LLVMBuildLShr(builder
,
2760 LLVMConstInt(ctx
->ac
.i32
, bufmask_for_stream
[stream
], false),
2761 ac_get_thread_id(&ctx
->ac
), "");
2762 tmp
= LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
2763 ac_build_ifcc(&ctx
->ac
, tmp
, 5222);
2765 tmp
= LLVMBuildSub(builder
, generated
, emit
, "");
2766 tmp
= LLVMBuildMul(builder
, tmp
, prim_stride_dw_vgpr
, "");
2767 tmp2
= LLVMBuildGEP(builder
, gdsbase
, &tid
, 1, "");
2768 LLVMBuildAtomicRMW(builder
, LLVMAtomicRMWBinOpSub
, tmp2
, tmp
,
2769 LLVMAtomicOrderingMonotonic
, false);
2771 ac_build_endif(&ctx
->ac
, 5222);
2772 ac_build_endif(&ctx
->ac
, 5221);
2775 /* Store the number of emitted primitives to LDS for later use. */
2776 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, ac_get_thread_id(&ctx
->ac
), i32_4
, "");
2777 ac_build_ifcc(&ctx
->ac
, cond
, 5225);
2779 tmp
= LLVMBuildAdd(builder
, ac_get_thread_id(&ctx
->ac
),
2780 scratch_emit_basev
, "");
2781 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tmp
);
2782 LLVMBuildStore(builder
, emit_vgpr
, tmp
);
2784 ac_build_endif(&ctx
->ac
, 5225);
2786 ac_build_endif(&ctx
->ac
, 5200);
2788 /* Determine the workgroup-relative per-thread / primitive offset into
2789 * the streamout buffers */
2790 struct ac_wg_scan primemit_scan
[4] = {};
2793 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2794 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
2797 primemit_scan
[stream
].enable_exclusive
= true;
2798 primemit_scan
[stream
].op
= nir_op_iadd
;
2799 primemit_scan
[stream
].src
= nggso
->prim_enable
[stream
];
2800 primemit_scan
[stream
].scratch
=
2801 ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
,
2802 LLVMConstInt(ctx
->ac
.i32
, 12 + 8 * stream
, false));
2803 primemit_scan
[stream
].waveidx
= get_wave_id_in_tg(ctx
);
2804 primemit_scan
[stream
].numwaves
= get_tgsize(ctx
);
2805 primemit_scan
[stream
].maxwaves
= 8;
2806 ac_build_wg_scan_top(&ctx
->ac
, &primemit_scan
[stream
]);
2810 ac_build_s_barrier(&ctx
->ac
);
2812 /* Fetch the per-buffer offsets and per-stream emit counts in all waves. */
2813 LLVMValueRef wgoffset_dw
[4] = {};
2816 LLVMValueRef scratch_vgpr
;
2818 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, ac_get_thread_id(&ctx
->ac
));
2819 scratch_vgpr
= LLVMBuildLoad(builder
, tmp
, "");
2821 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2822 if (stream_for_buffer
[buffer
] >= 0) {
2823 wgoffset_dw
[buffer
] = ac_build_readlane(
2824 &ctx
->ac
, scratch_vgpr
,
2825 LLVMConstInt(ctx
->ac
.i32
, scratch_offset_base
+ buffer
, false));
2829 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2830 if (ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
]) {
2831 nggso
->emit
[stream
] = ac_build_readlane(
2832 &ctx
->ac
, scratch_vgpr
,
2833 LLVMConstInt(ctx
->ac
.i32
, scratch_emit_base
+ stream
, false));
2838 /* Write out primitive data */
2839 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2840 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
2844 ac_build_wg_scan_bottom(&ctx
->ac
, &primemit_scan
[stream
]);
2846 primemit_scan
[stream
].result_exclusive
= tid
;
2849 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
2850 primemit_scan
[stream
].result_exclusive
,
2851 nggso
->emit
[stream
], "");
2852 cond
= LLVMBuildAnd(builder
, cond
, nggso
->prim_enable
[stream
], "");
2853 ac_build_ifcc(&ctx
->ac
, cond
, 5240);
2855 LLVMValueRef offset_vtx
=
2856 LLVMBuildMul(builder
, primemit_scan
[stream
].result_exclusive
,
2857 nggso
->num_vertices
, "");
2859 for (unsigned i
= 0; i
< max_num_vertices
; ++i
) {
2860 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
2861 LLVMConstInt(ctx
->ac
.i32
, i
, false),
2862 nggso
->num_vertices
, "");
2863 ac_build_ifcc(&ctx
->ac
, cond
, 5241);
2864 build_streamout_vertex(ctx
, so_buffer
, wgoffset_dw
,
2865 stream
, offset_vtx
, nggso
->vertices
[i
]);
2866 ac_build_endif(&ctx
->ac
, 5241);
2867 offset_vtx
= LLVMBuildAdd(builder
, offset_vtx
, ctx
->ac
.i32_1
, "");
2870 ac_build_endif(&ctx
->ac
, 5240);
2874 static unsigned ngg_nogs_vertex_size(struct radv_shader_context
*ctx
)
2876 unsigned lds_vertex_size
= 0;
2878 if (ctx
->args
->shader_info
->so
.num_outputs
)
2879 lds_vertex_size
= 4 * ctx
->args
->shader_info
->so
.num_outputs
+ 1;
2881 return lds_vertex_size
;
2885 * Returns an `[N x i32] addrspace(LDS)*` pointing at contiguous LDS storage
2886 * for the vertex outputs.
2888 static LLVMValueRef
ngg_nogs_vertex_ptr(struct radv_shader_context
*ctx
,
2891 /* The extra dword is used to avoid LDS bank conflicts. */
2892 unsigned vertex_size
= ngg_nogs_vertex_size(ctx
);
2893 LLVMTypeRef ai32
= LLVMArrayType(ctx
->ac
.i32
, vertex_size
);
2894 LLVMTypeRef pai32
= LLVMPointerType(ai32
, AC_ADDR_SPACE_LDS
);
2895 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->esgs_ring
, pai32
, "");
2896 return LLVMBuildGEP(ctx
->ac
.builder
, tmp
, &vtxid
, 1, "");
2900 handle_ngg_outputs_post_1(struct radv_shader_context
*ctx
)
2902 struct radv_streamout_info
*so
= &ctx
->args
->shader_info
->so
;
2903 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2904 LLVMValueRef vertex_ptr
= NULL
;
2905 LLVMValueRef tmp
, tmp2
;
2907 assert((ctx
->stage
== MESA_SHADER_VERTEX
||
2908 ctx
->stage
== MESA_SHADER_TESS_EVAL
) && !ctx
->args
->is_gs_copy_shader
);
2910 if (!ctx
->args
->shader_info
->so
.num_outputs
)
2913 vertex_ptr
= ngg_nogs_vertex_ptr(ctx
, get_thread_id_in_tg(ctx
));
2915 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
2916 struct radv_stream_output
*output
=
2917 &ctx
->args
->shader_info
->so
.outputs
[i
];
2919 unsigned loc
= output
->location
;
2921 for (unsigned comp
= 0; comp
< 4; comp
++) {
2922 if (!(output
->component_mask
& (1 << comp
)))
2925 tmp
= ac_build_gep0(&ctx
->ac
, vertex_ptr
,
2926 LLVMConstInt(ctx
->ac
.i32
, 4 * i
+ comp
, false));
2927 tmp2
= LLVMBuildLoad(builder
,
2928 ctx
->abi
.outputs
[4 * loc
+ comp
], "");
2929 tmp2
= ac_to_integer(&ctx
->ac
, tmp2
);
2930 LLVMBuildStore(builder
, tmp2
, tmp
);
2936 handle_ngg_outputs_post_2(struct radv_shader_context
*ctx
)
2938 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2941 assert((ctx
->stage
== MESA_SHADER_VERTEX
||
2942 ctx
->stage
== MESA_SHADER_TESS_EVAL
) && !ctx
->args
->is_gs_copy_shader
);
2944 LLVMValueRef prims_in_wave
= ac_unpack_param(&ctx
->ac
,
2945 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 8, 8);
2946 LLVMValueRef vtx_in_wave
= ac_unpack_param(&ctx
->ac
,
2947 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 0, 8);
2948 LLVMValueRef is_gs_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
2949 ac_get_thread_id(&ctx
->ac
), prims_in_wave
, "");
2950 LLVMValueRef is_es_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
2951 ac_get_thread_id(&ctx
->ac
), vtx_in_wave
, "");
2952 LLVMValueRef vtxindex
[] = {
2953 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[0]), 0, 16),
2954 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[0]), 16, 16),
2955 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[2]), 0, 16),
2958 /* Determine the number of vertices per primitive. */
2959 unsigned num_vertices
;
2960 LLVMValueRef num_vertices_val
;
2962 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2963 LLVMValueRef outprim_val
=
2964 LLVMConstInt(ctx
->ac
.i32
,
2965 ctx
->args
->options
->key
.vs
.outprim
, false);
2966 num_vertices_val
= LLVMBuildAdd(builder
, outprim_val
,
2968 num_vertices
= 3; /* TODO: optimize for points & lines */
2970 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2972 if (ctx
->shader
->info
.tess
.point_mode
)
2974 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
2979 num_vertices_val
= LLVMConstInt(ctx
->ac
.i32
, num_vertices
, false);
2983 if (ctx
->args
->shader_info
->so
.num_outputs
) {
2984 struct ngg_streamout nggso
= {};
2986 nggso
.num_vertices
= num_vertices_val
;
2987 nggso
.prim_enable
[0] = is_gs_thread
;
2989 for (unsigned i
= 0; i
< num_vertices
; ++i
)
2990 nggso
.vertices
[i
] = ngg_nogs_vertex_ptr(ctx
, vtxindex
[i
]);
2992 build_streamout(ctx
, &nggso
);
2995 /* Copy Primitive IDs from GS threads to the LDS address corresponding
2996 * to the ES thread of the provoking vertex.
2998 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2999 ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
3000 if (ctx
->args
->shader_info
->so
.num_outputs
)
3001 ac_build_s_barrier(&ctx
->ac
);
3003 ac_build_ifcc(&ctx
->ac
, is_gs_thread
, 5400);
3004 /* Extract the PROVOKING_VTX_INDEX field. */
3005 LLVMValueRef provoking_vtx_in_prim
=
3006 LLVMConstInt(ctx
->ac
.i32
, 0, false);
3008 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
3009 LLVMValueRef indices
= ac_build_gather_values(&ctx
->ac
, vtxindex
, 3);
3010 LLVMValueRef provoking_vtx_index
=
3011 LLVMBuildExtractElement(builder
, indices
, provoking_vtx_in_prim
, "");
3013 LLVMBuildStore(builder
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.gs_prim_id
),
3014 ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
, provoking_vtx_index
));
3015 ac_build_endif(&ctx
->ac
, 5400);
3018 /* TODO: primitive culling */
3020 build_sendmsg_gs_alloc_req(ctx
, ngg_get_vtx_cnt(ctx
), ngg_get_prim_cnt(ctx
));
3022 /* TODO: streamout queries */
3023 /* Export primitive data to the index buffer. Format is:
3024 * - bits 0..8: index 0
3025 * - bit 9: edge flag 0
3026 * - bits 10..18: index 1
3027 * - bit 19: edge flag 1
3028 * - bits 20..28: index 2
3029 * - bit 29: edge flag 2
3030 * - bit 31: null primitive (skip)
3032 * For the first version, we will always build up all three indices
3033 * independent of the primitive type. The additional garbage data
3036 * TODO: culling depends on the primitive type, so can have some
3039 ac_build_ifcc(&ctx
->ac
, is_gs_thread
, 6001);
3041 struct ngg_prim prim
= {};
3043 prim
.num_vertices
= num_vertices
;
3044 prim
.isnull
= ctx
->ac
.i1false
;
3045 prim
.swap
= ctx
->ac
.i1false
;
3046 memcpy(prim
.index
, vtxindex
, sizeof(vtxindex
[0]) * 3);
3048 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
3049 tmp
= LLVMBuildLShr(builder
,
3050 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.gs_invocation_id
),
3051 LLVMConstInt(ctx
->ac
.i32
, 8 + i
, false), "");
3052 prim
.edgeflag
[i
] = LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3055 build_export_prim(ctx
, &prim
);
3057 ac_build_endif(&ctx
->ac
, 6001);
3059 /* Export per-vertex data (positions and parameters). */
3060 ac_build_ifcc(&ctx
->ac
, is_es_thread
, 6002);
3062 struct radv_vs_output_info
*outinfo
=
3063 ctx
->stage
== MESA_SHADER_TESS_EVAL
?
3064 &ctx
->args
->shader_info
->tes
.outinfo
: &ctx
->args
->shader_info
->vs
.outinfo
;
3066 /* Exporting the primitive ID is handled below. */
3067 /* TODO: use the new VS export path */
3068 handle_vs_outputs_post(ctx
, false,
3069 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
,
3072 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
3073 unsigned param_count
= outinfo
->param_exports
;
3074 LLVMValueRef values
[4];
3076 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3077 /* Wait for GS stores to finish. */
3078 ac_build_s_barrier(&ctx
->ac
);
3080 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
,
3081 get_thread_id_in_tg(ctx
));
3082 values
[0] = LLVMBuildLoad(builder
, tmp
, "");
3084 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
3085 values
[0] = ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tes_patch_id
);
3088 values
[0] = ac_to_float(&ctx
->ac
, values
[0]);
3089 for (unsigned j
= 1; j
< 4; j
++)
3090 values
[j
] = ctx
->ac
.f32_0
;
3092 radv_export_param(ctx
, param_count
, values
, 0x1);
3094 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
3095 outinfo
->param_exports
= param_count
;
3098 ac_build_endif(&ctx
->ac
, 6002);
3101 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context
*ctx
)
3103 /* Zero out the part of LDS scratch that is used to accumulate the
3104 * per-stream generated primitive count.
3106 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3107 LLVMValueRef scratchptr
= ctx
->gs_ngg_scratch
;
3108 LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3109 LLVMBasicBlockRef merge_block
;
3112 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
3113 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
3114 merge_block
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
3116 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3117 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, then_block
, merge_block
);
3118 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, then_block
);
3120 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, scratchptr
, tid
);
3121 LLVMBuildStore(builder
, ctx
->ac
.i32_0
, ptr
);
3123 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
3124 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
3126 ac_build_s_barrier(&ctx
->ac
);
3129 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context
*ctx
)
3131 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3132 LLVMValueRef i8_0
= LLVMConstInt(ctx
->ac
.i8
, 0, false);
3135 /* Zero out remaining (non-emitted) primitive flags.
3137 * Note: Alternatively, we could pass the relevant gs_next_vertex to
3138 * the emit threads via LDS. This is likely worse in the expected
3139 * typical case where each GS thread emits the full set of
3142 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3143 unsigned num_components
;
3146 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
3147 if (!num_components
)
3150 const LLVMValueRef gsthread
= get_thread_id_in_tg(ctx
);
3152 ac_build_bgnloop(&ctx
->ac
, 5100);
3154 const LLVMValueRef vertexidx
=
3155 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
3156 tmp
= LLVMBuildICmp(builder
, LLVMIntUGE
, vertexidx
,
3157 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
3158 ac_build_ifcc(&ctx
->ac
, tmp
, 5101);
3159 ac_build_break(&ctx
->ac
);
3160 ac_build_endif(&ctx
->ac
, 5101);
3162 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
3163 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
3165 tmp
= ngg_gs_emit_vertex_ptr(ctx
, gsthread
, vertexidx
);
3166 LLVMValueRef gep_idx
[3] = {
3167 ctx
->ac
.i32_0
, /* implied C-style array */
3168 ctx
->ac
.i32_1
, /* second entry of struct */
3169 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
3171 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3172 LLVMBuildStore(builder
, i8_0
, tmp
);
3174 ac_build_endloop(&ctx
->ac
, 5100);
3177 /* Accumulate generated primitives counts across the entire threadgroup. */
3178 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3179 unsigned num_components
;
3182 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
3183 if (!num_components
)
3186 LLVMValueRef numprims
=
3187 LLVMBuildLoad(builder
, ctx
->gs_generated_prims
[stream
], "");
3188 numprims
= ac_build_reduce(&ctx
->ac
, numprims
, nir_op_iadd
, ctx
->ac
.wave_size
);
3190 tmp
= LLVMBuildICmp(builder
, LLVMIntEQ
, ac_get_thread_id(&ctx
->ac
), ctx
->ac
.i32_0
, "");
3191 ac_build_ifcc(&ctx
->ac
, tmp
, 5105);
3193 LLVMBuildAtomicRMW(builder
, LLVMAtomicRMWBinOpAdd
,
3194 ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
,
3195 LLVMConstInt(ctx
->ac
.i32
, stream
, false)),
3196 numprims
, LLVMAtomicOrderingMonotonic
, false);
3198 ac_build_endif(&ctx
->ac
, 5105);
3202 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context
*ctx
)
3204 const unsigned verts_per_prim
= si_conv_gl_prim_to_vertices(ctx
->shader
->info
.gs
.output_primitive
);
3205 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3206 LLVMValueRef tmp
, tmp2
;
3208 ac_build_s_barrier(&ctx
->ac
);
3210 const LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3211 LLVMValueRef num_emit_threads
= ngg_get_prim_cnt(ctx
);
3214 if (ctx
->args
->shader_info
->so
.num_outputs
) {
3215 struct ngg_streamout nggso
= {};
3217 nggso
.num_vertices
= LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
, false);
3219 LLVMValueRef vertexptr
= ngg_gs_vertex_ptr(ctx
, tid
);
3220 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3221 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
3224 LLVMValueRef gep_idx
[3] = {
3225 ctx
->ac
.i32_0
, /* implicit C-style array */
3226 ctx
->ac
.i32_1
, /* second value of struct */
3227 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
3229 tmp
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3230 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3231 tmp
= LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3232 tmp2
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3233 nggso
.prim_enable
[stream
] = LLVMBuildAnd(builder
, tmp
, tmp2
, "");
3236 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3237 tmp
= LLVMBuildSub(builder
, tid
,
3238 LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
- i
- 1, false), "");
3239 tmp
= ngg_gs_vertex_ptr(ctx
, tmp
);
3240 nggso
.vertices
[i
] = ac_build_gep0(&ctx
->ac
, tmp
, ctx
->ac
.i32_0
);
3243 build_streamout(ctx
, &nggso
);
3248 /* Determine vertex liveness. */
3249 LLVMValueRef vertliveptr
= ac_build_alloca(&ctx
->ac
, ctx
->ac
.i1
, "vertexlive");
3251 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3252 ac_build_ifcc(&ctx
->ac
, tmp
, 5120);
3254 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3255 const LLVMValueRef primidx
=
3256 LLVMBuildAdd(builder
, tid
,
3257 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
3260 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, primidx
, num_emit_threads
, "");
3261 ac_build_ifcc(&ctx
->ac
, tmp
, 5121 + i
);
3264 /* Load primitive liveness */
3265 tmp
= ngg_gs_vertex_ptr(ctx
, primidx
);
3266 LLVMValueRef gep_idx
[3] = {
3267 ctx
->ac
.i32_0
, /* implicit C-style array */
3268 ctx
->ac
.i32_1
, /* second value of struct */
3269 ctx
->ac
.i32_0
, /* stream 0 */
3271 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3272 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3273 const LLVMValueRef primlive
=
3274 LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3276 tmp
= LLVMBuildLoad(builder
, vertliveptr
, "");
3277 tmp
= LLVMBuildOr(builder
, tmp
, primlive
, ""),
3278 LLVMBuildStore(builder
, tmp
, vertliveptr
);
3281 ac_build_endif(&ctx
->ac
, 5121 + i
);
3284 ac_build_endif(&ctx
->ac
, 5120);
3286 /* Inclusive scan addition across the current wave. */
3287 LLVMValueRef vertlive
= LLVMBuildLoad(builder
, vertliveptr
, "");
3288 struct ac_wg_scan vertlive_scan
= {};
3289 vertlive_scan
.op
= nir_op_iadd
;
3290 vertlive_scan
.enable_reduce
= true;
3291 vertlive_scan
.enable_exclusive
= true;
3292 vertlive_scan
.src
= vertlive
;
3293 vertlive_scan
.scratch
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, ctx
->ac
.i32_0
);
3294 vertlive_scan
.waveidx
= get_wave_id_in_tg(ctx
);
3295 vertlive_scan
.numwaves
= get_tgsize(ctx
);
3296 vertlive_scan
.maxwaves
= 8;
3298 ac_build_wg_scan(&ctx
->ac
, &vertlive_scan
);
3300 /* Skip all exports (including index exports) when possible. At least on
3301 * early gfx10 revisions this is also to avoid hangs.
3303 LLVMValueRef have_exports
=
3304 LLVMBuildICmp(builder
, LLVMIntNE
, vertlive_scan
.result_reduce
, ctx
->ac
.i32_0
, "");
3306 LLVMBuildSelect(builder
, have_exports
, num_emit_threads
, ctx
->ac
.i32_0
, "");
3308 /* Allocate export space. Send this message as early as possible, to
3309 * hide the latency of the SQ <-> SPI roundtrip.
3311 * Note: We could consider compacting primitives for export as well.
3312 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3313 * prim data per clock and skips null primitives at no additional
3314 * cost. So compacting primitives can only be beneficial when
3315 * there are 4 or more contiguous null primitives in the export
3316 * (in the common case of single-dword prim exports).
3318 build_sendmsg_gs_alloc_req(ctx
, vertlive_scan
.result_reduce
, num_emit_threads
);
3320 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3321 * of the primitive liveness flags, relying on the fact that each
3322 * threadgroup can have at most 256 threads. */
3323 ac_build_ifcc(&ctx
->ac
, vertlive
, 5130);
3325 tmp
= ngg_gs_vertex_ptr(ctx
, vertlive_scan
.result_exclusive
);
3326 LLVMValueRef gep_idx
[3] = {
3327 ctx
->ac
.i32_0
, /* implicit C-style array */
3328 ctx
->ac
.i32_1
, /* second value of struct */
3329 ctx
->ac
.i32_1
, /* stream 1 */
3331 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3332 tmp2
= LLVMBuildTrunc(builder
, tid
, ctx
->ac
.i8
, "");
3333 LLVMBuildStore(builder
, tmp2
, tmp
);
3335 ac_build_endif(&ctx
->ac
, 5130);
3337 ac_build_s_barrier(&ctx
->ac
);
3339 /* Export primitive data */
3340 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3341 ac_build_ifcc(&ctx
->ac
, tmp
, 5140);
3343 struct ngg_prim prim
= {};
3344 prim
.num_vertices
= verts_per_prim
;
3346 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
3347 LLVMValueRef gep_idx
[3] = {
3348 ctx
->ac
.i32_0
, /* implicit C-style array */
3349 ctx
->ac
.i32_1
, /* second value of struct */
3350 ctx
->ac
.i32_0
, /* primflag */
3352 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3353 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3354 prim
.isnull
= LLVMBuildICmp(builder
, LLVMIntEQ
, tmp
,
3355 LLVMConstInt(ctx
->ac
.i8
, 0, false), "");
3356 prim
.swap
= LLVMBuildICmp(builder
, LLVMIntEQ
,
3357 LLVMBuildAnd(builder
, tid
, LLVMConstInt(ctx
->ac
.i32
, 1, false), ""),
3358 LLVMConstInt(ctx
->ac
.i32
, 1, false), "");
3360 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3361 prim
.index
[i
] = LLVMBuildSub(builder
, vertlive_scan
.result_exclusive
,
3362 LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
- i
- 1, false), "");
3363 prim
.edgeflag
[i
] = ctx
->ac
.i1false
;
3366 build_export_prim(ctx
, &prim
);
3368 ac_build_endif(&ctx
->ac
, 5140);
3370 /* Export position and parameter data */
3371 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, vertlive_scan
.result_reduce
, "");
3372 ac_build_ifcc(&ctx
->ac
, tmp
, 5145);
3374 struct radv_vs_output_info
*outinfo
= &ctx
->args
->shader_info
->vs
.outinfo
;
3375 bool export_view_index
= ctx
->args
->options
->key
.has_multiview_view_index
;
3376 struct radv_shader_output_values
*outputs
;
3377 unsigned noutput
= 0;
3379 /* Allocate a temporary array for the output values. */
3380 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_view_index
;
3381 outputs
= calloc(num_outputs
, sizeof(outputs
[0]));
3383 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
3384 sizeof(outinfo
->vs_output_param_offset
));
3385 outinfo
->pos_exports
= 0;
3387 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
3388 LLVMValueRef gep_idx
[3] = {
3389 ctx
->ac
.i32_0
, /* implicit C-style array */
3390 ctx
->ac
.i32_1
, /* second value of struct */
3391 ctx
->ac
.i32_1
, /* stream 1: source data index */
3393 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3394 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3395 tmp
= LLVMBuildZExt(builder
, tmp
, ctx
->ac
.i32
, "");
3396 const LLVMValueRef vertexptr
= ngg_gs_vertex_ptr(ctx
, tmp
);
3398 unsigned out_idx
= 0;
3399 gep_idx
[1] = ctx
->ac
.i32_0
;
3400 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3401 unsigned output_usage_mask
=
3402 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
3403 int length
= util_last_bit(output_usage_mask
);
3405 if (!(ctx
->output_mask
& (1ull << i
)))
3408 outputs
[noutput
].slot_name
= i
;
3409 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
3410 outputs
[noutput
].usage_mask
= output_usage_mask
;
3412 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
3413 if (!(output_usage_mask
& (1 << j
)))
3416 gep_idx
[2] = LLVMConstInt(ctx
->ac
.i32
, out_idx
, false);
3417 tmp
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3418 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3420 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
3421 if (ac_get_type_size(type
) == 2) {
3422 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
3423 tmp
= LLVMBuildTrunc(ctx
->ac
.builder
, tmp
, ctx
->ac
.i16
, "");
3426 outputs
[noutput
].values
[j
] = ac_to_float(&ctx
->ac
, tmp
);
3429 for (unsigned j
= length
; j
< 4; j
++)
3430 outputs
[noutput
].values
[j
] = LLVMGetUndef(ctx
->ac
.f32
);
3435 /* Export ViewIndex. */
3436 if (export_view_index
) {
3437 outputs
[noutput
].slot_name
= VARYING_SLOT_LAYER
;
3438 outputs
[noutput
].slot_index
= 0;
3439 outputs
[noutput
].usage_mask
= 0x1;
3440 outputs
[noutput
].values
[0] =
3441 ac_to_float(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.view_index
));
3442 for (unsigned j
= 1; j
< 4; j
++)
3443 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
3447 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
,
3448 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
);
3451 ac_build_endif(&ctx
->ac
, 5145);
3454 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
3456 LLVMValueRef
*addrs
)
3458 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3460 const LLVMValueRef vertexidx
=
3461 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
3463 /* If this thread has already emitted the declared maximum number of
3464 * vertices, skip the write: excessive vertex emissions are not
3465 * supposed to have any effect.
3467 const LLVMValueRef can_emit
=
3468 LLVMBuildICmp(builder
, LLVMIntULT
, vertexidx
,
3469 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
3470 ac_build_ifcc(&ctx
->ac
, can_emit
, 9001);
3472 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
3473 tmp
= LLVMBuildSelect(builder
, can_emit
, tmp
, vertexidx
, "");
3474 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
3476 const LLVMValueRef vertexptr
=
3477 ngg_gs_emit_vertex_ptr(ctx
, get_thread_id_in_tg(ctx
), vertexidx
);
3478 unsigned out_idx
= 0;
3479 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3480 unsigned output_usage_mask
=
3481 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
3482 uint8_t output_stream
=
3483 ctx
->args
->shader_info
->gs
.output_streams
[i
];
3484 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
3485 int length
= util_last_bit(output_usage_mask
);
3487 if (!(ctx
->output_mask
& (1ull << i
)) ||
3488 output_stream
!= stream
)
3491 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
3492 if (!(output_usage_mask
& (1 << j
)))
3495 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
3497 LLVMValueRef gep_idx
[3] = {
3498 ctx
->ac
.i32_0
, /* implied C-style array */
3499 ctx
->ac
.i32_0
, /* first entry of struct */
3500 LLVMConstInt(ctx
->ac
.i32
, out_idx
, false),
3502 LLVMValueRef ptr
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3504 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
3505 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
3507 LLVMBuildStore(builder
, out_val
, ptr
);
3510 assert(out_idx
* 4 <= ctx
->args
->shader_info
->gs
.gsvs_vertex_size
);
3512 /* Determine and store whether this vertex completed a primitive. */
3513 const LLVMValueRef curverts
= LLVMBuildLoad(builder
, ctx
->gs_curprim_verts
[stream
], "");
3515 tmp
= LLVMConstInt(ctx
->ac
.i32
, si_conv_gl_prim_to_vertices(ctx
->shader
->info
.gs
.output_primitive
) - 1, false);
3516 const LLVMValueRef iscompleteprim
=
3517 LLVMBuildICmp(builder
, LLVMIntUGE
, curverts
, tmp
, "");
3519 tmp
= LLVMBuildAdd(builder
, curverts
, ctx
->ac
.i32_1
, "");
3520 LLVMBuildStore(builder
, tmp
, ctx
->gs_curprim_verts
[stream
]);
3522 LLVMValueRef gep_idx
[3] = {
3523 ctx
->ac
.i32_0
, /* implied C-style array */
3524 ctx
->ac
.i32_1
, /* second struct entry */
3525 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
3527 const LLVMValueRef primflagptr
=
3528 LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3530 tmp
= LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i8
, "");
3531 LLVMBuildStore(builder
, tmp
, primflagptr
);
3533 tmp
= LLVMBuildLoad(builder
, ctx
->gs_generated_prims
[stream
], "");
3534 tmp
= LLVMBuildAdd(builder
, tmp
, LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i32
, ""), "");
3535 LLVMBuildStore(builder
, tmp
, ctx
->gs_generated_prims
[stream
]);
3537 ac_build_endif(&ctx
->ac
, 9001);
3541 write_tess_factors(struct radv_shader_context
*ctx
)
3543 unsigned stride
, outer_comps
, inner_comps
;
3544 LLVMValueRef tcs_rel_ids
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_rel_ids
);
3545 LLVMValueRef invocation_id
= ac_unpack_param(&ctx
->ac
, tcs_rel_ids
, 8, 5);
3546 LLVMValueRef rel_patch_id
= ac_unpack_param(&ctx
->ac
, tcs_rel_ids
, 0, 8);
3547 unsigned tess_inner_index
= 0, tess_outer_index
;
3548 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
3549 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
3551 ac_emit_barrier(&ctx
->ac
, ctx
->stage
);
3553 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
3573 ac_build_ifcc(&ctx
->ac
,
3574 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3575 invocation_id
, ctx
->ac
.i32_0
, ""), 6503);
3577 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
3580 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3581 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3582 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
3585 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3586 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3587 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
3589 for (i
= 0; i
< 4; i
++) {
3590 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3591 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3595 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
3596 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
3597 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3599 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
3601 for (i
= 0; i
< outer_comps
; i
++) {
3603 ac_lds_load(&ctx
->ac
, lds_outer
);
3604 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3607 for (i
= 0; i
< inner_comps
; i
++) {
3608 inner
[i
] = out
[outer_comps
+i
] =
3609 ac_lds_load(&ctx
->ac
, lds_inner
);
3610 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
3615 /* Convert the outputs to vectors for stores. */
3616 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
3620 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
3623 buffer
= ctx
->hs_ring_tess_factor
;
3624 tf_base
= ac_get_arg(&ctx
->ac
, ctx
->args
->tess_factor_offset
);
3625 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
3626 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
3627 unsigned tf_offset
= 0;
3629 if (ctx
->ac
.chip_class
<= GFX8
) {
3630 ac_build_ifcc(&ctx
->ac
,
3631 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3632 rel_patch_id
, ctx
->ac
.i32_0
, ""), 6504);
3634 /* Store the dynamic HS control word. */
3635 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
3636 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
3637 1, ctx
->ac
.i32_0
, tf_base
,
3641 ac_build_endif(&ctx
->ac
, 6504);
3644 /* Store the tessellation factors. */
3645 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
3646 MIN2(stride
, 4), byteoffset
, tf_base
,
3649 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
3650 stride
- 4, byteoffset
, tf_base
,
3651 16 + tf_offset
, ac_glc
);
3653 //store to offchip for TES to read - only if TES reads them
3654 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
3655 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
3656 LLVMValueRef tf_inner_offset
;
3657 unsigned param_outer
, param_inner
;
3659 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3660 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3661 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
3663 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
3664 util_next_power_of_two(outer_comps
));
3666 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
3667 outer_comps
, tf_outer_offset
,
3668 ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
),
3671 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3672 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3673 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
3675 inner_vec
= inner_comps
== 1 ? inner
[0] :
3676 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
3677 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
3678 inner_comps
, tf_inner_offset
,
3679 ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
),
3684 ac_build_endif(&ctx
->ac
, 6503);
3688 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
3690 write_tess_factors(ctx
);
3694 si_export_mrt_color(struct radv_shader_context
*ctx
,
3695 LLVMValueRef
*color
, unsigned index
,
3696 struct ac_export_args
*args
)
3699 si_llvm_init_export_args(ctx
, color
, 0xf,
3700 V_008DFC_SQ_EXP_MRT
+ index
, args
);
3701 if (!args
->enabled_channels
)
3702 return false; /* unnecessary NULL export */
3708 radv_export_mrt_z(struct radv_shader_context
*ctx
,
3709 LLVMValueRef depth
, LLVMValueRef stencil
,
3710 LLVMValueRef samplemask
)
3712 struct ac_export_args args
;
3714 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
3716 ac_build_export(&ctx
->ac
, &args
);
3720 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
3723 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3724 struct ac_export_args color_args
[8];
3726 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3727 LLVMValueRef values
[4];
3729 if (!(ctx
->output_mask
& (1ull << i
)))
3732 if (i
< FRAG_RESULT_DATA0
)
3735 for (unsigned j
= 0; j
< 4; j
++)
3736 values
[j
] = ac_to_float(&ctx
->ac
,
3737 radv_load_output(ctx
, i
, j
));
3739 bool ret
= si_export_mrt_color(ctx
, values
,
3740 i
- FRAG_RESULT_DATA0
,
3741 &color_args
[index
]);
3746 /* Process depth, stencil, samplemask. */
3747 if (ctx
->args
->shader_info
->ps
.writes_z
) {
3748 depth
= ac_to_float(&ctx
->ac
,
3749 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
3751 if (ctx
->args
->shader_info
->ps
.writes_stencil
) {
3752 stencil
= ac_to_float(&ctx
->ac
,
3753 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
3755 if (ctx
->args
->shader_info
->ps
.writes_sample_mask
) {
3756 samplemask
= ac_to_float(&ctx
->ac
,
3757 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
3760 /* Set the DONE bit on last non-null color export only if Z isn't
3764 !ctx
->args
->shader_info
->ps
.writes_z
&&
3765 !ctx
->args
->shader_info
->ps
.writes_stencil
&&
3766 !ctx
->args
->shader_info
->ps
.writes_sample_mask
) {
3767 unsigned last
= index
- 1;
3769 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
3770 color_args
[last
].done
= 1; /* DONE bit */
3773 /* Export PS outputs. */
3774 for (unsigned i
= 0; i
< index
; i
++)
3775 ac_build_export(&ctx
->ac
, &color_args
[i
]);
3777 if (depth
|| stencil
|| samplemask
)
3778 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
3780 ac_build_export_null(&ctx
->ac
);
3784 emit_gs_epilogue(struct radv_shader_context
*ctx
)
3786 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
3787 gfx10_ngg_gs_emit_epilogue_1(ctx
);
3791 if (ctx
->ac
.chip_class
>= GFX10
)
3792 LLVMBuildFence(ctx
->ac
.builder
, LLVMAtomicOrderingRelease
, false, "");
3794 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
3798 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
3799 LLVMValueRef
*addrs
)
3801 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
3803 switch (ctx
->stage
) {
3804 case MESA_SHADER_VERTEX
:
3805 if (ctx
->args
->options
->key
.vs_common_out
.as_ls
)
3806 handle_ls_outputs_post(ctx
);
3807 else if (ctx
->args
->options
->key
.vs_common_out
.as_es
)
3808 handle_es_outputs_post(ctx
, &ctx
->args
->shader_info
->vs
.es_info
);
3809 else if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
)
3810 handle_ngg_outputs_post_1(ctx
);
3812 handle_vs_outputs_post(ctx
, ctx
->args
->options
->key
.vs_common_out
.export_prim_id
,
3813 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
,
3814 &ctx
->args
->shader_info
->vs
.outinfo
);
3816 case MESA_SHADER_FRAGMENT
:
3817 handle_fs_outputs_post(ctx
);
3819 case MESA_SHADER_GEOMETRY
:
3820 emit_gs_epilogue(ctx
);
3822 case MESA_SHADER_TESS_CTRL
:
3823 handle_tcs_outputs_post(ctx
);
3825 case MESA_SHADER_TESS_EVAL
:
3826 if (ctx
->args
->options
->key
.vs_common_out
.as_es
)
3827 handle_es_outputs_post(ctx
, &ctx
->args
->shader_info
->tes
.es_info
);
3828 else if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
)
3829 handle_ngg_outputs_post_1(ctx
);
3831 handle_vs_outputs_post(ctx
, ctx
->args
->options
->key
.vs_common_out
.export_prim_id
,
3832 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
,
3833 &ctx
->args
->shader_info
->tes
.outinfo
);
3840 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
,
3841 LLVMPassManagerRef passmgr
,
3842 const struct radv_nir_compiler_options
*options
)
3844 LLVMRunPassManager(passmgr
, ctx
->ac
.module
);
3845 LLVMDisposeBuilder(ctx
->ac
.builder
);
3847 ac_llvm_context_dispose(&ctx
->ac
);
3851 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
3853 struct radv_vs_output_info
*outinfo
;
3855 switch (ctx
->stage
) {
3856 case MESA_SHADER_FRAGMENT
:
3857 case MESA_SHADER_COMPUTE
:
3858 case MESA_SHADER_TESS_CTRL
:
3859 case MESA_SHADER_GEOMETRY
:
3861 case MESA_SHADER_VERTEX
:
3862 if (ctx
->args
->options
->key
.vs_common_out
.as_ls
||
3863 ctx
->args
->options
->key
.vs_common_out
.as_es
)
3865 outinfo
= &ctx
->args
->shader_info
->vs
.outinfo
;
3867 case MESA_SHADER_TESS_EVAL
:
3868 if (ctx
->args
->options
->key
.vs_common_out
.as_es
)
3870 outinfo
= &ctx
->args
->shader_info
->tes
.outinfo
;
3873 unreachable("Unhandled shader type");
3876 ac_optimize_vs_outputs(&ctx
->ac
,
3878 outinfo
->vs_output_param_offset
,
3880 &outinfo
->param_exports
);
3884 ac_setup_rings(struct radv_shader_context
*ctx
)
3886 if (ctx
->args
->options
->chip_class
<= GFX8
&&
3887 (ctx
->stage
== MESA_SHADER_GEOMETRY
||
3888 ctx
->args
->options
->key
.vs_common_out
.as_es
|| ctx
->args
->options
->key
.vs_common_out
.as_es
)) {
3889 unsigned ring
= ctx
->stage
== MESA_SHADER_GEOMETRY
? RING_ESGS_GS
3891 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, ring
, false);
3893 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
,
3898 if (ctx
->args
->is_gs_copy_shader
) {
3900 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3901 LLVMConstInt(ctx
->ac
.i32
,
3902 RING_GSVS_VS
, false));
3905 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3906 /* The conceptual layout of the GSVS ring is
3907 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3908 * but the real memory layout is swizzled across
3910 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3912 * Override the buffer descriptor accordingly.
3914 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->ac
.i64
, 2);
3915 uint64_t stream_offset
= 0;
3916 unsigned num_records
= ctx
->ac
.wave_size
;
3917 LLVMValueRef base_ring
;
3920 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3921 LLVMConstInt(ctx
->ac
.i32
,
3922 RING_GSVS_GS
, false));
3924 for (unsigned stream
= 0; stream
< 4; stream
++) {
3925 unsigned num_components
, stride
;
3926 LLVMValueRef ring
, tmp
;
3929 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
3931 if (!num_components
)
3934 stride
= 4 * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
3936 /* Limit on the stride field for <= GFX7. */
3937 assert(stride
< (1 << 14));
3939 ring
= LLVMBuildBitCast(ctx
->ac
.builder
,
3940 base_ring
, v2i64
, "");
3941 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
3942 ring
, ctx
->ac
.i32_0
, "");
3943 tmp
= LLVMBuildAdd(ctx
->ac
.builder
, tmp
,
3944 LLVMConstInt(ctx
->ac
.i64
,
3945 stream_offset
, 0), "");
3946 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
,
3947 ring
, tmp
, ctx
->ac
.i32_0
, "");
3949 stream_offset
+= stride
* ctx
->ac
.wave_size
;
3951 ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ring
,
3954 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ring
,
3956 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
,
3957 LLVMConstInt(ctx
->ac
.i32
,
3958 S_008F04_STRIDE(stride
), false), "");
3959 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
, tmp
,
3962 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
,
3963 LLVMConstInt(ctx
->ac
.i32
,
3964 num_records
, false),
3965 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
3967 ctx
->gsvs_ring
[stream
] = ring
;
3971 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3972 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3973 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
3974 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
3979 radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
3980 gl_shader_stage stage
,
3981 const struct nir_shader
*nir
)
3983 const unsigned backup_sizes
[] = {chip_class
>= GFX9
? 128 : 64, 1, 1};
3985 for (unsigned i
= 0; i
< 3; i
++)
3986 sizes
[i
] = nir
? nir
->info
.cs
.local_size
[i
] : backup_sizes
[i
];
3987 return radv_get_max_workgroup_size(chip_class
, stage
, sizes
);
3990 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3991 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
3993 LLVMValueRef count
=
3994 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 8, 8);
3995 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
3997 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
,
3998 ac_get_arg(&ctx
->ac
, ctx
->args
->rel_auto_id
),
3999 ctx
->abi
.instance_id
, "");
4000 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
,
4001 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_rel_ids
),
4004 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
,
4005 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_patch_id
),
4006 ctx
->abi
.vertex_id
, "");
4009 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
, bool merged
)
4012 for(int i
= 5; i
>= 0; --i
) {
4013 ctx
->gs_vtx_offset
[i
] =
4014 ac_unpack_param(&ctx
->ac
,
4015 ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[i
& ~1]),
4019 ctx
->gs_wave_id
= ac_unpack_param(&ctx
->ac
,
4020 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
),
4023 for (int i
= 0; i
< 6; i
++)
4024 ctx
->gs_vtx_offset
[i
] = ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[i
]);
4025 ctx
->gs_wave_id
= ac_get_arg(&ctx
->ac
, ctx
->args
->gs_wave_id
);
4029 /* Ensure that the esgs ring is declared.
4031 * We declare it with 64KB alignment as a hint that the
4032 * pointer value will always be 0.
4034 static void declare_esgs_ring(struct radv_shader_context
*ctx
)
4039 assert(!LLVMGetNamedGlobal(ctx
->ac
.module
, "esgs_ring"));
4041 ctx
->esgs_ring
= LLVMAddGlobalInAddressSpace(
4042 ctx
->ac
.module
, LLVMArrayType(ctx
->ac
.i32
, 0),
4045 LLVMSetLinkage(ctx
->esgs_ring
, LLVMExternalLinkage
);
4046 LLVMSetAlignment(ctx
->esgs_ring
, 64 * 1024);
4050 LLVMModuleRef
ac_translate_nir_to_llvm(struct ac_llvm_compiler
*ac_llvm
,
4051 struct nir_shader
*const *shaders
,
4053 const struct radv_shader_args
*args
)
4055 struct radv_shader_context ctx
= {0};
4058 enum ac_float_mode float_mode
= AC_FLOAT_MODE_DEFAULT
;
4060 if (args
->shader_info
->float_controls_mode
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
) {
4061 float_mode
= AC_FLOAT_MODE_DENORM_FLUSH_TO_ZERO
;
4064 ac_llvm_context_init(&ctx
.ac
, ac_llvm
, args
->options
->chip_class
,
4065 args
->options
->family
, float_mode
,
4066 args
->shader_info
->wave_size
, 64);
4067 ctx
.context
= ctx
.ac
.context
;
4069 ctx
.max_workgroup_size
= 0;
4070 for (int i
= 0; i
< shader_count
; ++i
) {
4071 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
4072 radv_nir_get_max_workgroup_size(args
->options
->chip_class
,
4073 shaders
[i
]->info
.stage
,
4077 if (ctx
.ac
.chip_class
>= GFX10
) {
4078 if (is_pre_gs_stage(shaders
[0]->info
.stage
) &&
4079 args
->options
->key
.vs_common_out
.as_ngg
) {
4080 ctx
.max_workgroup_size
= 128;
4084 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2);
4086 ctx
.abi
.inputs
= &ctx
.inputs
[0];
4087 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
4088 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
4089 ctx
.abi
.load_ubo
= radv_load_ubo
;
4090 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
4091 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
4092 ctx
.abi
.load_resource
= radv_load_resource
;
4093 ctx
.abi
.clamp_shadow_reference
= false;
4094 ctx
.abi
.robust_buffer_access
= args
->options
->robust_buffer_access
;
4096 bool is_ngg
= is_pre_gs_stage(shaders
[0]->info
.stage
) && args
->options
->key
.vs_common_out
.as_ngg
;
4097 if (shader_count
>= 2 || is_ngg
)
4098 ac_init_exec_full_mask(&ctx
.ac
);
4100 if (args
->ac
.vertex_id
.used
)
4101 ctx
.abi
.vertex_id
= ac_get_arg(&ctx
.ac
, args
->ac
.vertex_id
);
4102 if (args
->rel_auto_id
.used
)
4103 ctx
.rel_auto_id
= ac_get_arg(&ctx
.ac
, args
->rel_auto_id
);
4104 if (args
->ac
.instance_id
.used
)
4105 ctx
.abi
.instance_id
= ac_get_arg(&ctx
.ac
, args
->ac
.instance_id
);
4107 if (args
->options
->has_ls_vgpr_init_bug
&&
4108 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
4109 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
4112 /* Declare scratch space base for streamout and vertex
4113 * compaction. Whether space is actually allocated is
4114 * determined during linking / PM4 creation.
4116 * Add an extra dword per vertex to ensure an odd stride, which
4117 * avoids bank conflicts for SoA accesses.
4119 declare_esgs_ring(&ctx
);
4121 /* This is really only needed when streamout and / or vertex
4122 * compaction is enabled.
4124 LLVMTypeRef asi32
= LLVMArrayType(ctx
.ac
.i32
, 8);
4125 ctx
.gs_ngg_scratch
= LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4126 asi32
, "ngg_scratch", AC_ADDR_SPACE_LDS
);
4127 LLVMSetInitializer(ctx
.gs_ngg_scratch
, LLVMGetUndef(asi32
));
4128 LLVMSetAlignment(ctx
.gs_ngg_scratch
, 4);
4131 for(int i
= 0; i
< shader_count
; ++i
) {
4132 ctx
.stage
= shaders
[i
]->info
.stage
;
4133 ctx
.shader
= shaders
[i
];
4134 ctx
.output_mask
= 0;
4136 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4137 for (int i
= 0; i
< 4; i
++) {
4138 ctx
.gs_next_vertex
[i
] =
4139 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4141 if (args
->options
->key
.vs_common_out
.as_ngg
) {
4142 for (unsigned i
= 0; i
< 4; ++i
) {
4143 ctx
.gs_curprim_verts
[i
] =
4144 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4145 ctx
.gs_generated_prims
[i
] =
4146 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4149 unsigned scratch_size
= 8;
4150 if (args
->shader_info
->so
.num_outputs
)
4153 LLVMTypeRef ai32
= LLVMArrayType(ctx
.ac
.i32
, scratch_size
);
4154 ctx
.gs_ngg_scratch
=
4155 LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4156 ai32
, "ngg_scratch", AC_ADDR_SPACE_LDS
);
4157 LLVMSetInitializer(ctx
.gs_ngg_scratch
, LLVMGetUndef(ai32
));
4158 LLVMSetAlignment(ctx
.gs_ngg_scratch
, 4);
4160 ctx
.gs_ngg_emit
= LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4161 LLVMArrayType(ctx
.ac
.i32
, 0), "ngg_emit", AC_ADDR_SPACE_LDS
);
4162 LLVMSetLinkage(ctx
.gs_ngg_emit
, LLVMExternalLinkage
);
4163 LLVMSetAlignment(ctx
.gs_ngg_emit
, 4);
4166 ctx
.abi
.load_inputs
= load_gs_input
;
4167 ctx
.abi
.emit_primitive
= visit_end_primitive
;
4168 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4169 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
4170 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4171 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
4172 if (shader_count
== 1)
4173 ctx
.tcs_num_inputs
= args
->options
->key
.tcs
.num_inputs
;
4175 ctx
.tcs_num_inputs
= util_last_bit64(args
->shader_info
->vs
.ls_outputs_written
);
4176 ctx
.tcs_num_patches
= get_tcs_num_patches(&ctx
);
4177 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4178 ctx
.abi
.load_tess_varyings
= load_tes_input
;
4179 ctx
.abi
.load_tess_coord
= load_tess_coord
;
4180 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4181 ctx
.tcs_num_patches
= args
->options
->key
.tes
.num_patches
;
4182 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
4183 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
4184 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
4185 ctx
.abi
.load_sample_position
= load_sample_position
;
4186 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
4187 ctx
.abi
.emit_kill
= radv_emit_kill
;
4190 if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&&
4191 args
->options
->key
.vs_common_out
.as_ngg
&&
4192 args
->options
->key
.vs_common_out
.export_prim_id
) {
4193 declare_esgs_ring(&ctx
);
4196 bool nested_barrier
= false;
4199 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4200 args
->options
->key
.vs_common_out
.as_ngg
) {
4201 gfx10_ngg_gs_emit_prologue(&ctx
);
4202 nested_barrier
= false;
4204 nested_barrier
= true;
4208 if (nested_barrier
) {
4209 /* Execute a barrier before the second shader in
4212 * Execute the barrier inside the conditional block,
4213 * so that empty waves can jump directly to s_endpgm,
4214 * which will also signal the barrier.
4216 * This is possible in gfx9, because an empty wave
4217 * for the second shader does not participate in
4218 * the epilogue. With NGG, empty waves may still
4219 * be required to export data (e.g. GS output vertices),
4220 * so we cannot let them exit early.
4222 * If the shader is TCS and the TCS epilog is present
4223 * and contains a barrier, it will wait there and then
4226 ac_emit_barrier(&ctx
.ac
, ctx
.stage
);
4229 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
4230 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
4232 ac_setup_rings(&ctx
);
4234 LLVMBasicBlockRef merge_block
;
4235 if (shader_count
>= 2 || is_ngg
) {
4236 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
4237 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4238 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4240 LLVMValueRef count
=
4241 ac_unpack_param(&ctx
.ac
,
4242 ac_get_arg(&ctx
.ac
, args
->merged_wave_info
),
4244 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
4245 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
4246 thread_id
, count
, "");
4247 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
4249 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
4252 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
4253 prepare_interp_optimize(&ctx
, shaders
[i
]);
4254 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
4255 handle_vs_inputs(&ctx
, shaders
[i
]);
4256 else if(shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
4257 prepare_gs_input_vgprs(&ctx
, shader_count
>= 2);
4259 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, &args
->ac
, shaders
[i
]);
4261 if (shader_count
>= 2 || is_ngg
) {
4262 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
4263 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
4266 /* This needs to be outside the if wrapping the shader body, as sometimes
4267 * the HW generates waves with 0 es/vs threads. */
4268 if (is_pre_gs_stage(shaders
[i
]->info
.stage
) &&
4269 args
->options
->key
.vs_common_out
.as_ngg
&&
4270 i
== shader_count
- 1) {
4271 handle_ngg_outputs_post_2(&ctx
);
4272 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4273 args
->options
->key
.vs_common_out
.as_ngg
) {
4274 gfx10_ngg_gs_emit_epilogue_2(&ctx
);
4277 if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4278 args
->shader_info
->tcs
.num_patches
= ctx
.tcs_num_patches
;
4279 args
->shader_info
->tcs
.lds_size
= calculate_tess_lds_size(&ctx
);
4283 LLVMBuildRetVoid(ctx
.ac
.builder
);
4285 if (args
->options
->dump_preoptir
) {
4286 fprintf(stderr
, "%s LLVM IR:\n\n",
4287 radv_get_shader_name(args
->shader_info
,
4288 shaders
[shader_count
- 1]->info
.stage
));
4289 ac_dump_module(ctx
.ac
.module
);
4290 fprintf(stderr
, "\n");
4293 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, args
->options
);
4295 if (shader_count
== 1)
4296 ac_nir_eliminate_const_vs_outputs(&ctx
);
4298 if (args
->options
->dump_shader
) {
4299 args
->shader_info
->private_mem_vgprs
=
4300 ac_count_scratch_private_memory(ctx
.main_function
);
4303 return ctx
.ac
.module
;
4306 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
4308 unsigned *retval
= (unsigned *)context
;
4309 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
4310 char *description
= LLVMGetDiagInfoDescription(di
);
4312 if (severity
== LLVMDSError
) {
4314 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
4318 LLVMDisposeMessage(description
);
4321 static unsigned radv_llvm_compile(LLVMModuleRef M
,
4322 char **pelf_buffer
, size_t *pelf_size
,
4323 struct ac_llvm_compiler
*ac_llvm
)
4325 unsigned retval
= 0;
4326 LLVMContextRef llvm_ctx
;
4328 /* Setup Diagnostic Handler*/
4329 llvm_ctx
= LLVMGetModuleContext(M
);
4331 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
4335 if (!radv_compile_to_elf(ac_llvm
, M
, pelf_buffer
, pelf_size
))
4340 static void ac_compile_llvm_module(struct ac_llvm_compiler
*ac_llvm
,
4341 LLVMModuleRef llvm_module
,
4342 struct radv_shader_binary
**rbinary
,
4343 gl_shader_stage stage
,
4345 const struct radv_nir_compiler_options
*options
)
4347 char *elf_buffer
= NULL
;
4348 size_t elf_size
= 0;
4349 char *llvm_ir_string
= NULL
;
4351 if (options
->dump_shader
) {
4352 fprintf(stderr
, "%s LLVM IR:\n\n", name
);
4353 ac_dump_module(llvm_module
);
4354 fprintf(stderr
, "\n");
4357 if (options
->record_ir
) {
4358 char *llvm_ir
= LLVMPrintModuleToString(llvm_module
);
4359 llvm_ir_string
= strdup(llvm_ir
);
4360 LLVMDisposeMessage(llvm_ir
);
4363 int v
= radv_llvm_compile(llvm_module
, &elf_buffer
, &elf_size
, ac_llvm
);
4365 fprintf(stderr
, "compile failed\n");
4368 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
4369 LLVMDisposeModule(llvm_module
);
4370 LLVMContextDispose(ctx
);
4372 size_t llvm_ir_size
= llvm_ir_string
? strlen(llvm_ir_string
) : 0;
4373 size_t alloc_size
= sizeof(struct radv_shader_binary_rtld
) + elf_size
+ llvm_ir_size
+ 1;
4374 struct radv_shader_binary_rtld
*rbin
= calloc(1, alloc_size
);
4375 memcpy(rbin
->data
, elf_buffer
, elf_size
);
4377 memcpy(rbin
->data
+ elf_size
, llvm_ir_string
, llvm_ir_size
+ 1);
4379 rbin
->base
.type
= RADV_BINARY_TYPE_RTLD
;
4380 rbin
->base
.stage
= stage
;
4381 rbin
->base
.total_size
= alloc_size
;
4382 rbin
->elf_size
= elf_size
;
4383 rbin
->llvm_ir_size
= llvm_ir_size
;
4384 *rbinary
= &rbin
->base
;
4386 free(llvm_ir_string
);
4391 radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
4392 struct radv_shader_binary
**rbinary
,
4393 const struct radv_shader_args
*args
,
4394 struct nir_shader
*const *nir
,
4398 LLVMModuleRef llvm_module
;
4400 llvm_module
= ac_translate_nir_to_llvm(ac_llvm
, nir
, nir_count
, args
);
4402 ac_compile_llvm_module(ac_llvm
, llvm_module
, rbinary
,
4403 nir
[nir_count
- 1]->info
.stage
,
4404 radv_get_shader_name(args
->shader_info
,
4405 nir
[nir_count
- 1]->info
.stage
),
4408 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4409 if (args
->options
->chip_class
>= GFX9
) {
4410 if (nir_count
== 2 &&
4411 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4412 args
->shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
4418 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
4420 LLVMValueRef vtx_offset
=
4421 LLVMBuildMul(ctx
->ac
.builder
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.vertex_id
),
4422 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4423 LLVMValueRef stream_id
;
4425 /* Fetch the vertex stream ID. */
4426 if (!ctx
->args
->options
->use_ngg_streamout
&&
4427 ctx
->args
->shader_info
->so
.num_outputs
) {
4429 ac_unpack_param(&ctx
->ac
,
4430 ac_get_arg(&ctx
->ac
,
4431 ctx
->args
->streamout_config
),
4434 stream_id
= ctx
->ac
.i32_0
;
4437 LLVMBasicBlockRef end_bb
;
4438 LLVMValueRef switch_inst
;
4440 end_bb
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
,
4441 ctx
->main_function
, "end");
4442 switch_inst
= LLVMBuildSwitch(ctx
->ac
.builder
, stream_id
, end_bb
, 4);
4444 for (unsigned stream
= 0; stream
< 4; stream
++) {
4445 unsigned num_components
=
4446 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
4447 LLVMBasicBlockRef bb
;
4450 if (stream
> 0 && !num_components
)
4453 if (stream
> 0 && !ctx
->args
->shader_info
->so
.num_outputs
)
4456 bb
= LLVMInsertBasicBlockInContext(ctx
->ac
.context
, end_bb
, "out");
4457 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
->ac
.i32
, stream
, 0), bb
);
4458 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, bb
);
4461 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4462 unsigned output_usage_mask
=
4463 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
4464 unsigned output_stream
=
4465 ctx
->args
->shader_info
->gs
.output_streams
[i
];
4466 int length
= util_last_bit(output_usage_mask
);
4468 if (!(ctx
->output_mask
& (1ull << i
)) ||
4469 output_stream
!= stream
)
4472 for (unsigned j
= 0; j
< length
; j
++) {
4473 LLVMValueRef value
, soffset
;
4475 if (!(output_usage_mask
& (1 << j
)))
4478 soffset
= LLVMConstInt(ctx
->ac
.i32
,
4480 ctx
->shader
->info
.gs
.vertices_out
* 16 * 4, false);
4484 value
= ac_build_buffer_load(&ctx
->ac
,
4487 vtx_offset
, soffset
,
4488 0, ac_glc
| ac_slc
, true, false);
4490 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4491 if (ac_get_type_size(type
) == 2) {
4492 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
4493 value
= LLVMBuildTrunc(ctx
->ac
.builder
, value
, ctx
->ac
.i16
, "");
4496 LLVMBuildStore(ctx
->ac
.builder
,
4497 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4501 if (!ctx
->args
->options
->use_ngg_streamout
&&
4502 ctx
->args
->shader_info
->so
.num_outputs
)
4503 radv_emit_streamout(ctx
, stream
);
4506 handle_vs_outputs_post(ctx
, false, true,
4507 &ctx
->args
->shader_info
->vs
.outinfo
);
4510 LLVMBuildBr(ctx
->ac
.builder
, end_bb
);
4513 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, end_bb
);
4517 radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
4518 struct nir_shader
*geom_shader
,
4519 struct radv_shader_binary
**rbinary
,
4520 const struct radv_shader_args
*args
)
4522 struct radv_shader_context ctx
= {0};
4525 assert(args
->is_gs_copy_shader
);
4527 ac_llvm_context_init(&ctx
.ac
, ac_llvm
, args
->options
->chip_class
,
4528 args
->options
->family
, AC_FLOAT_MODE_DEFAULT
, 64, 64);
4529 ctx
.context
= ctx
.ac
.context
;
4531 ctx
.stage
= MESA_SHADER_VERTEX
;
4532 ctx
.shader
= geom_shader
;
4534 create_function(&ctx
, MESA_SHADER_VERTEX
, false);
4536 ac_setup_rings(&ctx
);
4538 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
4539 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
4540 ac_handle_shader_output_decl(&ctx
.ac
, &ctx
.abi
, geom_shader
,
4541 variable
, MESA_SHADER_VERTEX
);
4544 ac_gs_copy_shader_emit(&ctx
);
4546 LLVMBuildRetVoid(ctx
.ac
.builder
);
4548 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, args
->options
);
4550 ac_compile_llvm_module(ac_llvm
, ctx
.ac
.module
, rbinary
,
4551 MESA_SHADER_VERTEX
, "GS Copy Shader", args
->options
);
4552 (*rbinary
)->is_gs_copy_shader
= true;