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radv: implement VK_AMD_shader_explicit_vertex_parameter
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "radv_shader_args.h"
32 #include "nir/nir.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36 #include <llvm-c/Transforms/Scalar.h>
37 #include <llvm-c/Transforms/Utils.h>
38
39 #include "sid.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_llvm_build.h"
43 #include "ac_shader_abi.h"
44 #include "ac_shader_util.h"
45 #include "ac_exp_param.h"
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48
49 struct radv_shader_context {
50 struct ac_llvm_context ac;
51 const struct nir_shader *shader;
52 struct ac_shader_abi abi;
53 const struct radv_shader_args *args;
54
55 gl_shader_stage stage;
56
57 unsigned max_workgroup_size;
58 LLVMContextRef context;
59 LLVMValueRef main_function;
60
61 LLVMValueRef descriptor_sets[MAX_SETS];
62
63 LLVMValueRef ring_offsets;
64
65 LLVMValueRef rel_auto_id;
66
67 LLVMValueRef gs_wave_id;
68 LLVMValueRef gs_vtx_offset[6];
69
70 LLVMValueRef esgs_ring;
71 LLVMValueRef gsvs_ring[4];
72 LLVMValueRef hs_ring_tess_offchip;
73 LLVMValueRef hs_ring_tess_factor;
74
75 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
76
77 uint64_t output_mask;
78
79 LLVMValueRef gs_next_vertex[4];
80 LLVMValueRef gs_curprim_verts[4];
81 LLVMValueRef gs_generated_prims[4];
82 LLVMValueRef gs_ngg_emit;
83 LLVMValueRef gs_ngg_scratch;
84
85 uint32_t tcs_num_inputs;
86 uint32_t tcs_num_patches;
87
88 LLVMValueRef vertexptr; /* GFX10 only */
89 };
90
91 struct radv_shader_output_values {
92 LLVMValueRef values[4];
93 unsigned slot_name;
94 unsigned slot_index;
95 unsigned usage_mask;
96 };
97
98 static inline struct radv_shader_context *
99 radv_shader_context_from_abi(struct ac_shader_abi *abi)
100 {
101 struct radv_shader_context *ctx = NULL;
102 return container_of(abi, ctx, abi);
103 }
104
105 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
106 {
107 switch (ctx->stage) {
108 case MESA_SHADER_TESS_CTRL:
109 return ac_unpack_param(&ctx->ac,
110 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),
111 0, 8);
112 case MESA_SHADER_TESS_EVAL:
113 return ac_get_arg(&ctx->ac, ctx->args->tes_rel_patch_id);
114 break;
115 default:
116 unreachable("Illegal stage");
117 }
118 }
119
120 static unsigned
121 get_tcs_num_patches(struct radv_shader_context *ctx)
122 {
123 unsigned num_tcs_input_cp = ctx->args->options->key.tcs.input_vertices;
124 unsigned num_tcs_output_cp = ctx->shader->info.tess.tcs_vertices_out;
125 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
126 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
127 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
128 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
129 uint32_t output_vertex_size = num_tcs_outputs * 16;
130 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
131 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
132 unsigned num_patches;
133 unsigned hardware_lds_size;
134
135 /* Ensure that we only need one wave per SIMD so we don't need to check
136 * resource usage. Also ensures that the number of tcs in and out
137 * vertices per threadgroup are at most 256.
138 */
139 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
140 /* Make sure that the data fits in LDS. This assumes the shaders only
141 * use LDS for the inputs and outputs.
142 */
143 hardware_lds_size = 32768;
144
145 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
146 * threadgroup, even though there is more than 32 KiB LDS.
147 *
148 * Test: dEQP-VK.tessellation.shader_input_output.barrier
149 */
150 if (ctx->args->options->chip_class >= GFX7 && ctx->args->options->family != CHIP_STONEY)
151 hardware_lds_size = 65536;
152
153 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
154 /* Make sure the output data fits in the offchip buffer */
155 num_patches = MIN2(num_patches, (ctx->args->options->tess_offchip_block_dw_size * 4) / output_patch_size);
156 /* Not necessary for correctness, but improves performance. The
157 * specific value is taken from the proprietary driver.
158 */
159 num_patches = MIN2(num_patches, 40);
160
161 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
162 if (ctx->args->options->chip_class == GFX6) {
163 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
164 num_patches = MIN2(num_patches, one_wave);
165 }
166 return num_patches;
167 }
168
169 static unsigned
170 calculate_tess_lds_size(struct radv_shader_context *ctx)
171 {
172 unsigned num_tcs_input_cp = ctx->args->options->key.tcs.input_vertices;
173 unsigned num_tcs_output_cp;
174 unsigned num_tcs_outputs, num_tcs_patch_outputs;
175 unsigned input_vertex_size, output_vertex_size;
176 unsigned input_patch_size, output_patch_size;
177 unsigned pervertex_output_patch_size;
178 unsigned output_patch0_offset;
179 unsigned num_patches;
180 unsigned lds_size;
181
182 num_tcs_output_cp = ctx->shader->info.tess.tcs_vertices_out;
183 num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
184 num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
185
186 input_vertex_size = ctx->tcs_num_inputs * 16;
187 output_vertex_size = num_tcs_outputs * 16;
188
189 input_patch_size = num_tcs_input_cp * input_vertex_size;
190
191 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
192 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
193
194 num_patches = ctx->tcs_num_patches;
195 output_patch0_offset = input_patch_size * num_patches;
196
197 lds_size = output_patch0_offset + output_patch_size * num_patches;
198 return lds_size;
199 }
200
201 /* Tessellation shaders pass outputs to the next shader using LDS.
202 *
203 * LS outputs = TCS inputs
204 * TCS outputs = TES inputs
205 *
206 * The LDS layout is:
207 * - TCS inputs for patch 0
208 * - TCS inputs for patch 1
209 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
210 * - ...
211 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
212 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
213 * - TCS outputs for patch 1
214 * - Per-patch TCS outputs for patch 1
215 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
216 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
217 * - ...
218 *
219 * All three shaders VS(LS), TCS, TES share the same LDS space.
220 */
221 static LLVMValueRef
222 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
223 {
224 assert(ctx->stage == MESA_SHADER_TESS_CTRL);
225 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
226 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
227
228 input_patch_size /= 4;
229 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
230 }
231
232 static LLVMValueRef
233 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
234 {
235 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
236 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
237 uint32_t output_vertex_size = num_tcs_outputs * 16;
238 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
239 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
240 output_patch_size /= 4;
241 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
242 }
243
244 static LLVMValueRef
245 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
246 {
247 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
248 uint32_t output_vertex_size = num_tcs_outputs * 16;
249 output_vertex_size /= 4;
250 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
251 }
252
253 static LLVMValueRef
254 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
255 {
256 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
257 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
258 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
259 uint32_t output_patch0_offset = input_patch_size;
260 unsigned num_patches = ctx->tcs_num_patches;
261
262 output_patch0_offset *= num_patches;
263 output_patch0_offset /= 4;
264 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
265 }
266
267 static LLVMValueRef
268 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
269 {
270 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
271 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
272 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
273 uint32_t output_patch0_offset = input_patch_size;
274
275 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
276 uint32_t output_vertex_size = num_tcs_outputs * 16;
277 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
278 unsigned num_patches = ctx->tcs_num_patches;
279
280 output_patch0_offset *= num_patches;
281 output_patch0_offset += pervertex_output_patch_size;
282 output_patch0_offset /= 4;
283 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
284 }
285
286 static LLVMValueRef
287 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
288 {
289 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
290 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
291
292 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
293 }
294
295 static LLVMValueRef
296 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
297 {
298 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
299 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
300 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
301
302 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
303 patch0_offset);
304 }
305
306 static LLVMValueRef
307 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
308 {
309 LLVMValueRef patch0_patch_data_offset =
310 get_tcs_out_patch0_patch_data_offset(ctx);
311 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
312 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
313
314 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
315 patch0_patch_data_offset);
316 }
317
318 static LLVMValueRef
319 create_llvm_function(struct ac_llvm_context *ctx, LLVMModuleRef module,
320 LLVMBuilderRef builder,
321 const struct ac_shader_args *args,
322 enum ac_llvm_calling_convention convention,
323 unsigned max_workgroup_size,
324 const struct radv_nir_compiler_options *options)
325 {
326 LLVMValueRef main_function =
327 ac_build_main(args, ctx, convention, "main", ctx->voidt, module);
328
329 if (options->address32_hi) {
330 ac_llvm_add_target_dep_function_attr(main_function,
331 "amdgpu-32bit-address-high-bits",
332 options->address32_hi);
333 }
334
335 ac_llvm_set_workgroup_size(main_function, max_workgroup_size);
336
337 return main_function;
338 }
339
340 static void
341 load_descriptor_sets(struct radv_shader_context *ctx)
342 {
343 uint32_t mask = ctx->args->shader_info->desc_set_used_mask;
344 if (ctx->args->shader_info->need_indirect_descriptor_sets) {
345 LLVMValueRef desc_sets =
346 ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[0]);
347 while (mask) {
348 int i = u_bit_scan(&mask);
349
350 ctx->descriptor_sets[i] =
351 ac_build_load_to_sgpr(&ctx->ac, desc_sets,
352 LLVMConstInt(ctx->ac.i32, i, false));
353
354 }
355 } else {
356 while (mask) {
357 int i = u_bit_scan(&mask);
358
359 ctx->descriptor_sets[i] =
360 ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[i]);
361 }
362 }
363 }
364
365 static enum ac_llvm_calling_convention
366 get_llvm_calling_convention(LLVMValueRef func, gl_shader_stage stage)
367 {
368 switch (stage) {
369 case MESA_SHADER_VERTEX:
370 case MESA_SHADER_TESS_EVAL:
371 return AC_LLVM_AMDGPU_VS;
372 break;
373 case MESA_SHADER_GEOMETRY:
374 return AC_LLVM_AMDGPU_GS;
375 break;
376 case MESA_SHADER_TESS_CTRL:
377 return AC_LLVM_AMDGPU_HS;
378 break;
379 case MESA_SHADER_FRAGMENT:
380 return AC_LLVM_AMDGPU_PS;
381 break;
382 case MESA_SHADER_COMPUTE:
383 return AC_LLVM_AMDGPU_CS;
384 break;
385 default:
386 unreachable("Unhandle shader type");
387 }
388 }
389
390 /* Returns whether the stage is a stage that can be directly before the GS */
391 static bool is_pre_gs_stage(gl_shader_stage stage)
392 {
393 return stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL;
394 }
395
396 static void create_function(struct radv_shader_context *ctx,
397 gl_shader_stage stage,
398 bool has_previous_stage)
399 {
400 if (ctx->ac.chip_class >= GFX10) {
401 if (is_pre_gs_stage(stage) && ctx->args->options->key.vs_common_out.as_ngg) {
402 /* On GFX10, VS is merged into GS for NGG. */
403 stage = MESA_SHADER_GEOMETRY;
404 has_previous_stage = true;
405 }
406 }
407
408 ctx->main_function = create_llvm_function(
409 &ctx->ac, ctx->ac.module, ctx->ac.builder, &ctx->args->ac,
410 get_llvm_calling_convention(ctx->main_function, stage),
411 ctx->max_workgroup_size,
412 ctx->args->options);
413
414 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
415 LLVMPointerType(ctx->ac.i8, AC_ADDR_SPACE_CONST),
416 NULL, 0, AC_FUNC_ATTR_READNONE);
417 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
418 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
419
420 load_descriptor_sets(ctx);
421
422 if (stage == MESA_SHADER_TESS_CTRL ||
423 (stage == MESA_SHADER_VERTEX && ctx->args->options->key.vs_common_out.as_ls) ||
424 /* GFX9 has the ESGS ring buffer in LDS. */
425 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
426 ac_declare_lds_as_pointer(&ctx->ac);
427 }
428
429 }
430
431
432 static LLVMValueRef
433 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
434 unsigned desc_set, unsigned binding)
435 {
436 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
437 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
438 struct radv_pipeline_layout *pipeline_layout = ctx->args->options->layout;
439 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
440 unsigned base_offset = layout->binding[binding].offset;
441 LLVMValueRef offset, stride;
442
443 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
444 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
445 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
446 layout->binding[binding].dynamic_offset_offset;
447 desc_ptr = ac_get_arg(&ctx->ac, ctx->args->ac.push_constants);
448 base_offset = pipeline_layout->push_constant_size + 16 * idx;
449 stride = LLVMConstInt(ctx->ac.i32, 16, false);
450 } else
451 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
452
453 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
454
455 if (layout->binding[binding].type != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
456 offset = ac_build_imad(&ctx->ac, index, stride, offset);
457 }
458
459 desc_ptr = LLVMBuildGEP(ctx->ac.builder, desc_ptr, &offset, 1, "");
460 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
461 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
462
463 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
464 uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
465 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
466 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
467 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
468
469 if (ctx->ac.chip_class >= GFX10) {
470 desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
471 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
472 S_008F0C_RESOURCE_LEVEL(1);
473 } else {
474 desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
475 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
476 }
477
478 LLVMValueRef desc_components[4] = {
479 LLVMBuildPtrToInt(ctx->ac.builder, desc_ptr, ctx->ac.intptr, ""),
480 LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->args->options->address32_hi), false),
481 /* High limit to support variable sizes. */
482 LLVMConstInt(ctx->ac.i32, 0xffffffff, false),
483 LLVMConstInt(ctx->ac.i32, desc_type, false),
484 };
485
486 return ac_build_gather_values(&ctx->ac, desc_components, 4);
487 }
488
489 return desc_ptr;
490 }
491
492
493 /* The offchip buffer layout for TCS->TES is
494 *
495 * - attribute 0 of patch 0 vertex 0
496 * - attribute 0 of patch 0 vertex 1
497 * - attribute 0 of patch 0 vertex 2
498 * ...
499 * - attribute 0 of patch 1 vertex 0
500 * - attribute 0 of patch 1 vertex 1
501 * ...
502 * - attribute 1 of patch 0 vertex 0
503 * - attribute 1 of patch 0 vertex 1
504 * ...
505 * - per patch attribute 0 of patch 0
506 * - per patch attribute 0 of patch 1
507 * ...
508 *
509 * Note that every attribute has 4 components.
510 */
511 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
512 {
513 uint32_t num_patches = ctx->tcs_num_patches;
514 uint32_t num_tcs_outputs;
515 if (ctx->stage == MESA_SHADER_TESS_CTRL)
516 num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
517 else
518 num_tcs_outputs = ctx->args->options->key.tes.tcs_num_outputs;
519
520 uint32_t output_vertex_size = num_tcs_outputs * 16;
521 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
522
523 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
524 }
525
526 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
527 LLVMValueRef vertex_index)
528 {
529 LLVMValueRef param_stride;
530 if (vertex_index)
531 param_stride = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out * ctx->tcs_num_patches, false);
532 else
533 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
534 return param_stride;
535 }
536
537 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
538 LLVMValueRef vertex_index,
539 LLVMValueRef param_index)
540 {
541 LLVMValueRef base_addr;
542 LLVMValueRef param_stride, constant16;
543 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
544 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out, false);
545 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
546 param_stride = calc_param_stride(ctx, vertex_index);
547 if (vertex_index) {
548 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
549 vertices_per_patch, vertex_index);
550 } else {
551 base_addr = rel_patch_id;
552 }
553
554 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
555 LLVMBuildMul(ctx->ac.builder, param_index,
556 param_stride, ""), "");
557
558 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
559
560 if (!vertex_index) {
561 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
562
563 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
564 patch_data_offset, "");
565 }
566 return base_addr;
567 }
568
569 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
570 unsigned param,
571 unsigned const_index,
572 bool is_compact,
573 LLVMValueRef vertex_index,
574 LLVMValueRef indir_index)
575 {
576 LLVMValueRef param_index;
577
578 if (indir_index)
579 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
580 indir_index, "");
581 else {
582 if (const_index && !is_compact)
583 param += const_index;
584 param_index = LLVMConstInt(ctx->ac.i32, param, false);
585 }
586 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
587 }
588
589 static LLVMValueRef
590 get_dw_address(struct radv_shader_context *ctx,
591 LLVMValueRef dw_addr,
592 unsigned param,
593 unsigned const_index,
594 bool compact_const_index,
595 LLVMValueRef vertex_index,
596 LLVMValueRef stride,
597 LLVMValueRef indir_index)
598
599 {
600
601 if (vertex_index) {
602 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
603 LLVMBuildMul(ctx->ac.builder,
604 vertex_index,
605 stride, ""), "");
606 }
607
608 if (indir_index)
609 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
610 LLVMBuildMul(ctx->ac.builder, indir_index,
611 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
612 else if (const_index && !compact_const_index)
613 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
614 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
615
616 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
617 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
618
619 if (const_index && compact_const_index)
620 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
621 LLVMConstInt(ctx->ac.i32, const_index, false), "");
622 return dw_addr;
623 }
624
625 static LLVMValueRef
626 load_tcs_varyings(struct ac_shader_abi *abi,
627 LLVMTypeRef type,
628 LLVMValueRef vertex_index,
629 LLVMValueRef indir_index,
630 unsigned const_index,
631 unsigned location,
632 unsigned driver_location,
633 unsigned component,
634 unsigned num_components,
635 bool is_patch,
636 bool is_compact,
637 bool load_input)
638 {
639 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
640 LLVMValueRef dw_addr, stride;
641 LLVMValueRef value[4], result;
642 unsigned param = shader_io_get_unique_index(location);
643
644 if (load_input) {
645 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
646 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
647 dw_addr = get_tcs_in_current_patch_offset(ctx);
648 } else {
649 if (!is_patch) {
650 stride = get_tcs_out_vertex_stride(ctx);
651 dw_addr = get_tcs_out_current_patch_offset(ctx);
652 } else {
653 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
654 stride = NULL;
655 }
656 }
657
658 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
659 indir_index);
660
661 for (unsigned i = 0; i < num_components + component; i++) {
662 value[i] = ac_lds_load(&ctx->ac, dw_addr);
663 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
664 ctx->ac.i32_1, "");
665 }
666 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
667 return result;
668 }
669
670 static void
671 store_tcs_output(struct ac_shader_abi *abi,
672 const nir_variable *var,
673 LLVMValueRef vertex_index,
674 LLVMValueRef param_index,
675 unsigned const_index,
676 LLVMValueRef src,
677 unsigned writemask)
678 {
679 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
680 const unsigned location = var->data.location;
681 unsigned component = var->data.location_frac;
682 const bool is_patch = var->data.patch;
683 const bool is_compact = var->data.compact;
684 LLVMValueRef dw_addr;
685 LLVMValueRef stride = NULL;
686 LLVMValueRef buf_addr = NULL;
687 LLVMValueRef oc_lds = ac_get_arg(&ctx->ac, ctx->args->oc_lds);
688 unsigned param;
689 bool store_lds = true;
690
691 if (is_patch) {
692 if (!(ctx->shader->info.patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
693 store_lds = false;
694 } else {
695 if (!(ctx->shader->info.outputs_read & (1ULL << location)))
696 store_lds = false;
697 }
698
699 param = shader_io_get_unique_index(location);
700 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
701 const_index += component;
702 component = 0;
703
704 if (const_index >= 4) {
705 const_index -= 4;
706 param++;
707 }
708 }
709
710 if (!is_patch) {
711 stride = get_tcs_out_vertex_stride(ctx);
712 dw_addr = get_tcs_out_current_patch_offset(ctx);
713 } else {
714 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
715 }
716
717 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
718 param_index);
719 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
720 vertex_index, param_index);
721
722 bool is_tess_factor = false;
723 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
724 location == VARYING_SLOT_TESS_LEVEL_OUTER)
725 is_tess_factor = true;
726
727 unsigned base = is_compact ? const_index : 0;
728 for (unsigned chan = 0; chan < 8; chan++) {
729 if (!(writemask & (1 << chan)))
730 continue;
731 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
732 value = ac_to_integer(&ctx->ac, value);
733 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
734
735 if (store_lds || is_tess_factor) {
736 LLVMValueRef dw_addr_chan =
737 LLVMBuildAdd(ctx->ac.builder, dw_addr,
738 LLVMConstInt(ctx->ac.i32, chan, false), "");
739 ac_lds_store(&ctx->ac, dw_addr_chan, value);
740 }
741
742 if (!is_tess_factor && writemask != 0xF)
743 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
744 buf_addr, oc_lds,
745 4 * (base + chan), ac_glc);
746 }
747
748 if (writemask == 0xF) {
749 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
750 buf_addr, oc_lds,
751 (base * 4), ac_glc);
752 }
753 }
754
755 static LLVMValueRef
756 load_tes_input(struct ac_shader_abi *abi,
757 LLVMTypeRef type,
758 LLVMValueRef vertex_index,
759 LLVMValueRef param_index,
760 unsigned const_index,
761 unsigned location,
762 unsigned driver_location,
763 unsigned component,
764 unsigned num_components,
765 bool is_patch,
766 bool is_compact,
767 bool load_input)
768 {
769 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
770 LLVMValueRef buf_addr;
771 LLVMValueRef result;
772 LLVMValueRef oc_lds = ac_get_arg(&ctx->ac, ctx->args->oc_lds);
773 unsigned param = shader_io_get_unique_index(location);
774
775 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
776 const_index += component;
777 component = 0;
778 if (const_index >= 4) {
779 const_index -= 4;
780 param++;
781 }
782 }
783
784 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
785 is_compact, vertex_index, param_index);
786
787 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
788 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
789
790 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
791 buf_addr, oc_lds, is_compact ? (4 * const_index) : 0, ac_glc, true, false);
792 result = ac_trim_vector(&ctx->ac, result, num_components);
793 return result;
794 }
795
796 static LLVMValueRef
797 radv_emit_fetch_64bit(struct radv_shader_context *ctx,
798 LLVMTypeRef type, LLVMValueRef a, LLVMValueRef b)
799 {
800 LLVMValueRef values[2] = {
801 ac_to_integer(&ctx->ac, a),
802 ac_to_integer(&ctx->ac, b),
803 };
804 LLVMValueRef result = ac_build_gather_values(&ctx->ac, values, 2);
805 return LLVMBuildBitCast(ctx->ac.builder, result, type, "");
806 }
807
808 static LLVMValueRef
809 load_gs_input(struct ac_shader_abi *abi,
810 unsigned location,
811 unsigned driver_location,
812 unsigned component,
813 unsigned num_components,
814 unsigned vertex_index,
815 unsigned const_index,
816 LLVMTypeRef type)
817 {
818 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
819 LLVMValueRef vtx_offset;
820 unsigned param, vtx_offset_param;
821 LLVMValueRef value[4], result;
822
823 vtx_offset_param = vertex_index;
824 assert(vtx_offset_param < 6);
825 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
826 LLVMConstInt(ctx->ac.i32, 4, false), "");
827
828 param = shader_io_get_unique_index(location);
829
830 for (unsigned i = component; i < num_components + component; i++) {
831 if (ctx->ac.chip_class >= GFX9) {
832 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
833 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
834 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
835 value[i] = ac_lds_load(&ctx->ac, dw_addr);
836
837 if (ac_get_type_size(type) == 8) {
838 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
839 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index + 1, 0), "");
840 LLVMValueRef tmp = ac_lds_load(&ctx->ac, dw_addr);
841
842 value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
843 }
844 } else {
845 LLVMValueRef soffset =
846 LLVMConstInt(ctx->ac.i32,
847 (param * 4 + i + const_index) * 256,
848 false);
849
850 value[i] = ac_build_buffer_load(&ctx->ac,
851 ctx->esgs_ring, 1,
852 ctx->ac.i32_0,
853 vtx_offset, soffset,
854 0, ac_glc, true, false);
855
856 if (ac_get_type_size(type) == 8) {
857 soffset = LLVMConstInt(ctx->ac.i32,
858 (param * 4 + i + const_index + 1) * 256,
859 false);
860
861 LLVMValueRef tmp =
862 ac_build_buffer_load(&ctx->ac,
863 ctx->esgs_ring, 1,
864 ctx->ac.i32_0,
865 vtx_offset, soffset,
866 0, ac_glc, true, false);
867
868 value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
869 }
870 }
871
872 if (ac_get_type_size(type) == 2) {
873 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], ctx->ac.i32, "");
874 value[i] = LLVMBuildTrunc(ctx->ac.builder, value[i], ctx->ac.i16, "");
875 }
876 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
877 }
878 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
879 result = ac_to_integer(&ctx->ac, result);
880 return result;
881 }
882
883
884 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
885 {
886 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
887 ac_build_kill_if_false(&ctx->ac, visible);
888 }
889
890 static uint32_t
891 radv_get_sample_pos_offset(uint32_t num_samples)
892 {
893 uint32_t sample_pos_offset = 0;
894
895 switch (num_samples) {
896 case 2:
897 sample_pos_offset = 1;
898 break;
899 case 4:
900 sample_pos_offset = 3;
901 break;
902 case 8:
903 sample_pos_offset = 7;
904 break;
905 default:
906 break;
907 }
908 return sample_pos_offset;
909 }
910
911 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
912 LLVMValueRef sample_id)
913 {
914 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
915
916 LLVMValueRef result;
917 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false);
918 LLVMValueRef ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ring_offsets, &index, 1, "");
919
920 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
921 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
922
923 uint32_t sample_pos_offset =
924 radv_get_sample_pos_offset(ctx->args->options->key.fs.num_samples);
925
926 sample_id =
927 LLVMBuildAdd(ctx->ac.builder, sample_id,
928 LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
929 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
930
931 return result;
932 }
933
934
935 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
936 {
937 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
938 uint8_t log2_ps_iter_samples;
939
940 if (ctx->args->shader_info->ps.force_persample) {
941 log2_ps_iter_samples =
942 util_logbase2(ctx->args->options->key.fs.num_samples);
943 } else {
944 log2_ps_iter_samples = ctx->args->options->key.fs.log2_ps_iter_samples;
945 }
946
947 /* The bit pattern matches that used by fixed function fragment
948 * processing. */
949 static const uint16_t ps_iter_masks[] = {
950 0xffff, /* not used */
951 0x5555,
952 0x1111,
953 0x0101,
954 0x0001,
955 };
956 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
957
958 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
959
960 LLVMValueRef result, sample_id;
961 sample_id = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.ancillary), 8, 4);
962 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
963 result = LLVMBuildAnd(ctx->ac.builder, sample_id,
964 ac_get_arg(&ctx->ac, ctx->args->ac.sample_coverage), "");
965 return result;
966 }
967
968
969 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
970 unsigned stream,
971 LLVMValueRef *addrs);
972
973 static void
974 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
975 {
976 LLVMValueRef gs_next_vertex;
977 LLVMValueRef can_emit;
978 unsigned offset = 0;
979 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
980
981 if (ctx->args->options->key.vs_common_out.as_ngg) {
982 gfx10_ngg_gs_emit_vertex(ctx, stream, addrs);
983 return;
984 }
985
986 /* Write vertex attribute values to GSVS ring */
987 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
988 ctx->gs_next_vertex[stream],
989 "");
990
991 /* If this thread has already emitted the declared maximum number of
992 * vertices, don't emit any more: excessive vertex emissions are not
993 * supposed to have any effect.
994 */
995 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
996 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
997
998 bool use_kill = !ctx->args->shader_info->gs.writes_memory;
999 if (use_kill)
1000 ac_build_kill_if_false(&ctx->ac, can_emit);
1001 else
1002 ac_build_ifcc(&ctx->ac, can_emit, 6505);
1003
1004 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1005 unsigned output_usage_mask =
1006 ctx->args->shader_info->gs.output_usage_mask[i];
1007 uint8_t output_stream =
1008 ctx->args->shader_info->gs.output_streams[i];
1009 LLVMValueRef *out_ptr = &addrs[i * 4];
1010 int length = util_last_bit(output_usage_mask);
1011
1012 if (!(ctx->output_mask & (1ull << i)) ||
1013 output_stream != stream)
1014 continue;
1015
1016 for (unsigned j = 0; j < length; j++) {
1017 if (!(output_usage_mask & (1 << j)))
1018 continue;
1019
1020 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1021 out_ptr[j], "");
1022 LLVMValueRef voffset =
1023 LLVMConstInt(ctx->ac.i32, offset *
1024 ctx->shader->info.gs.vertices_out, false);
1025
1026 offset++;
1027
1028 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1029 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1030
1031 out_val = ac_to_integer(&ctx->ac, out_val);
1032 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1033
1034 ac_build_buffer_store_dword(&ctx->ac,
1035 ctx->gsvs_ring[stream],
1036 out_val, 1,
1037 voffset,
1038 ac_get_arg(&ctx->ac,
1039 ctx->args->gs2vs_offset),
1040 0, ac_glc | ac_slc | ac_swizzled);
1041 }
1042 }
1043
1044 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1045 ctx->ac.i32_1, "");
1046 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
1047
1048 ac_build_sendmsg(&ctx->ac,
1049 AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
1050 ctx->gs_wave_id);
1051
1052 if (!use_kill)
1053 ac_build_endif(&ctx->ac, 6505);
1054 }
1055
1056 static void
1057 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1058 {
1059 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1060
1061 if (ctx->args->options->key.vs_common_out.as_ngg) {
1062 LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0, ctx->gs_curprim_verts[stream]);
1063 return;
1064 }
1065
1066 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1067 }
1068
1069 static LLVMValueRef
1070 load_tess_coord(struct ac_shader_abi *abi)
1071 {
1072 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1073
1074 LLVMValueRef coord[4] = {
1075 ac_get_arg(&ctx->ac, ctx->args->tes_u),
1076 ac_get_arg(&ctx->ac, ctx->args->tes_v),
1077 ctx->ac.f32_0,
1078 ctx->ac.f32_0,
1079 };
1080
1081 if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES)
1082 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1083 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1084
1085 return ac_build_gather_values(&ctx->ac, coord, 3);
1086 }
1087
1088 static LLVMValueRef
1089 load_patch_vertices_in(struct ac_shader_abi *abi)
1090 {
1091 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1092 return LLVMConstInt(ctx->ac.i32, ctx->args->options->key.tcs.input_vertices, false);
1093 }
1094
1095
1096 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1097 {
1098 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1099 return ac_get_arg(&ctx->ac, ctx->args->ac.base_vertex);
1100 }
1101
1102 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1103 LLVMValueRef buffer_ptr, bool write)
1104 {
1105 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1106 LLVMValueRef result;
1107
1108 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1109
1110 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1111 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1112
1113 return result;
1114 }
1115
1116 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1117 {
1118 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1119 LLVMValueRef result;
1120
1121 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr)) != LLVMPointerTypeKind) {
1122 /* Do not load the descriptor for inlined uniform blocks. */
1123 return buffer_ptr;
1124 }
1125
1126 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1127
1128 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1129 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1130
1131 return result;
1132 }
1133
1134 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1135 unsigned descriptor_set,
1136 unsigned base_index,
1137 unsigned constant_index,
1138 LLVMValueRef index,
1139 enum ac_descriptor_type desc_type,
1140 bool image, bool write,
1141 bool bindless)
1142 {
1143 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1144 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1145 struct radv_descriptor_set_layout *layout = ctx->args->options->layout->set[descriptor_set].layout;
1146 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1147 unsigned offset = binding->offset;
1148 unsigned stride = binding->size;
1149 unsigned type_size;
1150 LLVMBuilderRef builder = ctx->ac.builder;
1151 LLVMTypeRef type;
1152
1153 assert(base_index < layout->binding_count);
1154
1155 switch (desc_type) {
1156 case AC_DESC_IMAGE:
1157 type = ctx->ac.v8i32;
1158 type_size = 32;
1159 break;
1160 case AC_DESC_FMASK:
1161 type = ctx->ac.v8i32;
1162 offset += 32;
1163 type_size = 32;
1164 break;
1165 case AC_DESC_SAMPLER:
1166 type = ctx->ac.v4i32;
1167 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
1168 offset += radv_combined_image_descriptor_sampler_offset(binding);
1169 }
1170
1171 type_size = 16;
1172 break;
1173 case AC_DESC_BUFFER:
1174 type = ctx->ac.v4i32;
1175 type_size = 16;
1176 break;
1177 case AC_DESC_PLANE_0:
1178 case AC_DESC_PLANE_1:
1179 case AC_DESC_PLANE_2:
1180 type = ctx->ac.v8i32;
1181 type_size = 32;
1182 offset += 32 * (desc_type - AC_DESC_PLANE_0);
1183 break;
1184 default:
1185 unreachable("invalid desc_type\n");
1186 }
1187
1188 offset += constant_index * stride;
1189
1190 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1191 (!index || binding->immutable_samplers_equal)) {
1192 if (binding->immutable_samplers_equal)
1193 constant_index = 0;
1194
1195 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1196
1197 LLVMValueRef constants[] = {
1198 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1199 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1200 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1201 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1202 };
1203 return ac_build_gather_values(&ctx->ac, constants, 4);
1204 }
1205
1206 assert(stride % type_size == 0);
1207
1208 LLVMValueRef adjusted_index = index;
1209 if (!adjusted_index)
1210 adjusted_index = ctx->ac.i32_0;
1211
1212 adjusted_index = LLVMBuildMul(builder, adjusted_index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1213
1214 LLVMValueRef val_offset = LLVMConstInt(ctx->ac.i32, offset, 0);
1215 list = LLVMBuildGEP(builder, list, &val_offset, 1, "");
1216 list = LLVMBuildPointerCast(builder, list,
1217 ac_array_in_const32_addr_space(type), "");
1218
1219 LLVMValueRef descriptor = ac_build_load_to_sgpr(&ctx->ac, list, adjusted_index);
1220
1221 /* 3 plane formats always have same size and format for plane 1 & 2, so
1222 * use the tail from plane 1 so that we can store only the first 16 bytes
1223 * of the last plane. */
1224 if (desc_type == AC_DESC_PLANE_2) {
1225 LLVMValueRef descriptor2 = radv_get_sampler_desc(abi, descriptor_set, base_index, constant_index, index, AC_DESC_PLANE_1,image, write, bindless);
1226
1227 LLVMValueRef components[8];
1228 for (unsigned i = 0; i < 4; ++i)
1229 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor, i);
1230
1231 for (unsigned i = 4; i < 8; ++i)
1232 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor2, i);
1233 descriptor = ac_build_gather_values(&ctx->ac, components, 8);
1234 }
1235
1236 return descriptor;
1237 }
1238
1239 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1240 * so we may need to fix it up. */
1241 static LLVMValueRef
1242 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1243 unsigned adjustment,
1244 LLVMValueRef alpha)
1245 {
1246 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1247 return alpha;
1248
1249 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1250
1251 alpha = LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.f32, "");
1252
1253 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1254 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1255 else
1256 alpha = ac_to_integer(&ctx->ac, alpha);
1257
1258 /* For the integer-like cases, do a natural sign extension.
1259 *
1260 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1261 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1262 * exponent.
1263 */
1264 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1265 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1266 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1267 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1268
1269 /* Convert back to the right type. */
1270 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1271 LLVMValueRef clamp;
1272 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1273 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1274 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1275 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
1276 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
1277 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1278 }
1279
1280 return LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.i32, "");
1281 }
1282
1283 static LLVMValueRef
1284 radv_fixup_vertex_input_fetches(struct radv_shader_context *ctx,
1285 LLVMValueRef value,
1286 unsigned num_channels,
1287 bool is_float)
1288 {
1289 LLVMValueRef zero = is_float ? ctx->ac.f32_0 : ctx->ac.i32_0;
1290 LLVMValueRef one = is_float ? ctx->ac.f32_1 : ctx->ac.i32_1;
1291 LLVMValueRef chan[4];
1292
1293 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMVectorTypeKind) {
1294 unsigned vec_size = LLVMGetVectorSize(LLVMTypeOf(value));
1295
1296 if (num_channels == 4 && num_channels == vec_size)
1297 return value;
1298
1299 num_channels = MIN2(num_channels, vec_size);
1300
1301 for (unsigned i = 0; i < num_channels; i++)
1302 chan[i] = ac_llvm_extract_elem(&ctx->ac, value, i);
1303 } else {
1304 assert(num_channels == 1);
1305 chan[0] = value;
1306 }
1307
1308 for (unsigned i = num_channels; i < 4; i++) {
1309 chan[i] = i == 3 ? one : zero;
1310 chan[i] = ac_to_integer(&ctx->ac, chan[i]);
1311 }
1312
1313 return ac_build_gather_values(&ctx->ac, chan, 4);
1314 }
1315
1316 static void
1317 handle_vs_input_decl(struct radv_shader_context *ctx,
1318 struct nir_variable *variable)
1319 {
1320 LLVMValueRef t_list_ptr = ac_get_arg(&ctx->ac, ctx->args->vertex_buffers);
1321 LLVMValueRef t_offset;
1322 LLVMValueRef t_list;
1323 LLVMValueRef input;
1324 LLVMValueRef buffer_index;
1325 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1326 uint8_t input_usage_mask =
1327 ctx->args->shader_info->vs.input_usage_mask[variable->data.location];
1328 unsigned num_input_channels = util_last_bit(input_usage_mask);
1329
1330 variable->data.driver_location = variable->data.location * 4;
1331
1332 enum glsl_base_type type = glsl_get_base_type(variable->type);
1333 for (unsigned i = 0; i < attrib_count; ++i) {
1334 LLVMValueRef output[4];
1335 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
1336 unsigned attrib_format = ctx->args->options->key.vs.vertex_attribute_formats[attrib_index];
1337 unsigned data_format = attrib_format & 0x0f;
1338 unsigned num_format = (attrib_format >> 4) & 0x07;
1339 bool is_float = num_format != V_008F0C_BUF_NUM_FORMAT_UINT &&
1340 num_format != V_008F0C_BUF_NUM_FORMAT_SINT;
1341
1342 if (ctx->args->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
1343 uint32_t divisor = ctx->args->options->key.vs.instance_rate_divisors[attrib_index];
1344
1345 if (divisor) {
1346 buffer_index = ctx->abi.instance_id;
1347
1348 if (divisor != 1) {
1349 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
1350 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
1351 }
1352 } else {
1353 buffer_index = ctx->ac.i32_0;
1354 }
1355
1356 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1357 ac_get_arg(&ctx->ac,
1358 ctx->args->ac.start_instance),\
1359 buffer_index, "");
1360 } else {
1361 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1362 ctx->abi.vertex_id,
1363 ac_get_arg(&ctx->ac,
1364 ctx->args->ac.base_vertex), "");
1365 }
1366
1367 const struct ac_data_format_info *vtx_info = ac_get_data_format_info(data_format);
1368
1369 /* Adjust the number of channels to load based on the vertex
1370 * attribute format.
1371 */
1372 unsigned num_channels = MIN2(num_input_channels, vtx_info->num_channels);
1373 unsigned attrib_binding = ctx->args->options->key.vs.vertex_attribute_bindings[attrib_index];
1374 unsigned attrib_offset = ctx->args->options->key.vs.vertex_attribute_offsets[attrib_index];
1375 unsigned attrib_stride = ctx->args->options->key.vs.vertex_attribute_strides[attrib_index];
1376
1377 if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
1378 /* Always load, at least, 3 channels for formats that
1379 * need to be shuffled because X<->Z.
1380 */
1381 num_channels = MAX2(num_channels, 3);
1382 }
1383
1384 t_offset = LLVMConstInt(ctx->ac.i32, attrib_binding, false);
1385 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1386
1387 /* Perform per-channel vertex fetch operations if unaligned
1388 * access are detected. Only GFX6 and GFX10 are affected.
1389 */
1390 bool unaligned_vertex_fetches = false;
1391 if ((ctx->ac.chip_class == GFX6 || ctx->ac.chip_class == GFX10) &&
1392 vtx_info->chan_format != data_format &&
1393 ((attrib_offset % vtx_info->element_size) ||
1394 (attrib_stride % vtx_info->element_size)))
1395 unaligned_vertex_fetches = true;
1396
1397 if (unaligned_vertex_fetches) {
1398 unsigned chan_format = vtx_info->chan_format;
1399 LLVMValueRef values[4];
1400
1401 assert(ctx->ac.chip_class == GFX6 ||
1402 ctx->ac.chip_class == GFX10);
1403
1404 for (unsigned chan = 0; chan < num_channels; chan++) {
1405 unsigned chan_offset = attrib_offset + chan * vtx_info->chan_byte_size;
1406 LLVMValueRef chan_index = buffer_index;
1407
1408 if (attrib_stride != 0 && chan_offset > attrib_stride) {
1409 LLVMValueRef buffer_offset =
1410 LLVMConstInt(ctx->ac.i32,
1411 chan_offset / attrib_stride, false);
1412
1413 chan_index = LLVMBuildAdd(ctx->ac.builder,
1414 buffer_index,
1415 buffer_offset, "");
1416
1417 chan_offset = chan_offset % attrib_stride;
1418 }
1419
1420 values[chan] = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
1421 chan_index,
1422 LLVMConstInt(ctx->ac.i32, chan_offset, false),
1423 ctx->ac.i32_0, ctx->ac.i32_0, 1,
1424 chan_format, num_format, 0, true);
1425 }
1426
1427 input = ac_build_gather_values(&ctx->ac, values, num_channels);
1428 } else {
1429 if (attrib_stride != 0 && attrib_offset > attrib_stride) {
1430 LLVMValueRef buffer_offset =
1431 LLVMConstInt(ctx->ac.i32,
1432 attrib_offset / attrib_stride, false);
1433
1434 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1435 buffer_index,
1436 buffer_offset, "");
1437
1438 attrib_offset = attrib_offset % attrib_stride;
1439 }
1440
1441 input = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
1442 buffer_index,
1443 LLVMConstInt(ctx->ac.i32, attrib_offset, false),
1444 ctx->ac.i32_0, ctx->ac.i32_0,
1445 num_channels,
1446 data_format, num_format, 0, true);
1447 }
1448
1449 if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
1450 LLVMValueRef c[4];
1451 c[0] = ac_llvm_extract_elem(&ctx->ac, input, 2);
1452 c[1] = ac_llvm_extract_elem(&ctx->ac, input, 1);
1453 c[2] = ac_llvm_extract_elem(&ctx->ac, input, 0);
1454 c[3] = ac_llvm_extract_elem(&ctx->ac, input, 3);
1455
1456 input = ac_build_gather_values(&ctx->ac, c, 4);
1457 }
1458
1459 input = radv_fixup_vertex_input_fetches(ctx, input, num_channels,
1460 is_float);
1461
1462 for (unsigned chan = 0; chan < 4; chan++) {
1463 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1464 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
1465 if (type == GLSL_TYPE_FLOAT16) {
1466 output[chan] = LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
1467 output[chan] = LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
1468 }
1469 }
1470
1471 unsigned alpha_adjust = (ctx->args->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
1472 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
1473
1474 for (unsigned chan = 0; chan < 4; chan++) {
1475 output[chan] = ac_to_integer(&ctx->ac, output[chan]);
1476 if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
1477 output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
1478
1479 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = output[chan];
1480 }
1481 }
1482 }
1483
1484 static void
1485 handle_vs_inputs(struct radv_shader_context *ctx,
1486 struct nir_shader *nir) {
1487 nir_foreach_variable(variable, &nir->inputs)
1488 handle_vs_input_decl(ctx, variable);
1489 }
1490
1491 static void
1492 prepare_interp_optimize(struct radv_shader_context *ctx,
1493 struct nir_shader *nir)
1494 {
1495 bool uses_center = false;
1496 bool uses_centroid = false;
1497 nir_foreach_variable(variable, &nir->inputs) {
1498 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
1499 variable->data.sample)
1500 continue;
1501
1502 if (variable->data.centroid)
1503 uses_centroid = true;
1504 else
1505 uses_center = true;
1506 }
1507
1508 ctx->abi.persp_centroid = ac_get_arg(&ctx->ac, ctx->args->ac.persp_centroid);
1509 ctx->abi.linear_centroid = ac_get_arg(&ctx->ac, ctx->args->ac.linear_centroid);
1510
1511 if (uses_center && uses_centroid) {
1512 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT,
1513 ac_get_arg(&ctx->ac, ctx->args->ac.prim_mask),
1514 ctx->ac.i32_0, "");
1515 ctx->abi.persp_centroid =
1516 LLVMBuildSelect(ctx->ac.builder, sel,
1517 ac_get_arg(&ctx->ac, ctx->args->ac.persp_center),
1518 ctx->abi.persp_centroid, "");
1519 ctx->abi.linear_centroid =
1520 LLVMBuildSelect(ctx->ac.builder, sel,
1521 ac_get_arg(&ctx->ac, ctx->args->ac.linear_center),
1522 ctx->abi.linear_centroid, "");
1523 }
1524 }
1525
1526 static void
1527 scan_shader_output_decl(struct radv_shader_context *ctx,
1528 struct nir_variable *variable,
1529 struct nir_shader *shader,
1530 gl_shader_stage stage)
1531 {
1532 int idx = variable->data.location + variable->data.index;
1533 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1534 uint64_t mask_attribs;
1535
1536 variable->data.driver_location = idx * 4;
1537
1538 /* tess ctrl has it's own load/store paths for outputs */
1539 if (stage == MESA_SHADER_TESS_CTRL)
1540 return;
1541
1542 if (variable->data.compact) {
1543 unsigned component_count = variable->data.location_frac +
1544 glsl_get_length(variable->type);
1545 attrib_count = (component_count + 3) / 4;
1546 }
1547
1548 mask_attribs = ((1ull << attrib_count) - 1) << idx;
1549
1550 ctx->output_mask |= mask_attribs;
1551 }
1552
1553
1554 /* Initialize arguments for the shader export intrinsic */
1555 static void
1556 si_llvm_init_export_args(struct radv_shader_context *ctx,
1557 LLVMValueRef *values,
1558 unsigned enabled_channels,
1559 unsigned target,
1560 struct ac_export_args *args)
1561 {
1562 /* Specify the channels that are enabled. */
1563 args->enabled_channels = enabled_channels;
1564
1565 /* Specify whether the EXEC mask represents the valid mask */
1566 args->valid_mask = 0;
1567
1568 /* Specify whether this is the last export */
1569 args->done = 0;
1570
1571 /* Specify the target we are exporting */
1572 args->target = target;
1573
1574 args->compr = false;
1575 args->out[0] = LLVMGetUndef(ctx->ac.f32);
1576 args->out[1] = LLVMGetUndef(ctx->ac.f32);
1577 args->out[2] = LLVMGetUndef(ctx->ac.f32);
1578 args->out[3] = LLVMGetUndef(ctx->ac.f32);
1579
1580 if (!values)
1581 return;
1582
1583 bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
1584 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1585 unsigned index = target - V_008DFC_SQ_EXP_MRT;
1586 unsigned col_format = (ctx->args->options->key.fs.col_format >> (4 * index)) & 0xf;
1587 bool is_int8 = (ctx->args->options->key.fs.is_int8 >> index) & 1;
1588 bool is_int10 = (ctx->args->options->key.fs.is_int10 >> index) & 1;
1589 unsigned chan;
1590
1591 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
1592 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
1593 unsigned bits, bool hi) = NULL;
1594
1595 switch(col_format) {
1596 case V_028714_SPI_SHADER_ZERO:
1597 args->enabled_channels = 0; /* writemask */
1598 args->target = V_008DFC_SQ_EXP_NULL;
1599 break;
1600
1601 case V_028714_SPI_SHADER_32_R:
1602 args->enabled_channels = 1;
1603 args->out[0] = values[0];
1604 break;
1605
1606 case V_028714_SPI_SHADER_32_GR:
1607 args->enabled_channels = 0x3;
1608 args->out[0] = values[0];
1609 args->out[1] = values[1];
1610 break;
1611
1612 case V_028714_SPI_SHADER_32_AR:
1613 if (ctx->ac.chip_class >= GFX10) {
1614 args->enabled_channels = 0x3;
1615 args->out[0] = values[0];
1616 args->out[1] = values[3];
1617 } else {
1618 args->enabled_channels = 0x9;
1619 args->out[0] = values[0];
1620 args->out[3] = values[3];
1621 }
1622 break;
1623
1624 case V_028714_SPI_SHADER_FP16_ABGR:
1625 args->enabled_channels = 0x5;
1626 packf = ac_build_cvt_pkrtz_f16;
1627 if (is_16bit) {
1628 for (unsigned chan = 0; chan < 4; chan++)
1629 values[chan] = LLVMBuildFPExt(ctx->ac.builder,
1630 values[chan],
1631 ctx->ac.f32, "");
1632 }
1633 break;
1634
1635 case V_028714_SPI_SHADER_UNORM16_ABGR:
1636 args->enabled_channels = 0x5;
1637 packf = ac_build_cvt_pknorm_u16;
1638 break;
1639
1640 case V_028714_SPI_SHADER_SNORM16_ABGR:
1641 args->enabled_channels = 0x5;
1642 packf = ac_build_cvt_pknorm_i16;
1643 break;
1644
1645 case V_028714_SPI_SHADER_UINT16_ABGR:
1646 args->enabled_channels = 0x5;
1647 packi = ac_build_cvt_pk_u16;
1648 if (is_16bit) {
1649 for (unsigned chan = 0; chan < 4; chan++)
1650 values[chan] = LLVMBuildZExt(ctx->ac.builder,
1651 ac_to_integer(&ctx->ac, values[chan]),
1652 ctx->ac.i32, "");
1653 }
1654 break;
1655
1656 case V_028714_SPI_SHADER_SINT16_ABGR:
1657 args->enabled_channels = 0x5;
1658 packi = ac_build_cvt_pk_i16;
1659 if (is_16bit) {
1660 for (unsigned chan = 0; chan < 4; chan++)
1661 values[chan] = LLVMBuildSExt(ctx->ac.builder,
1662 ac_to_integer(&ctx->ac, values[chan]),
1663 ctx->ac.i32, "");
1664 }
1665 break;
1666
1667 default:
1668 case V_028714_SPI_SHADER_32_ABGR:
1669 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1670 break;
1671 }
1672
1673 /* Pack f16 or norm_i16/u16. */
1674 if (packf) {
1675 for (chan = 0; chan < 2; chan++) {
1676 LLVMValueRef pack_args[2] = {
1677 values[2 * chan],
1678 values[2 * chan + 1]
1679 };
1680 LLVMValueRef packed;
1681
1682 packed = packf(&ctx->ac, pack_args);
1683 args->out[chan] = ac_to_float(&ctx->ac, packed);
1684 }
1685 args->compr = 1; /* COMPR flag */
1686 }
1687
1688 /* Pack i16/u16. */
1689 if (packi) {
1690 for (chan = 0; chan < 2; chan++) {
1691 LLVMValueRef pack_args[2] = {
1692 ac_to_integer(&ctx->ac, values[2 * chan]),
1693 ac_to_integer(&ctx->ac, values[2 * chan + 1])
1694 };
1695 LLVMValueRef packed;
1696
1697 packed = packi(&ctx->ac, pack_args,
1698 is_int8 ? 8 : is_int10 ? 10 : 16,
1699 chan == 1);
1700 args->out[chan] = ac_to_float(&ctx->ac, packed);
1701 }
1702 args->compr = 1; /* COMPR flag */
1703 }
1704 return;
1705 }
1706
1707 if (is_16bit) {
1708 for (unsigned chan = 0; chan < 4; chan++) {
1709 values[chan] = LLVMBuildBitCast(ctx->ac.builder, values[chan], ctx->ac.i16, "");
1710 args->out[chan] = LLVMBuildZExt(ctx->ac.builder, values[chan], ctx->ac.i32, "");
1711 }
1712 } else
1713 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1714
1715 for (unsigned i = 0; i < 4; ++i)
1716 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
1717 }
1718
1719 static void
1720 radv_export_param(struct radv_shader_context *ctx, unsigned index,
1721 LLVMValueRef *values, unsigned enabled_channels)
1722 {
1723 struct ac_export_args args;
1724
1725 si_llvm_init_export_args(ctx, values, enabled_channels,
1726 V_008DFC_SQ_EXP_PARAM + index, &args);
1727 ac_build_export(&ctx->ac, &args);
1728 }
1729
1730 static LLVMValueRef
1731 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
1732 {
1733 LLVMValueRef output = ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
1734 return LLVMBuildLoad(ctx->ac.builder, output, "");
1735 }
1736
1737 static void
1738 radv_emit_stream_output(struct radv_shader_context *ctx,
1739 LLVMValueRef const *so_buffers,
1740 LLVMValueRef const *so_write_offsets,
1741 const struct radv_stream_output *output,
1742 struct radv_shader_output_values *shader_out)
1743 {
1744 unsigned num_comps = util_bitcount(output->component_mask);
1745 unsigned buf = output->buffer;
1746 unsigned offset = output->offset;
1747 unsigned start;
1748 LLVMValueRef out[4];
1749
1750 assert(num_comps && num_comps <= 4);
1751 if (!num_comps || num_comps > 4)
1752 return;
1753
1754 /* Get the first component. */
1755 start = ffs(output->component_mask) - 1;
1756
1757 /* Load the output as int. */
1758 for (int i = 0; i < num_comps; i++) {
1759 out[i] = ac_to_integer(&ctx->ac, shader_out->values[start + i]);
1760 }
1761
1762 /* Pack the output. */
1763 LLVMValueRef vdata = NULL;
1764
1765 switch (num_comps) {
1766 case 1: /* as i32 */
1767 vdata = out[0];
1768 break;
1769 case 2: /* as v2i32 */
1770 case 3: /* as v4i32 (aligned to 4) */
1771 out[3] = LLVMGetUndef(ctx->ac.i32);
1772 /* fall through */
1773 case 4: /* as v4i32 */
1774 vdata = ac_build_gather_values(&ctx->ac, out,
1775 !ac_has_vec3_support(ctx->ac.chip_class, false) ?
1776 util_next_power_of_two(num_comps) :
1777 num_comps);
1778 break;
1779 }
1780
1781 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf],
1782 vdata, num_comps, so_write_offsets[buf],
1783 ctx->ac.i32_0, offset,
1784 ac_glc | ac_slc);
1785 }
1786
1787 static void
1788 radv_emit_streamout(struct radv_shader_context *ctx, unsigned stream)
1789 {
1790 int i;
1791
1792 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1793 assert(ctx->args->streamout_config.used);
1794 LLVMValueRef so_vtx_count =
1795 ac_build_bfe(&ctx->ac,
1796 ac_get_arg(&ctx->ac, ctx->args->streamout_config),
1797 LLVMConstInt(ctx->ac.i32, 16, false),
1798 LLVMConstInt(ctx->ac.i32, 7, false), false);
1799
1800 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
1801
1802 /* can_emit = tid < so_vtx_count; */
1803 LLVMValueRef can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
1804 tid, so_vtx_count, "");
1805
1806 /* Emit the streamout code conditionally. This actually avoids
1807 * out-of-bounds buffer access. The hw tells us via the SGPR
1808 * (so_vtx_count) which threads are allowed to emit streamout data.
1809 */
1810 ac_build_ifcc(&ctx->ac, can_emit, 6501);
1811 {
1812 /* The buffer offset is computed as follows:
1813 * ByteOffset = streamout_offset[buffer_id]*4 +
1814 * (streamout_write_index + thread_id)*stride[buffer_id] +
1815 * attrib_offset
1816 */
1817 LLVMValueRef so_write_index =
1818 ac_get_arg(&ctx->ac, ctx->args->streamout_write_idx);
1819
1820 /* Compute (streamout_write_index + thread_id). */
1821 so_write_index =
1822 LLVMBuildAdd(ctx->ac.builder, so_write_index, tid, "");
1823
1824 /* Load the descriptor and compute the write offset for each
1825 * enabled buffer.
1826 */
1827 LLVMValueRef so_write_offset[4] = {};
1828 LLVMValueRef so_buffers[4] = {};
1829 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->args->streamout_buffers);
1830
1831 for (i = 0; i < 4; i++) {
1832 uint16_t stride = ctx->args->shader_info->so.strides[i];
1833
1834 if (!stride)
1835 continue;
1836
1837 LLVMValueRef offset =
1838 LLVMConstInt(ctx->ac.i32, i, false);
1839
1840 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac,
1841 buf_ptr, offset);
1842
1843 LLVMValueRef so_offset =
1844 ac_get_arg(&ctx->ac, ctx->args->streamout_offset[i]);
1845
1846 so_offset = LLVMBuildMul(ctx->ac.builder, so_offset,
1847 LLVMConstInt(ctx->ac.i32, 4, false), "");
1848
1849 so_write_offset[i] =
1850 ac_build_imad(&ctx->ac, so_write_index,
1851 LLVMConstInt(ctx->ac.i32,
1852 stride * 4, false),
1853 so_offset);
1854 }
1855
1856 /* Write streamout data. */
1857 for (i = 0; i < ctx->args->shader_info->so.num_outputs; i++) {
1858 struct radv_shader_output_values shader_out = {};
1859 struct radv_stream_output *output =
1860 &ctx->args->shader_info->so.outputs[i];
1861
1862 if (stream != output->stream)
1863 continue;
1864
1865 for (int j = 0; j < 4; j++) {
1866 shader_out.values[j] =
1867 radv_load_output(ctx, output->location, j);
1868 }
1869
1870 radv_emit_stream_output(ctx, so_buffers,so_write_offset,
1871 output, &shader_out);
1872 }
1873 }
1874 ac_build_endif(&ctx->ac, 6501);
1875 }
1876
1877 static void
1878 radv_build_param_exports(struct radv_shader_context *ctx,
1879 struct radv_shader_output_values *outputs,
1880 unsigned noutput,
1881 struct radv_vs_output_info *outinfo,
1882 bool export_clip_dists)
1883 {
1884 unsigned param_count = 0;
1885
1886 for (unsigned i = 0; i < noutput; i++) {
1887 unsigned slot_name = outputs[i].slot_name;
1888 unsigned usage_mask = outputs[i].usage_mask;
1889
1890 if (slot_name != VARYING_SLOT_LAYER &&
1891 slot_name != VARYING_SLOT_PRIMITIVE_ID &&
1892 slot_name != VARYING_SLOT_CLIP_DIST0 &&
1893 slot_name != VARYING_SLOT_CLIP_DIST1 &&
1894 slot_name < VARYING_SLOT_VAR0)
1895 continue;
1896
1897 if ((slot_name == VARYING_SLOT_CLIP_DIST0 ||
1898 slot_name == VARYING_SLOT_CLIP_DIST1) && !export_clip_dists)
1899 continue;
1900
1901 radv_export_param(ctx, param_count, outputs[i].values, usage_mask);
1902
1903 assert(i < ARRAY_SIZE(outinfo->vs_output_param_offset));
1904 outinfo->vs_output_param_offset[slot_name] = param_count++;
1905 }
1906
1907 outinfo->param_exports = param_count;
1908 }
1909
1910 /* Generate export instructions for hardware VS shader stage or NGG GS stage
1911 * (position and parameter data only).
1912 */
1913 static void
1914 radv_llvm_export_vs(struct radv_shader_context *ctx,
1915 struct radv_shader_output_values *outputs,
1916 unsigned noutput,
1917 struct radv_vs_output_info *outinfo,
1918 bool export_clip_dists)
1919 {
1920 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_value = NULL;
1921 struct ac_export_args pos_args[4] = {};
1922 unsigned pos_idx, index;
1923 int i;
1924
1925 /* Build position exports */
1926 for (i = 0; i < noutput; i++) {
1927 switch (outputs[i].slot_name) {
1928 case VARYING_SLOT_POS:
1929 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
1930 V_008DFC_SQ_EXP_POS, &pos_args[0]);
1931 break;
1932 case VARYING_SLOT_PSIZ:
1933 psize_value = outputs[i].values[0];
1934 break;
1935 case VARYING_SLOT_LAYER:
1936 layer_value = outputs[i].values[0];
1937 break;
1938 case VARYING_SLOT_VIEWPORT:
1939 viewport_value = outputs[i].values[0];
1940 break;
1941 case VARYING_SLOT_CLIP_DIST0:
1942 case VARYING_SLOT_CLIP_DIST1:
1943 index = 2 + outputs[i].slot_index;
1944 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
1945 V_008DFC_SQ_EXP_POS + index,
1946 &pos_args[index]);
1947 break;
1948 default:
1949 break;
1950 }
1951 }
1952
1953 /* We need to add the position output manually if it's missing. */
1954 if (!pos_args[0].out[0]) {
1955 pos_args[0].enabled_channels = 0xf; /* writemask */
1956 pos_args[0].valid_mask = 0; /* EXEC mask */
1957 pos_args[0].done = 0; /* last export? */
1958 pos_args[0].target = V_008DFC_SQ_EXP_POS;
1959 pos_args[0].compr = 0; /* COMPR flag */
1960 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
1961 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
1962 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
1963 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
1964 }
1965
1966 if (outinfo->writes_pointsize ||
1967 outinfo->writes_layer ||
1968 outinfo->writes_viewport_index) {
1969 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
1970 (outinfo->writes_layer == true ? 4 : 0));
1971 pos_args[1].valid_mask = 0;
1972 pos_args[1].done = 0;
1973 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
1974 pos_args[1].compr = 0;
1975 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
1976 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
1977 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
1978 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
1979
1980 if (outinfo->writes_pointsize == true)
1981 pos_args[1].out[0] = psize_value;
1982 if (outinfo->writes_layer == true)
1983 pos_args[1].out[2] = layer_value;
1984 if (outinfo->writes_viewport_index == true) {
1985 if (ctx->args->options->chip_class >= GFX9) {
1986 /* GFX9 has the layer in out.z[10:0] and the viewport
1987 * index in out.z[19:16].
1988 */
1989 LLVMValueRef v = viewport_value;
1990 v = ac_to_integer(&ctx->ac, v);
1991 v = LLVMBuildShl(ctx->ac.builder, v,
1992 LLVMConstInt(ctx->ac.i32, 16, false),
1993 "");
1994 v = LLVMBuildOr(ctx->ac.builder, v,
1995 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
1996
1997 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
1998 pos_args[1].enabled_channels |= 1 << 2;
1999 } else {
2000 pos_args[1].out[3] = viewport_value;
2001 pos_args[1].enabled_channels |= 1 << 3;
2002 }
2003 }
2004 }
2005
2006 for (i = 0; i < 4; i++) {
2007 if (pos_args[i].out[0])
2008 outinfo->pos_exports++;
2009 }
2010
2011 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
2012 * Setting valid_mask=1 prevents it and has no other effect.
2013 */
2014 if (ctx->ac.family == CHIP_NAVI10 ||
2015 ctx->ac.family == CHIP_NAVI12 ||
2016 ctx->ac.family == CHIP_NAVI14)
2017 pos_args[0].valid_mask = 1;
2018
2019 pos_idx = 0;
2020 for (i = 0; i < 4; i++) {
2021 if (!pos_args[i].out[0])
2022 continue;
2023
2024 /* Specify the target we are exporting */
2025 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2026
2027 if (pos_idx == outinfo->pos_exports)
2028 /* Specify that this is the last export */
2029 pos_args[i].done = 1;
2030
2031 ac_build_export(&ctx->ac, &pos_args[i]);
2032 }
2033
2034 /* Build parameter exports */
2035 radv_build_param_exports(ctx, outputs, noutput, outinfo, export_clip_dists);
2036 }
2037
2038 static void
2039 handle_vs_outputs_post(struct radv_shader_context *ctx,
2040 bool export_prim_id,
2041 bool export_clip_dists,
2042 struct radv_vs_output_info *outinfo)
2043 {
2044 struct radv_shader_output_values *outputs;
2045 unsigned noutput = 0;
2046
2047 if (ctx->args->options->key.has_multiview_view_index) {
2048 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2049 if(!*tmp_out) {
2050 for(unsigned i = 0; i < 4; ++i)
2051 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2052 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2053 }
2054
2055 LLVMValueRef view_index = ac_get_arg(&ctx->ac, ctx->args->ac.view_index);
2056 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, view_index), *tmp_out);
2057 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2058 }
2059
2060 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2061 sizeof(outinfo->vs_output_param_offset));
2062 outinfo->pos_exports = 0;
2063
2064 if (!ctx->args->options->use_ngg_streamout &&
2065 ctx->args->shader_info->so.num_outputs &&
2066 !ctx->args->is_gs_copy_shader) {
2067 /* The GS copy shader emission already emits streamout. */
2068 radv_emit_streamout(ctx, 0);
2069 }
2070
2071 /* Allocate a temporary array for the output values. */
2072 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_prim_id;
2073 outputs = malloc(num_outputs * sizeof(outputs[0]));
2074
2075 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2076 if (!(ctx->output_mask & (1ull << i)))
2077 continue;
2078
2079 outputs[noutput].slot_name = i;
2080 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
2081
2082 if (ctx->stage == MESA_SHADER_VERTEX &&
2083 !ctx->args->is_gs_copy_shader) {
2084 outputs[noutput].usage_mask =
2085 ctx->args->shader_info->vs.output_usage_mask[i];
2086 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2087 outputs[noutput].usage_mask =
2088 ctx->args->shader_info->tes.output_usage_mask[i];
2089 } else {
2090 assert(ctx->args->is_gs_copy_shader);
2091 outputs[noutput].usage_mask =
2092 ctx->args->shader_info->gs.output_usage_mask[i];
2093 }
2094
2095 for (unsigned j = 0; j < 4; j++) {
2096 outputs[noutput].values[j] =
2097 ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2098 }
2099
2100 noutput++;
2101 }
2102
2103 /* Export PrimitiveID. */
2104 if (export_prim_id) {
2105 outputs[noutput].slot_name = VARYING_SLOT_PRIMITIVE_ID;
2106 outputs[noutput].slot_index = 0;
2107 outputs[noutput].usage_mask = 0x1;
2108 outputs[noutput].values[0] =
2109 ac_get_arg(&ctx->ac, ctx->args->vs_prim_id);
2110 for (unsigned j = 1; j < 4; j++)
2111 outputs[noutput].values[j] = ctx->ac.f32_0;
2112 noutput++;
2113 }
2114
2115 radv_llvm_export_vs(ctx, outputs, noutput, outinfo, export_clip_dists);
2116
2117 free(outputs);
2118 }
2119
2120 static void
2121 handle_es_outputs_post(struct radv_shader_context *ctx,
2122 struct radv_es_output_info *outinfo)
2123 {
2124 int j;
2125 LLVMValueRef lds_base = NULL;
2126
2127 if (ctx->ac.chip_class >= GFX9) {
2128 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2129 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2130 LLVMValueRef wave_idx =
2131 ac_unpack_param(&ctx->ac,
2132 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 24, 4);
2133 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2134 LLVMBuildMul(ctx->ac.builder, wave_idx,
2135 LLVMConstInt(ctx->ac.i32,
2136 ctx->ac.wave_size, false), ""), "");
2137 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2138 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2139 }
2140
2141 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2142 LLVMValueRef dw_addr = NULL;
2143 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2144 unsigned output_usage_mask;
2145 int param_index;
2146
2147 if (!(ctx->output_mask & (1ull << i)))
2148 continue;
2149
2150 if (ctx->stage == MESA_SHADER_VERTEX) {
2151 output_usage_mask =
2152 ctx->args->shader_info->vs.output_usage_mask[i];
2153 } else {
2154 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2155 output_usage_mask =
2156 ctx->args->shader_info->tes.output_usage_mask[i];
2157 }
2158
2159 param_index = shader_io_get_unique_index(i);
2160
2161 if (lds_base) {
2162 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2163 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2164 "");
2165 }
2166
2167 for (j = 0; j < 4; j++) {
2168 if (!(output_usage_mask & (1 << j)))
2169 continue;
2170
2171 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2172 out_val = ac_to_integer(&ctx->ac, out_val);
2173 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2174
2175 if (ctx->ac.chip_class >= GFX9) {
2176 LLVMValueRef dw_addr_offset =
2177 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2178 LLVMConstInt(ctx->ac.i32,
2179 j, false), "");
2180
2181 ac_lds_store(&ctx->ac, dw_addr_offset, out_val);
2182 } else {
2183 ac_build_buffer_store_dword(&ctx->ac,
2184 ctx->esgs_ring,
2185 out_val, 1,
2186 NULL,
2187 ac_get_arg(&ctx->ac, ctx->args->es2gs_offset),
2188 (4 * param_index + j) * 4,
2189 ac_glc | ac_slc | ac_swizzled);
2190 }
2191 }
2192 }
2193 }
2194
2195 static void
2196 handle_ls_outputs_post(struct radv_shader_context *ctx)
2197 {
2198 LLVMValueRef vertex_id = ctx->rel_auto_id;
2199 uint32_t num_tcs_inputs = util_last_bit64(ctx->args->shader_info->vs.ls_outputs_written);
2200 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2201 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2202 vertex_dw_stride, "");
2203
2204 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2205 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2206
2207 if (!(ctx->output_mask & (1ull << i)))
2208 continue;
2209
2210 int param = shader_io_get_unique_index(i);
2211 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2212 LLVMConstInt(ctx->ac.i32, param * 4, false),
2213 "");
2214 for (unsigned j = 0; j < 4; j++) {
2215 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2216 value = ac_to_integer(&ctx->ac, value);
2217 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
2218 ac_lds_store(&ctx->ac, dw_addr, value);
2219 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2220 }
2221 }
2222 }
2223
2224 static LLVMValueRef get_wave_id_in_tg(struct radv_shader_context *ctx)
2225 {
2226 return ac_unpack_param(&ctx->ac,
2227 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 24, 4);
2228 }
2229
2230 static LLVMValueRef get_tgsize(struct radv_shader_context *ctx)
2231 {
2232 return ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 28, 4);
2233 }
2234
2235 static LLVMValueRef get_thread_id_in_tg(struct radv_shader_context *ctx)
2236 {
2237 LLVMBuilderRef builder = ctx->ac.builder;
2238 LLVMValueRef tmp;
2239 tmp = LLVMBuildMul(builder, get_wave_id_in_tg(ctx),
2240 LLVMConstInt(ctx->ac.i32, ctx->ac.wave_size, false), "");
2241 return LLVMBuildAdd(builder, tmp, ac_get_thread_id(&ctx->ac), "");
2242 }
2243
2244 static LLVMValueRef ngg_get_vtx_cnt(struct radv_shader_context *ctx)
2245 {
2246 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2247 LLVMConstInt(ctx->ac.i32, 12, false),
2248 LLVMConstInt(ctx->ac.i32, 9, false),
2249 false);
2250 }
2251
2252 static LLVMValueRef ngg_get_prim_cnt(struct radv_shader_context *ctx)
2253 {
2254 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2255 LLVMConstInt(ctx->ac.i32, 22, false),
2256 LLVMConstInt(ctx->ac.i32, 9, false),
2257 false);
2258 }
2259
2260 static LLVMValueRef ngg_get_ordered_id(struct radv_shader_context *ctx)
2261 {
2262 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2263 ctx->ac.i32_0,
2264 LLVMConstInt(ctx->ac.i32, 12, false),
2265 false);
2266 }
2267
2268 static LLVMValueRef
2269 ngg_gs_get_vertex_storage(struct radv_shader_context *ctx)
2270 {
2271 unsigned num_outputs = util_bitcount64(ctx->output_mask);
2272
2273 if (ctx->args->options->key.has_multiview_view_index)
2274 num_outputs++;
2275
2276 LLVMTypeRef elements[2] = {
2277 LLVMArrayType(ctx->ac.i32, 4 * num_outputs),
2278 LLVMArrayType(ctx->ac.i8, 4),
2279 };
2280 LLVMTypeRef type = LLVMStructTypeInContext(ctx->ac.context, elements, 2, false);
2281 type = LLVMPointerType(LLVMArrayType(type, 0), AC_ADDR_SPACE_LDS);
2282 return LLVMBuildBitCast(ctx->ac.builder, ctx->gs_ngg_emit, type, "");
2283 }
2284
2285 /**
2286 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
2287 * is in emit order; that is:
2288 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
2289 * - during vertex emit, i.e. while the API GS shader invocation is running,
2290 * N = threadidx * gs_max_out_vertices + emitidx
2291 *
2292 * Goals of the LDS memory layout:
2293 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
2294 * in uniform control flow
2295 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
2296 * culling
2297 * 3. Agnostic to the number of waves (since we don't know it before compiling)
2298 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
2299 * 5. Avoid wasting memory.
2300 *
2301 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
2302 * layout, elimination of bank conflicts requires that each vertex occupy an
2303 * odd number of dwords. We use the additional dword to store the output stream
2304 * index as well as a flag to indicate whether this vertex ends a primitive
2305 * for rasterization.
2306 *
2307 * Swizzling is required to satisfy points 1 and 2 simultaneously.
2308 *
2309 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
2310 * Indices are swizzled in groups of 32, which ensures point 1 without
2311 * disturbing point 2.
2312 *
2313 * \return an LDS pointer to type {[N x i32], [4 x i8]}
2314 */
2315 static LLVMValueRef
2316 ngg_gs_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexidx)
2317 {
2318 LLVMBuilderRef builder = ctx->ac.builder;
2319 LLVMValueRef storage = ngg_gs_get_vertex_storage(ctx);
2320
2321 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
2322 unsigned write_stride_2exp = ffs(ctx->shader->info.gs.vertices_out) - 1;
2323 if (write_stride_2exp) {
2324 LLVMValueRef row =
2325 LLVMBuildLShr(builder, vertexidx,
2326 LLVMConstInt(ctx->ac.i32, 5, false), "");
2327 LLVMValueRef swizzle =
2328 LLVMBuildAnd(builder, row,
2329 LLVMConstInt(ctx->ac.i32, (1u << write_stride_2exp) - 1,
2330 false), "");
2331 vertexidx = LLVMBuildXor(builder, vertexidx, swizzle, "");
2332 }
2333
2334 return ac_build_gep0(&ctx->ac, storage, vertexidx);
2335 }
2336
2337 static LLVMValueRef
2338 ngg_gs_emit_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef gsthread,
2339 LLVMValueRef emitidx)
2340 {
2341 LLVMBuilderRef builder = ctx->ac.builder;
2342 LLVMValueRef tmp;
2343
2344 tmp = LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false);
2345 tmp = LLVMBuildMul(builder, tmp, gsthread, "");
2346 const LLVMValueRef vertexidx = LLVMBuildAdd(builder, tmp, emitidx, "");
2347 return ngg_gs_vertex_ptr(ctx, vertexidx);
2348 }
2349
2350 static LLVMValueRef
2351 ngg_gs_get_emit_output_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexptr,
2352 unsigned out_idx)
2353 {
2354 LLVMValueRef gep_idx[3] = {
2355 ctx->ac.i32_0, /* implied C-style array */
2356 ctx->ac.i32_0, /* first struct entry */
2357 LLVMConstInt(ctx->ac.i32, out_idx, false),
2358 };
2359 return LLVMBuildGEP(ctx->ac.builder, vertexptr, gep_idx, 3, "");
2360 }
2361
2362 static LLVMValueRef
2363 ngg_gs_get_emit_primflag_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexptr,
2364 unsigned stream)
2365 {
2366 LLVMValueRef gep_idx[3] = {
2367 ctx->ac.i32_0, /* implied C-style array */
2368 ctx->ac.i32_1, /* second struct entry */
2369 LLVMConstInt(ctx->ac.i32, stream, false),
2370 };
2371 return LLVMBuildGEP(ctx->ac.builder, vertexptr, gep_idx, 3, "");
2372 }
2373
2374 static struct radv_stream_output *
2375 radv_get_stream_output_by_loc(struct radv_streamout_info *so, unsigned location)
2376 {
2377 for (unsigned i = 0; i < so->num_outputs; ++i) {
2378 if (so->outputs[i].location == location)
2379 return &so->outputs[i];
2380 }
2381
2382 return NULL;
2383 }
2384
2385 static void build_streamout_vertex(struct radv_shader_context *ctx,
2386 LLVMValueRef *so_buffer, LLVMValueRef *wg_offset_dw,
2387 unsigned stream, LLVMValueRef offset_vtx,
2388 LLVMValueRef vertexptr)
2389 {
2390 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2391 LLVMBuilderRef builder = ctx->ac.builder;
2392 LLVMValueRef offset[4] = {};
2393 LLVMValueRef tmp;
2394
2395 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2396 if (!wg_offset_dw[buffer])
2397 continue;
2398
2399 tmp = LLVMBuildMul(builder, offset_vtx,
2400 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false), "");
2401 tmp = LLVMBuildAdd(builder, wg_offset_dw[buffer], tmp, "");
2402 offset[buffer] = LLVMBuildShl(builder, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
2403 }
2404
2405 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2406 struct radv_shader_output_values outputs[AC_LLVM_MAX_OUTPUTS];
2407 unsigned noutput = 0;
2408 unsigned out_idx = 0;
2409
2410 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2411 unsigned output_usage_mask =
2412 ctx->args->shader_info->gs.output_usage_mask[i];
2413 uint8_t output_stream =
2414 output_stream = ctx->args->shader_info->gs.output_streams[i];
2415
2416 if (!(ctx->output_mask & (1ull << i)) ||
2417 output_stream != stream)
2418 continue;
2419
2420 outputs[noutput].slot_name = i;
2421 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
2422 outputs[noutput].usage_mask = output_usage_mask;
2423
2424 int length = util_last_bit(output_usage_mask);
2425
2426 for (unsigned j = 0; j < length; j++, out_idx++) {
2427 if (!(output_usage_mask & (1 << j)))
2428 continue;
2429
2430 tmp = ac_build_gep0(&ctx->ac, vertexptr,
2431 LLVMConstInt(ctx->ac.i32, out_idx, false));
2432 outputs[noutput].values[j] = LLVMBuildLoad(builder, tmp, "");
2433 }
2434
2435 for (unsigned j = length; j < 4; j++)
2436 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
2437
2438 noutput++;
2439 }
2440
2441 for (unsigned i = 0; i < noutput; i++) {
2442 struct radv_stream_output *output =
2443 radv_get_stream_output_by_loc(so, outputs[i].slot_name);
2444
2445 if (!output ||
2446 output->stream != stream)
2447 continue;
2448
2449 struct radv_shader_output_values out = {};
2450
2451 for (unsigned j = 0; j < 4; j++) {
2452 out.values[j] = outputs[i].values[j];
2453 }
2454
2455 radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
2456 }
2457 } else {
2458 for (unsigned i = 0; i < so->num_outputs; ++i) {
2459 struct radv_stream_output *output =
2460 &ctx->args->shader_info->so.outputs[i];
2461
2462 if (stream != output->stream)
2463 continue;
2464
2465 struct radv_shader_output_values out = {};
2466
2467 for (unsigned comp = 0; comp < 4; comp++) {
2468 if (!(output->component_mask & (1 << comp)))
2469 continue;
2470
2471 tmp = ac_build_gep0(&ctx->ac, vertexptr,
2472 LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
2473 out.values[comp] = LLVMBuildLoad(builder, tmp, "");
2474 }
2475
2476 radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
2477 }
2478 }
2479 }
2480
2481 struct ngg_streamout {
2482 LLVMValueRef num_vertices;
2483
2484 /* per-thread data */
2485 LLVMValueRef prim_enable[4]; /* i1 per stream */
2486 LLVMValueRef vertices[3]; /* [N x i32] addrspace(LDS)* */
2487
2488 /* Output */
2489 LLVMValueRef emit[4]; /* per-stream emitted primitives (only valid for used streams) */
2490 };
2491
2492 /**
2493 * Build streamout logic.
2494 *
2495 * Implies a barrier.
2496 *
2497 * Writes number of emitted primitives to gs_ngg_scratch[4:7].
2498 *
2499 * Clobbers gs_ngg_scratch[8:].
2500 */
2501 static void build_streamout(struct radv_shader_context *ctx,
2502 struct ngg_streamout *nggso)
2503 {
2504 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2505 LLVMBuilderRef builder = ctx->ac.builder;
2506 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->args->streamout_buffers);
2507 LLVMValueRef tid = get_thread_id_in_tg(ctx);
2508 LLVMValueRef cond, tmp, tmp2;
2509 LLVMValueRef i32_2 = LLVMConstInt(ctx->ac.i32, 2, false);
2510 LLVMValueRef i32_4 = LLVMConstInt(ctx->ac.i32, 4, false);
2511 LLVMValueRef i32_8 = LLVMConstInt(ctx->ac.i32, 8, false);
2512 LLVMValueRef so_buffer[4] = {};
2513 unsigned max_num_vertices = 1 + (nggso->vertices[1] ? 1 : 0) +
2514 (nggso->vertices[2] ? 1 : 0);
2515 LLVMValueRef prim_stride_dw[4] = {};
2516 LLVMValueRef prim_stride_dw_vgpr = LLVMGetUndef(ctx->ac.i32);
2517 int stream_for_buffer[4] = { -1, -1, -1, -1 };
2518 unsigned bufmask_for_stream[4] = {};
2519 bool isgs = ctx->stage == MESA_SHADER_GEOMETRY;
2520 unsigned scratch_emit_base = isgs ? 4 : 0;
2521 LLVMValueRef scratch_emit_basev = isgs ? i32_4 : ctx->ac.i32_0;
2522 unsigned scratch_offset_base = isgs ? 8 : 4;
2523 LLVMValueRef scratch_offset_basev = isgs ? i32_8 : i32_4;
2524
2525 ac_llvm_add_target_dep_function_attr(ctx->main_function,
2526 "amdgpu-gds-size", 256);
2527
2528 /* Determine the mapping of streamout buffers to vertex streams. */
2529 for (unsigned i = 0; i < so->num_outputs; ++i) {
2530 unsigned buf = so->outputs[i].buffer;
2531 unsigned stream = so->outputs[i].stream;
2532 assert(stream_for_buffer[buf] < 0 || stream_for_buffer[buf] == stream);
2533 stream_for_buffer[buf] = stream;
2534 bufmask_for_stream[stream] |= 1 << buf;
2535 }
2536
2537 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2538 if (stream_for_buffer[buffer] == -1)
2539 continue;
2540
2541 assert(so->strides[buffer]);
2542
2543 LLVMValueRef stride_for_buffer =
2544 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false);
2545 prim_stride_dw[buffer] =
2546 LLVMBuildMul(builder, stride_for_buffer,
2547 nggso->num_vertices, "");
2548 prim_stride_dw_vgpr = ac_build_writelane(
2549 &ctx->ac, prim_stride_dw_vgpr, prim_stride_dw[buffer],
2550 LLVMConstInt(ctx->ac.i32, buffer, false));
2551
2552 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, buffer, false);
2553 so_buffer[buffer] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr,
2554 offset);
2555 }
2556
2557 cond = LLVMBuildICmp(builder, LLVMIntEQ, get_wave_id_in_tg(ctx), ctx->ac.i32_0, "");
2558 ac_build_ifcc(&ctx->ac, cond, 5200);
2559 {
2560 LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS);
2561 LLVMValueRef gdsbase = LLVMBuildIntToPtr(builder, ctx->ac.i32_0, gdsptr, "");
2562
2563 /* Advance the streamout offsets in GDS. */
2564 LLVMValueRef offsets_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
2565 LLVMValueRef generated_by_stream_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
2566
2567 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
2568 ac_build_ifcc(&ctx->ac, cond, 5210);
2569 {
2570 /* Fetch the number of generated primitives and store
2571 * it in GDS for later use.
2572 */
2573 if (isgs) {
2574 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tid);
2575 tmp = LLVMBuildLoad(builder, tmp, "");
2576 } else {
2577 tmp = ac_build_writelane(&ctx->ac, ctx->ac.i32_0,
2578 ngg_get_prim_cnt(ctx), ctx->ac.i32_0);
2579 }
2580 LLVMBuildStore(builder, tmp, generated_by_stream_vgpr);
2581
2582 unsigned swizzle[4];
2583 int unused_stream = -1;
2584 for (unsigned stream = 0; stream < 4; ++stream) {
2585 if (!ctx->args->shader_info->gs.num_stream_output_components[stream]) {
2586 unused_stream = stream;
2587 break;
2588 }
2589 }
2590 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2591 if (stream_for_buffer[buffer] >= 0) {
2592 swizzle[buffer] = stream_for_buffer[buffer];
2593 } else {
2594 assert(unused_stream >= 0);
2595 swizzle[buffer] = unused_stream;
2596 }
2597 }
2598
2599 tmp = ac_build_quad_swizzle(&ctx->ac, tmp,
2600 swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
2601 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
2602
2603 LLVMValueRef args[] = {
2604 LLVMBuildIntToPtr(builder, ngg_get_ordered_id(ctx), gdsptr, ""),
2605 tmp,
2606 ctx->ac.i32_0, // ordering
2607 ctx->ac.i32_0, // scope
2608 ctx->ac.i1false, // isVolatile
2609 LLVMConstInt(ctx->ac.i32, 4 << 24, false), // OA index
2610 ctx->ac.i1true, // wave release
2611 ctx->ac.i1true, // wave done
2612 };
2613
2614 tmp = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ds.ordered.add",
2615 ctx->ac.i32, args, ARRAY_SIZE(args), 0);
2616
2617 /* Keep offsets in a VGPR for quick retrieval via readlane by
2618 * the first wave for bounds checking, and also store in LDS
2619 * for retrieval by all waves later. */
2620 LLVMBuildStore(builder, tmp, offsets_vgpr);
2621
2622 tmp2 = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
2623 scratch_offset_basev, "");
2624 tmp2 = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp2);
2625 LLVMBuildStore(builder, tmp, tmp2);
2626 }
2627 ac_build_endif(&ctx->ac, 5210);
2628
2629 /* Determine the max emit per buffer. This is done via the SALU, in part
2630 * because LLVM can't generate divide-by-multiply if we try to do this
2631 * via VALU with one lane per buffer.
2632 */
2633 LLVMValueRef max_emit[4] = {};
2634 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2635 if (stream_for_buffer[buffer] == -1)
2636 continue;
2637
2638 /* Compute the streamout buffer size in DWORD. */
2639 LLVMValueRef bufsize_dw =
2640 LLVMBuildLShr(builder,
2641 LLVMBuildExtractElement(builder, so_buffer[buffer], i32_2, ""),
2642 i32_2, "");
2643
2644 /* Load the streamout buffer offset from GDS. */
2645 tmp = LLVMBuildLoad(builder, offsets_vgpr, "");
2646 LLVMValueRef offset_dw =
2647 ac_build_readlane(&ctx->ac, tmp,
2648 LLVMConstInt(ctx->ac.i32, buffer, false));
2649
2650 /* Compute the remaining size to emit. */
2651 LLVMValueRef remaining_dw =
2652 LLVMBuildSub(builder, bufsize_dw, offset_dw, "");
2653 tmp = LLVMBuildUDiv(builder, remaining_dw,
2654 prim_stride_dw[buffer], "");
2655
2656 cond = LLVMBuildICmp(builder, LLVMIntULT,
2657 bufsize_dw, offset_dw, "");
2658 max_emit[buffer] = LLVMBuildSelect(builder, cond,
2659 ctx->ac.i32_0, tmp, "");
2660 }
2661
2662 /* Determine the number of emitted primitives per stream and fixup the
2663 * GDS counter if necessary.
2664 *
2665 * This is complicated by the fact that a single stream can emit to
2666 * multiple buffers (but luckily not vice versa).
2667 */
2668 LLVMValueRef emit_vgpr = ctx->ac.i32_0;
2669
2670 for (unsigned stream = 0; stream < 4; ++stream) {
2671 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2672 continue;
2673
2674 /* Load the number of generated primitives from GDS and
2675 * determine that number for the given stream.
2676 */
2677 tmp = LLVMBuildLoad(builder, generated_by_stream_vgpr, "");
2678 LLVMValueRef generated =
2679 ac_build_readlane(&ctx->ac, tmp,
2680 LLVMConstInt(ctx->ac.i32, stream, false));
2681
2682
2683 /* Compute the number of emitted primitives. */
2684 LLVMValueRef emit = generated;
2685 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2686 if (stream_for_buffer[buffer] == stream)
2687 emit = ac_build_umin(&ctx->ac, emit, max_emit[buffer]);
2688 }
2689
2690 /* Store the number of emitted primitives for that
2691 * stream.
2692 */
2693 emit_vgpr = ac_build_writelane(&ctx->ac, emit_vgpr, emit,
2694 LLVMConstInt(ctx->ac.i32, stream, false));
2695
2696 /* Fixup the offset using a plain GDS atomic if we overflowed. */
2697 cond = LLVMBuildICmp(builder, LLVMIntULT, emit, generated, "");
2698 ac_build_ifcc(&ctx->ac, cond, 5221); /* scalar branch */
2699 tmp = LLVMBuildLShr(builder,
2700 LLVMConstInt(ctx->ac.i32, bufmask_for_stream[stream], false),
2701 ac_get_thread_id(&ctx->ac), "");
2702 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
2703 ac_build_ifcc(&ctx->ac, tmp, 5222);
2704 {
2705 tmp = LLVMBuildSub(builder, generated, emit, "");
2706 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
2707 tmp2 = LLVMBuildGEP(builder, gdsbase, &tid, 1, "");
2708 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpSub, tmp2, tmp,
2709 LLVMAtomicOrderingMonotonic, false);
2710 }
2711 ac_build_endif(&ctx->ac, 5222);
2712 ac_build_endif(&ctx->ac, 5221);
2713 }
2714
2715 /* Store the number of emitted primitives to LDS for later use. */
2716 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
2717 ac_build_ifcc(&ctx->ac, cond, 5225);
2718 {
2719 tmp = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
2720 scratch_emit_basev, "");
2721 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp);
2722 LLVMBuildStore(builder, emit_vgpr, tmp);
2723 }
2724 ac_build_endif(&ctx->ac, 5225);
2725 }
2726 ac_build_endif(&ctx->ac, 5200);
2727
2728 /* Determine the workgroup-relative per-thread / primitive offset into
2729 * the streamout buffers */
2730 struct ac_wg_scan primemit_scan[4] = {};
2731
2732 if (isgs) {
2733 for (unsigned stream = 0; stream < 4; ++stream) {
2734 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2735 continue;
2736
2737 primemit_scan[stream].enable_exclusive = true;
2738 primemit_scan[stream].op = nir_op_iadd;
2739 primemit_scan[stream].src = nggso->prim_enable[stream];
2740 primemit_scan[stream].scratch =
2741 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
2742 LLVMConstInt(ctx->ac.i32, 12 + 8 * stream, false));
2743 primemit_scan[stream].waveidx = get_wave_id_in_tg(ctx);
2744 primemit_scan[stream].numwaves = get_tgsize(ctx);
2745 primemit_scan[stream].maxwaves = 8;
2746 ac_build_wg_scan_top(&ctx->ac, &primemit_scan[stream]);
2747 }
2748 }
2749
2750 ac_build_s_barrier(&ctx->ac);
2751
2752 /* Fetch the per-buffer offsets and per-stream emit counts in all waves. */
2753 LLVMValueRef wgoffset_dw[4] = {};
2754
2755 {
2756 LLVMValueRef scratch_vgpr;
2757
2758 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ac_get_thread_id(&ctx->ac));
2759 scratch_vgpr = LLVMBuildLoad(builder, tmp, "");
2760
2761 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2762 if (stream_for_buffer[buffer] >= 0) {
2763 wgoffset_dw[buffer] = ac_build_readlane(
2764 &ctx->ac, scratch_vgpr,
2765 LLVMConstInt(ctx->ac.i32, scratch_offset_base + buffer, false));
2766 }
2767 }
2768
2769 for (unsigned stream = 0; stream < 4; ++stream) {
2770 if (ctx->args->shader_info->gs.num_stream_output_components[stream]) {
2771 nggso->emit[stream] = ac_build_readlane(
2772 &ctx->ac, scratch_vgpr,
2773 LLVMConstInt(ctx->ac.i32, scratch_emit_base + stream, false));
2774 }
2775 }
2776 }
2777
2778 /* Write out primitive data */
2779 for (unsigned stream = 0; stream < 4; ++stream) {
2780 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2781 continue;
2782
2783 if (isgs) {
2784 ac_build_wg_scan_bottom(&ctx->ac, &primemit_scan[stream]);
2785 } else {
2786 primemit_scan[stream].result_exclusive = tid;
2787 }
2788
2789 cond = LLVMBuildICmp(builder, LLVMIntULT,
2790 primemit_scan[stream].result_exclusive,
2791 nggso->emit[stream], "");
2792 cond = LLVMBuildAnd(builder, cond, nggso->prim_enable[stream], "");
2793 ac_build_ifcc(&ctx->ac, cond, 5240);
2794 {
2795 LLVMValueRef offset_vtx =
2796 LLVMBuildMul(builder, primemit_scan[stream].result_exclusive,
2797 nggso->num_vertices, "");
2798
2799 for (unsigned i = 0; i < max_num_vertices; ++i) {
2800 cond = LLVMBuildICmp(builder, LLVMIntULT,
2801 LLVMConstInt(ctx->ac.i32, i, false),
2802 nggso->num_vertices, "");
2803 ac_build_ifcc(&ctx->ac, cond, 5241);
2804 build_streamout_vertex(ctx, so_buffer, wgoffset_dw,
2805 stream, offset_vtx, nggso->vertices[i]);
2806 ac_build_endif(&ctx->ac, 5241);
2807 offset_vtx = LLVMBuildAdd(builder, offset_vtx, ctx->ac.i32_1, "");
2808 }
2809 }
2810 ac_build_endif(&ctx->ac, 5240);
2811 }
2812 }
2813
2814 static unsigned ngg_nogs_vertex_size(struct radv_shader_context *ctx)
2815 {
2816 unsigned lds_vertex_size = 0;
2817
2818 if (ctx->args->shader_info->so.num_outputs)
2819 lds_vertex_size = 4 * ctx->args->shader_info->so.num_outputs + 1;
2820
2821 return lds_vertex_size;
2822 }
2823
2824 /**
2825 * Returns an `[N x i32] addrspace(LDS)*` pointing at contiguous LDS storage
2826 * for the vertex outputs.
2827 */
2828 static LLVMValueRef ngg_nogs_vertex_ptr(struct radv_shader_context *ctx,
2829 LLVMValueRef vtxid)
2830 {
2831 /* The extra dword is used to avoid LDS bank conflicts. */
2832 unsigned vertex_size = ngg_nogs_vertex_size(ctx);
2833 LLVMTypeRef ai32 = LLVMArrayType(ctx->ac.i32, vertex_size);
2834 LLVMTypeRef pai32 = LLVMPointerType(ai32, AC_ADDR_SPACE_LDS);
2835 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, ctx->esgs_ring, pai32, "");
2836 return LLVMBuildGEP(ctx->ac.builder, tmp, &vtxid, 1, "");
2837 }
2838
2839 static void
2840 handle_ngg_outputs_post_1(struct radv_shader_context *ctx)
2841 {
2842 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2843 LLVMBuilderRef builder = ctx->ac.builder;
2844 LLVMValueRef vertex_ptr = NULL;
2845 LLVMValueRef tmp, tmp2;
2846
2847 assert((ctx->stage == MESA_SHADER_VERTEX ||
2848 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->args->is_gs_copy_shader);
2849
2850 if (!ctx->args->shader_info->so.num_outputs)
2851 return;
2852
2853 vertex_ptr = ngg_nogs_vertex_ptr(ctx, get_thread_id_in_tg(ctx));
2854
2855 for (unsigned i = 0; i < so->num_outputs; ++i) {
2856 struct radv_stream_output *output =
2857 &ctx->args->shader_info->so.outputs[i];
2858
2859 unsigned loc = output->location;
2860
2861 for (unsigned comp = 0; comp < 4; comp++) {
2862 if (!(output->component_mask & (1 << comp)))
2863 continue;
2864
2865 tmp = ac_build_gep0(&ctx->ac, vertex_ptr,
2866 LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
2867 tmp2 = LLVMBuildLoad(builder,
2868 ctx->abi.outputs[4 * loc + comp], "");
2869 tmp2 = ac_to_integer(&ctx->ac, tmp2);
2870 LLVMBuildStore(builder, tmp2, tmp);
2871 }
2872 }
2873 }
2874
2875 static void
2876 handle_ngg_outputs_post_2(struct radv_shader_context *ctx)
2877 {
2878 LLVMBuilderRef builder = ctx->ac.builder;
2879 LLVMValueRef tmp;
2880
2881 assert((ctx->stage == MESA_SHADER_VERTEX ||
2882 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->args->is_gs_copy_shader);
2883
2884 LLVMValueRef prims_in_wave = ac_unpack_param(&ctx->ac,
2885 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 8, 8);
2886 LLVMValueRef vtx_in_wave = ac_unpack_param(&ctx->ac,
2887 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 0, 8);
2888 LLVMValueRef is_gs_thread = LLVMBuildICmp(builder, LLVMIntULT,
2889 ac_get_thread_id(&ctx->ac), prims_in_wave, "");
2890 LLVMValueRef is_es_thread = LLVMBuildICmp(builder, LLVMIntULT,
2891 ac_get_thread_id(&ctx->ac), vtx_in_wave, "");
2892 LLVMValueRef vtxindex[] = {
2893 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]), 0, 16),
2894 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]), 16, 16),
2895 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[2]), 0, 16),
2896 };
2897
2898 /* Determine the number of vertices per primitive. */
2899 unsigned num_vertices;
2900 LLVMValueRef num_vertices_val;
2901
2902 if (ctx->stage == MESA_SHADER_VERTEX) {
2903 LLVMValueRef outprim_val =
2904 LLVMConstInt(ctx->ac.i32,
2905 ctx->args->options->key.vs.outprim, false);
2906 num_vertices_val = LLVMBuildAdd(builder, outprim_val,
2907 ctx->ac.i32_1, "");
2908 num_vertices = 3; /* TODO: optimize for points & lines */
2909 } else {
2910 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2911
2912 if (ctx->shader->info.tess.point_mode)
2913 num_vertices = 1;
2914 else if (ctx->shader->info.tess.primitive_mode == GL_ISOLINES)
2915 num_vertices = 2;
2916 else
2917 num_vertices = 3;
2918
2919 num_vertices_val = LLVMConstInt(ctx->ac.i32, num_vertices, false);
2920 }
2921
2922 /* Streamout */
2923 if (ctx->args->shader_info->so.num_outputs) {
2924 struct ngg_streamout nggso = {};
2925
2926 nggso.num_vertices = num_vertices_val;
2927 nggso.prim_enable[0] = is_gs_thread;
2928
2929 for (unsigned i = 0; i < num_vertices; ++i)
2930 nggso.vertices[i] = ngg_nogs_vertex_ptr(ctx, vtxindex[i]);
2931
2932 build_streamout(ctx, &nggso);
2933 }
2934
2935 /* Copy Primitive IDs from GS threads to the LDS address corresponding
2936 * to the ES thread of the provoking vertex.
2937 */
2938 if (ctx->stage == MESA_SHADER_VERTEX &&
2939 ctx->args->options->key.vs_common_out.export_prim_id) {
2940 if (ctx->args->shader_info->so.num_outputs)
2941 ac_build_s_barrier(&ctx->ac);
2942
2943 ac_build_ifcc(&ctx->ac, is_gs_thread, 5400);
2944 /* Extract the PROVOKING_VTX_INDEX field. */
2945 LLVMValueRef provoking_vtx_in_prim =
2946 LLVMConstInt(ctx->ac.i32, 0, false);
2947
2948 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
2949 LLVMValueRef indices = ac_build_gather_values(&ctx->ac, vtxindex, 3);
2950 LLVMValueRef provoking_vtx_index =
2951 LLVMBuildExtractElement(builder, indices, provoking_vtx_in_prim, "");
2952
2953 LLVMBuildStore(builder, ac_get_arg(&ctx->ac, ctx->args->ac.gs_prim_id),
2954 ac_build_gep0(&ctx->ac, ctx->esgs_ring, provoking_vtx_index));
2955 ac_build_endif(&ctx->ac, 5400);
2956 }
2957
2958 /* TODO: primitive culling */
2959
2960 ac_build_sendmsg_gs_alloc_req(&ctx->ac, get_wave_id_in_tg(ctx),
2961 ngg_get_vtx_cnt(ctx), ngg_get_prim_cnt(ctx));
2962
2963 /* TODO: streamout queries */
2964 /* Export primitive data to the index buffer.
2965 *
2966 * For the first version, we will always build up all three indices
2967 * independent of the primitive type. The additional garbage data
2968 * shouldn't hurt.
2969 *
2970 * TODO: culling depends on the primitive type, so can have some
2971 * interaction here.
2972 */
2973 ac_build_ifcc(&ctx->ac, is_gs_thread, 6001);
2974 {
2975 struct ac_ngg_prim prim = {};
2976
2977 if (ctx->args->options->key.vs_common_out.as_ngg_passthrough) {
2978 prim.passthrough = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]);
2979 } else {
2980 prim.num_vertices = num_vertices;
2981 prim.isnull = ctx->ac.i1false;
2982 memcpy(prim.index, vtxindex, sizeof(vtxindex[0]) * 3);
2983
2984 for (unsigned i = 0; i < num_vertices; ++i) {
2985 tmp = LLVMBuildLShr(builder,
2986 ac_get_arg(&ctx->ac, ctx->args->ac.gs_invocation_id),
2987 LLVMConstInt(ctx->ac.i32, 8 + i, false), "");
2988 prim.edgeflag[i] = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
2989 }
2990 }
2991
2992 ac_build_export_prim(&ctx->ac, &prim);
2993 }
2994 ac_build_endif(&ctx->ac, 6001);
2995
2996 /* Export per-vertex data (positions and parameters). */
2997 ac_build_ifcc(&ctx->ac, is_es_thread, 6002);
2998 {
2999 struct radv_vs_output_info *outinfo =
3000 ctx->stage == MESA_SHADER_TESS_EVAL ?
3001 &ctx->args->shader_info->tes.outinfo : &ctx->args->shader_info->vs.outinfo;
3002
3003 /* Exporting the primitive ID is handled below. */
3004 /* TODO: use the new VS export path */
3005 handle_vs_outputs_post(ctx, false,
3006 ctx->args->options->key.vs_common_out.export_clip_dists,
3007 outinfo);
3008
3009 if (ctx->args->options->key.vs_common_out.export_prim_id) {
3010 unsigned param_count = outinfo->param_exports;
3011 LLVMValueRef values[4];
3012
3013 if (ctx->stage == MESA_SHADER_VERTEX) {
3014 /* Wait for GS stores to finish. */
3015 ac_build_s_barrier(&ctx->ac);
3016
3017 tmp = ac_build_gep0(&ctx->ac, ctx->esgs_ring,
3018 get_thread_id_in_tg(ctx));
3019 values[0] = LLVMBuildLoad(builder, tmp, "");
3020 } else {
3021 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
3022 values[0] = ac_get_arg(&ctx->ac, ctx->args->ac.tes_patch_id);
3023 }
3024
3025 values[0] = ac_to_float(&ctx->ac, values[0]);
3026 for (unsigned j = 1; j < 4; j++)
3027 values[j] = ctx->ac.f32_0;
3028
3029 radv_export_param(ctx, param_count, values, 0x1);
3030
3031 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
3032 outinfo->param_exports = param_count;
3033 }
3034 }
3035 ac_build_endif(&ctx->ac, 6002);
3036 }
3037
3038 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context *ctx)
3039 {
3040 /* Zero out the part of LDS scratch that is used to accumulate the
3041 * per-stream generated primitive count.
3042 */
3043 LLVMBuilderRef builder = ctx->ac.builder;
3044 LLVMValueRef scratchptr = ctx->gs_ngg_scratch;
3045 LLVMValueRef tid = get_thread_id_in_tg(ctx);
3046 LLVMBasicBlockRef merge_block;
3047 LLVMValueRef cond;
3048
3049 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
3050 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
3051 merge_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
3052
3053 cond = LLVMBuildICmp(builder, LLVMIntULT, tid, LLVMConstInt(ctx->ac.i32, 4, false), "");
3054 LLVMBuildCondBr(ctx->ac.builder, cond, then_block, merge_block);
3055 LLVMPositionBuilderAtEnd(ctx->ac.builder, then_block);
3056
3057 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, scratchptr, tid);
3058 LLVMBuildStore(builder, ctx->ac.i32_0, ptr);
3059
3060 LLVMBuildBr(ctx->ac.builder, merge_block);
3061 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
3062
3063 ac_build_s_barrier(&ctx->ac);
3064 }
3065
3066 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context *ctx)
3067 {
3068 LLVMBuilderRef builder = ctx->ac.builder;
3069 LLVMValueRef i8_0 = LLVMConstInt(ctx->ac.i8, 0, false);
3070 LLVMValueRef tmp;
3071
3072 /* Zero out remaining (non-emitted) primitive flags.
3073 *
3074 * Note: Alternatively, we could pass the relevant gs_next_vertex to
3075 * the emit threads via LDS. This is likely worse in the expected
3076 * typical case where each GS thread emits the full set of
3077 * vertices.
3078 */
3079 for (unsigned stream = 0; stream < 4; ++stream) {
3080 unsigned num_components;
3081
3082 num_components =
3083 ctx->args->shader_info->gs.num_stream_output_components[stream];
3084 if (!num_components)
3085 continue;
3086
3087 const LLVMValueRef gsthread = get_thread_id_in_tg(ctx);
3088
3089 ac_build_bgnloop(&ctx->ac, 5100);
3090
3091 const LLVMValueRef vertexidx =
3092 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
3093 tmp = LLVMBuildICmp(builder, LLVMIntUGE, vertexidx,
3094 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
3095 ac_build_ifcc(&ctx->ac, tmp, 5101);
3096 ac_build_break(&ctx->ac);
3097 ac_build_endif(&ctx->ac, 5101);
3098
3099 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3100 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3101
3102 tmp = ngg_gs_emit_vertex_ptr(ctx, gsthread, vertexidx);
3103 LLVMBuildStore(builder, i8_0,
3104 ngg_gs_get_emit_primflag_ptr(ctx, tmp, stream));
3105
3106 ac_build_endloop(&ctx->ac, 5100);
3107 }
3108
3109 /* Accumulate generated primitives counts across the entire threadgroup. */
3110 for (unsigned stream = 0; stream < 4; ++stream) {
3111 unsigned num_components;
3112
3113 num_components =
3114 ctx->args->shader_info->gs.num_stream_output_components[stream];
3115 if (!num_components)
3116 continue;
3117
3118 LLVMValueRef numprims =
3119 LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3120 numprims = ac_build_reduce(&ctx->ac, numprims, nir_op_iadd, ctx->ac.wave_size);
3121
3122 tmp = LLVMBuildICmp(builder, LLVMIntEQ, ac_get_thread_id(&ctx->ac), ctx->ac.i32_0, "");
3123 ac_build_ifcc(&ctx->ac, tmp, 5105);
3124 {
3125 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpAdd,
3126 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
3127 LLVMConstInt(ctx->ac.i32, stream, false)),
3128 numprims, LLVMAtomicOrderingMonotonic, false);
3129 }
3130 ac_build_endif(&ctx->ac, 5105);
3131 }
3132 }
3133
3134 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context *ctx)
3135 {
3136 const unsigned verts_per_prim = si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive);
3137 LLVMBuilderRef builder = ctx->ac.builder;
3138 LLVMValueRef tmp, tmp2;
3139
3140 ac_build_s_barrier(&ctx->ac);
3141
3142 const LLVMValueRef tid = get_thread_id_in_tg(ctx);
3143 LLVMValueRef num_emit_threads = ngg_get_prim_cnt(ctx);
3144
3145 /* Streamout */
3146 if (ctx->args->shader_info->so.num_outputs) {
3147 struct ngg_streamout nggso = {};
3148
3149 nggso.num_vertices = LLVMConstInt(ctx->ac.i32, verts_per_prim, false);
3150
3151 LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tid);
3152 for (unsigned stream = 0; stream < 4; ++stream) {
3153 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
3154 continue;
3155
3156 tmp = LLVMBuildLoad(builder,
3157 ngg_gs_get_emit_primflag_ptr(ctx, vertexptr, stream), "");
3158 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3159 tmp2 = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3160 nggso.prim_enable[stream] = LLVMBuildAnd(builder, tmp, tmp2, "");
3161 }
3162
3163 for (unsigned i = 0; i < verts_per_prim; ++i) {
3164 tmp = LLVMBuildSub(builder, tid,
3165 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3166 tmp = ngg_gs_vertex_ptr(ctx, tmp);
3167 nggso.vertices[i] = ac_build_gep0(&ctx->ac, tmp, ctx->ac.i32_0);
3168 }
3169
3170 build_streamout(ctx, &nggso);
3171 }
3172
3173 /* TODO: culling */
3174
3175 /* Determine vertex liveness. */
3176 LLVMValueRef vertliveptr = ac_build_alloca(&ctx->ac, ctx->ac.i1, "vertexlive");
3177
3178 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3179 ac_build_ifcc(&ctx->ac, tmp, 5120);
3180 {
3181 for (unsigned i = 0; i < verts_per_prim; ++i) {
3182 const LLVMValueRef primidx =
3183 LLVMBuildAdd(builder, tid,
3184 LLVMConstInt(ctx->ac.i32, i, false), "");
3185
3186 if (i > 0) {
3187 tmp = LLVMBuildICmp(builder, LLVMIntULT, primidx, num_emit_threads, "");
3188 ac_build_ifcc(&ctx->ac, tmp, 5121 + i);
3189 }
3190
3191 /* Load primitive liveness */
3192 tmp = ngg_gs_vertex_ptr(ctx, primidx);
3193 tmp = LLVMBuildLoad(builder,
3194 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 0), "");
3195 const LLVMValueRef primlive =
3196 LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3197
3198 tmp = LLVMBuildLoad(builder, vertliveptr, "");
3199 tmp = LLVMBuildOr(builder, tmp, primlive, ""),
3200 LLVMBuildStore(builder, tmp, vertliveptr);
3201
3202 if (i > 0)
3203 ac_build_endif(&ctx->ac, 5121 + i);
3204 }
3205 }
3206 ac_build_endif(&ctx->ac, 5120);
3207
3208 /* Inclusive scan addition across the current wave. */
3209 LLVMValueRef vertlive = LLVMBuildLoad(builder, vertliveptr, "");
3210 struct ac_wg_scan vertlive_scan = {};
3211 vertlive_scan.op = nir_op_iadd;
3212 vertlive_scan.enable_reduce = true;
3213 vertlive_scan.enable_exclusive = true;
3214 vertlive_scan.src = vertlive;
3215 vertlive_scan.scratch = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ctx->ac.i32_0);
3216 vertlive_scan.waveidx = get_wave_id_in_tg(ctx);
3217 vertlive_scan.numwaves = get_tgsize(ctx);
3218 vertlive_scan.maxwaves = 8;
3219
3220 ac_build_wg_scan(&ctx->ac, &vertlive_scan);
3221
3222 /* Skip all exports (including index exports) when possible. At least on
3223 * early gfx10 revisions this is also to avoid hangs.
3224 */
3225 LLVMValueRef have_exports =
3226 LLVMBuildICmp(builder, LLVMIntNE, vertlive_scan.result_reduce, ctx->ac.i32_0, "");
3227 num_emit_threads =
3228 LLVMBuildSelect(builder, have_exports, num_emit_threads, ctx->ac.i32_0, "");
3229
3230 /* Allocate export space. Send this message as early as possible, to
3231 * hide the latency of the SQ <-> SPI roundtrip.
3232 *
3233 * Note: We could consider compacting primitives for export as well.
3234 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3235 * prim data per clock and skips null primitives at no additional
3236 * cost. So compacting primitives can only be beneficial when
3237 * there are 4 or more contiguous null primitives in the export
3238 * (in the common case of single-dword prim exports).
3239 */
3240 ac_build_sendmsg_gs_alloc_req(&ctx->ac, get_wave_id_in_tg(ctx),
3241 vertlive_scan.result_reduce, num_emit_threads);
3242
3243 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3244 * of the primitive liveness flags, relying on the fact that each
3245 * threadgroup can have at most 256 threads. */
3246 ac_build_ifcc(&ctx->ac, vertlive, 5130);
3247 {
3248 tmp = ngg_gs_vertex_ptr(ctx, vertlive_scan.result_exclusive);
3249 tmp2 = LLVMBuildTrunc(builder, tid, ctx->ac.i8, "");
3250 LLVMBuildStore(builder, tmp2,
3251 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 1));
3252 }
3253 ac_build_endif(&ctx->ac, 5130);
3254
3255 ac_build_s_barrier(&ctx->ac);
3256
3257 /* Export primitive data */
3258 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3259 ac_build_ifcc(&ctx->ac, tmp, 5140);
3260 {
3261 LLVMValueRef flags;
3262 struct ac_ngg_prim prim = {};
3263 prim.num_vertices = verts_per_prim;
3264
3265 tmp = ngg_gs_vertex_ptr(ctx, tid);
3266 flags = LLVMBuildLoad(builder,
3267 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 0), "");
3268 prim.isnull = LLVMBuildNot(builder, LLVMBuildTrunc(builder, flags, ctx->ac.i1, ""), "");
3269
3270 for (unsigned i = 0; i < verts_per_prim; ++i) {
3271 prim.index[i] = LLVMBuildSub(builder, vertlive_scan.result_exclusive,
3272 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3273 prim.edgeflag[i] = ctx->ac.i1false;
3274 }
3275
3276 /* Geometry shaders output triangle strips, but NGG expects
3277 * triangles. We need to change the vertex order for odd
3278 * triangles to get correct front/back facing by swapping 2
3279 * vertex indices, but we also have to keep the provoking
3280 * vertex in the same place.
3281 */
3282 if (verts_per_prim == 3) {
3283 LLVMValueRef is_odd = LLVMBuildLShr(builder, flags, ctx->ac.i8_1, "");
3284 is_odd = LLVMBuildTrunc(builder, is_odd, ctx->ac.i1, "");
3285
3286 struct ac_ngg_prim in = prim;
3287 prim.index[0] = in.index[0];
3288 prim.index[1] = LLVMBuildSelect(builder, is_odd,
3289 in.index[2], in.index[1], "");
3290 prim.index[2] = LLVMBuildSelect(builder, is_odd,
3291 in.index[1], in.index[2], "");
3292 }
3293
3294 ac_build_export_prim(&ctx->ac, &prim);
3295 }
3296 ac_build_endif(&ctx->ac, 5140);
3297
3298 /* Export position and parameter data */
3299 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, vertlive_scan.result_reduce, "");
3300 ac_build_ifcc(&ctx->ac, tmp, 5145);
3301 {
3302 struct radv_vs_output_info *outinfo = &ctx->args->shader_info->vs.outinfo;
3303 bool export_view_index = ctx->args->options->key.has_multiview_view_index;
3304 struct radv_shader_output_values *outputs;
3305 unsigned noutput = 0;
3306
3307 /* Allocate a temporary array for the output values. */
3308 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_view_index;
3309 outputs = calloc(num_outputs, sizeof(outputs[0]));
3310
3311 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
3312 sizeof(outinfo->vs_output_param_offset));
3313 outinfo->pos_exports = 0;
3314
3315 tmp = ngg_gs_vertex_ptr(ctx, tid);
3316 tmp = LLVMBuildLoad(builder,
3317 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 1), "");
3318 tmp = LLVMBuildZExt(builder, tmp, ctx->ac.i32, "");
3319 const LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tmp);
3320
3321 unsigned out_idx = 0;
3322 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3323 unsigned output_usage_mask =
3324 ctx->args->shader_info->gs.output_usage_mask[i];
3325 int length = util_last_bit(output_usage_mask);
3326
3327 if (!(ctx->output_mask & (1ull << i)))
3328 continue;
3329
3330 outputs[noutput].slot_name = i;
3331 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
3332 outputs[noutput].usage_mask = output_usage_mask;
3333
3334 for (unsigned j = 0; j < length; j++, out_idx++) {
3335 if (!(output_usage_mask & (1 << j)))
3336 continue;
3337
3338 tmp = ngg_gs_get_emit_output_ptr(ctx, vertexptr, out_idx);
3339 tmp = LLVMBuildLoad(builder, tmp, "");
3340
3341 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3342 if (ac_get_type_size(type) == 2) {
3343 tmp = ac_to_integer(&ctx->ac, tmp);
3344 tmp = LLVMBuildTrunc(ctx->ac.builder, tmp, ctx->ac.i16, "");
3345 }
3346
3347 outputs[noutput].values[j] = ac_to_float(&ctx->ac, tmp);
3348 }
3349
3350 for (unsigned j = length; j < 4; j++)
3351 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
3352
3353 noutput++;
3354 }
3355
3356 /* Export ViewIndex. */
3357 if (export_view_index) {
3358 outputs[noutput].slot_name = VARYING_SLOT_LAYER;
3359 outputs[noutput].slot_index = 0;
3360 outputs[noutput].usage_mask = 0x1;
3361 outputs[noutput].values[0] =
3362 ac_to_float(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.view_index));
3363 for (unsigned j = 1; j < 4; j++)
3364 outputs[noutput].values[j] = ctx->ac.f32_0;
3365 noutput++;
3366 }
3367
3368 radv_llvm_export_vs(ctx, outputs, noutput, outinfo,
3369 ctx->args->options->key.vs_common_out.export_clip_dists);
3370 FREE(outputs);
3371 }
3372 ac_build_endif(&ctx->ac, 5145);
3373 }
3374
3375 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
3376 unsigned stream,
3377 LLVMValueRef *addrs)
3378 {
3379 LLVMBuilderRef builder = ctx->ac.builder;
3380 LLVMValueRef tmp;
3381 const LLVMValueRef vertexidx =
3382 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
3383
3384 /* If this thread has already emitted the declared maximum number of
3385 * vertices, skip the write: excessive vertex emissions are not
3386 * supposed to have any effect.
3387 */
3388 const LLVMValueRef can_emit =
3389 LLVMBuildICmp(builder, LLVMIntULT, vertexidx,
3390 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
3391 ac_build_ifcc(&ctx->ac, can_emit, 9001);
3392
3393 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3394 tmp = LLVMBuildSelect(builder, can_emit, tmp, vertexidx, "");
3395 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3396
3397 const LLVMValueRef vertexptr =
3398 ngg_gs_emit_vertex_ptr(ctx, get_thread_id_in_tg(ctx), vertexidx);
3399 unsigned out_idx = 0;
3400 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3401 unsigned output_usage_mask =
3402 ctx->args->shader_info->gs.output_usage_mask[i];
3403 uint8_t output_stream =
3404 ctx->args->shader_info->gs.output_streams[i];
3405 LLVMValueRef *out_ptr = &addrs[i * 4];
3406 int length = util_last_bit(output_usage_mask);
3407
3408 if (!(ctx->output_mask & (1ull << i)) ||
3409 output_stream != stream)
3410 continue;
3411
3412 for (unsigned j = 0; j < length; j++, out_idx++) {
3413 if (!(output_usage_mask & (1 << j)))
3414 continue;
3415
3416 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
3417 out_ptr[j], "");
3418 out_val = ac_to_integer(&ctx->ac, out_val);
3419 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
3420
3421 LLVMBuildStore(builder, out_val,
3422 ngg_gs_get_emit_output_ptr(ctx, vertexptr, out_idx));
3423 }
3424 }
3425 assert(out_idx * 4 <= ctx->args->shader_info->gs.gsvs_vertex_size);
3426
3427 /* Determine and store whether this vertex completed a primitive. */
3428 const LLVMValueRef curverts = LLVMBuildLoad(builder, ctx->gs_curprim_verts[stream], "");
3429
3430 tmp = LLVMConstInt(ctx->ac.i32, si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) - 1, false);
3431 const LLVMValueRef iscompleteprim =
3432 LLVMBuildICmp(builder, LLVMIntUGE, curverts, tmp, "");
3433
3434 /* Since the geometry shader emits triangle strips, we need to
3435 * track which primitive is odd and swap vertex indices to get
3436 * the correct vertex order.
3437 */
3438 LLVMValueRef is_odd = ctx->ac.i1false;
3439 if (stream == 0 &&
3440 si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) == 3) {
3441 tmp = LLVMBuildAnd(builder, curverts, ctx->ac.i32_1, "");
3442 is_odd = LLVMBuildICmp(builder, LLVMIntEQ, tmp, ctx->ac.i32_1, "");
3443 }
3444
3445 tmp = LLVMBuildAdd(builder, curverts, ctx->ac.i32_1, "");
3446 LLVMBuildStore(builder, tmp, ctx->gs_curprim_verts[stream]);
3447
3448 /* The per-vertex primitive flag encoding:
3449 * bit 0: whether this vertex finishes a primitive
3450 * bit 1: whether the primitive is odd (if we are emitting triangle strips)
3451 */
3452 tmp = LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i8, "");
3453 tmp = LLVMBuildOr(builder, tmp,
3454 LLVMBuildShl(builder,
3455 LLVMBuildZExt(builder, is_odd, ctx->ac.i8, ""),
3456 ctx->ac.i8_1, ""), "");
3457 LLVMBuildStore(builder, tmp,
3458 ngg_gs_get_emit_primflag_ptr(ctx, vertexptr, stream));
3459
3460 tmp = LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3461 tmp = LLVMBuildAdd(builder, tmp, LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i32, ""), "");
3462 LLVMBuildStore(builder, tmp, ctx->gs_generated_prims[stream]);
3463
3464 ac_build_endif(&ctx->ac, 9001);
3465 }
3466
3467 static void
3468 write_tess_factors(struct radv_shader_context *ctx)
3469 {
3470 unsigned stride, outer_comps, inner_comps;
3471 LLVMValueRef tcs_rel_ids = ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids);
3472 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, tcs_rel_ids, 8, 5);
3473 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, tcs_rel_ids, 0, 8);
3474 unsigned tess_inner_index = 0, tess_outer_index;
3475 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
3476 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3477 int i;
3478 ac_emit_barrier(&ctx->ac, ctx->stage);
3479
3480 switch (ctx->args->options->key.tcs.primitive_mode) {
3481 case GL_ISOLINES:
3482 stride = 2;
3483 outer_comps = 2;
3484 inner_comps = 0;
3485 break;
3486 case GL_TRIANGLES:
3487 stride = 4;
3488 outer_comps = 3;
3489 inner_comps = 1;
3490 break;
3491 case GL_QUADS:
3492 stride = 6;
3493 outer_comps = 4;
3494 inner_comps = 2;
3495 break;
3496 default:
3497 return;
3498 }
3499
3500 ac_build_ifcc(&ctx->ac,
3501 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3502 invocation_id, ctx->ac.i32_0, ""), 6503);
3503
3504 lds_base = get_tcs_out_current_patch_data_offset(ctx);
3505
3506 if (inner_comps) {
3507 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3508 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3509 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
3510 }
3511
3512 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3513 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3514 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
3515
3516 for (i = 0; i < 4; i++) {
3517 inner[i] = LLVMGetUndef(ctx->ac.i32);
3518 outer[i] = LLVMGetUndef(ctx->ac.i32);
3519 }
3520
3521 // LINES reversal
3522 if (ctx->args->options->key.tcs.primitive_mode == GL_ISOLINES) {
3523 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
3524 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3525 ctx->ac.i32_1, "");
3526 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
3527 } else {
3528 for (i = 0; i < outer_comps; i++) {
3529 outer[i] = out[i] =
3530 ac_lds_load(&ctx->ac, lds_outer);
3531 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3532 ctx->ac.i32_1, "");
3533 }
3534 for (i = 0; i < inner_comps; i++) {
3535 inner[i] = out[outer_comps+i] =
3536 ac_lds_load(&ctx->ac, lds_inner);
3537 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
3538 ctx->ac.i32_1, "");
3539 }
3540 }
3541
3542 /* Convert the outputs to vectors for stores. */
3543 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3544 vec1 = NULL;
3545
3546 if (stride > 4)
3547 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
3548
3549
3550 buffer = ctx->hs_ring_tess_factor;
3551 tf_base = ac_get_arg(&ctx->ac, ctx->args->tess_factor_offset);
3552 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3553 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
3554 unsigned tf_offset = 0;
3555
3556 if (ctx->ac.chip_class <= GFX8) {
3557 ac_build_ifcc(&ctx->ac,
3558 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3559 rel_patch_id, ctx->ac.i32_0, ""), 6504);
3560
3561 /* Store the dynamic HS control word. */
3562 ac_build_buffer_store_dword(&ctx->ac, buffer,
3563 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
3564 1, ctx->ac.i32_0, tf_base,
3565 0, ac_glc);
3566 tf_offset += 4;
3567
3568 ac_build_endif(&ctx->ac, 6504);
3569 }
3570
3571 /* Store the tessellation factors. */
3572 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3573 MIN2(stride, 4), byteoffset, tf_base,
3574 tf_offset, ac_glc);
3575 if (vec1)
3576 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3577 stride - 4, byteoffset, tf_base,
3578 16 + tf_offset, ac_glc);
3579
3580 //store to offchip for TES to read - only if TES reads them
3581 if (ctx->args->options->key.tcs.tes_reads_tess_factors) {
3582 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
3583 LLVMValueRef tf_inner_offset;
3584 unsigned param_outer, param_inner;
3585
3586 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3587 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
3588 LLVMConstInt(ctx->ac.i32, param_outer, 0));
3589
3590 outer_vec = ac_build_gather_values(&ctx->ac, outer,
3591 util_next_power_of_two(outer_comps));
3592
3593 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
3594 outer_comps, tf_outer_offset,
3595 ac_get_arg(&ctx->ac, ctx->args->oc_lds),
3596 0, ac_glc);
3597 if (inner_comps) {
3598 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3599 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
3600 LLVMConstInt(ctx->ac.i32, param_inner, 0));
3601
3602 inner_vec = inner_comps == 1 ? inner[0] :
3603 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3604 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
3605 inner_comps, tf_inner_offset,
3606 ac_get_arg(&ctx->ac, ctx->args->oc_lds),
3607 0, ac_glc);
3608 }
3609 }
3610
3611 ac_build_endif(&ctx->ac, 6503);
3612 }
3613
3614 static void
3615 handle_tcs_outputs_post(struct radv_shader_context *ctx)
3616 {
3617 write_tess_factors(ctx);
3618 }
3619
3620 static bool
3621 si_export_mrt_color(struct radv_shader_context *ctx,
3622 LLVMValueRef *color, unsigned index,
3623 struct ac_export_args *args)
3624 {
3625 /* Export */
3626 si_llvm_init_export_args(ctx, color, 0xf,
3627 V_008DFC_SQ_EXP_MRT + index, args);
3628 if (!args->enabled_channels)
3629 return false; /* unnecessary NULL export */
3630
3631 return true;
3632 }
3633
3634 static void
3635 radv_export_mrt_z(struct radv_shader_context *ctx,
3636 LLVMValueRef depth, LLVMValueRef stencil,
3637 LLVMValueRef samplemask)
3638 {
3639 struct ac_export_args args;
3640
3641 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3642
3643 ac_build_export(&ctx->ac, &args);
3644 }
3645
3646 static void
3647 handle_fs_outputs_post(struct radv_shader_context *ctx)
3648 {
3649 unsigned index = 0;
3650 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3651 struct ac_export_args color_args[8];
3652
3653 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3654 LLVMValueRef values[4];
3655
3656 if (!(ctx->output_mask & (1ull << i)))
3657 continue;
3658
3659 if (i < FRAG_RESULT_DATA0)
3660 continue;
3661
3662 for (unsigned j = 0; j < 4; j++)
3663 values[j] = ac_to_float(&ctx->ac,
3664 radv_load_output(ctx, i, j));
3665
3666 bool ret = si_export_mrt_color(ctx, values,
3667 i - FRAG_RESULT_DATA0,
3668 &color_args[index]);
3669 if (ret)
3670 index++;
3671 }
3672
3673 /* Process depth, stencil, samplemask. */
3674 if (ctx->args->shader_info->ps.writes_z) {
3675 depth = ac_to_float(&ctx->ac,
3676 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
3677 }
3678 if (ctx->args->shader_info->ps.writes_stencil) {
3679 stencil = ac_to_float(&ctx->ac,
3680 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
3681 }
3682 if (ctx->args->shader_info->ps.writes_sample_mask) {
3683 samplemask = ac_to_float(&ctx->ac,
3684 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
3685 }
3686
3687 /* Set the DONE bit on last non-null color export only if Z isn't
3688 * exported.
3689 */
3690 if (index > 0 &&
3691 !ctx->args->shader_info->ps.writes_z &&
3692 !ctx->args->shader_info->ps.writes_stencil &&
3693 !ctx->args->shader_info->ps.writes_sample_mask) {
3694 unsigned last = index - 1;
3695
3696 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
3697 color_args[last].done = 1; /* DONE bit */
3698 }
3699
3700 /* Export PS outputs. */
3701 for (unsigned i = 0; i < index; i++)
3702 ac_build_export(&ctx->ac, &color_args[i]);
3703
3704 if (depth || stencil || samplemask)
3705 radv_export_mrt_z(ctx, depth, stencil, samplemask);
3706 else if (!index)
3707 ac_build_export_null(&ctx->ac);
3708 }
3709
3710 static void
3711 emit_gs_epilogue(struct radv_shader_context *ctx)
3712 {
3713 if (ctx->args->options->key.vs_common_out.as_ngg) {
3714 gfx10_ngg_gs_emit_epilogue_1(ctx);
3715 return;
3716 }
3717
3718 if (ctx->ac.chip_class >= GFX10)
3719 LLVMBuildFence(ctx->ac.builder, LLVMAtomicOrderingRelease, false, "");
3720
3721 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
3722 }
3723
3724 static void
3725 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
3726 LLVMValueRef *addrs)
3727 {
3728 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3729
3730 switch (ctx->stage) {
3731 case MESA_SHADER_VERTEX:
3732 if (ctx->args->options->key.vs_common_out.as_ls)
3733 handle_ls_outputs_post(ctx);
3734 else if (ctx->args->options->key.vs_common_out.as_es)
3735 handle_es_outputs_post(ctx, &ctx->args->shader_info->vs.es_info);
3736 else if (ctx->args->options->key.vs_common_out.as_ngg)
3737 handle_ngg_outputs_post_1(ctx);
3738 else
3739 handle_vs_outputs_post(ctx, ctx->args->options->key.vs_common_out.export_prim_id,
3740 ctx->args->options->key.vs_common_out.export_clip_dists,
3741 &ctx->args->shader_info->vs.outinfo);
3742 break;
3743 case MESA_SHADER_FRAGMENT:
3744 handle_fs_outputs_post(ctx);
3745 break;
3746 case MESA_SHADER_GEOMETRY:
3747 emit_gs_epilogue(ctx);
3748 break;
3749 case MESA_SHADER_TESS_CTRL:
3750 handle_tcs_outputs_post(ctx);
3751 break;
3752 case MESA_SHADER_TESS_EVAL:
3753 if (ctx->args->options->key.vs_common_out.as_es)
3754 handle_es_outputs_post(ctx, &ctx->args->shader_info->tes.es_info);
3755 else if (ctx->args->options->key.vs_common_out.as_ngg)
3756 handle_ngg_outputs_post_1(ctx);
3757 else
3758 handle_vs_outputs_post(ctx, ctx->args->options->key.vs_common_out.export_prim_id,
3759 ctx->args->options->key.vs_common_out.export_clip_dists,
3760 &ctx->args->shader_info->tes.outinfo);
3761 break;
3762 default:
3763 break;
3764 }
3765 }
3766
3767 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
3768 LLVMPassManagerRef passmgr,
3769 const struct radv_nir_compiler_options *options)
3770 {
3771 LLVMRunPassManager(passmgr, ctx->ac.module);
3772 LLVMDisposeBuilder(ctx->ac.builder);
3773
3774 ac_llvm_context_dispose(&ctx->ac);
3775 }
3776
3777 static void
3778 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
3779 {
3780 struct radv_vs_output_info *outinfo;
3781
3782 switch (ctx->stage) {
3783 case MESA_SHADER_FRAGMENT:
3784 case MESA_SHADER_COMPUTE:
3785 case MESA_SHADER_TESS_CTRL:
3786 case MESA_SHADER_GEOMETRY:
3787 return;
3788 case MESA_SHADER_VERTEX:
3789 if (ctx->args->options->key.vs_common_out.as_ls ||
3790 ctx->args->options->key.vs_common_out.as_es)
3791 return;
3792 outinfo = &ctx->args->shader_info->vs.outinfo;
3793 break;
3794 case MESA_SHADER_TESS_EVAL:
3795 if (ctx->args->options->key.vs_common_out.as_es)
3796 return;
3797 outinfo = &ctx->args->shader_info->tes.outinfo;
3798 break;
3799 default:
3800 unreachable("Unhandled shader type");
3801 }
3802
3803 ac_optimize_vs_outputs(&ctx->ac,
3804 ctx->main_function,
3805 outinfo->vs_output_param_offset,
3806 VARYING_SLOT_MAX,
3807 &outinfo->param_exports);
3808 }
3809
3810 static void
3811 ac_setup_rings(struct radv_shader_context *ctx)
3812 {
3813 if (ctx->args->options->chip_class <= GFX8 &&
3814 (ctx->stage == MESA_SHADER_GEOMETRY ||
3815 ctx->args->options->key.vs_common_out.as_es || ctx->args->options->key.vs_common_out.as_es)) {
3816 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3817 : RING_ESGS_VS;
3818 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3819
3820 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3821 ctx->ring_offsets,
3822 offset);
3823 }
3824
3825 if (ctx->args->is_gs_copy_shader) {
3826 ctx->gsvs_ring[0] =
3827 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3828 LLVMConstInt(ctx->ac.i32,
3829 RING_GSVS_VS, false));
3830 }
3831
3832 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3833 /* The conceptual layout of the GSVS ring is
3834 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3835 * but the real memory layout is swizzled across
3836 * threads:
3837 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3838 * t16v0c0 ..
3839 * Override the buffer descriptor accordingly.
3840 */
3841 LLVMTypeRef v2i64 = LLVMVectorType(ctx->ac.i64, 2);
3842 uint64_t stream_offset = 0;
3843 unsigned num_records = ctx->ac.wave_size;
3844 LLVMValueRef base_ring;
3845
3846 base_ring =
3847 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3848 LLVMConstInt(ctx->ac.i32,
3849 RING_GSVS_GS, false));
3850
3851 for (unsigned stream = 0; stream < 4; stream++) {
3852 unsigned num_components, stride;
3853 LLVMValueRef ring, tmp;
3854
3855 num_components =
3856 ctx->args->shader_info->gs.num_stream_output_components[stream];
3857
3858 if (!num_components)
3859 continue;
3860
3861 stride = 4 * num_components * ctx->shader->info.gs.vertices_out;
3862
3863 /* Limit on the stride field for <= GFX7. */
3864 assert(stride < (1 << 14));
3865
3866 ring = LLVMBuildBitCast(ctx->ac.builder,
3867 base_ring, v2i64, "");
3868 tmp = LLVMBuildExtractElement(ctx->ac.builder,
3869 ring, ctx->ac.i32_0, "");
3870 tmp = LLVMBuildAdd(ctx->ac.builder, tmp,
3871 LLVMConstInt(ctx->ac.i64,
3872 stream_offset, 0), "");
3873 ring = LLVMBuildInsertElement(ctx->ac.builder,
3874 ring, tmp, ctx->ac.i32_0, "");
3875
3876 stream_offset += stride * ctx->ac.wave_size;
3877
3878 ring = LLVMBuildBitCast(ctx->ac.builder, ring,
3879 ctx->ac.v4i32, "");
3880
3881 tmp = LLVMBuildExtractElement(ctx->ac.builder, ring,
3882 ctx->ac.i32_1, "");
3883 tmp = LLVMBuildOr(ctx->ac.builder, tmp,
3884 LLVMConstInt(ctx->ac.i32,
3885 S_008F04_STRIDE(stride), false), "");
3886 ring = LLVMBuildInsertElement(ctx->ac.builder, ring, tmp,
3887 ctx->ac.i32_1, "");
3888
3889 ring = LLVMBuildInsertElement(ctx->ac.builder, ring,
3890 LLVMConstInt(ctx->ac.i32,
3891 num_records, false),
3892 LLVMConstInt(ctx->ac.i32, 2, false), "");
3893
3894 ctx->gsvs_ring[stream] = ring;
3895 }
3896 }
3897
3898 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3899 ctx->stage == MESA_SHADER_TESS_EVAL) {
3900 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3901 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3902 }
3903 }
3904
3905 unsigned
3906 radv_nir_get_max_workgroup_size(enum chip_class chip_class,
3907 gl_shader_stage stage,
3908 const struct nir_shader *nir)
3909 {
3910 const unsigned backup_sizes[] = {chip_class >= GFX9 ? 128 : 64, 1, 1};
3911 unsigned sizes[3];
3912 for (unsigned i = 0; i < 3; i++)
3913 sizes[i] = nir ? nir->info.cs.local_size[i] : backup_sizes[i];
3914 return radv_get_max_workgroup_size(chip_class, stage, sizes);
3915 }
3916
3917 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3918 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3919 {
3920 LLVMValueRef count =
3921 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 8, 8);
3922 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3923 ctx->ac.i32_0, "");
3924 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3925 ac_get_arg(&ctx->ac, ctx->args->rel_auto_id),
3926 ctx->abi.instance_id, "");
3927 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3928 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),
3929 ctx->rel_auto_id,
3930 "");
3931 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3932 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_patch_id),
3933 ctx->abi.vertex_id, "");
3934 }
3935
3936 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx, bool merged)
3937 {
3938 if (merged) {
3939 for(int i = 5; i >= 0; --i) {
3940 ctx->gs_vtx_offset[i] =
3941 ac_unpack_param(&ctx->ac,
3942 ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[i & ~1]),
3943 (i & 1) * 16, 16);
3944 }
3945
3946 ctx->gs_wave_id = ac_unpack_param(&ctx->ac,
3947 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info),
3948 16, 8);
3949 } else {
3950 for (int i = 0; i < 6; i++)
3951 ctx->gs_vtx_offset[i] = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[i]);
3952 ctx->gs_wave_id = ac_get_arg(&ctx->ac, ctx->args->gs_wave_id);
3953 }
3954 }
3955
3956 /* Ensure that the esgs ring is declared.
3957 *
3958 * We declare it with 64KB alignment as a hint that the
3959 * pointer value will always be 0.
3960 */
3961 static void declare_esgs_ring(struct radv_shader_context *ctx)
3962 {
3963 if (ctx->esgs_ring)
3964 return;
3965
3966 assert(!LLVMGetNamedGlobal(ctx->ac.module, "esgs_ring"));
3967
3968 ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
3969 ctx->ac.module, LLVMArrayType(ctx->ac.i32, 0),
3970 "esgs_ring",
3971 AC_ADDR_SPACE_LDS);
3972 LLVMSetLinkage(ctx->esgs_ring, LLVMExternalLinkage);
3973 LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
3974 }
3975
3976 static
3977 LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
3978 struct nir_shader *const *shaders,
3979 int shader_count,
3980 const struct radv_shader_args *args)
3981 {
3982 struct radv_shader_context ctx = {0};
3983 ctx.args = args;
3984
3985 enum ac_float_mode float_mode = AC_FLOAT_MODE_DEFAULT;
3986
3987 if (args->shader_info->float_controls_mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32) {
3988 float_mode = AC_FLOAT_MODE_DENORM_FLUSH_TO_ZERO;
3989 }
3990
3991 ac_llvm_context_init(&ctx.ac, ac_llvm, args->options->chip_class,
3992 args->options->family, float_mode,
3993 args->shader_info->wave_size, 64);
3994 ctx.context = ctx.ac.context;
3995
3996 ctx.max_workgroup_size = 0;
3997 for (int i = 0; i < shader_count; ++i) {
3998 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3999 radv_nir_get_max_workgroup_size(args->options->chip_class,
4000 shaders[i]->info.stage,
4001 shaders[i]));
4002 }
4003
4004 if (ctx.ac.chip_class >= GFX10) {
4005 if (is_pre_gs_stage(shaders[0]->info.stage) &&
4006 args->options->key.vs_common_out.as_ngg) {
4007 ctx.max_workgroup_size = 128;
4008 }
4009 }
4010
4011 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2);
4012
4013 ctx.abi.inputs = &ctx.inputs[0];
4014 ctx.abi.emit_outputs = handle_shader_outputs_post;
4015 ctx.abi.emit_vertex = visit_emit_vertex;
4016 ctx.abi.load_ubo = radv_load_ubo;
4017 ctx.abi.load_ssbo = radv_load_ssbo;
4018 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
4019 ctx.abi.load_resource = radv_load_resource;
4020 ctx.abi.clamp_shadow_reference = false;
4021 ctx.abi.robust_buffer_access = args->options->robust_buffer_access;
4022
4023 bool is_ngg = is_pre_gs_stage(shaders[0]->info.stage) && args->options->key.vs_common_out.as_ngg;
4024 if (shader_count >= 2 || is_ngg)
4025 ac_init_exec_full_mask(&ctx.ac);
4026
4027 if (args->ac.vertex_id.used)
4028 ctx.abi.vertex_id = ac_get_arg(&ctx.ac, args->ac.vertex_id);
4029 if (args->rel_auto_id.used)
4030 ctx.rel_auto_id = ac_get_arg(&ctx.ac, args->rel_auto_id);
4031 if (args->ac.instance_id.used)
4032 ctx.abi.instance_id = ac_get_arg(&ctx.ac, args->ac.instance_id);
4033
4034 if (args->options->has_ls_vgpr_init_bug &&
4035 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
4036 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
4037
4038 if (is_ngg) {
4039 /* Declare scratch space base for streamout and vertex
4040 * compaction. Whether space is actually allocated is
4041 * determined during linking / PM4 creation.
4042 *
4043 * Add an extra dword per vertex to ensure an odd stride, which
4044 * avoids bank conflicts for SoA accesses.
4045 */
4046 if (!args->options->key.vs_common_out.as_ngg_passthrough)
4047 declare_esgs_ring(&ctx);
4048
4049 /* This is really only needed when streamout and / or vertex
4050 * compaction is enabled.
4051 */
4052 if (args->shader_info->so.num_outputs) {
4053 LLVMTypeRef asi32 = LLVMArrayType(ctx.ac.i32, 8);
4054 ctx.gs_ngg_scratch = LLVMAddGlobalInAddressSpace(ctx.ac.module,
4055 asi32, "ngg_scratch", AC_ADDR_SPACE_LDS);
4056 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(asi32));
4057 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
4058 }
4059 }
4060
4061 for(int i = 0; i < shader_count; ++i) {
4062 ctx.stage = shaders[i]->info.stage;
4063 ctx.shader = shaders[i];
4064 ctx.output_mask = 0;
4065
4066 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
4067 for (int i = 0; i < 4; i++) {
4068 ctx.gs_next_vertex[i] =
4069 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4070 }
4071 if (args->options->key.vs_common_out.as_ngg) {
4072 for (unsigned i = 0; i < 4; ++i) {
4073 ctx.gs_curprim_verts[i] =
4074 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4075 ctx.gs_generated_prims[i] =
4076 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4077 }
4078
4079 unsigned scratch_size = 8;
4080 if (args->shader_info->so.num_outputs)
4081 scratch_size = 44;
4082
4083 LLVMTypeRef ai32 = LLVMArrayType(ctx.ac.i32, scratch_size);
4084 ctx.gs_ngg_scratch =
4085 LLVMAddGlobalInAddressSpace(ctx.ac.module,
4086 ai32, "ngg_scratch", AC_ADDR_SPACE_LDS);
4087 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(ai32));
4088 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
4089
4090 ctx.gs_ngg_emit = LLVMAddGlobalInAddressSpace(ctx.ac.module,
4091 LLVMArrayType(ctx.ac.i32, 0), "ngg_emit", AC_ADDR_SPACE_LDS);
4092 LLVMSetLinkage(ctx.gs_ngg_emit, LLVMExternalLinkage);
4093 LLVMSetAlignment(ctx.gs_ngg_emit, 4);
4094 }
4095
4096 ctx.abi.load_inputs = load_gs_input;
4097 ctx.abi.emit_primitive = visit_end_primitive;
4098 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4099 ctx.abi.load_tess_varyings = load_tcs_varyings;
4100 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4101 ctx.abi.store_tcs_outputs = store_tcs_output;
4102 if (shader_count == 1)
4103 ctx.tcs_num_inputs = args->options->key.tcs.num_inputs;
4104 else
4105 ctx.tcs_num_inputs = util_last_bit64(args->shader_info->vs.ls_outputs_written);
4106 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
4107 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
4108 ctx.abi.load_tess_varyings = load_tes_input;
4109 ctx.abi.load_tess_coord = load_tess_coord;
4110 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4111 ctx.tcs_num_patches = args->options->key.tes.num_patches;
4112 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
4113 ctx.abi.load_base_vertex = radv_load_base_vertex;
4114 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
4115 ctx.abi.load_sample_position = load_sample_position;
4116 ctx.abi.load_sample_mask_in = load_sample_mask_in;
4117 ctx.abi.emit_kill = radv_emit_kill;
4118 }
4119
4120 if (shaders[i]->info.stage == MESA_SHADER_VERTEX &&
4121 args->options->key.vs_common_out.as_ngg &&
4122 args->options->key.vs_common_out.export_prim_id) {
4123 declare_esgs_ring(&ctx);
4124 }
4125
4126 bool nested_barrier = false;
4127
4128 if (i) {
4129 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4130 args->options->key.vs_common_out.as_ngg) {
4131 gfx10_ngg_gs_emit_prologue(&ctx);
4132 nested_barrier = false;
4133 } else {
4134 nested_barrier = true;
4135 }
4136 }
4137
4138 if (nested_barrier) {
4139 /* Execute a barrier before the second shader in
4140 * a merged shader.
4141 *
4142 * Execute the barrier inside the conditional block,
4143 * so that empty waves can jump directly to s_endpgm,
4144 * which will also signal the barrier.
4145 *
4146 * This is possible in gfx9, because an empty wave
4147 * for the second shader does not participate in
4148 * the epilogue. With NGG, empty waves may still
4149 * be required to export data (e.g. GS output vertices),
4150 * so we cannot let them exit early.
4151 *
4152 * If the shader is TCS and the TCS epilog is present
4153 * and contains a barrier, it will wait there and then
4154 * reach s_endpgm.
4155 */
4156 ac_emit_barrier(&ctx.ac, ctx.stage);
4157 }
4158
4159 nir_foreach_variable(variable, &shaders[i]->outputs)
4160 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
4161
4162 ac_setup_rings(&ctx);
4163
4164 LLVMBasicBlockRef merge_block;
4165 if (shader_count >= 2 || is_ngg) {
4166 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
4167 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4168 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4169
4170 LLVMValueRef count =
4171 ac_unpack_param(&ctx.ac,
4172 ac_get_arg(&ctx.ac, args->merged_wave_info),
4173 8 * i, 8);
4174 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
4175 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
4176 thread_id, count, "");
4177 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
4178
4179 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
4180 }
4181
4182 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
4183 prepare_interp_optimize(&ctx, shaders[i]);
4184 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
4185 handle_vs_inputs(&ctx, shaders[i]);
4186 else if(shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
4187 prepare_gs_input_vgprs(&ctx, shader_count >= 2);
4188
4189 ac_nir_translate(&ctx.ac, &ctx.abi, &args->ac, shaders[i]);
4190
4191 if (shader_count >= 2 || is_ngg) {
4192 LLVMBuildBr(ctx.ac.builder, merge_block);
4193 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
4194 }
4195
4196 /* This needs to be outside the if wrapping the shader body, as sometimes
4197 * the HW generates waves with 0 es/vs threads. */
4198 if (is_pre_gs_stage(shaders[i]->info.stage) &&
4199 args->options->key.vs_common_out.as_ngg &&
4200 i == shader_count - 1) {
4201 handle_ngg_outputs_post_2(&ctx);
4202 } else if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4203 args->options->key.vs_common_out.as_ngg) {
4204 gfx10_ngg_gs_emit_epilogue_2(&ctx);
4205 }
4206
4207 if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4208 args->shader_info->tcs.num_patches = ctx.tcs_num_patches;
4209 args->shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
4210 }
4211 }
4212
4213 LLVMBuildRetVoid(ctx.ac.builder);
4214
4215 if (args->options->dump_preoptir) {
4216 fprintf(stderr, "%s LLVM IR:\n\n",
4217 radv_get_shader_name(args->shader_info,
4218 shaders[shader_count - 1]->info.stage));
4219 ac_dump_module(ctx.ac.module);
4220 fprintf(stderr, "\n");
4221 }
4222
4223 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, args->options);
4224
4225 if (shader_count == 1)
4226 ac_nir_eliminate_const_vs_outputs(&ctx);
4227
4228 if (args->options->dump_shader) {
4229 args->shader_info->private_mem_vgprs =
4230 ac_count_scratch_private_memory(ctx.main_function);
4231 }
4232
4233 return ctx.ac.module;
4234 }
4235
4236 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4237 {
4238 unsigned *retval = (unsigned *)context;
4239 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4240 char *description = LLVMGetDiagInfoDescription(di);
4241
4242 if (severity == LLVMDSError) {
4243 *retval = 1;
4244 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4245 description);
4246 }
4247
4248 LLVMDisposeMessage(description);
4249 }
4250
4251 static unsigned radv_llvm_compile(LLVMModuleRef M,
4252 char **pelf_buffer, size_t *pelf_size,
4253 struct ac_llvm_compiler *ac_llvm)
4254 {
4255 unsigned retval = 0;
4256 LLVMContextRef llvm_ctx;
4257
4258 /* Setup Diagnostic Handler*/
4259 llvm_ctx = LLVMGetModuleContext(M);
4260
4261 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4262 &retval);
4263
4264 /* Compile IR*/
4265 if (!radv_compile_to_elf(ac_llvm, M, pelf_buffer, pelf_size))
4266 retval = 1;
4267 return retval;
4268 }
4269
4270 static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
4271 LLVMModuleRef llvm_module,
4272 struct radv_shader_binary **rbinary,
4273 gl_shader_stage stage,
4274 const char *name,
4275 const struct radv_nir_compiler_options *options)
4276 {
4277 char *elf_buffer = NULL;
4278 size_t elf_size = 0;
4279 char *llvm_ir_string = NULL;
4280
4281 if (options->dump_shader) {
4282 fprintf(stderr, "%s LLVM IR:\n\n", name);
4283 ac_dump_module(llvm_module);
4284 fprintf(stderr, "\n");
4285 }
4286
4287 if (options->record_ir) {
4288 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
4289 llvm_ir_string = strdup(llvm_ir);
4290 LLVMDisposeMessage(llvm_ir);
4291 }
4292
4293 int v = radv_llvm_compile(llvm_module, &elf_buffer, &elf_size, ac_llvm);
4294 if (v) {
4295 fprintf(stderr, "compile failed\n");
4296 }
4297
4298 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4299 LLVMDisposeModule(llvm_module);
4300 LLVMContextDispose(ctx);
4301
4302 size_t llvm_ir_size = llvm_ir_string ? strlen(llvm_ir_string) : 0;
4303 size_t alloc_size = sizeof(struct radv_shader_binary_rtld) + elf_size + llvm_ir_size + 1;
4304 struct radv_shader_binary_rtld *rbin = calloc(1, alloc_size);
4305 memcpy(rbin->data, elf_buffer, elf_size);
4306 if (llvm_ir_string)
4307 memcpy(rbin->data + elf_size, llvm_ir_string, llvm_ir_size + 1);
4308
4309 rbin->base.type = RADV_BINARY_TYPE_RTLD;
4310 rbin->base.stage = stage;
4311 rbin->base.total_size = alloc_size;
4312 rbin->elf_size = elf_size;
4313 rbin->llvm_ir_size = llvm_ir_size;
4314 *rbinary = &rbin->base;
4315
4316 free(llvm_ir_string);
4317 free(elf_buffer);
4318 }
4319
4320 void
4321 radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
4322 struct radv_shader_binary **rbinary,
4323 const struct radv_shader_args *args,
4324 struct nir_shader *const *nir,
4325 int nir_count)
4326 {
4327
4328 LLVMModuleRef llvm_module;
4329
4330 llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, args);
4331
4332 ac_compile_llvm_module(ac_llvm, llvm_module, rbinary,
4333 nir[nir_count - 1]->info.stage,
4334 radv_get_shader_name(args->shader_info,
4335 nir[nir_count - 1]->info.stage),
4336 args->options);
4337
4338 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4339 if (args->options->chip_class >= GFX9) {
4340 if (nir_count == 2 &&
4341 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
4342 args->shader_info->gs.es_type = nir[0]->info.stage;
4343 }
4344 }
4345 }
4346
4347 static void
4348 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
4349 {
4350 LLVMValueRef vtx_offset =
4351 LLVMBuildMul(ctx->ac.builder, ac_get_arg(&ctx->ac, ctx->args->ac.vertex_id),
4352 LLVMConstInt(ctx->ac.i32, 4, false), "");
4353 LLVMValueRef stream_id;
4354
4355 /* Fetch the vertex stream ID. */
4356 if (!ctx->args->options->use_ngg_streamout &&
4357 ctx->args->shader_info->so.num_outputs) {
4358 stream_id =
4359 ac_unpack_param(&ctx->ac,
4360 ac_get_arg(&ctx->ac,
4361 ctx->args->streamout_config),
4362 24, 2);
4363 } else {
4364 stream_id = ctx->ac.i32_0;
4365 }
4366
4367 LLVMBasicBlockRef end_bb;
4368 LLVMValueRef switch_inst;
4369
4370 end_bb = LLVMAppendBasicBlockInContext(ctx->ac.context,
4371 ctx->main_function, "end");
4372 switch_inst = LLVMBuildSwitch(ctx->ac.builder, stream_id, end_bb, 4);
4373
4374 for (unsigned stream = 0; stream < 4; stream++) {
4375 unsigned num_components =
4376 ctx->args->shader_info->gs.num_stream_output_components[stream];
4377 LLVMBasicBlockRef bb;
4378 unsigned offset;
4379
4380 if (stream > 0 && !num_components)
4381 continue;
4382
4383 if (stream > 0 && !ctx->args->shader_info->so.num_outputs)
4384 continue;
4385
4386 bb = LLVMInsertBasicBlockInContext(ctx->ac.context, end_bb, "out");
4387 LLVMAddCase(switch_inst, LLVMConstInt(ctx->ac.i32, stream, 0), bb);
4388 LLVMPositionBuilderAtEnd(ctx->ac.builder, bb);
4389
4390 offset = 0;
4391 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4392 unsigned output_usage_mask =
4393 ctx->args->shader_info->gs.output_usage_mask[i];
4394 unsigned output_stream =
4395 ctx->args->shader_info->gs.output_streams[i];
4396 int length = util_last_bit(output_usage_mask);
4397
4398 if (!(ctx->output_mask & (1ull << i)) ||
4399 output_stream != stream)
4400 continue;
4401
4402 for (unsigned j = 0; j < length; j++) {
4403 LLVMValueRef value, soffset;
4404
4405 if (!(output_usage_mask & (1 << j)))
4406 continue;
4407
4408 soffset = LLVMConstInt(ctx->ac.i32,
4409 offset *
4410 ctx->shader->info.gs.vertices_out * 16 * 4, false);
4411
4412 offset++;
4413
4414 value = ac_build_buffer_load(&ctx->ac,
4415 ctx->gsvs_ring[0],
4416 1, ctx->ac.i32_0,
4417 vtx_offset, soffset,
4418 0, ac_glc | ac_slc, true, false);
4419
4420 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4421 if (ac_get_type_size(type) == 2) {
4422 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
4423 value = LLVMBuildTrunc(ctx->ac.builder, value, ctx->ac.i16, "");
4424 }
4425
4426 LLVMBuildStore(ctx->ac.builder,
4427 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4428 }
4429 }
4430
4431 if (!ctx->args->options->use_ngg_streamout &&
4432 ctx->args->shader_info->so.num_outputs)
4433 radv_emit_streamout(ctx, stream);
4434
4435 if (stream == 0) {
4436 handle_vs_outputs_post(ctx, false, true,
4437 &ctx->args->shader_info->vs.outinfo);
4438 }
4439
4440 LLVMBuildBr(ctx->ac.builder, end_bb);
4441 }
4442
4443 LLVMPositionBuilderAtEnd(ctx->ac.builder, end_bb);
4444 }
4445
4446 void
4447 radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
4448 struct nir_shader *geom_shader,
4449 struct radv_shader_binary **rbinary,
4450 const struct radv_shader_args *args)
4451 {
4452 struct radv_shader_context ctx = {0};
4453 ctx.args = args;
4454
4455 assert(args->is_gs_copy_shader);
4456
4457 ac_llvm_context_init(&ctx.ac, ac_llvm, args->options->chip_class,
4458 args->options->family, AC_FLOAT_MODE_DEFAULT, 64, 64);
4459 ctx.context = ctx.ac.context;
4460
4461 ctx.stage = MESA_SHADER_VERTEX;
4462 ctx.shader = geom_shader;
4463
4464 create_function(&ctx, MESA_SHADER_VERTEX, false);
4465
4466 ac_setup_rings(&ctx);
4467
4468 nir_foreach_variable(variable, &geom_shader->outputs) {
4469 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
4470 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
4471 variable, MESA_SHADER_VERTEX);
4472 }
4473
4474 ac_gs_copy_shader_emit(&ctx);
4475
4476 LLVMBuildRetVoid(ctx.ac.builder);
4477
4478 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, args->options);
4479
4480 ac_compile_llvm_module(ac_llvm, ctx.ac.module, rbinary,
4481 MESA_SHADER_VERTEX, "GS Copy Shader", args->options);
4482 (*rbinary)->is_gs_copy_shader = true;
4483
4484 }